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第一次上传E3boot

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liumin
2025-08-22 09:18:17 +08:00
parent 17dcc44980
commit e248b10f07
16 changed files with 2715 additions and 0 deletions
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main.c Normal file
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#include <armv7-r/barriers.h>
#include <armv7-r/cache.h>
#include <clock_cfg.h>
#include <clock_ip.h>
#include <debug.h>
#include <param.h>
#include <part.h>
#include <pinmux_cfg.h>
#include <regs_base.h>
#include <remap/remap.h>
#include <reset_cfg.h>
#include <reset_ip.h>
#include <scr_hw.h>
#include <sdrv_ckgen.h>
#include <sdrv_rstgen.h>
#include <sdrv_scr.h>
#include <sdrv_spi_nor.h>
#include <sdrv_xspi.h>
#include <stdlib.h>
#include <string.h>
#include <types.h>
#include <udelay/udelay.h>
#include <sd_boot_img/sd_boot_img.h>
#include "board.h"
#include "irq_num.h"
#include <flexcan_cfg.h>
#include "IAP_Task.h"
#include "btm_init.h"
#include "flexcan_init.h"
#include "irq.h"
#include <sdrv_gpio.h>
#include <wdt_refresh.h>
#include "eth_cfg.h"
#include "sdrv_eth.h"
#include "interface_ethernet.h"
extern sdrv_scr_t g_scr_ctrl;
uint32_t udp_length = 0;
#define RFD_ENABLE 0
static struct spi_nor_host spi_nor_host = {0};
static struct xspi_pdata xspi = {0};
struct spi_nor flash = {0};
struct flash_info *flash_info;
flexcan_handle_t g_flexcan_handle;
static struct xspi_config host_config = {
.id = 0,
.apb_base = APB_XSPI1PORTA_BASE,
.direct_base = XSPI1_XSPI1PORTA_BASE,
};
static struct spi_nor_config config = {
.id = 0,
.cs = 0,
.baudrate = 20000000,
.xfer_mode = SPI_NOR_XFER_POLLING_MODE,
.dev_mode = SPI_NOR_DEV_SINGLE_MODE,
.sw_rst = false, /* config soft reset spi norflash */
.async_mode = false,
#ifdef CONFIG_HYPERBUS_MODE
.hyperbus_mode = CONFIG_HYPERBUS_MODE,
#else
.hyperbus_mode = false,
#endif
};
void xspi_lockstep_enable(bool flag)
{
#if ((CONFIG_E3210) || (CONFIG_E3110))
scr_signal_t signal = SCR_SF_XSPI1_SRC_CFG_LOCKSTEP_MODE_N;
#else
scr_signal_t signal = SCR_SF_XSPI1_LOCKSTEP_DISABLE;
#endif
sdrv_rstgen_assert(&rstsig_xspi1b);
sdrv_rstgen_assert(&rstsig_xspi1a);
udelay(10u);
scr_set(&g_scr_ctrl, &signal, !flag);
udelay(10u);
sdrv_rstgen_deassert(&rstsig_xspi1a);
sdrv_rstgen_deassert(&rstsig_xspi1b);
}
void xspi_parallel_enable(bool flag)
{
scr_signal_t signal = SCR_SF_XSPI1_SRC_CFG_PARALLEL_MODE;
sdrv_rstgen_assert(&rstsig_xspi1b);
sdrv_rstgen_assert(&rstsig_xspi1a);
udelay(10u);
scr_set(&g_scr_ctrl, &signal, flag);
udelay(10u);
sdrv_rstgen_deassert(&rstsig_xspi1a);
sdrv_rstgen_deassert(&rstsig_xspi1b);
}
void board_norflash_init(void)
{
bool locksetp_mode = false;
bool parallel_mode = false;
/* get xspi1a clk node */
sdrv_ckgen_node_t *clk = CLK_NODE(g_ckgen_ip_xspi1a);
/* config dev spi nor dev single mode */
switch (config.dev_mode) {
case SPI_NOR_DEV_LOCKSTEP_MODE:
locksetp_mode = true;
break;
case SPI_NOR_DEV_PARALLEL_MODE:
parallel_mode = true;
break;
default:
break;
}
/* close locksetp/parallel mode */
xspi_lockstep_enable(locksetp_mode);
xspi_parallel_enable(parallel_mode);
/* initializes xspi host */
host_config.ref_clk = sdrv_ckgen_get_rate(clk);
sdrv_xspi_host_init(&spi_nor_host, &xspi, &host_config);
spi_nor_host.clk = clk;
sdrv_ckgen_set_rate(clk, config.baudrate);
ssdk_printf(SSDK_CRIT, "xspi clock rate is %u!\r\n",
sdrv_ckgen_get_rate(clk));
/* initializes spi nor device */
if (sdrv_spi_nor_init(&flash, &spi_nor_host, &config)) {
ssdk_printf(SSDK_CRIT, "spinor init failed!\r\n");
return;
}
/* get flash info data information */
flash_info = sdrv_spi_nor_get_info(&flash);
ssdk_printf(SSDK_CRIT,
"spinor flash size = 0x%llx, sector_size = 0x%x \r\n",
flash_info->size, flash_info->sector_size);
#if RFD_ENABLE
/* enable rfd */
uint8_t rfd_mask = 0;
if(!check_rfd(host_config.direct_base, &rfd_mask) && rfd_mask) {
sdrv_spi_nor_enable_rfd(&flash, rfd_mask);
}
#endif
return;
}
uint8_t mainCnt = 0;
//uint8_t mainCntarr[8] = {0x56,0x88,0x98,0x79,0x23};
//uint8_t mainCntarrRx[8] = {0,0,0,0,0};
//uint32_t timeus = 0;
int main(void)
{
uint8_t BOOT_Arr[2] = {0x00,0x01};
static uint8_t RgWDT500msflg = 0;
//---------------------------------------------------------------
/* reset module */
board_reset_init();
/* initializes clock source */
sdrv_ckgen_init(&g_clock_config);
/*VIC<49><43>ʼ<EFBFBD><CABC>*/
irq_initialize(VIC1_BASE, IRQ_MAX_INTR_NUM);
/* config spinor pinmux */
sdrv_pinctrl_init(NUM_OF_CONFIGURED_PINS, g_pin_init_config);
sdrv_gpio_set_pin_output_level(GPIO_B9, 1); //<2F><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
External_wdt_refresh();
// Timer<65><72>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ṩLWIP sys_now<6F>ӿڻ<D3BF>ȡ<EFBFBD><C8A1>ǰʱ<C7B0><CAB1>
btm_init();
/* board debug console uart init */
board_debug_console_init();
sdrv_gpio_set_pin_output_level(GPIO_H12, 0); //CANʹ<4E><CAB9>
/* initialize the FlexCAN handle. */
flexcan_handle_t *handle = &g_flexcan_handle;
flexcan_create_handle(handle, FLEXCAN6, (void *)APB_CANFD6_BASE,
CANFD6_CANFD_INTR_NUM, flexcan_transfer_callback,
NULL);
/* initialize flexCAN. */
flexcan_init(handle, &g_flexcan_config);
/* unfreeze the flexCAN by demo. */
flexcan_freeze(handle, false);
/* enable busoff interrupt. */
flexcan_enable_interrupts(handle, FLEXCAN_BusOffInterruptEnable);//
/* enable irq. */
irq_attach(handle->irq_num, flexcan_irq_handler, handle);
irq_enable(handle->irq_num);
/* assign fifo only for rx. */
flexcan_config_rx_fifo(handle, &flexcan_fifo_cfg);
/* assign mailbox14-20 for tx. */
for (uint8_t i = TX_MB_INDEX; i < (TX_MB_INDEX + TX_MAILBOX_NUM); i++)
{
flexcan_set_tx_mb_config(handle, i, true);
}
sdrv_gpio_set_pin_output_level(GPIO_Y1, 0); //E2дʹ<D0B4><CAB9>
External_wdt_refresh();
board_norflash_init();//flash <20><>ʼ<EFBFBD><CABC>
initSpi();
// ETH<54><48>ʼ<EFBFBD><CABC>
board_eth_init();
// wdt_init(WDT_OUTms);
// wrbyte_24c02(0x00,1);
UDP_Echo_Init(UDPCB_1, udp_Callback_1, DOWNLOAR_PORT);
ethernetInterfaceInit();
g_systemDataRecord.canBootloaderUpgrade = rdbyte_24c02(0x00);
des_ipaddr[0] = rdbyte_24c02(BOOT_DES_IP);//<2F><>ȡ<EFBFBD><C8A1><EFBFBD>ص<EFBFBD>IP
des_ipaddr[1] = rdbyte_24c02(BOOT_DES_IP+1);//<2F><>ȡ<EFBFBD><C8A1><EFBFBD>ص<EFBFBD>IP
des_ipaddr[2] = rdbyte_24c02(BOOT_DES_IP+2);//<2F><>ȡ<EFBFBD><C8A1><EFBFBD>ص<EFBFBD>IP
des_ipaddr[3] = rdbyte_24c02(BOOT_DES_IP+3);//<2F><>ȡ<EFBFBD><C8A1><EFBFBD>ص<EFBFBD>IP
if(g_systemDataRecord.canBootloaderUpgrade == NORMAL_ON)//0<><30><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD>APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD>BOOT<4F><54><EFBFBD><EFBFBD>
{
goToApp();
}
else
{
CAN_Send_Msg(handle,OTA_CANTxID, FLEXCAN_STANDARD_FRAME, FLEXCAN_FrameTypeData, BOOT_Arr,2, TX_MB_INDEX);//boot ֡
UdpSendToData(UDPCB_1, BOOT_Arr, 2, des_ipaddr, BOOT_TX_PORT);
}
ssdk_printf(SSDK_INFO, "SSDK E3 boot! verison V1.22 \r\n");
for(;;)
{
lwip_Ethernet();
if(1 == Btm1ms)
{
ReadUpgradeFlag(); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
Btm1ms = 0;
}
if(1 == Btm10ms)//10ms<6D><73>
{
Btm10ms = 0;
// if (busoff_occur_flag == true) //busoff
// {
// flexcan_busoff_recovery_demo(handle);
// busoff_occur_flag = false;
// }
RgWDT500msflg ++ ;
if(RgWDT500msflg >= 5)
{
RgWDT500msflg = 0;
External_wdt_refresh();
printf("RUN11! \r\n");
}
}
}
}