289 lines
7.8 KiB
C
289 lines
7.8 KiB
C
#include <armv7-r/barriers.h>
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#include <armv7-r/cache.h>
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#include <clock_cfg.h>
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#include <clock_ip.h>
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#include <debug.h>
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#include <param.h>
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#include <part.h>
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#include <pinmux_cfg.h>
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#include <regs_base.h>
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#include <remap/remap.h>
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#include <reset_cfg.h>
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#include <reset_ip.h>
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#include <scr_hw.h>
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#include <sdrv_ckgen.h>
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#include <sdrv_rstgen.h>
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#include <sdrv_scr.h>
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#include <sdrv_spi_nor.h>
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#include <sdrv_xspi.h>
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#include <stdlib.h>
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#include <string.h>
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#include <types.h>
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#include <udelay/udelay.h>
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#include <sd_boot_img/sd_boot_img.h>
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#include "board.h"
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#include "irq_num.h"
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#include <flexcan_cfg.h>
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#include "IAP_Task.h"
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#include "btm_init.h"
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#include "flexcan_init.h"
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#include "irq.h"
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#include <sdrv_gpio.h>
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#include <wdt_refresh.h>
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#include "eth_cfg.h"
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#include "sdrv_eth.h"
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#include "interface_ethernet.h"
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extern sdrv_scr_t g_scr_ctrl;
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uint32_t udp_length = 0;
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#define RFD_ENABLE 0
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static struct spi_nor_host spi_nor_host = {0};
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static struct xspi_pdata xspi = {0};
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struct spi_nor flash = {0};
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struct flash_info *flash_info;
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flexcan_handle_t g_flexcan_handle;
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static struct xspi_config host_config = {
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.id = 0,
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.apb_base = APB_XSPI1PORTA_BASE,
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.direct_base = XSPI1_XSPI1PORTA_BASE,
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};
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static struct spi_nor_config config = {
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.id = 0,
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.cs = 0,
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.baudrate = 20000000,
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.xfer_mode = SPI_NOR_XFER_POLLING_MODE,
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.dev_mode = SPI_NOR_DEV_SINGLE_MODE,
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.sw_rst = false, /* config soft reset spi norflash */
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.async_mode = false,
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#ifdef CONFIG_HYPERBUS_MODE
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.hyperbus_mode = CONFIG_HYPERBUS_MODE,
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#else
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.hyperbus_mode = false,
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#endif
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};
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void xspi_lockstep_enable(bool flag)
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{
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#if ((CONFIG_E3210) || (CONFIG_E3110))
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scr_signal_t signal = SCR_SF_XSPI1_SRC_CFG_LOCKSTEP_MODE_N;
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#else
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scr_signal_t signal = SCR_SF_XSPI1_LOCKSTEP_DISABLE;
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#endif
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sdrv_rstgen_assert(&rstsig_xspi1b);
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sdrv_rstgen_assert(&rstsig_xspi1a);
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udelay(10u);
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scr_set(&g_scr_ctrl, &signal, !flag);
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udelay(10u);
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sdrv_rstgen_deassert(&rstsig_xspi1a);
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sdrv_rstgen_deassert(&rstsig_xspi1b);
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}
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void xspi_parallel_enable(bool flag)
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{
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scr_signal_t signal = SCR_SF_XSPI1_SRC_CFG_PARALLEL_MODE;
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sdrv_rstgen_assert(&rstsig_xspi1b);
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sdrv_rstgen_assert(&rstsig_xspi1a);
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udelay(10u);
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scr_set(&g_scr_ctrl, &signal, flag);
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udelay(10u);
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sdrv_rstgen_deassert(&rstsig_xspi1a);
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sdrv_rstgen_deassert(&rstsig_xspi1b);
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}
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void board_norflash_init(void)
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{
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bool locksetp_mode = false;
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bool parallel_mode = false;
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/* get xspi1a clk node */
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sdrv_ckgen_node_t *clk = CLK_NODE(g_ckgen_ip_xspi1a);
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/* config dev spi nor dev single mode */
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switch (config.dev_mode) {
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case SPI_NOR_DEV_LOCKSTEP_MODE:
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locksetp_mode = true;
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break;
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case SPI_NOR_DEV_PARALLEL_MODE:
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parallel_mode = true;
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break;
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default:
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break;
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}
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/* close locksetp/parallel mode */
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xspi_lockstep_enable(locksetp_mode);
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xspi_parallel_enable(parallel_mode);
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/* initializes xspi host */
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host_config.ref_clk = sdrv_ckgen_get_rate(clk);
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sdrv_xspi_host_init(&spi_nor_host, &xspi, &host_config);
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spi_nor_host.clk = clk;
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sdrv_ckgen_set_rate(clk, config.baudrate);
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ssdk_printf(SSDK_CRIT, "xspi clock rate is %u!\r\n",
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sdrv_ckgen_get_rate(clk));
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/* initializes spi nor device */
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if (sdrv_spi_nor_init(&flash, &spi_nor_host, &config)) {
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ssdk_printf(SSDK_CRIT, "spinor init failed!\r\n");
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return;
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}
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/* get flash info data information */
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flash_info = sdrv_spi_nor_get_info(&flash);
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ssdk_printf(SSDK_CRIT,
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"spinor flash size = 0x%llx, sector_size = 0x%x \r\n",
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flash_info->size, flash_info->sector_size);
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#if RFD_ENABLE
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/* enable rfd */
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uint8_t rfd_mask = 0;
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if(!check_rfd(host_config.direct_base, &rfd_mask) && rfd_mask) {
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sdrv_spi_nor_enable_rfd(&flash, rfd_mask);
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}
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#endif
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return;
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}
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uint8_t mainCnt = 0;
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//uint8_t mainCntarr[8] = {0x56,0x88,0x98,0x79,0x23};
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//uint8_t mainCntarrRx[8] = {0,0,0,0,0};
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//uint32_t timeus = 0;
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int main(void)
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{
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uint8_t BOOT_Arr[2] = {0x00,0x01};
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static uint8_t RgWDT500msflg = 0;
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//---------------------------------------------------------------
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/* reset module */
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board_reset_init();
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/* initializes clock source */
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sdrv_ckgen_init(&g_clock_config);
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/*VIC<49><43>ʼ<EFBFBD><CABC>*/
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irq_initialize(VIC1_BASE, IRQ_MAX_INTR_NUM);
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/* config spinor pinmux */
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sdrv_pinctrl_init(NUM_OF_CONFIGURED_PINS, g_pin_init_config);
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sdrv_gpio_set_pin_output_level(GPIO_B9, 1); //<2F><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
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External_wdt_refresh();
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// Timer<65><72>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ṩLWIP sys_now<6F>ӿڻ<D3BF>ȡ<EFBFBD><C8A1>ǰʱ<C7B0><CAB1>
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btm_init();
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/* board debug console uart init */
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board_debug_console_init();
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sdrv_gpio_set_pin_output_level(GPIO_H12, 0); //CANʹ<4E><CAB9>
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/* initialize the FlexCAN handle. */
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flexcan_handle_t *handle = &g_flexcan_handle;
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flexcan_create_handle(handle, FLEXCAN6, (void *)APB_CANFD6_BASE,
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CANFD6_CANFD_INTR_NUM, flexcan_transfer_callback,
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NULL);
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/* initialize flexCAN. */
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flexcan_init(handle, &g_flexcan_config);
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/* unfreeze the flexCAN by demo. */
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flexcan_freeze(handle, false);
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/* enable busoff interrupt. */
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flexcan_enable_interrupts(handle, FLEXCAN_BusOffInterruptEnable);//
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/* enable irq. */
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irq_attach(handle->irq_num, flexcan_irq_handler, handle);
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irq_enable(handle->irq_num);
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/* assign fifo only for rx. */
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flexcan_config_rx_fifo(handle, &flexcan_fifo_cfg);
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/* assign mailbox14-20 for tx. */
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for (uint8_t i = TX_MB_INDEX; i < (TX_MB_INDEX + TX_MAILBOX_NUM); i++)
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{
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flexcan_set_tx_mb_config(handle, i, true);
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}
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sdrv_gpio_set_pin_output_level(GPIO_Y1, 0); //E2дʹ<D0B4><CAB9>
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External_wdt_refresh();
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board_norflash_init();//flash <20><>ʼ<EFBFBD><CABC>
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initSpi();
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// ETH<54><48>ʼ<EFBFBD><CABC>
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board_eth_init();
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// wdt_init(WDT_OUTms);
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// wrbyte_24c02(0x00,1);
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UDP_Echo_Init(UDPCB_1, udp_Callback_1, DOWNLOAR_PORT);
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ethernetInterfaceInit();
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g_systemDataRecord.canBootloaderUpgrade = rdbyte_24c02(0x00);
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des_ipaddr[0] = rdbyte_24c02(BOOT_DES_IP);//<2F><>ȡ<EFBFBD><C8A1><EFBFBD>ص<EFBFBD>IP
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des_ipaddr[1] = rdbyte_24c02(BOOT_DES_IP+1);//<2F><>ȡ<EFBFBD><C8A1><EFBFBD>ص<EFBFBD>IP
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des_ipaddr[2] = rdbyte_24c02(BOOT_DES_IP+2);//<2F><>ȡ<EFBFBD><C8A1><EFBFBD>ص<EFBFBD>IP
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des_ipaddr[3] = rdbyte_24c02(BOOT_DES_IP+3);//<2F><>ȡ<EFBFBD><C8A1><EFBFBD>ص<EFBFBD>IP
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if(g_systemDataRecord.canBootloaderUpgrade == NORMAL_ON)//0<><30><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD>APP<50><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD>BOOT<4F><54><EFBFBD><EFBFBD>
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{
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goToApp();
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}
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else
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{
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CAN_Send_Msg(handle,OTA_CANTxID, FLEXCAN_STANDARD_FRAME, FLEXCAN_FrameTypeData, BOOT_Arr,2, TX_MB_INDEX);//boot ֡
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UdpSendToData(UDPCB_1, BOOT_Arr, 2, des_ipaddr, BOOT_TX_PORT);
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}
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ssdk_printf(SSDK_INFO, "SSDK E3 boot! verison V1.22 \r\n");
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for(;;)
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{
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lwip_Ethernet();
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if(1 == Btm1ms)
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{
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ReadUpgradeFlag(); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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Btm1ms = 0;
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}
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if(1 == Btm10ms)//10ms<6D><73>
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{
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Btm10ms = 0;
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// if (busoff_occur_flag == true) //busoff
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// {
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// flexcan_busoff_recovery_demo(handle);
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// busoff_occur_flag = false;
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// }
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RgWDT500msflg ++ ;
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if(RgWDT500msflg >= 5)
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{
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RgWDT500msflg = 0;
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External_wdt_refresh();
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printf("RUN11! \r\n");
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}
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}
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}
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}
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