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<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_ee023d43c33bfccc31aa50a48a76892b.html">include</a></li> </ul>
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<a href="sdrv__rstgen_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno"> 1</span> </div>
<div class="line"><a id="l00008" name="l00008"></a><span class="lineno"> 8</span><span class="preprocessor">#ifndef SDRV_RSTGEN_H_</span></div>
<div class="line"><a id="l00009" name="l00009"></a><span class="lineno"> 9</span><span class="preprocessor">#define SDRV_RSTGEN_H_</span></div>
<div class="line"><a id="l00010" name="l00010"></a><span class="lineno"> 10</span> </div>
<div class="line"><a id="l00011" name="l00011"></a><span class="lineno"> 11</span><span class="preprocessor">#include &lt;types.h&gt;</span></div>
<div class="line"><a id="l00012" name="l00012"></a><span class="lineno"> 12</span><span class="preprocessor">#include &lt;<a class="code" href="sdrv__common_8h.html">sdrv_common.h</a>&gt;</span></div>
<div class="line"><a id="l00013" name="l00013"></a><span class="lineno"> 13</span> </div>
<div class="line"><a id="l00014" name="l00014"></a><span class="lineno"> 14</span><span class="comment">/* Define the type of rstgen */</span></div>
<div class="line"><a id="l00015" name="l00015"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a8699ca89f6c67b19a8ca21d2d9c2f75b"> 15</a></span><span class="preprocessor">#define SDRV_RSTGEN_CORE 1</span></div>
<div class="line"><a id="l00016" name="l00016"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a875382884d3d311f9d29eca8669850cf"> 16</a></span><span class="preprocessor">#define SDRV_RSTGEN_LATENT 2</span></div>
<div class="line"><a id="l00017" name="l00017"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a941370b99bca07a9da90d27b3141bfe5"> 17</a></span><span class="preprocessor">#define SDRV_RSTGEN_MISSION 3</span></div>
<div class="line"><a id="l00018" name="l00018"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#af04d09fea7c19e3e59655f9fb0b79566"> 18</a></span><span class="preprocessor">#define SDRV_RSTGEN_MODULE 4</span></div>
<div class="line"><a id="l00019" name="l00019"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a1a200b16b0a6f9a83c1467b5e72b5ff9"> 19</a></span><span class="preprocessor">#define SDRV_RSTGEN_IST 5</span></div>
<div class="line"><a id="l00020" name="l00020"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a57bfcf0c368182438491dd42b8359c81"> 20</a></span><span class="preprocessor">#define SDRV_RSTGEN_DEBUG 6</span></div>
<div class="line"><a id="l00021" name="l00021"></a><span class="lineno"> 21</span> </div>
<div class="line"><a id="l00022" name="l00022"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a82cffc586c07ab9c6ff5722686883f28"> 22</a></span><span class="preprocessor">#define SDRV_RSTGEN_TYPE_SHIFT 24</span></div>
<div class="line"><a id="l00023" name="l00023"></a><span class="lineno"> 23</span> </div>
<div class="line"><a id="l00024" name="l00024"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a2700172ef9af08e3bd542075e5bccc6e"> 24</a></span><span class="preprocessor">#define SDRV_RSTGEN_SIG_ID(type, idx) \</span></div>
<div class="line"><a id="l00025" name="l00025"></a><span class="lineno"> 25</span><span class="preprocessor"> ((uint32_t)((((uint32_t)(type)) &lt;&lt; ((uint32_t)SDRV_RSTGEN_TYPE_SHIFT)) | ((uint32_t)(idx))))</span></div>
<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"> 26</span> </div>
<div class="line"><a id="l00027" name="l00027"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#ac3673063c1af75c7ad4b21a5f04b2647"> 27</a></span><span class="preprocessor">#define SDRV_RSTGEN_TYPE(id) ((uint32_t)(((uint32_t)(id)) &gt;&gt; ((uint32_t)SDRV_RSTGEN_TYPE_SHIFT)))</span></div>
<div class="line"><a id="l00028" name="l00028"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#ae6d9d8fbcc0f0b4077fc784f29a8d4bb"> 28</a></span><span class="preprocessor">#define SDRV_RSTGEN_INDEX(id) ((uint32_t)(((uint32_t)(id)) &amp; BIT_MASK(SDRV_RSTGEN_TYPE_SHIFT)))</span></div>
<div class="line"><a id="l00029" name="l00029"></a><span class="lineno"> 29</span> </div>
<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a3202225cb77b8c78c13499a12e7a2e5c"> 30</a></span><span class="preprocessor">#define SDRV_RSTGEN_GENERAL_REG_NUM 8</span></div>
<div class="line"><a id="l00031" name="l00031"></a><span class="lineno"> 31</span> </div>
<div class="line"><a id="l00035" name="l00035"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8d"> 35</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8d">sdrv_reset_error</a></div>
<div class="line"><a id="l00036" name="l00036"></a><span class="lineno"> 36</span>{</div>
<div class="line"><a id="l00037" name="l00037"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8dad1b57de90df5b6f0a24c99a2251fb6a5"> 37</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8dad1b57de90df5b6f0a24c99a2251fb6a5">SDRV_RESET_STATUS_SIGNAL_ASSERT</a> = <a class="code hl_define" href="sdrv__common_8h.html#aef8aef2653fac9cb1b5fbe2a5976314c">SDRV_ERROR_STATUS</a>(<a class="code hl_enumvalue" href="sdrv__common_8h.html#a19e0f226537905b9e022007ff40c57c6afad92cda127221f8ec802df09f536c3f">SDRV_STATUS_GROUP_RESET</a>, 1), <span class="comment">/* RESET singal assert. */</span></div>
<div class="line"><a id="l00038" name="l00038"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8dac6a6e5ddd79dd814b49646d021ab3d83"> 38</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8dac6a6e5ddd79dd814b49646d021ab3d83">SDRV_RESET_STATUS_LOCK</a> = <a class="code hl_define" href="sdrv__common_8h.html#aef8aef2653fac9cb1b5fbe2a5976314c">SDRV_ERROR_STATUS</a>(<a class="code hl_enumvalue" href="sdrv__common_8h.html#a19e0f226537905b9e022007ff40c57c6afad92cda127221f8ec802df09f536c3f">SDRV_STATUS_GROUP_RESET</a>, 2), <span class="comment">/* RESET lock error. */</span></div>
<div class="line"><a id="l00039" name="l00039"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8da47eaf13d223bf25cc064e593aaedf1a9"> 39</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8da47eaf13d223bf25cc064e593aaedf1a9">SDRV_RESET_STATUS_TIMEOUT</a> = <a class="code hl_define" href="sdrv__common_8h.html#aef8aef2653fac9cb1b5fbe2a5976314c">SDRV_ERROR_STATUS</a>(<a class="code hl_enumvalue" href="sdrv__common_8h.html#a19e0f226537905b9e022007ff40c57c6afad92cda127221f8ec802df09f536c3f">SDRV_STATUS_GROUP_RESET</a>, 3), <span class="comment">/* RESET timeout error. */</span></div>
<div class="line"><a id="l00040" name="l00040"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8da31f84ee6f527370a15698b1a101b054a"> 40</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8da31f84ee6f527370a15698b1a101b054a">SDRV_RESET_STATUS_WRONG_SIGNAL</a> = <a class="code hl_define" href="sdrv__common_8h.html#aef8aef2653fac9cb1b5fbe2a5976314c">SDRV_ERROR_STATUS</a>(<a class="code hl_enumvalue" href="sdrv__common_8h.html#a19e0f226537905b9e022007ff40c57c6afad92cda127221f8ec802df09f536c3f">SDRV_STATUS_GROUP_RESET</a>, 4), <span class="comment">/* RESET wrong signal. */</span></div>
<div class="line"><a id="l00041" name="l00041"></a><span class="lineno"> 41</span>};</div>
<div class="line"><a id="l00042" name="l00042"></a><span class="lineno"> 42</span> </div>
<div class="line"><a id="l00043" name="l00043"></a><span class="lineno"> 43</span><span class="comment">/* Define lowpower mode */</span></div>
<div class="line"><a id="l00044" name="l00044"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874c"> 44</a></span><span class="keyword">enum</span> <a class="code hl_enumeration" href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874c">reset_lowpower_mode</a> {</div>
<div class="line"><a id="l00045" name="l00045"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874caee6743bff37e3cf2575abfb45ed46979"> 45</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874caee6743bff37e3cf2575abfb45ed46979">RESET_LP_HIB</a> = 0,</div>
<div class="line"><a id="l00046" name="l00046"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874ca55f22e14d5b74467fb22464287185cc3"> 46</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874ca55f22e14d5b74467fb22464287185cc3">RESET_LP_SLEEP</a> = 1,</div>
<div class="line"><a id="l00047" name="l00047"></a><span class="lineno"> 47</span>};</div>
<div class="line"><a id="l00048" name="l00048"></a><span class="lineno"> 48</span> </div>
<div class="line"><a id="l00049" name="l00049"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4"> 49</a></span><span class="keyword">typedef</span> <span class="keyword">enum</span> <a class="code hl_enumeration" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4">reset_wdt_id</a> {</div>
<div class="line"><a id="l00050" name="l00050"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4af85f5ea2a79400704796fcf14a74e4e2"> 50</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4af85f5ea2a79400704796fcf14a74e4e2">RESET_WDT1</a>, <span class="comment">/* Trigger global reset or SF core reset */</span></div>
<div class="line"><a id="l00051" name="l00051"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4ab77c8d24a1cae6d5f89dacf59e737874"> 51</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4ab77c8d24a1cae6d5f89dacf59e737874">RESET_WDT2</a>, <span class="comment">/* Trigger global reset or SF core reset */</span></div>
<div class="line"><a id="l00052" name="l00052"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4a6cf810cc314bc89d88eefcc864d9e66e"> 52</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4a6cf810cc314bc89d88eefcc864d9e66e">RESET_WDT3</a>, <span class="comment">/* Trigger global reset or SP0/SP1 core reset */</span></div>
<div class="line"><a id="l00053" name="l00053"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4a5f97dc4aaff0c408ed468d4c0bce8758"> 53</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4a5f97dc4aaff0c408ed468d4c0bce8758">RESET_WDT4</a>, <span class="comment">/* Trigger global reset or SP0/SP1 core reset */</span></div>
<div class="line"><a id="l00054" name="l00054"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4aba07ff62f906c3b381cadfa40feaf3a0"> 54</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4aba07ff62f906c3b381cadfa40feaf3a0">RESET_WDT5</a>, <span class="comment">/* Trigger global reset or SX0/SX1 core reset */</span></div>
<div class="line"><a id="l00055" name="l00055"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4a14ad451c2dac6f555dd93ca4bf72b638"> 55</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4a14ad451c2dac6f555dd93ca4bf72b638">RESET_WDT6</a>, <span class="comment">/* Trigger global reset or SX0/SX1 core reset */</span></div>
<div class="line"><a id="l00056" name="l00056"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a5a6258409dc5b32f5ea190ef6ff1c017"> 56</a></span>} <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a5a6258409dc5b32f5ea190ef6ff1c017">reset_wdt_id_e</a>;</div>
<div class="line"><a id="l00057" name="l00057"></a><span class="lineno"> 57</span> </div>
<div class="line"><a id="l00058" name="l00058"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6"> 58</a></span><span class="keyword">typedef</span> <span class="keyword">enum</span> <a class="code hl_enumeration" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6">reset_core_id</a> {</div>
<div class="line"><a id="l00059" name="l00059"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6a5daca59ed51f1e2889d65586a364cf9b"> 59</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6a5daca59ed51f1e2889d65586a364cf9b">RESET_CORE_SF</a> = 1,</div>
<div class="line"><a id="l00060" name="l00060"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6ad406e35953141f83ad359e3b73c0195c"> 60</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6ad406e35953141f83ad359e3b73c0195c">RESET_CORE_SP0</a>,</div>
<div class="line"><a id="l00061" name="l00061"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6a1f4a157eafa37a4aca8805d28e85bcbe"> 61</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6a1f4a157eafa37a4aca8805d28e85bcbe">RESET_CORE_SP1</a>,</div>
<div class="line"><a id="l00062" name="l00062"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6ac4f70f8d2f0723899a4cef2f42531a35"> 62</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6ac4f70f8d2f0723899a4cef2f42531a35">RESET_CORE_SX0</a>,</div>
<div class="line"><a id="l00063" name="l00063"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6ae0a3422be08c341afe381a47dc4e9230"> 63</a></span> <a class="code hl_enumvalue" href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6ae0a3422be08c341afe381a47dc4e9230">RESET_CORE_SX1</a>,</div>
<div class="line"><a id="l00064" name="l00064"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a8dffb7fec18fcbb349994c9de703141a"> 64</a></span>} <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a8dffb7fec18fcbb349994c9de703141a">reset_core_id_e</a>;</div>
<div class="line"><a id="l00065" name="l00065"></a><span class="lineno"> 65</span> </div>
<div class="line"><a id="l00072" name="l00072"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a81742b8488efdd1527d7b6e4c9fb16ed"> 72</a></span><span class="keyword">typedef</span> void (*<a class="code hl_typedef" href="sdrv__rstgen_8h.html#a81742b8488efdd1527d7b6e4c9fb16ed">sdrv_rstgen_sig_handler</a>)(uint32_t rstgen_sig_id);</div>
<div class="line"><a id="l00073" name="l00073"></a><span class="lineno"> 73</span> </div>
<div class="line"><a id="l00077" name="l00077"></a><span class="lineno"><a class="line" href="structsdrv__rstgen.html"> 77</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code hl_struct" href="structsdrv__rstgen.html">sdrv_rstgen</a> {</div>
<div class="line"><a id="l00078" name="l00078"></a><span class="lineno"><a class="line" href="structsdrv__rstgen.html#abc81edd3d3caf9e6c2e0762881da6016"> 78</a></span> paddr_t <a class="code hl_variable" href="structsdrv__rstgen.html#abc81edd3d3caf9e6c2e0762881da6016">base</a>;</div>
<div class="line"><a id="l00079" name="l00079"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a7ee8f465807f25ace997be437181cf5d"> 79</a></span>} <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a7ee8f465807f25ace997be437181cf5d">sdrv_rstgen_t</a>;</div>
<div class="line"><a id="l00080" name="l00080"></a><span class="lineno"> 80</span> </div>
<div class="line"><a id="l00084" name="l00084"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__sig.html"> 84</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code hl_struct" href="structsdrv__rstgen__sig.html">sdrv_rstgen_sig</a> {</div>
<div class="line"><a id="l00085" name="l00085"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__sig.html#a80c53b8ccf61e87b40bd80606bb1716e"> 85</a></span> <a class="code hl_struct" href="structsdrv__rstgen.html">sdrv_rstgen_t</a> *<a class="code hl_variable" href="structsdrv__rstgen__sig.html#a80c53b8ccf61e87b40bd80606bb1716e">rst_ctl</a>;</div>
<div class="line"><a id="l00086" name="l00086"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__sig.html#abaabdc509cdaba7df9f56c6c76f3ae19"> 86</a></span> uint32_t <a class="code hl_variable" href="structsdrv__rstgen__sig.html#abaabdc509cdaba7df9f56c6c76f3ae19">id</a>;</div>
<div class="line"><a id="l00087" name="l00087"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__sig.html#ae6a399ac2cbee4605bdc8fb43b22b861"> 87</a></span> <span class="keywordtype">bool</span> <a class="code hl_variable" href="structsdrv__rstgen__sig.html#ae6a399ac2cbee4605bdc8fb43b22b861">need_clr_rst</a>;</div>
<div class="line"><a id="l00088" name="l00088"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__sig.html#aee73b976b871d1326ddf6debc401098b"> 88</a></span> <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a81742b8488efdd1527d7b6e4c9fb16ed">sdrv_rstgen_sig_handler</a> <a class="code hl_variable" href="structsdrv__rstgen__sig.html#aee73b976b871d1326ddf6debc401098b">pre_handler</a>;</div>
<div class="line"><a id="l00089" name="l00089"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__sig.html#afaf7637cf56dd511a2781deac43ab0ab"> 89</a></span> <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a81742b8488efdd1527d7b6e4c9fb16ed">sdrv_rstgen_sig_handler</a> <a class="code hl_variable" href="structsdrv__rstgen__sig.html#afaf7637cf56dd511a2781deac43ab0ab">post_handler</a>;</div>
<div class="line"><a id="l00090" name="l00090"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125"> 90</a></span>} <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a>;</div>
<div class="line"><a id="l00091" name="l00091"></a><span class="lineno"> 91</span> </div>
<div class="line"><a id="l00095" name="l00095"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__general__reg.html"> 95</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code hl_struct" href="structsdrv__rstgen__general__reg.html">sdrv_rstgen_general_reg</a> {</div>
<div class="line"><a id="l00096" name="l00096"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__general__reg.html#a80c53b8ccf61e87b40bd80606bb1716e"> 96</a></span> <a class="code hl_struct" href="structsdrv__rstgen.html">sdrv_rstgen_t</a> *<a class="code hl_variable" href="structsdrv__rstgen__general__reg.html#a80c53b8ccf61e87b40bd80606bb1716e">rst_ctl</a>;</div>
<div class="line"><a id="l00097" name="l00097"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__general__reg.html#abaabdc509cdaba7df9f56c6c76f3ae19"> 97</a></span> uint32_t <a class="code hl_variable" href="structsdrv__rstgen__general__reg.html#abaabdc509cdaba7df9f56c6c76f3ae19">id</a>; <span class="comment">/* id 1 ~ 7 */</span></div>
<div class="line"><a id="l00098" name="l00098"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a92e5731422c69ec1c5fff5495238eab5"> 98</a></span>} <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a92e5731422c69ec1c5fff5495238eab5">sdrv_rstgen_general_reg_t</a>;</div>
<div class="line"><a id="l00099" name="l00099"></a><span class="lineno"> 99</span> </div>
<div class="line"><a id="l00103" name="l00103"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__glb__ctl.html"> 103</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code hl_struct" href="structsdrv__rstgen__glb__ctl.html">sdrv_rstgen_glb_ctl</a> {</div>
<div class="line"><a id="l00104" name="l00104"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__glb__ctl.html#adb46f9d091752da9db94d92bb42e9eaf"> 104</a></span> <a class="code hl_struct" href="structsdrv__rstgen.html">sdrv_rstgen_t</a> *<a class="code hl_variable" href="structsdrv__rstgen__glb__ctl.html#adb46f9d091752da9db94d92bb42e9eaf">rst_sf_ctl</a>;</div>
<div class="line"><a id="l00105" name="l00105"></a><span class="lineno"><a class="line" href="structsdrv__rstgen__glb__ctl.html#a468ffd6eefb7ffd443db42e961df76bc"> 105</a></span> <a class="code hl_struct" href="structsdrv__rstgen.html">sdrv_rstgen_t</a> *<a class="code hl_variable" href="structsdrv__rstgen__glb__ctl.html#a468ffd6eefb7ffd443db42e961df76bc">rst_ap_ctl</a>;</div>
<div class="line"><a id="l00106" name="l00106"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd"> 106</a></span>} <a class="code hl_typedef" href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd">sdrv_rstgen_glb_t</a>;</div>
<div class="line"><a id="l00107" name="l00107"></a><span class="lineno"> 107</span> </div>
<div class="line"><a id="l00111" name="l00111"></a><span class="lineno"><a class="line" href="structsdrv__recovery__btm.html"> 111</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code hl_struct" href="structsdrv__recovery__btm.html">sdrv_recovery_btm</a> {</div>
<div class="line"><a id="l00112" name="l00112"></a><span class="lineno"><a class="line" href="structsdrv__recovery__btm.html#a799f1dc40bcd084335b1f93a4872c44e"> 112</a></span> uint32_t <a class="code hl_variable" href="structsdrv__recovery__btm.html#a799f1dc40bcd084335b1f93a4872c44e">btm_num</a>; <span class="comment">/* btm numbers */</span></div>
<div class="line"><a id="l00113" name="l00113"></a><span class="lineno"><a class="line" href="structsdrv__recovery__btm.html#aefbbaecf6e01357b62ecda16aed4bd33"> 113</a></span> uint32_t <a class="code hl_variable" href="structsdrv__recovery__btm.html#aefbbaecf6e01357b62ecda16aed4bd33">btm_base</a>[]; <span class="comment">/* btm base list */</span></div>
<div class="line"><a id="l00114" name="l00114"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a42d0646052af858609125621e12e73df"> 114</a></span>} <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a42d0646052af858609125621e12e73df">sdrv_recovery_btm_t</a>;</div>
<div class="line"><a id="l00115" name="l00115"></a><span class="lineno"> 115</span> </div>
<div class="line"><a id="l00116" name="l00116"></a><span class="lineno"><a class="line" href="structsdrv__recovery__etimer.html"> 116</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code hl_struct" href="structsdrv__recovery__etimer.html">sdrv_recovery_etimer</a> {</div>
<div class="line"><a id="l00117" name="l00117"></a><span class="lineno"><a class="line" href="structsdrv__recovery__etimer.html#a21a326c6793c2925919dabaedcc2b9a1"> 117</a></span> uint32_t <a class="code hl_variable" href="structsdrv__recovery__etimer.html#a21a326c6793c2925919dabaedcc2b9a1">etimer_num</a>; <span class="comment">/* etimer numbers */</span></div>
<div class="line"><a id="l00118" name="l00118"></a><span class="lineno"><a class="line" href="structsdrv__recovery__etimer.html#aee26abb9faea71679af99ee766426772"> 118</a></span> uint32_t <a class="code hl_variable" href="structsdrv__recovery__etimer.html#aee26abb9faea71679af99ee766426772">etimer_base</a>[]; <span class="comment">/* etimer base list */</span></div>
<div class="line"><a id="l00119" name="l00119"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a1c688c1260c4ac042088825c62e283f6"> 119</a></span>} <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a1c688c1260c4ac042088825c62e283f6">sdrv_recovery_etimer_t</a>;</div>
<div class="line"><a id="l00120" name="l00120"></a><span class="lineno"> 120</span> </div>
<div class="line"><a id="l00121" name="l00121"></a><span class="lineno"><a class="line" href="structsdrv__recovery__epwm.html"> 121</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code hl_struct" href="structsdrv__recovery__epwm.html">sdrv_recovery_epwm</a> {</div>
<div class="line"><a id="l00122" name="l00122"></a><span class="lineno"><a class="line" href="structsdrv__recovery__epwm.html#a3c9d4192a0a30db0237f259df93df9f3"> 122</a></span> uint32_t <a class="code hl_variable" href="structsdrv__recovery__epwm.html#a3c9d4192a0a30db0237f259df93df9f3">epwm_num</a>; <span class="comment">/* epwm numbers */</span></div>
<div class="line"><a id="l00123" name="l00123"></a><span class="lineno"><a class="line" href="structsdrv__recovery__epwm.html#ad8345f012943d2453119e405456d3a4c"> 123</a></span> uint32_t <a class="code hl_variable" href="structsdrv__recovery__epwm.html#ad8345f012943d2453119e405456d3a4c">epwm_base</a>[]; <span class="comment">/* epwm base list */</span></div>
<div class="line"><a id="l00124" name="l00124"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a21f8bc5eeca047f8cfc64737db5f6233"> 124</a></span>} <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a21f8bc5eeca047f8cfc64737db5f6233">sdrv_recovery_epwm_t</a>;</div>
<div class="line"><a id="l00125" name="l00125"></a><span class="lineno"> 125</span> </div>
<div class="line"><a id="l00126" name="l00126"></a><span class="lineno"> 126</span><span class="comment">/* semidrive recovery latent module */</span></div>
<div class="line"><a id="l00127" name="l00127"></a><span class="lineno"><a class="line" href="structsdrv__recovery__module.html"> 127</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span><a class="code hl_struct" href="structsdrv__recovery__module.html">sdrv_recovery_module</a> {</div>
<div class="line"><a id="l00128" name="l00128"></a><span class="lineno"><a class="line" href="structsdrv__recovery__module.html#a910a3e21a29a251914a77d3519f09d0a"> 128</a></span> <a class="code hl_struct" href="structsdrv__recovery__btm.html">sdrv_recovery_btm_t</a> <span class="keyword">const</span> *<a class="code hl_variable" href="structsdrv__recovery__module.html#a910a3e21a29a251914a77d3519f09d0a">btm_list</a>;</div>
<div class="line"><a id="l00129" name="l00129"></a><span class="lineno"><a class="line" href="structsdrv__recovery__module.html#ad55ef5d08c8638a2234c9d87cd783467"> 129</a></span> <a class="code hl_struct" href="structsdrv__recovery__etimer.html">sdrv_recovery_etimer_t</a> <span class="keyword">const</span> *<a class="code hl_variable" href="structsdrv__recovery__module.html#ad55ef5d08c8638a2234c9d87cd783467">etimer_list</a>;</div>
<div class="line"><a id="l00130" name="l00130"></a><span class="lineno"><a class="line" href="structsdrv__recovery__module.html#ac591c604176ef8614c0c887c14f6a635"> 130</a></span> <a class="code hl_struct" href="structsdrv__recovery__epwm.html">sdrv_recovery_epwm_t</a> <span class="keyword">const</span> *<a class="code hl_variable" href="structsdrv__recovery__module.html#ac591c604176ef8614c0c887c14f6a635">epwm_list</a>;</div>
<div class="line"><a id="l00131" name="l00131"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a5b0ade04f5bda906381772e55b4b97ac"> 131</a></span>} <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a5b0ade04f5bda906381772e55b4b97ac">sdrv_recovery_module_t</a>;</div>
<div class="line"><a id="l00132" name="l00132"></a><span class="lineno"> 132</span> </div>
<div class="line"><a id="l00141" name="l00141"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a90eb1f94509a65eec0ef47e9cab365dc"> 141</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#a90eb1f94509a65eec0ef47e9cab365dc">sdrv_rstgen_assert</a>(<a class="code hl_struct" href="structsdrv__rstgen__sig.html">sdrv_rstgen_sig_t</a> *rst_sig);</div>
<div class="line"><a id="l00142" name="l00142"></a><span class="lineno"> 142</span> </div>
<div class="line"><a id="l00151" name="l00151"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#aa6189f234be2939d24c0b9e543ec6442"> 151</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#aa6189f234be2939d24c0b9e543ec6442">sdrv_rstgen_deassert</a>(<a class="code hl_struct" href="structsdrv__rstgen__sig.html">sdrv_rstgen_sig_t</a> *rst_sig);</div>
<div class="line"><a id="l00152" name="l00152"></a><span class="lineno"> 152</span> </div>
<div class="line"><a id="l00161" name="l00161"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a7b24afa273fa54f81963c02942e858d8"> 161</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#a7b24afa273fa54f81963c02942e858d8">sdrv_rstgen_reset</a>(<a class="code hl_struct" href="structsdrv__rstgen__sig.html">sdrv_rstgen_sig_t</a> *rst_sig);</div>
<div class="line"><a id="l00162" name="l00162"></a><span class="lineno"> 162</span> </div>
<div class="line"><a id="l00171" name="l00171"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a10dde50d7ec285cde7a052ee221c6713"> 171</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#a10dde50d7ec285cde7a052ee221c6713">sdrv_rstgen_global_reset</a>(<a class="code hl_struct" href="structsdrv__rstgen__glb__ctl.html">sdrv_rstgen_glb_t</a> *rst_glb_ctl);</div>
<div class="line"><a id="l00172" name="l00172"></a><span class="lineno"> 172</span> </div>
<div class="line"><a id="l00179" name="l00179"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a0726f32906766eb1b8dfb2ba3d38f1fc"> 179</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#a0726f32906766eb1b8dfb2ba3d38f1fc">sdrv_rstgen_status</a>(<a class="code hl_struct" href="structsdrv__rstgen__sig.html">sdrv_rstgen_sig_t</a> *rst_sig);</div>
<div class="line"><a id="l00180" name="l00180"></a><span class="lineno"> 180</span> </div>
<div class="line"><a id="l00227" name="l00227"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a43254dd94c3b9d923b73c189996299c2"> 227</a></span>uint32_t <a class="code hl_function" href="sdrv__rstgen_8h.html#a43254dd94c3b9d923b73c189996299c2">sdrv_rstgen_global_status</a>(<a class="code hl_struct" href="structsdrv__rstgen__glb__ctl.html">sdrv_rstgen_glb_t</a> *rst_glb_ctl);</div>
<div class="line"><a id="l00228" name="l00228"></a><span class="lineno"> 228</span> </div>
<div class="line"><a id="l00236" name="l00236"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a0432a9bac0e2a616cfe8a6100019c123"> 236</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#a0432a9bac0e2a616cfe8a6100019c123">sdrv_rstgen_global_status_clear</a>(<a class="code hl_struct" href="structsdrv__rstgen__glb__ctl.html">sdrv_rstgen_glb_t</a> *rst_glb_ctl);</div>
<div class="line"><a id="l00237" name="l00237"></a><span class="lineno"> 237</span> </div>
<div class="line"><a id="l00283" name="l00283"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a2cd8666bfe5ca507530dfb003faa1b15"> 283</a></span>uint32_t <a class="code hl_function" href="sdrv__rstgen_8h.html#a2cd8666bfe5ca507530dfb003faa1b15">sdrv_rstgen_current_global_status</a>(<a class="code hl_struct" href="structsdrv__rstgen__glb__ctl.html">sdrv_rstgen_glb_t</a> *rst_glb_ctl);</div>
<div class="line"><a id="l00284" name="l00284"></a><span class="lineno"> 284</span> </div>
<div class="line"><a id="l00293" name="l00293"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a32b88bc068653b8f08eae962b0060a40"> 293</a></span>uint32_t <a class="code hl_function" href="sdrv__rstgen_8h.html#a32b88bc068653b8f08eae962b0060a40">sdrv_rstgen_read_general</a>(<a class="code hl_struct" href="structsdrv__rstgen__general__reg.html">sdrv_rstgen_general_reg_t</a> *rst_gen_reg);</div>
<div class="line"><a id="l00294" name="l00294"></a><span class="lineno"> 294</span> </div>
<div class="line"><a id="l00303" name="l00303"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#af26011c9b69ad7af846f1b1078a6dbc0"> 303</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#af26011c9b69ad7af846f1b1078a6dbc0">sdrv_rstgen_write_general</a>(<a class="code hl_struct" href="structsdrv__rstgen__general__reg.html">sdrv_rstgen_general_reg_t</a> *rst_gen_reg,</div>
<div class="line"><a id="l00304" name="l00304"></a><span class="lineno"> 304</span> uint32_t val);</div>
<div class="line"><a id="l00305" name="l00305"></a><span class="lineno"> 305</span> </div>
<div class="line"><a id="l00316" name="l00316"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a4b3c16f1ab217cfe2a912ea001e87cd7"> 316</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#a4b3c16f1ab217cfe2a912ea001e87cd7">sdrv_rstgen_write_general_bit</a>(<a class="code hl_struct" href="structsdrv__rstgen__general__reg.html">sdrv_rstgen_general_reg_t</a> *rst_gen_reg,</div>
<div class="line"><a id="l00317" name="l00317"></a><span class="lineno"> 317</span> uint8_t start, uint8_t <a class="code hl_variable" href="logo__rgb565_8h.html#aca34d28e3d8bcbcadb8edb4e3af24f8c">width</a>, uint32_t val);</div>
<div class="line"><a id="l00318" name="l00318"></a><span class="lineno"> 318</span> </div>
<div class="line"><a id="l00328" name="l00328"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a7cbe2d46015f48d329d35575999ee34e"> 328</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#a7cbe2d46015f48d329d35575999ee34e">sdrv_rstgen_lowpower_set</a>(<a class="code hl_struct" href="structsdrv__rstgen__sig.html">sdrv_rstgen_sig_t</a> *rst_sig,</div>
<div class="line"><a id="l00329" name="l00329"></a><span class="lineno"> 329</span> <span class="keyword">enum</span> <a class="code hl_enumeration" href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874c">reset_lowpower_mode</a> mode, uint32_t val);</div>
<div class="line"><a id="l00330" name="l00330"></a><span class="lineno"> 330</span> </div>
<div class="line"><a id="l00338" name="l00338"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a9c6285cd7cc8c41956bf7f6c3970b94d"> 338</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#a9c6285cd7cc8c41956bf7f6c3970b94d">sdrv_rstgen_wdt_reset_enable</a>(<a class="code hl_typedef" href="sdrv__rstgen_8h.html#a5a6258409dc5b32f5ea190ef6ff1c017">reset_wdt_id_e</a> wdt, <span class="keywordtype">bool</span> enable);</div>
<div class="line"><a id="l00339" name="l00339"></a><span class="lineno"> 339</span> </div>
<div class="line"><a id="l00352" name="l00352"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#aeffb793b19f8ac6c847c56a35ca12933"> 352</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#aeffb793b19f8ac6c847c56a35ca12933">sdrv_rstgen_wdt_core_reset_enable</a>(<a class="code hl_typedef" href="sdrv__rstgen_8h.html#a5a6258409dc5b32f5ea190ef6ff1c017">reset_wdt_id_e</a> wdt, <a class="code hl_typedef" href="sdrv__rstgen_8h.html#a8dffb7fec18fcbb349994c9de703141a">reset_core_id_e</a> core, <span class="keywordtype">bool</span> enable);</div>
<div class="line"><a id="l00353" name="l00353"></a><span class="lineno"> 353</span> </div>
<div class="line"><a id="l00363" name="l00363"></a><span class="lineno"><a class="line" href="sdrv__rstgen_8h.html#a9e0d89b5bf32daf40a926cf71f02ea6d"> 363</a></span><a class="code hl_typedef" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> <a class="code hl_function" href="sdrv__rstgen_8h.html#a9e0d89b5bf32daf40a926cf71f02ea6d">sdrv_recovery_module</a>(<a class="code hl_struct" href="structsdrv__recovery__module.html">sdrv_recovery_module_t</a>* recovery_module);</div>
<div class="line"><a id="l00364" name="l00364"></a><span class="lineno"> 364</span> </div>
<div class="line"><a id="l00365" name="l00365"></a><span class="lineno"> 365</span><span class="preprocessor">#endif </span><span class="comment">/* SDRV_RSTGEN_RSTGEN_H_ */</span><span class="preprocessor"></span></div>
<div class="ttc" id="alogo__rgb565_8h_html_aca34d28e3d8bcbcadb8edb4e3af24f8c"><div class="ttname"><a href="logo__rgb565_8h.html#aca34d28e3d8bcbcadb8edb4e3af24f8c">width</a></div><div class="ttdeci">unsigned int width</div><div class="ttdef"><b>Definition:</b> logo_rgb565.h:32912</div></div>
<div class="ttc" id="asdrv__common_8h_html"><div class="ttname"><a href="sdrv__common_8h.html">sdrv_common.h</a></div><div class="ttdoc">SemiDrive driver common header file.</div></div>
<div class="ttc" id="asdrv__common_8h_html_a19e0f226537905b9e022007ff40c57c6afad92cda127221f8ec802df09f536c3f"><div class="ttname"><a href="sdrv__common_8h.html#a19e0f226537905b9e022007ff40c57c6afad92cda127221f8ec802df09f536c3f">SDRV_STATUS_GROUP_RESET</a></div><div class="ttdeci">@ SDRV_STATUS_GROUP_RESET</div><div class="ttdef"><b>Definition:</b> sdrv_common.h:23</div></div>
<div class="ttc" id="asdrv__common_8h_html_aaabdaf7ee58ca7269bd4bf24efcde092"><div class="ttname"><a href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a></div><div class="ttdeci">int32_t status_t</div><div class="ttdoc">Type used for all status and error return values.</div><div class="ttdef"><b>Definition:</b> sdrv_common.h:82</div></div>
<div class="ttc" id="asdrv__common_8h_html_aef8aef2653fac9cb1b5fbe2a5976314c"><div class="ttname"><a href="sdrv__common_8h.html#aef8aef2653fac9cb1b5fbe2a5976314c">SDRV_ERROR_STATUS</a></div><div class="ttdeci">#define SDRV_ERROR_STATUS(group, code)</div><div class="ttdoc">Construct a status code value from a group and code number. All the error statuses are negetive numbe...</div><div class="ttdef"><b>Definition:</b> sdrv_common.h:17</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a0432a9bac0e2a616cfe8a6100019c123"><div class="ttname"><a href="sdrv__rstgen_8h.html#a0432a9bac0e2a616cfe8a6100019c123">sdrv_rstgen_global_status_clear</a></div><div class="ttdeci">status_t sdrv_rstgen_global_status_clear(sdrv_rstgen_glb_t *rst_glb_ctl)</div><div class="ttdoc">clear global reset status.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a0726f32906766eb1b8dfb2ba3d38f1fc"><div class="ttname"><a href="sdrv__rstgen_8h.html#a0726f32906766eb1b8dfb2ba3d38f1fc">sdrv_rstgen_status</a></div><div class="ttdeci">status_t sdrv_rstgen_status(sdrv_rstgen_sig_t *rst_sig)</div><div class="ttdoc">Check reset signal status.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a10dde50d7ec285cde7a052ee221c6713"><div class="ttname"><a href="sdrv__rstgen_8h.html#a10dde50d7ec285cde7a052ee221c6713">sdrv_rstgen_global_reset</a></div><div class="ttdeci">status_t sdrv_rstgen_global_reset(sdrv_rstgen_glb_t *rst_glb_ctl)</div><div class="ttdoc">Global reset.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a1c688c1260c4ac042088825c62e283f6"><div class="ttname"><a href="sdrv__rstgen_8h.html#a1c688c1260c4ac042088825c62e283f6">sdrv_recovery_etimer_t</a></div><div class="ttdeci">struct sdrv_recovery_etimer sdrv_recovery_etimer_t</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a21f8bc5eeca047f8cfc64737db5f6233"><div class="ttname"><a href="sdrv__rstgen_8h.html#a21f8bc5eeca047f8cfc64737db5f6233">sdrv_recovery_epwm_t</a></div><div class="ttdeci">struct sdrv_recovery_epwm sdrv_recovery_epwm_t</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a2cd8666bfe5ca507530dfb003faa1b15"><div class="ttname"><a href="sdrv__rstgen_8h.html#a2cd8666bfe5ca507530dfb003faa1b15">sdrv_rstgen_current_global_status</a></div><div class="ttdeci">uint32_t sdrv_rstgen_current_global_status(sdrv_rstgen_glb_t *rst_glb_ctl)</div><div class="ttdoc">Check current global reset status.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a32b88bc068653b8f08eae962b0060a40"><div class="ttname"><a href="sdrv__rstgen_8h.html#a32b88bc068653b8f08eae962b0060a40">sdrv_rstgen_read_general</a></div><div class="ttdeci">uint32_t sdrv_rstgen_read_general(sdrv_rstgen_general_reg_t *rst_gen_reg)</div><div class="ttdoc">Read reset general reg.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a338f7ed846d720e8eda0201ecd3e4ce6"><div class="ttname"><a href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6">reset_core_id</a></div><div class="ttdeci">reset_core_id</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:58</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a338f7ed846d720e8eda0201ecd3e4ce6a1f4a157eafa37a4aca8805d28e85bcbe"><div class="ttname"><a href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6a1f4a157eafa37a4aca8805d28e85bcbe">RESET_CORE_SP1</a></div><div class="ttdeci">@ RESET_CORE_SP1</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:61</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a338f7ed846d720e8eda0201ecd3e4ce6a5daca59ed51f1e2889d65586a364cf9b"><div class="ttname"><a href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6a5daca59ed51f1e2889d65586a364cf9b">RESET_CORE_SF</a></div><div class="ttdeci">@ RESET_CORE_SF</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:59</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a338f7ed846d720e8eda0201ecd3e4ce6ac4f70f8d2f0723899a4cef2f42531a35"><div class="ttname"><a href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6ac4f70f8d2f0723899a4cef2f42531a35">RESET_CORE_SX0</a></div><div class="ttdeci">@ RESET_CORE_SX0</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:62</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a338f7ed846d720e8eda0201ecd3e4ce6ad406e35953141f83ad359e3b73c0195c"><div class="ttname"><a href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6ad406e35953141f83ad359e3b73c0195c">RESET_CORE_SP0</a></div><div class="ttdeci">@ RESET_CORE_SP0</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:60</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a338f7ed846d720e8eda0201ecd3e4ce6ae0a3422be08c341afe381a47dc4e9230"><div class="ttname"><a href="sdrv__rstgen_8h.html#a338f7ed846d720e8eda0201ecd3e4ce6ae0a3422be08c341afe381a47dc4e9230">RESET_CORE_SX1</a></div><div class="ttdeci">@ RESET_CORE_SX1</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:63</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a3c844a646e50c274a3d86b965fdbdd8d"><div class="ttname"><a href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8d">sdrv_reset_error</a></div><div class="ttdeci">sdrv_reset_error</div><div class="ttdoc">RESET status error code.</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:36</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a3c844a646e50c274a3d86b965fdbdd8da31f84ee6f527370a15698b1a101b054a"><div class="ttname"><a href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8da31f84ee6f527370a15698b1a101b054a">SDRV_RESET_STATUS_WRONG_SIGNAL</a></div><div class="ttdeci">@ SDRV_RESET_STATUS_WRONG_SIGNAL</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:40</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a3c844a646e50c274a3d86b965fdbdd8da47eaf13d223bf25cc064e593aaedf1a9"><div class="ttname"><a href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8da47eaf13d223bf25cc064e593aaedf1a9">SDRV_RESET_STATUS_TIMEOUT</a></div><div class="ttdeci">@ SDRV_RESET_STATUS_TIMEOUT</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:39</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a3c844a646e50c274a3d86b965fdbdd8dac6a6e5ddd79dd814b49646d021ab3d83"><div class="ttname"><a href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8dac6a6e5ddd79dd814b49646d021ab3d83">SDRV_RESET_STATUS_LOCK</a></div><div class="ttdeci">@ SDRV_RESET_STATUS_LOCK</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:38</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a3c844a646e50c274a3d86b965fdbdd8dad1b57de90df5b6f0a24c99a2251fb6a5"><div class="ttname"><a href="sdrv__rstgen_8h.html#a3c844a646e50c274a3d86b965fdbdd8dad1b57de90df5b6f0a24c99a2251fb6a5">SDRV_RESET_STATUS_SIGNAL_ASSERT</a></div><div class="ttdeci">@ SDRV_RESET_STATUS_SIGNAL_ASSERT</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:37</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a41d48b277bbb9e943071ea368e876125"><div class="ttname"><a href="sdrv__rstgen_8h.html#a41d48b277bbb9e943071ea368e876125">sdrv_rstgen_sig_t</a></div><div class="ttdeci">struct sdrv_rstgen_sig sdrv_rstgen_sig_t</div><div class="ttdoc">SDRV rstgen signal.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a42d0646052af858609125621e12e73df"><div class="ttname"><a href="sdrv__rstgen_8h.html#a42d0646052af858609125621e12e73df">sdrv_recovery_btm_t</a></div><div class="ttdeci">struct sdrv_recovery_btm sdrv_recovery_btm_t</div><div class="ttdoc">semidrive recovery device.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a43254dd94c3b9d923b73c189996299c2"><div class="ttname"><a href="sdrv__rstgen_8h.html#a43254dd94c3b9d923b73c189996299c2">sdrv_rstgen_global_status</a></div><div class="ttdeci">uint32_t sdrv_rstgen_global_status(sdrv_rstgen_glb_t *rst_glb_ctl)</div><div class="ttdoc">Check global reset status.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a4b3c16f1ab217cfe2a912ea001e87cd7"><div class="ttname"><a href="sdrv__rstgen_8h.html#a4b3c16f1ab217cfe2a912ea001e87cd7">sdrv_rstgen_write_general_bit</a></div><div class="ttdeci">status_t sdrv_rstgen_write_general_bit(sdrv_rstgen_general_reg_t *rst_gen_reg, uint8_t start, uint8_t width, uint32_t val)</div><div class="ttdoc">Write reset general reg bit.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a5a6258409dc5b32f5ea190ef6ff1c017"><div class="ttname"><a href="sdrv__rstgen_8h.html#a5a6258409dc5b32f5ea190ef6ff1c017">reset_wdt_id_e</a></div><div class="ttdeci">enum reset_wdt_id reset_wdt_id_e</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a5b0ade04f5bda906381772e55b4b97ac"><div class="ttname"><a href="sdrv__rstgen_8h.html#a5b0ade04f5bda906381772e55b4b97ac">sdrv_recovery_module_t</a></div><div class="ttdeci">struct sdrv_recovery_module sdrv_recovery_module_t</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a6eb9e62ef9966b9f79ac98f479c3874c"><div class="ttname"><a href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874c">reset_lowpower_mode</a></div><div class="ttdeci">reset_lowpower_mode</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:44</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a6eb9e62ef9966b9f79ac98f479c3874ca55f22e14d5b74467fb22464287185cc3"><div class="ttname"><a href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874ca55f22e14d5b74467fb22464287185cc3">RESET_LP_SLEEP</a></div><div class="ttdeci">@ RESET_LP_SLEEP</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:46</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a6eb9e62ef9966b9f79ac98f479c3874caee6743bff37e3cf2575abfb45ed46979"><div class="ttname"><a href="sdrv__rstgen_8h.html#a6eb9e62ef9966b9f79ac98f479c3874caee6743bff37e3cf2575abfb45ed46979">RESET_LP_HIB</a></div><div class="ttdeci">@ RESET_LP_HIB</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:45</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a7b24afa273fa54f81963c02942e858d8"><div class="ttname"><a href="sdrv__rstgen_8h.html#a7b24afa273fa54f81963c02942e858d8">sdrv_rstgen_reset</a></div><div class="ttdeci">status_t sdrv_rstgen_reset(sdrv_rstgen_sig_t *rst_sig)</div><div class="ttdoc">Reset a reset signal.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a7cbe2d46015f48d329d35575999ee34e"><div class="ttname"><a href="sdrv__rstgen_8h.html#a7cbe2d46015f48d329d35575999ee34e">sdrv_rstgen_lowpower_set</a></div><div class="ttdeci">status_t sdrv_rstgen_lowpower_set(sdrv_rstgen_sig_t *rst_sig, enum reset_lowpower_mode mode, uint32_t val)</div><div class="ttdoc">Config reset signal assert/deassert in lowpower mode.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a7ee8f465807f25ace997be437181cf5d"><div class="ttname"><a href="sdrv__rstgen_8h.html#a7ee8f465807f25ace997be437181cf5d">sdrv_rstgen_t</a></div><div class="ttdeci">struct sdrv_rstgen sdrv_rstgen_t</div><div class="ttdoc">SDRV rstgen controller.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a81742b8488efdd1527d7b6e4c9fb16ed"><div class="ttname"><a href="sdrv__rstgen_8h.html#a81742b8488efdd1527d7b6e4c9fb16ed">sdrv_rstgen_sig_handler</a></div><div class="ttdeci">void(* sdrv_rstgen_sig_handler)(uint32_t rstgen_sig_id)</div><div class="ttdoc">semidrive reset sig handler.</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:72</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a8dffb7fec18fcbb349994c9de703141a"><div class="ttname"><a href="sdrv__rstgen_8h.html#a8dffb7fec18fcbb349994c9de703141a">reset_core_id_e</a></div><div class="ttdeci">enum reset_core_id reset_core_id_e</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a90eb1f94509a65eec0ef47e9cab365dc"><div class="ttname"><a href="sdrv__rstgen_8h.html#a90eb1f94509a65eec0ef47e9cab365dc">sdrv_rstgen_assert</a></div><div class="ttdeci">status_t sdrv_rstgen_assert(sdrv_rstgen_sig_t *rst_sig)</div><div class="ttdoc">Assert a reset signal.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a92e5731422c69ec1c5fff5495238eab5"><div class="ttname"><a href="sdrv__rstgen_8h.html#a92e5731422c69ec1c5fff5495238eab5">sdrv_rstgen_general_reg_t</a></div><div class="ttdeci">struct sdrv_rstgen_general_reg sdrv_rstgen_general_reg_t</div><div class="ttdoc">SDRV rstgen general register.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a9c6285cd7cc8c41956bf7f6c3970b94d"><div class="ttname"><a href="sdrv__rstgen_8h.html#a9c6285cd7cc8c41956bf7f6c3970b94d">sdrv_rstgen_wdt_reset_enable</a></div><div class="ttdeci">status_t sdrv_rstgen_wdt_reset_enable(reset_wdt_id_e wdt, bool enable)</div><div class="ttdoc">Config wdt cause global reset enable.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_a9e0d89b5bf32daf40a926cf71f02ea6d"><div class="ttname"><a href="sdrv__rstgen_8h.html#a9e0d89b5bf32daf40a926cf71f02ea6d">sdrv_recovery_module</a></div><div class="ttdeci">status_t sdrv_recovery_module(sdrv_recovery_module_t *recovery_module)</div><div class="ttdoc">sdrv recovery latent module.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_aa1e8467a7125039f34727e96720472bd"><div class="ttname"><a href="sdrv__rstgen_8h.html#aa1e8467a7125039f34727e96720472bd">sdrv_rstgen_glb_t</a></div><div class="ttdeci">struct sdrv_rstgen_glb_ctl sdrv_rstgen_glb_t</div><div class="ttdoc">SDRV rstgen global reset controller.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_aa6189f234be2939d24c0b9e543ec6442"><div class="ttname"><a href="sdrv__rstgen_8h.html#aa6189f234be2939d24c0b9e543ec6442">sdrv_rstgen_deassert</a></div><div class="ttdeci">status_t sdrv_rstgen_deassert(sdrv_rstgen_sig_t *rst_sig)</div><div class="ttdoc">Deassert a reset signal.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_ac3922a71f3ae5643e43aee964112e0e4"><div class="ttname"><a href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4">reset_wdt_id</a></div><div class="ttdeci">reset_wdt_id</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:49</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_ac3922a71f3ae5643e43aee964112e0e4a14ad451c2dac6f555dd93ca4bf72b638"><div class="ttname"><a href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4a14ad451c2dac6f555dd93ca4bf72b638">RESET_WDT6</a></div><div class="ttdeci">@ RESET_WDT6</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:55</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_ac3922a71f3ae5643e43aee964112e0e4a5f97dc4aaff0c408ed468d4c0bce8758"><div class="ttname"><a href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4a5f97dc4aaff0c408ed468d4c0bce8758">RESET_WDT4</a></div><div class="ttdeci">@ RESET_WDT4</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:53</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_ac3922a71f3ae5643e43aee964112e0e4a6cf810cc314bc89d88eefcc864d9e66e"><div class="ttname"><a href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4a6cf810cc314bc89d88eefcc864d9e66e">RESET_WDT3</a></div><div class="ttdeci">@ RESET_WDT3</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:52</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_ac3922a71f3ae5643e43aee964112e0e4ab77c8d24a1cae6d5f89dacf59e737874"><div class="ttname"><a href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4ab77c8d24a1cae6d5f89dacf59e737874">RESET_WDT2</a></div><div class="ttdeci">@ RESET_WDT2</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:51</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_ac3922a71f3ae5643e43aee964112e0e4aba07ff62f906c3b381cadfa40feaf3a0"><div class="ttname"><a href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4aba07ff62f906c3b381cadfa40feaf3a0">RESET_WDT5</a></div><div class="ttdeci">@ RESET_WDT5</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:54</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_ac3922a71f3ae5643e43aee964112e0e4af85f5ea2a79400704796fcf14a74e4e2"><div class="ttname"><a href="sdrv__rstgen_8h.html#ac3922a71f3ae5643e43aee964112e0e4af85f5ea2a79400704796fcf14a74e4e2">RESET_WDT1</a></div><div class="ttdeci">@ RESET_WDT1</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:50</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_aeffb793b19f8ac6c847c56a35ca12933"><div class="ttname"><a href="sdrv__rstgen_8h.html#aeffb793b19f8ac6c847c56a35ca12933">sdrv_rstgen_wdt_core_reset_enable</a></div><div class="ttdeci">status_t sdrv_rstgen_wdt_core_reset_enable(reset_wdt_id_e wdt, reset_core_id_e core, bool enable)</div><div class="ttdoc">Config wdt cause single core reset enable.</div></div>
<div class="ttc" id="asdrv__rstgen_8h_html_af26011c9b69ad7af846f1b1078a6dbc0"><div class="ttname"><a href="sdrv__rstgen_8h.html#af26011c9b69ad7af846f1b1078a6dbc0">sdrv_rstgen_write_general</a></div><div class="ttdeci">status_t sdrv_rstgen_write_general(sdrv_rstgen_general_reg_t *rst_gen_reg, uint32_t val)</div><div class="ttdoc">Write reset general reg.</div></div>
<div class="ttc" id="astructsdrv__recovery__btm_html"><div class="ttname"><a href="structsdrv__recovery__btm.html">sdrv_recovery_btm</a></div><div class="ttdoc">semidrive recovery device.</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:111</div></div>
<div class="ttc" id="astructsdrv__recovery__btm_html_a799f1dc40bcd084335b1f93a4872c44e"><div class="ttname"><a href="structsdrv__recovery__btm.html#a799f1dc40bcd084335b1f93a4872c44e">sdrv_recovery_btm::btm_num</a></div><div class="ttdeci">uint32_t btm_num</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:112</div></div>
<div class="ttc" id="astructsdrv__recovery__btm_html_aefbbaecf6e01357b62ecda16aed4bd33"><div class="ttname"><a href="structsdrv__recovery__btm.html#aefbbaecf6e01357b62ecda16aed4bd33">sdrv_recovery_btm::btm_base</a></div><div class="ttdeci">uint32_t btm_base[]</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:113</div></div>
<div class="ttc" id="astructsdrv__recovery__epwm_html"><div class="ttname"><a href="structsdrv__recovery__epwm.html">sdrv_recovery_epwm</a></div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:121</div></div>
<div class="ttc" id="astructsdrv__recovery__epwm_html_a3c9d4192a0a30db0237f259df93df9f3"><div class="ttname"><a href="structsdrv__recovery__epwm.html#a3c9d4192a0a30db0237f259df93df9f3">sdrv_recovery_epwm::epwm_num</a></div><div class="ttdeci">uint32_t epwm_num</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:122</div></div>
<div class="ttc" id="astructsdrv__recovery__epwm_html_ad8345f012943d2453119e405456d3a4c"><div class="ttname"><a href="structsdrv__recovery__epwm.html#ad8345f012943d2453119e405456d3a4c">sdrv_recovery_epwm::epwm_base</a></div><div class="ttdeci">uint32_t epwm_base[]</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:123</div></div>
<div class="ttc" id="astructsdrv__recovery__etimer_html"><div class="ttname"><a href="structsdrv__recovery__etimer.html">sdrv_recovery_etimer</a></div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:116</div></div>
<div class="ttc" id="astructsdrv__recovery__etimer_html_a21a326c6793c2925919dabaedcc2b9a1"><div class="ttname"><a href="structsdrv__recovery__etimer.html#a21a326c6793c2925919dabaedcc2b9a1">sdrv_recovery_etimer::etimer_num</a></div><div class="ttdeci">uint32_t etimer_num</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:117</div></div>
<div class="ttc" id="astructsdrv__recovery__etimer_html_aee26abb9faea71679af99ee766426772"><div class="ttname"><a href="structsdrv__recovery__etimer.html#aee26abb9faea71679af99ee766426772">sdrv_recovery_etimer::etimer_base</a></div><div class="ttdeci">uint32_t etimer_base[]</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:118</div></div>
<div class="ttc" id="astructsdrv__recovery__module_html"><div class="ttname"><a href="structsdrv__recovery__module.html">sdrv_recovery_module</a></div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:127</div></div>
<div class="ttc" id="astructsdrv__recovery__module_html_a910a3e21a29a251914a77d3519f09d0a"><div class="ttname"><a href="structsdrv__recovery__module.html#a910a3e21a29a251914a77d3519f09d0a">sdrv_recovery_module::btm_list</a></div><div class="ttdeci">sdrv_recovery_btm_t const * btm_list</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:128</div></div>
<div class="ttc" id="astructsdrv__recovery__module_html_ac591c604176ef8614c0c887c14f6a635"><div class="ttname"><a href="structsdrv__recovery__module.html#ac591c604176ef8614c0c887c14f6a635">sdrv_recovery_module::epwm_list</a></div><div class="ttdeci">sdrv_recovery_epwm_t const * epwm_list</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:130</div></div>
<div class="ttc" id="astructsdrv__recovery__module_html_ad55ef5d08c8638a2234c9d87cd783467"><div class="ttname"><a href="structsdrv__recovery__module.html#ad55ef5d08c8638a2234c9d87cd783467">sdrv_recovery_module::etimer_list</a></div><div class="ttdeci">sdrv_recovery_etimer_t const * etimer_list</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:129</div></div>
<div class="ttc" id="astructsdrv__rstgen__general__reg_html"><div class="ttname"><a href="structsdrv__rstgen__general__reg.html">sdrv_rstgen_general_reg</a></div><div class="ttdoc">SDRV rstgen general register.</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:95</div></div>
<div class="ttc" id="astructsdrv__rstgen__general__reg_html_a80c53b8ccf61e87b40bd80606bb1716e"><div class="ttname"><a href="structsdrv__rstgen__general__reg.html#a80c53b8ccf61e87b40bd80606bb1716e">sdrv_rstgen_general_reg::rst_ctl</a></div><div class="ttdeci">sdrv_rstgen_t * rst_ctl</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:96</div></div>
<div class="ttc" id="astructsdrv__rstgen__general__reg_html_abaabdc509cdaba7df9f56c6c76f3ae19"><div class="ttname"><a href="structsdrv__rstgen__general__reg.html#abaabdc509cdaba7df9f56c6c76f3ae19">sdrv_rstgen_general_reg::id</a></div><div class="ttdeci">uint32_t id</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:97</div></div>
<div class="ttc" id="astructsdrv__rstgen__glb__ctl_html"><div class="ttname"><a href="structsdrv__rstgen__glb__ctl.html">sdrv_rstgen_glb_ctl</a></div><div class="ttdoc">SDRV rstgen global reset controller.</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:103</div></div>
<div class="ttc" id="astructsdrv__rstgen__glb__ctl_html_a468ffd6eefb7ffd443db42e961df76bc"><div class="ttname"><a href="structsdrv__rstgen__glb__ctl.html#a468ffd6eefb7ffd443db42e961df76bc">sdrv_rstgen_glb_ctl::rst_ap_ctl</a></div><div class="ttdeci">sdrv_rstgen_t * rst_ap_ctl</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:105</div></div>
<div class="ttc" id="astructsdrv__rstgen__glb__ctl_html_adb46f9d091752da9db94d92bb42e9eaf"><div class="ttname"><a href="structsdrv__rstgen__glb__ctl.html#adb46f9d091752da9db94d92bb42e9eaf">sdrv_rstgen_glb_ctl::rst_sf_ctl</a></div><div class="ttdeci">sdrv_rstgen_t * rst_sf_ctl</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:104</div></div>
<div class="ttc" id="astructsdrv__rstgen__sig_html"><div class="ttname"><a href="structsdrv__rstgen__sig.html">sdrv_rstgen_sig</a></div><div class="ttdoc">SDRV rstgen signal.</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:84</div></div>
<div class="ttc" id="astructsdrv__rstgen__sig_html_a80c53b8ccf61e87b40bd80606bb1716e"><div class="ttname"><a href="structsdrv__rstgen__sig.html#a80c53b8ccf61e87b40bd80606bb1716e">sdrv_rstgen_sig::rst_ctl</a></div><div class="ttdeci">sdrv_rstgen_t * rst_ctl</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:85</div></div>
<div class="ttc" id="astructsdrv__rstgen__sig_html_abaabdc509cdaba7df9f56c6c76f3ae19"><div class="ttname"><a href="structsdrv__rstgen__sig.html#abaabdc509cdaba7df9f56c6c76f3ae19">sdrv_rstgen_sig::id</a></div><div class="ttdeci">uint32_t id</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:86</div></div>
<div class="ttc" id="astructsdrv__rstgen__sig_html_ae6a399ac2cbee4605bdc8fb43b22b861"><div class="ttname"><a href="structsdrv__rstgen__sig.html#ae6a399ac2cbee4605bdc8fb43b22b861">sdrv_rstgen_sig::need_clr_rst</a></div><div class="ttdeci">bool need_clr_rst</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:87</div></div>
<div class="ttc" id="astructsdrv__rstgen__sig_html_aee73b976b871d1326ddf6debc401098b"><div class="ttname"><a href="structsdrv__rstgen__sig.html#aee73b976b871d1326ddf6debc401098b">sdrv_rstgen_sig::pre_handler</a></div><div class="ttdeci">sdrv_rstgen_sig_handler pre_handler</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:88</div></div>
<div class="ttc" id="astructsdrv__rstgen__sig_html_afaf7637cf56dd511a2781deac43ab0ab"><div class="ttname"><a href="structsdrv__rstgen__sig.html#afaf7637cf56dd511a2781deac43ab0ab">sdrv_rstgen_sig::post_handler</a></div><div class="ttdeci">sdrv_rstgen_sig_handler post_handler</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:89</div></div>
<div class="ttc" id="astructsdrv__rstgen_html"><div class="ttname"><a href="structsdrv__rstgen.html">sdrv_rstgen</a></div><div class="ttdoc">SDRV rstgen controller.</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:77</div></div>
<div class="ttc" id="astructsdrv__rstgen_html_abc81edd3d3caf9e6c2e0762881da6016"><div class="ttname"><a href="structsdrv__rstgen.html#abc81edd3d3caf9e6c2e0762881da6016">sdrv_rstgen::base</a></div><div class="ttdeci">paddr_t base</div><div class="ttdef"><b>Definition:</b> sdrv_rstgen.h:78</div></div>
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