359 lines
17 KiB
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359 lines
17 KiB
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<div id="projectname">SemiDrive SSDK Appication Program Interface<span id="projectnumber"> PTG3.0</span>
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="headertitle"><div class="title">host_caps</div></div>
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<div class="contents">
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<p><code>#include <<a class="el" href="sdrv__sdhci_8h_source.html">sdrv_sdhci.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:aaab15b44be013e897ce59f476d251bba"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#aaab15b44be013e897ce59f476d251bba">base_clk_rate</a></td></tr>
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<tr class="memitem:a9f329ecfb3b689f44a9fbbfff6d57aba"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#a9f329ecfb3b689f44a9fbbfff6d57aba">max_blk_len</a></td></tr>
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<tr class="memitem:a681f9b630696b4e2e70c21c814e9ba61"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#a681f9b630696b4e2e70c21c814e9ba61">bus_width_8bit</a></td></tr>
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<tr class="memitem:a494540492933d33589e89f98a15afb58"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#a494540492933d33589e89f98a15afb58">spec_version</a></td></tr>
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<tr class="memitem:a45927d1243a746e6035217cc51b6d7dc"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#a45927d1243a746e6035217cc51b6d7dc">adma2_support</a></td></tr>
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<tr class="memitem:a868259d093d46070a1e6c742cdf0c1b5"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#a868259d093d46070a1e6c742cdf0c1b5">addr_64bit_v3</a></td></tr>
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<tr class="memitem:a120013f4e7c361b194c2d6e2600b81ee"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#a120013f4e7c361b194c2d6e2600b81ee">addr_64bit_v4</a></td></tr>
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<tr class="memitem:a802fdc14b8dabf84a890df9b560f0409"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#a802fdc14b8dabf84a890df9b560f0409">voltage</a></td></tr>
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<tr class="memitem:aaa104adc28f326bff2dd9299cf7147e9"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#aaa104adc28f326bff2dd9299cf7147e9">sdr_support</a></td></tr>
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<tr class="memitem:ae6e972d74d4eab38c5052eb3e0d6e6da"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#ae6e972d74d4eab38c5052eb3e0d6e6da">ddr_support</a></td></tr>
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<tr class="memitem:a20bcb421aff92ad77b010581e98b721d"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#a20bcb421aff92ad77b010581e98b721d">sdr50_support</a></td></tr>
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<tr class="memitem:a4c42537b9846343a3fa9343d4d8dd14e"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#a4c42537b9846343a3fa9343d4d8dd14e">sdr104_support</a></td></tr>
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<tr class="memitem:a6d758a56fad767693a4995cbb2b7b36d"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#a6d758a56fad767693a4995cbb2b7b36d">hs200_support</a></td></tr>
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<tr class="memitem:acec97c333e5094545bca1aeba82c62ef"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#acec97c333e5094545bca1aeba82c62ef">hs400_support</a></td></tr>
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<tr class="separator:acec97c333e5094545bca1aeba82c62ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3caeab8b8383260dd63e14f35a10c11d"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#a3caeab8b8383260dd63e14f35a10c11d">hw_reset_support</a></td></tr>
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<tr class="memitem:af3fc645428d2d442ddc4a8546910df81"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structhost__caps.html#af3fc645428d2d442ddc4a8546910df81">uhs_support</a></td></tr>
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</table>
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<h2 class="groupheader">Field Documentation</h2>
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<a id="a868259d093d46070a1e6c742cdf0c1b5" name="a868259d093d46070a1e6c742cdf0c1b5"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a868259d093d46070a1e6c742cdf0c1b5">◆ </a></span>addr_64bit_v3</h2>
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<td class="memname">uint8_t addr_64bit_v3</td>
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</div><div class="memdoc">
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<p >addr 64bit for v3 support </p>
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</div>
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</div>
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<a id="a120013f4e7c361b194c2d6e2600b81ee" name="a120013f4e7c361b194c2d6e2600b81ee"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a120013f4e7c361b194c2d6e2600b81ee">◆ </a></span>addr_64bit_v4</h2>
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<td class="memname">uint8_t addr_64bit_v4</td>
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</div><div class="memdoc">
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<p >addr 64bit for v3 support </p>
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</div>
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<a id="a45927d1243a746e6035217cc51b6d7dc" name="a45927d1243a746e6035217cc51b6d7dc"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a45927d1243a746e6035217cc51b6d7dc">◆ </a></span>adma2_support</h2>
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<td class="memname">uint8_t adma2_support</td>
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</div><div class="memdoc">
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<p >Adma2 support </p>
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</div>
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<a id="aaab15b44be013e897ce59f476d251bba" name="aaab15b44be013e897ce59f476d251bba"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aaab15b44be013e897ce59f476d251bba">◆ </a></span>base_clk_rate</h2>
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<td class="memname">uint32_t base_clk_rate</td>
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</table>
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</div><div class="memdoc">
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<p >Max clock rate supported </p>
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</div>
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</div>
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<a id="a681f9b630696b4e2e70c21c814e9ba61" name="a681f9b630696b4e2e70c21c814e9ba61"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a681f9b630696b4e2e70c21c814e9ba61">◆ </a></span>bus_width_8bit</h2>
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<td class="memname">uint8_t bus_width_8bit</td>
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<p >8 Bit mode supported </p>
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</div>
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<a id="ae6e972d74d4eab38c5052eb3e0d6e6da" name="ae6e972d74d4eab38c5052eb3e0d6e6da"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ae6e972d74d4eab38c5052eb3e0d6e6da">◆ </a></span>ddr_support</h2>
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<td class="memname">uint8_t ddr_support</td>
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</div><div class="memdoc">
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<p >Dual Data rate </p>
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<a id="a6d758a56fad767693a4995cbb2b7b36d" name="a6d758a56fad767693a4995cbb2b7b36d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a6d758a56fad767693a4995cbb2b7b36d">◆ </a></span>hs200_support</h2>
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<td class="memname">uint8_t hs200_support</td>
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</div><div class="memdoc">
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<p >Hs200 mode, with 200 MHZ clock </p>
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</div>
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<a id="acec97c333e5094545bca1aeba82c62ef" name="acec97c333e5094545bca1aeba82c62ef"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#acec97c333e5094545bca1aeba82c62ef">◆ </a></span>hs400_support</h2>
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<td class="memname">uint8_t hs400_support</td>
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<p >Hs400 mode, with 400 MHZ clock </p>
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</div>
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<a id="a3caeab8b8383260dd63e14f35a10c11d" name="a3caeab8b8383260dd63e14f35a10c11d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a3caeab8b8383260dd63e14f35a10c11d">◆ </a></span>hw_reset_support</h2>
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<td class="memname">uint8_t hw_reset_support</td>
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<p >SDHC hardware reset supported or not </p>
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<a id="a9f329ecfb3b689f44a9fbbfff6d57aba" name="a9f329ecfb3b689f44a9fbbfff6d57aba"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a9f329ecfb3b689f44a9fbbfff6d57aba">◆ </a></span>max_blk_len</h2>
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<td class="memname">uint32_t max_blk_len</td>
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<p >Max block len supported </p>
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<a id="a4c42537b9846343a3fa9343d4d8dd14e" name="a4c42537b9846343a3fa9343d4d8dd14e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a4c42537b9846343a3fa9343d4d8dd14e">◆ </a></span>sdr104_support</h2>
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<p >UHS mode, with 200 MHZ clock </p>
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<a id="a20bcb421aff92ad77b010581e98b721d" name="a20bcb421aff92ad77b010581e98b721d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a20bcb421aff92ad77b010581e98b721d">◆ </a></span>sdr50_support</h2>
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<p >UHS mode, with 100 MHZ clock </p>
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<a id="aaa104adc28f326bff2dd9299cf7147e9" name="aaa104adc28f326bff2dd9299cf7147e9"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aaa104adc28f326bff2dd9299cf7147e9">◆ </a></span>sdr_support</h2>
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<p >Single Data rate </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a494540492933d33589e89f98a15afb58">◆ </a></span>spec_version</h2>
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<td class="memname">uint8_t spec_version</td>
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<p >spec version num in sdhci controller </p>
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<h2 class="memtitle"><span class="permalink"><a href="#af3fc645428d2d442ddc4a8546910df81">◆ </a></span>uhs_support</h2>
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<td class="memname">uint8_t uhs_support</td>
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<p >SDHC hardware supported uhs mode </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a802fdc14b8dabf84a890df9b560f0409">◆ </a></span>voltage</h2>
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<td class="memname">uint8_t voltage</td>
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<p >Supported voltage </p>
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<hr/>The documentation for this struct was generated from the following file:<ul>
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<li>Z:/01-Code/06-SSDK-DEV-Firewall/ssdk/drivers/include/<a class="el" href="sdrv__sdhci_8h_source.html">sdrv_sdhci.h</a></li>
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