sdrv_smc.h

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#ifndef SDRV_SMC_H_
#define SDRV_SMC_H_
 
#include <sdrv_common.h>
#include <types.h>
#include <part.h>
 
#if CONFIG_E3 || CONFIG_D3
#define SDRV_SMC_ASYNC_INT_USB (236 + 16)
#define SDRV_SMC_ASYNC_INT_IOC (237 + 16)
#define SDRV_SMC_ASYNC_INT_VIC1_SF_GPIO (238 + 16)
#define SDRV_SMC_ASYNC_INT_VIC1_AP_GPIO (239 + 16)
#define SDRV_SMC_ASYNC_INT_VIC2A_SF_GPIO (240 + 16)
#define SDRV_SMC_ASYNC_INT_VIC2A_AP_GPIO (241 + 16)
#define SDRV_SMC_ASYNC_INT_VIC2B_SF_GPIO (242 + 16)
#define SDRV_SMC_ASYNC_INT_VIC2B_AP_GPIO (243 + 16)
#define SDRV_SMC_ASYNC_INT_VIC3A_SF_GPIO (244 + 16)
#define SDRV_SMC_ASYNC_INT_VIC3A_AP_GPIO (245 + 16)
#define SDRV_SMC_ASYNC_INT_VIC3B_SF_GPIO (246 + 16)
#define SDRV_SMC_ASYNC_INT_VIC3B_AP_GPIO (247 + 16)
 
#define SDRV_SF_CKGEN_PCG_NUM  334
#define SDRV_SF_CKGEN_BCG_NUM  15
#define SDRV_SF_CKGEN_CCG_NUM  5
 
#endif
 
#if CONFIG_E3L || CONFIG_D3L
#define SDRV_SMC_ASYNC_INT_USB (163 + 16)
#define SDRV_SMC_ASYNC_INT_IOC (164 + 16)
#define SDRV_SMC_ASYNC_INT_VIC1_SF_GPIO (165 + 16)
 
#define SDRV_SF_CKGEN_PCG_NUM  207
#define SDRV_SF_CKGEN_BCG_NUM  8
#define SDRV_SF_CKGEN_CCG_NUM  1
 
#endif
 
#define RAM_LP_PG_EN 0x4u
#define RAM_LP_RET1N 0x2u
#define RAM_LP_RET2N 0x1u
 
#define SDRV_SMC_CHIP_ENABLE (RAM_LP_RET1N | RAM_LP_RET2N)
#define SDRV_SMC_SELECTIVE_PRECHARGE (RAM_LP_RET2N)
#define SDRV_SMC_RETENTION_1 (RAM_LP_PG_EN | RAM_LP_RET2N)
#define SDRV_SMC_RETENTION_2 (RAM_LP_PG_EN | RAM_LP_RET1N)
#define SDRV_SMC_POWER_DOWN (RAM_LP_PG_EN | RAM_LP_RET1N | RAM_LP_RET2N)
 
#define SDRV_SMC_IGNORE_AP (0x1u)
#define SDRV_SMC_AP_LP_ALIGN_SAF (0x2u)
#define SDRV_SMC_AP_WK_ALIGN_SAF (0x4u)
 
#define SDRV_SMC_SWM_RUN (0x0u)
#define SDRV_SMC_SWM_SLP (0x1u)
#define SDRV_SMC_SWM_HIB (0x2u)
#define SDRV_SMC_SWM_RTC (0x3u)
 
enum sdrv_smc_error {
    SDRV_SMC_CONFIG_TYPE_WRONG = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_SMC, 0),
    SDRV_SMC_CONFIG_NOT_SUPPORT = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_SMC, 1),
};
 
typedef enum sdrv_smc_domain {
    SDRV_SMC_SAF, 
    SDRV_SMC_AP,  
} sdrv_smc_domain_e;
 
typedef enum sdrv_smc_mode {
    SDRV_SMC_SLEEP,
 
    SDRV_SMC_HIBERNATE,
} sdrv_smc_mode_e;
 
#if CONFIG_E3 || CONFIG_D3
typedef enum sdrv_smc_power_switch {
    SDRV_SMC_POWER_SWITCH_SF = 0,    
    SDRV_SMC_POWER_SWITCH_SP,        
    SDRV_SMC_POWER_SWITCH_SX,        
    SDRV_SMC_POWER_SWITCH_GAMA1,     
    SDRV_SMC_POWER_SWITCH_AP_DISP,   
} sdrv_smc_power_switch_e;
 
typedef enum sdrv_smc_ram {
    SDRV_SMC_RAM_SF = 0,    
    SDRV_SMC_RAM_SP,        
    SDRV_SMC_RAM_SX,        
    SDRV_SMC_RAM_GAMA1,     
    SDRV_SMC_RAM_SF_MISC,   
    SDRV_SMC_RAM_AP,        
    SDRV_SMC_RAM_DISP,      
} sdrv_smc_ram_e;
#endif /* CONFIG_E3 || CONFIG_D3 */
 
#if CONFIG_E3L || CONFIG_D3L
typedef enum sdrv_smc_power_switch {
    SDRV_SMC_POWER_SWITCH_SF      = 0,        
    SDRV_SMC_POWER_SWITCH_SF_BOOT = 2,        
    SDRV_SMC_POWER_SWITCH_AP_MIX  = 3,        
} sdrv_smc_power_switch_e;
 
typedef enum sdrv_smc_ram {
    SDRV_SMC_RAM_SF      = 0,    
    SDRV_SMC_RAM_SF_BOOT = 2,    
    SDRV_SMC_RAM_AP_MIX  = 3,    
} sdrv_smc_ram_e;
#endif /* CONFIG_E3L || CONFIG_D3L */
 
typedef enum sdrv_smc_handshake {
    SDRV_SMC_HK_AP_CKGEN = 0,   
    SDRV_SMC_HK_AP_RSTGEN,      
    SDRV_SMC_HK_SAF_CKGEN,      
    SDRV_SMC_HK_SAF_RSTGEN,     
    SDRV_SMC_HK_PMU,            
} sdrv_smc_handshake_e;
 
typedef enum sdrv_smc_core {
    SDRV_SMC_CORE_SF = 0,   
    SDRV_SMC_CORE_SP0,      
    SDRV_SMC_CORE_SP1,      
    SDRV_SMC_CORE_SX0,      
    SDRV_SMC_CORE_SX1,      
} sdrv_smc_core_e;
 
typedef enum sdrv_smc_debug_mux {
    SDRV_SMC_DBG_HK_SAF = 1,
    SDRV_SMC_DBG_HK_AP,
    SDRV_SMC_DBG_HK_PMU
} sdrv_smc_debug_mux_e;
 
typedef struct sdrv_smc_domain_timeout {
    bool wkup_en; 
    bool wdt_en; 
    uint8_t ckgen_hk; 
    uint8_t rstgen_hk; 
    uint8_t mode_req_trans; 
} sdrv_smc_domain_timeout_t;
 
typedef struct sdrv_smc_soc_timeout {
    bool wkup_en; 
    bool wdt_en; 
    uint8_t pmu_hk; 
} sdrv_smc_soc_timeout_t;
 
typedef struct sdrv_smc_soc_wakeup_ctrl {
    bool lp2wkup_tout_wkup_en; 
    bool lp2wkup_wdt_en; 
    uint16_t lp2wkup_val; 
    bool wkup_wdt_en; 
    uint8_t wkup_done_src_sel; 
    uint16_t wkup_ack_val; 
    uint16_t soc_run_val; 
} sdrv_smc_soc_wakeup_ctrl_t;
 
typedef struct sdrv_smc_global_control {
    sdrv_smc_core_e saf_pri_core; 
    sdrv_smc_core_e ap_pri_core; 
    bool ap_off_en; 
    bool lp_align_saf_en; 
    bool wkup_align_saf_en; 
} sdrv_smc_global_control_t;
 
typedef struct sdrv_smc {
    paddr_t base;
 
    /* recored for wakeup irq info */
    uint32_t core_irq_status[5];
    uint32_t group_irq_status[8];
} sdrv_smc_t;
 
status_t sdrv_smc_ctrl_global_control_config(sdrv_smc_t *smc_ctrl, sdrv_smc_global_control_t *config);
 
status_t sdrv_smc_ctrl_set_primary_core(sdrv_smc_t *smc_ctrl, sdrv_smc_domain_e domain, sdrv_smc_core_e id);
 
status_t sdrv_smc_ctrl_set_lowpower_mode(sdrv_smc_t *smc_ctrl, sdrv_smc_domain_e domain, sdrv_smc_mode_e mode);
 
status_t sdrv_smc_ctrl_lowpower_enable(sdrv_smc_t *smc_ctrl, sdrv_smc_domain_e domain, bool enable);
 
status_t sdrv_smc_ctrl_power_switch_config(sdrv_smc_t *smc_ctrl, sdrv_smc_power_switch_e power_switch,
                                           sdrv_smc_mode_e mode, bool power_down_enable);
 
status_t sdrv_smc_ctrl_power_switch_delay_config(sdrv_smc_t *smc_ctrl, sdrv_smc_power_switch_e power_switch,
                                                 uint32_t iso_en, uint32_t pg, uint32_t po, uint32_t iso_dis);
 
status_t sdrv_smc_ctrl_ram_lowpower_config(sdrv_smc_t *smc_ctrl, sdrv_smc_ram_e ram, sdrv_smc_mode_e mode,
                                           uint32_t ram_mode);
 
status_t sdrv_smc_ctrl_domain_timeout_config(sdrv_smc_t *smc_ctrl, sdrv_smc_domain_e domain,
                                             sdrv_smc_domain_timeout_t *config);
 
status_t sdrv_smc_ctrl_domain_misc_config(sdrv_smc_t *smc_ctrl, sdrv_smc_domain_e domain,
                                          bool lp_trans_req, uint32_t irq_mask_dly, bool ill_trans_wkup_en);
 
status_t sdrv_smc_ctrl_ap_domain_config(sdrv_smc_t *smc_ctrl, uint32_t ap_bitmap);
 
status_t sdrv_smc_ctrl_rc24m_hibernate_enable(sdrv_smc_t *smc_ctrl, bool enable);
 
status_t sdrv_smc_ctrl_pre_divider_config(sdrv_smc_t *smc_ctrl, uint16_t div_32k, uint8_t div_24m);
 
status_t sdrv_smc_ctrl_soc_swm_timeout_config(sdrv_smc_t *smc_ctrl, sdrv_smc_soc_timeout_t *config);
 
status_t sdrv_smc_ctrl_soc_wakeup_control_config(sdrv_smc_t *smc_ctrl, sdrv_smc_soc_wakeup_ctrl_t *config);
 
status_t sdrv_smc_ctrl_clear_core_wakeup_ack(sdrv_smc_t *smc_ctrl);
 
status_t sdrv_smc_ctrl_set_core_wakeup_ack(sdrv_smc_t *smc_ctrl, uint32_t ack);
 
status_t sdrv_smc_ctrl_core_wakeup_irq_config(sdrv_smc_t *smc_ctrl, uint32_t err_wkup, uint32_t bk_wkup);
 
uint32_t sdrv_smc_ctrl_get_core_wakeup_irq_status(sdrv_smc_t *smc_ctrl);
 
status_t sdrv_smc_ctrl_clear_core_wakeup_irq_status(sdrv_smc_t *smc_ctrl, uint32_t clr);
 
status_t sdrv_smc_ctrl_soc_misc_config(sdrv_smc_t *smc_ctrl, bool ill_trans_wkup_en);
 
status_t sdrv_smc_ctrl_smc_misc_config(sdrv_smc_t *smc_ctrl, bool lpbk_force_check_en, bool permission_err_en);
 
status_t sdrv_smc_ctrl_trigger_software_handshake(sdrv_smc_t *smc_ctrl, sdrv_smc_handshake_e handshake,
                                                  uint32_t smc_swm);
 
status_t sdrv_smc_ctrl_trigger_software_power_switch(sdrv_smc_t *smc_ctrl,
            sdrv_smc_power_switch_e power_switch, bool power_down_enable);
 
bool sdrv_smc_ctrl_software_power_switch_gate_status(sdrv_smc_t *smc_ctrl, sdrv_smc_power_switch_e power_switch);
 
status_t sdrv_smc_ctrl_trigger_software_ram_lowpower(sdrv_smc_t *smc_ctrl, sdrv_smc_ram_e ram,
                                                     uint32_t ram_mode);
 
uint32_t sdrv_smc_ctrl_status_monitor(sdrv_smc_t *smc_ctrl);
 
status_t sdrv_smc_ctrl_clear_timeout_illegal_status(sdrv_smc_t *smc_ctrl);
 
uint32_t sdrv_smc_ctrl_timeout_status_monitor(sdrv_smc_t *smc_ctrl);
 
uint32_t sdrv_smc_ctrl_illegal_status_monitor(sdrv_smc_t *smc_ctrl);
 
status_t sdrv_smc_ctrl_all_wakeup_interrupt_disable(sdrv_smc_t *smc_ctrl);
 
status_t sdrv_smc_ctrl_wakeup_interrupt_enable(sdrv_smc_t *smc_ctrl, sdrv_smc_core_e core, uint32_t irq_num);
 
status_t sdrv_smc_ctrl_wakeup_interrupt_disable(sdrv_smc_t *smc_ctrl, sdrv_smc_core_e core, uint32_t irq_num);
 
status_t sdrv_smc_ctrl_all_interrupt_monitor_clear(sdrv_smc_t *smc_ctrl);
 
bool sdrv_smc_ctrl_interrupt_monitor_status(sdrv_smc_t *smc_ctrl, sdrv_smc_core_e core, uint32_t irq_num);
 
status_t sdrv_smc_ctrl_clear_interrupt_monitor_status(sdrv_smc_t *smc_ctrl, sdrv_smc_core_e core,
                                                      uint32_t irq_num);
 
status_t sdrv_smc_ctrl_record_interrupt_monitor_status(sdrv_smc_t *smc_ctrl);
 
status_t sdrv_smc_ctrl_ap_domain_handshake(sdrv_smc_t *smc_ctrl, bool enable);
 
uint32_t sdrv_smc_ctrl_debug_monitor(sdrv_smc_t *smc_ctrl, sdrv_smc_debug_mux_e dbg_mux);
 
status_t sdrv_smc_global_control_config(sdrv_smc_global_control_t *config);
 
status_t sdrv_smc_set_primary_core(sdrv_smc_domain_e domain, sdrv_smc_core_e id);
 
status_t sdrv_smc_set_lowpower_mode(sdrv_smc_domain_e domain, sdrv_smc_mode_e mode);
 
status_t sdrv_smc_lowpower_enable(sdrv_smc_domain_e domain, bool enable);
 
status_t sdrv_smc_power_switch_config(sdrv_smc_power_switch_e power_switch,
                                      sdrv_smc_mode_e mode, bool power_down_enable);
 
status_t sdrv_smc_power_switch_delay_config(sdrv_smc_power_switch_e power_switch,
                                            uint32_t iso_en, uint32_t pg, uint32_t po, uint32_t iso_dis);
 
status_t sdrv_smc_ram_lowpower_config(sdrv_smc_ram_e ram, sdrv_smc_mode_e mode,
                                      uint32_t ram_mode);
 
status_t sdrv_smc_domain_timeout_config(sdrv_smc_domain_e domain, sdrv_smc_domain_timeout_t *config);
 
status_t sdrv_smc_domain_misc_config(sdrv_smc_domain_e domain,
                                     bool lp_trans_req, uint32_t irq_mask_dly, bool ill_trans_wkup_en);
 
status_t sdrv_smc_ap_domain_config(uint32_t ap_bitmap);
 
status_t sdrv_smc_rc24m_hibernate_enable(bool enable);
 
status_t sdrv_smc_pre_divider_config(uint16_t div_32k, uint8_t div_24m);
 
status_t sdrv_smc_soc_swm_timeout_config(sdrv_smc_soc_timeout_t *config);
 
status_t sdrv_smc_soc_wakeup_control_config(sdrv_smc_soc_wakeup_ctrl_t *config);
 
status_t sdrv_smc_clear_core_wakeup_ack(void);
 
status_t sdrv_smc_set_core_wakeup_ack(uint32_t ack);
 
status_t sdrv_smc_core_wakeup_irq_config(uint32_t err_wkup, uint32_t bk_wkup);
 
uint32_t sdrv_smc_get_core_wakeup_irq_status(void);
 
status_t sdrv_smc_clear_core_wakeup_irq_status(uint32_t clr);
 
status_t sdrv_smc_soc_misc_config(bool ill_trans_wkup_en);
 
status_t sdrv_smc_smc_misc_config(bool lpbk_force_check_en, bool permission_err_en);
 
status_t sdrv_smc_trigger_software_handshake(sdrv_smc_handshake_e handshake,
                                             uint32_t smc_swm);
 
status_t sdrv_smc_trigger_software_power_switch(
            sdrv_smc_power_switch_e power_switch, bool power_down_enable);
 
bool sdrv_smc_software_power_switch_gate_status(sdrv_smc_power_switch_e power_switch);
 
status_t sdrv_smc_trigger_software_ram_lowpower(sdrv_smc_ram_e ram,
                                                uint32_t ram_mode);
 
uint32_t sdrv_smc_status_monitor(void);
 
status_t sdrv_smc_clear_timeout_illegal_status(void);
 
uint32_t sdrv_smc_timeout_status_monitor(void);
 
uint32_t sdrv_smc_illegal_status_monitor(void);
 
status_t sdrv_smc_all_wakeup_interrupt_disable(void);
 
status_t sdrv_smc_wakeup_interrupt_enable(sdrv_smc_core_e core, uint32_t irq_num);
 
status_t sdrv_smc_wakeup_interrupt_disable(sdrv_smc_core_e core, uint32_t irq_num);
 
status_t sdrv_smc_all_interrupt_monitor_clear(void);
 
bool sdrv_smc_interrupt_monitor_status(sdrv_smc_core_e core, uint32_t irq_num);
 
status_t sdrv_smc_clear_interrupt_monitor_status(sdrv_smc_core_e core,
                                                 uint32_t irq_num);
 
status_t sdrv_smc_record_interrupt_monitor_status(void);
 
status_t sdrv_smc_ap_domain_handshake(bool enable);
 
uint32_t sdrv_smc_debug_monitor(sdrv_smc_debug_mux_e dbg_mux);
 
#endif /* SDRV_SMC_H_ */