sdrv_sdramc.h File Reference

#include <types.h>
#include <debug.h>
#include <reg.h>
#include <sdrv_sdramc.h>
#include <sdrv_common.h>

Go to the source code of this file.

Data Structures
struct	sdram_comm_config
struct	sdram_config
struct	sd_para
struct	gate_record

Functions
struct sd_para *	sdrv_get_sd_para (void)
void	sdrv_set_sd_para (struct sd_para *cs)
int32_t	sdrv_sdramc_init (addr_t base, sdram_config_t *conf)

Detailed Description

Copyright

Copyright (c) 2021 Semidrive Semiconductor. All rights reserved.

Macro Definition Documentation

BIT

#define BIT

(

nr

)

((uint32_t)1u << (nr))

ddr_readl

#define ddr_readl

(

reg

)

readl(reg)

ddr_writel

#define ddr_writel	(		val,
			reg
	)		writel(val, reg)

RD_CLK

#define RD_CLK   (0x14u)

RD_CLK_ASYNC_FIFO_RD_SEL_LSB

#define RD_CLK_ASYNC_FIFO_RD_SEL_LSB   (2u)

RD_CLK_DUMMY_LSB

#define RD_CLK_DUMMY_LSB   (5u)

RD_CLK_SEL_LSB

#define RD_CLK_SEL_LSB   (0u)

SDRAM_BURST_MODE

#define SDRAM_BURST_MODE   (0x1Cu)

SDRAM_BURST_MODE_LSB

#define SDRAM_BURST_MODE_LSB   (0u)

SDRAM_BURST_MODE_TYPE

#define SDRAM_BURST_MODE_TYPE   BIT(3)

SDRAM_DDR_MODE

#define SDRAM_DDR_MODE   (0x18u)

SDRAM_DDR_MODE_CFG

#define SDRAM_DDR_MODE_CFG   BIT(0)

SDRAM_WIDTH_MODE

#define SDRAM_WIDTH_MODE   (0x20u)

SDRAM_WIDTH_MODE_LSB

#define SDRAM_WIDTH_MODE_LSB   (0u)

SDRAMC_ADDR_DIVED_MODE

#define SDRAMC_ADDR_DIVED_MODE   (0x54u)

SDRAMC_ADDR_DIVED_MODE_BANK_START_LSB

#define SDRAMC_ADDR_DIVED_MODE_BANK_START_LSB   (8u)

SDRAMC_ADDR_DIVED_MODE_COLOW_START_LSB

#define SDRAMC_ADDR_DIVED_MODE_COLOW_START_LSB   (16u)

SDRAMC_ADDR_DIVED_MODE_CS_START_LSB

#define SDRAMC_ADDR_DIVED_MODE_CS_START_LSB   (24u)

SDRAMC_ADDR_DIVED_MODE_ROW_MODE_LSB

#define SDRAMC_ADDR_DIVED_MODE_ROW_MODE_LSB   (5u)

SDRAMC_ADDR_DIVED_MODE_ROW_START_LSB

#define SDRAMC_ADDR_DIVED_MODE_ROW_START_LSB   (0u)

SDRAMC_AGING_WEIGHT

#define SDRAMC_AGING_WEIGHT   (0x34u)

SDRAMC_AGING_WEIGHT_LSB

#define SDRAMC_AGING_WEIGHT_LSB   (0u)

SDRAMC_AXI_ARCNT

#define SDRAMC_AXI_ARCNT   (0x80u)

SDRAMC_AXI_ARCNT_LSB

#define SDRAMC_AXI_ARCNT_LSB   (0u)

SDRAMC_AXI_AWCNT

#define SDRAMC_AXI_AWCNT   (0x78u)

SDRAMC_AXI_AWCNT_LSB

#define SDRAMC_AXI_AWCNT_LSB   (0u)

SDRAMC_AXI_BRESP_CNT

#define SDRAMC_AXI_BRESP_CNT   (0x84u)

SDRAMC_AXI_BRESP_CNT_LSB

#define SDRAMC_AXI_BRESP_CNT_LSB   (0u)

SDRAMC_AXI_FIFO_GAP

#define SDRAMC_AXI_FIFO_GAP   (0x8u)

SDRAMC_AXI_FIFO_GAP_AR_LSB

#define SDRAMC_AXI_FIFO_GAP_AR_LSB   (8u)

SDRAMC_AXI_FIFO_GAP_AW_LSB

#define SDRAMC_AXI_FIFO_GAP_AW_LSB   (4u)

SDRAMC_AXI_FIFO_GAP_B_LSB

#define SDRAMC_AXI_FIFO_GAP_B_LSB   (10u)

SDRAMC_AXI_FIFO_GAP_RD_LSB

#define SDRAMC_AXI_FIFO_GAP_RD_LSB   (6u)

SDRAMC_AXI_FIFO_GAP_WR_LSB

#define SDRAMC_AXI_FIFO_GAP_WR_LSB   (0u)

SDRAMC_AXI_RCNT

#define SDRAMC_AXI_RCNT   (0x88u)

SDRAMC_AXI_RCNT_LSB

#define SDRAMC_AXI_RCNT_LSB   (0u)

SDRAMC_AXI_RDY_CNT

#define SDRAMC_AXI_RDY_CNT   (0x4u)

SDRAMC_AXI_RDY_CNT_B_CH_LSB

#define SDRAMC_AXI_RDY_CNT_B_CH_LSB   (0u)

SDRAMC_AXI_RDY_CNT_R_CH_LSB

#define SDRAMC_AXI_RDY_CNT_R_CH_LSB   (16u)

SDRAMC_AXI_WCNT

#define SDRAMC_AXI_WCNT   (0x7Cu)

SDRAMC_AXI_WCNT_LSB

#define SDRAMC_AXI_WCNT_LSB   (0u)

SDRAMC_BA

#define SDRAMC_BA   (0x10u)

SDRAMC_BA_BASE_ADDR_LSB

#define SDRAMC_BA_BASE_ADDR_LSB   (0u)

SDRAMC_BANK_MODE

#define SDRAMC_BANK_MODE   (0x60u)

SDRAMC_BANK_MODE_LSB

#define SDRAMC_BANK_MODE_LSB   (0u)

SDRAMC_CAS_MODE

#define SDRAMC_CAS_MODE   (0x38u)

SDRAMC_CAS_MODE_LSB

#define SDRAMC_CAS_MODE_LSB   (0u)

SDRAMC_CAS_MODE_RD_NONE_DLY

#define SDRAMC_CAS_MODE_RD_NONE_DLY   (8u)

SDRAMC_CFG_CMD

#define SDRAMC_CFG_CMD   (0x6Cu)

SDRAMC_CFG_CMD_SELF_REFRESH

#define SDRAMC_CFG_CMD_SELF_REFRESH   BIT(0)

SDRAMC_CFG_PWR_DWN

#define SDRAMC_CFG_PWR_DWN   (0x70u)

SDRAMC_CFG_PWR_DWN_EN

#define SDRAMC_CFG_PWR_DWN_EN   BIT(0)

SDRAMC_CHIP_SELECT_COLOW_MODE_LSB

#define SDRAMC_CHIP_SELECT_COLOW_MODE_LSB   (2u)

SDRAMC_CHIP_SELECT_MODE

#define SDRAMC_CHIP_SELECT_MODE   (0x58u)

SDRAMC_CHIP_SELECT_MODE_LSB

#define SDRAMC_CHIP_SELECT_MODE_LSB   (0u)

SDRAMC_CTL_DATA_DEBUG

#define SDRAMC_CTL_DATA_DEBUG	(		format,
			...
	)

SDRAMC_DDR_DQS_SHIFT

#define SDRAMC_DDR_DQS_SHIFT   (0xC0u)

SDRAMC_DDR_DQS_SHIFT_GATE_FORCE_TIE1

#define SDRAMC_DDR_DQS_SHIFT_GATE_FORCE_TIE1   BIT(31)

SDRAMC_DDR_DQS_SHIFT_NUM0_LSB

#define SDRAMC_DDR_DQS_SHIFT_NUM0_LSB   (0u)

SDRAMC_DDR_DQS_SHIFT_NUM0NEG_LSB

#define SDRAMC_DDR_DQS_SHIFT_NUM0NEG_LSB   (16u)

SDRAMC_DDR_DQS_SHIFT_NUM1_LSB

#define SDRAMC_DDR_DQS_SHIFT_NUM1_LSB   (4u)

SDRAMC_DDR_DQS_SHIFT_NUM1NEG_LSB

#define SDRAMC_DDR_DQS_SHIFT_NUM1NEG_LSB   (20u)

SDRAMC_DDR_DQS_SHIFT_NUM2_LSB

#define SDRAMC_DDR_DQS_SHIFT_NUM2_LSB   (8u)

SDRAMC_DDR_DQS_SHIFT_NUM2NEG_LSB

#define SDRAMC_DDR_DQS_SHIFT_NUM2NEG_LSB   (24u)

SDRAMC_DDR_DQS_SHIFT_NUM3_LSB

#define SDRAMC_DDR_DQS_SHIFT_NUM3_LSB   (12u)

SDRAMC_DDR_DQS_SHIFT_NUM3NEG_LSB

#define SDRAMC_DDR_DQS_SHIFT_NUM3NEG_LSB   (28u)

SDRAMC_DLL0

#define SDRAMC_DLL0   (0x98u)

SDRAMC_DLL0_DLLEN

#define SDRAMC_DLL0_DLLEN   BIT(0)

SDRAMC_DLL0_OVRDEN

#define SDRAMC_DLL0_OVRDEN   BIT(8)

SDRAMC_DLL0_OVRDVAL_LSB

#define SDRAMC_DLL0_OVRDVAL_LSB   (9u)

SDRAMC_DLL0_REF0RSTV_LSB

#define SDRAMC_DLL0_REF0RSTV_LSB   (18u)

SDRAMC_DLL0_REFSEL1_LSB

#define SDRAMC_DLL0_REFSEL1_LSB   (16u)

SDRAMC_DLL0_REFUPDINT0_LSB

#define SDRAMC_DLL0_REFUPDINT0_LSB   (25u)

SDRAMC_DLL0_REFUPDINT1_LSB

#define SDRAMC_DLL0_REFUPDINT1_LSB   (28u)

SDRAMC_DLL0_SLVTGRT_LSB

#define SDRAMC_DLL0_SLVTGRT_LSB   (1u)

SDRAMC_DLL0_SLVUPDGATE

#define SDRAMC_DLL0_SLVUPDGATE   BIT(31)

SDRAMC_DLL1

#define SDRAMC_DLL1   (0x9Cu)

SDRAMC_DLL1_DLLEN

#define SDRAMC_DLL1_DLLEN   BIT(0)

SDRAMC_DLL1_OVRDEN

#define SDRAMC_DLL1_OVRDEN   BIT(8)

SDRAMC_DLL1_OVRDVAL_LSB

#define SDRAMC_DLL1_OVRDVAL_LSB   (9u)

SDRAMC_DLL1_REF0RSTV_LSB

#define SDRAMC_DLL1_REF0RSTV_LSB   (18u)

SDRAMC_DLL1_REFSEL1_LSB

#define SDRAMC_DLL1_REFSEL1_LSB   (16u)

SDRAMC_DLL1_REFUPDINT0_LSB

#define SDRAMC_DLL1_REFUPDINT0_LSB   (25u)

SDRAMC_DLL1_REFUPDINT1_LSB

#define SDRAMC_DLL1_REFUPDINT1_LSB   (28u)

SDRAMC_DLL1_SLVTGRT_LSB

#define SDRAMC_DLL1_SLVTGRT_LSB   (1u)

SDRAMC_DLL1_SLVUPDGATE

#define SDRAMC_DLL1_SLVUPDGATE   BIT(31)

SDRAMC_DLL2

#define SDRAMC_DLL2   (0xA0u)

SDRAMC_DLL2_DLLEN

#define SDRAMC_DLL2_DLLEN   BIT(0)

SDRAMC_DLL2_OVRDEN

#define SDRAMC_DLL2_OVRDEN   BIT(8)

SDRAMC_DLL2_OVRDVAL_LSB

#define SDRAMC_DLL2_OVRDVAL_LSB   (9u)

SDRAMC_DLL2_REF0RSTV_LSB

#define SDRAMC_DLL2_REF0RSTV_LSB   (18u)

SDRAMC_DLL2_REFSEL1_LSB

#define SDRAMC_DLL2_REFSEL1_LSB   (16u)

SDRAMC_DLL2_REFUPDINT0_LSB

#define SDRAMC_DLL2_REFUPDINT0_LSB   (25u)

SDRAMC_DLL2_REFUPDINT1_LSB

#define SDRAMC_DLL2_REFUPDINT1_LSB   (28u)

SDRAMC_DLL2_SLVTGRT_LSB

#define SDRAMC_DLL2_SLVTGRT_LSB   (1u)

SDRAMC_DLL2_SLVUPDGATE

#define SDRAMC_DLL2_SLVUPDGATE   BIT(31)

SDRAMC_DLL3

#define SDRAMC_DLL3   (0xA4u)

SDRAMC_DLL3_DLLEN

#define SDRAMC_DLL3_DLLEN   BIT(0)

SDRAMC_DLL3_OVRDEN

#define SDRAMC_DLL3_OVRDEN   BIT(8)

SDRAMC_DLL3_OVRDVAL_LSB

#define SDRAMC_DLL3_OVRDVAL_LSB   (9u)

SDRAMC_DLL3_REF0RSTV_LSB

#define SDRAMC_DLL3_REF0RSTV_LSB   (18u)

SDRAMC_DLL3_REFSEL1_LSB

#define SDRAMC_DLL3_REFSEL1_LSB   (16u)

SDRAMC_DLL3_REFUPDINT0_LSB

#define SDRAMC_DLL3_REFUPDINT0_LSB   (25u)

SDRAMC_DLL3_REFUPDINT1_LSB

#define SDRAMC_DLL3_REFUPDINT1_LSB   (28u)

SDRAMC_DLL3_SLVTGRT_LSB

#define SDRAMC_DLL3_SLVTGRT_LSB   (1u)

SDRAMC_DLL3_SLVUPDGATE

#define SDRAMC_DLL3_SLVUPDGATE   BIT(31)

SDRAMC_DLL_STATUS0

#define SDRAMC_DLL_STATUS0   (0xA8u)

SDRAMC_DLL_STATUS0_REFLOCK

#define SDRAMC_DLL_STATUS0_REFLOCK   BIT(0)

SDRAMC_DLL_STATUS0_REFSEL_LSB

#define SDRAMC_DLL_STATUS0_REFSEL_LSB   (1u)

SDRAMC_DLL_STATUS0_SLVLOCK

#define SDRAMC_DLL_STATUS0_SLVLOCK   BIT(8)

SDRAMC_DLL_STATUS0_SLVSEL_LSB

#define SDRAMC_DLL_STATUS0_SLVSEL_LSB   (9u)

SDRAMC_DLL_STATUS1

#define SDRAMC_DLL_STATUS1   (0xACu)

SDRAMC_DLL_STATUS1_REFLOCK

#define SDRAMC_DLL_STATUS1_REFLOCK   BIT(0)

SDRAMC_DLL_STATUS1_REFSEL_LSB

#define SDRAMC_DLL_STATUS1_REFSEL_LSB   (1u)

SDRAMC_DLL_STATUS1_SLVLOCK

#define SDRAMC_DLL_STATUS1_SLVLOCK   BIT(8)

SDRAMC_DLL_STATUS1_SLVSEL_LSB

#define SDRAMC_DLL_STATUS1_SLVSEL_LSB   (9u)

SDRAMC_DLL_STATUS2

#define SDRAMC_DLL_STATUS2   (0xB0u)

SDRAMC_DLL_STATUS2_REFLOCK

#define SDRAMC_DLL_STATUS2_REFLOCK   BIT(0)

SDRAMC_DLL_STATUS2_REFSEL_LSB

#define SDRAMC_DLL_STATUS2_REFSEL_LSB   (1u)

SDRAMC_DLL_STATUS2_SLVLOCK

#define SDRAMC_DLL_STATUS2_SLVLOCK   BIT(8)

SDRAMC_DLL_STATUS2_SLVSEL_LSB

#define SDRAMC_DLL_STATUS2_SLVSEL_LSB   (9u)

SDRAMC_DLL_STATUS3

#define SDRAMC_DLL_STATUS3   (0xB4u)

SDRAMC_DLL_STATUS3_REFLOCK

#define SDRAMC_DLL_STATUS3_REFLOCK   BIT(0)

SDRAMC_DLL_STATUS3_REFSEL_LSB

#define SDRAMC_DLL_STATUS3_REFSEL_LSB   (1u)

SDRAMC_DLL_STATUS3_SLVLOCK

#define SDRAMC_DLL_STATUS3_SLVLOCK   BIT(8)

SDRAMC_DLL_STATUS3_SLVSEL_LSB

#define SDRAMC_DLL_STATUS3_SLVSEL_LSB   (9u)

SDRAMC_DQS_QE_SET

#define SDRAMC_DQS_QE_SET   (0xB8u)

SDRAMC_DQS_QE_SET_EN

#define SDRAMC_DQS_QE_SET_EN   BIT(0)

SDRAMC_DQS_QE_SET_VAL

#define SDRAMC_DQS_QE_SET_VAL   BIT(1)

SDRAMC_DRAM_DCNT

#define SDRAMC_DRAM_DCNT   (0x94u)

SDRAMC_DRAM_DCNT_LSB

#define SDRAMC_DRAM_DCNT_LSB   (0u)

SDRAMC_DRAM_RCNT

#define SDRAMC_DRAM_RCNT   (0x8Cu)

SDRAMC_DRAM_RCNT_LSB

#define SDRAMC_DRAM_RCNT_LSB   (0u)

SDRAMC_DRAM_WCNT

#define SDRAMC_DRAM_WCNT   (0x90u)

SDRAMC_DRAM_WCNT_LSB

#define SDRAMC_DRAM_WCNT_LSB   (0u)

SDRAMC_EXTEND_CONTROL

#define SDRAMC_EXTEND_CONTROL   (0x40u)

SDRAMC_EXTEND_CONTROL_A13_A2_LSB

#define SDRAMC_EXTEND_CONTROL_A13_A2_LSB   (16u)

SDRAMC_EXTEND_CONTROL_DLL_EN

#define SDRAMC_EXTEND_CONTROL_DLL_EN   (0u)

SDRAMC_EXTEND_CONTROL_DRIVE_STRENGTH

#define SDRAMC_EXTEND_CONTROL_DRIVE_STRENGTH   (1u)

SDRAMC_FLOW_CTRL

#define SDRAMC_FLOW_CTRL   (0x24u)

SDRAMC_FLOW_CTRL_AR_MASK

#define SDRAMC_FLOW_CTRL_AR_MASK   BIT(8)

SDRAMC_FLOW_CTRL_AR_SET

#define SDRAMC_FLOW_CTRL_AR_SET   BIT(0)

SDRAMC_FLOW_CTRL_AR_STATUS

#define SDRAMC_FLOW_CTRL_AR_STATUS   BIT(16)

SDRAMC_FLOW_CTRL_AW_MASK

#define SDRAMC_FLOW_CTRL_AW_MASK   BIT(9)

SDRAMC_FLOW_CTRL_AW_SET

#define SDRAMC_FLOW_CTRL_AW_SET   BIT(1)

SDRAMC_FLOW_CTRL_AW_STATUS

#define SDRAMC_FLOW_CTRL_AW_STATUS   BIT(17)

SDRAMC_FLOW_CTRL_B_MASK

#define SDRAMC_FLOW_CTRL_B_MASK   BIT(11)

SDRAMC_FLOW_CTRL_B_SET

#define SDRAMC_FLOW_CTRL_B_SET   BIT(3)

SDRAMC_FLOW_CTRL_B_STATUS

#define SDRAMC_FLOW_CTRL_B_STATUS   BIT(19)

SDRAMC_FLOW_CTRL_RD_MASK

#define SDRAMC_FLOW_CTRL_RD_MASK   BIT(12)

SDRAMC_FLOW_CTRL_RD_SET

#define SDRAMC_FLOW_CTRL_RD_SET   BIT(4)

SDRAMC_FLOW_CTRL_RD_STATUS

#define SDRAMC_FLOW_CTRL_RD_STATUS   BIT(20)

SDRAMC_FLOW_CTRL_RETURN_MASK

#define SDRAMC_FLOW_CTRL_RETURN_MASK   BIT(14)

SDRAMC_FLOW_CTRL_RETURN_SET

#define SDRAMC_FLOW_CTRL_RETURN_SET   BIT(6)

SDRAMC_FLOW_CTRL_RETURN_STATUS

#define SDRAMC_FLOW_CTRL_RETURN_STATUS   BIT(22)

SDRAMC_FLOW_CTRL_RR_SCH_MASK

#define SDRAMC_FLOW_CTRL_RR_SCH_MASK   BIT(24)

SDRAMC_FLOW_CTRL_RR_SCH_SET

#define SDRAMC_FLOW_CTRL_RR_SCH_SET   BIT(23)

SDRAMC_FLOW_CTRL_RR_SCH_STATUS

#define SDRAMC_FLOW_CTRL_RR_SCH_STATUS   BIT(25)

SDRAMC_FLOW_CTRL_SCH_MASK

#define SDRAMC_FLOW_CTRL_SCH_MASK   BIT(13)

SDRAMC_FLOW_CTRL_SCH_SET

#define SDRAMC_FLOW_CTRL_SCH_SET   BIT(5)

SDRAMC_FLOW_CTRL_SCH_STATUS

#define SDRAMC_FLOW_CTRL_SCH_STATUS   BIT(21)

SDRAMC_FLOW_CTRL_WR_MASK

#define SDRAMC_FLOW_CTRL_WR_MASK   BIT(10)

SDRAMC_FLOW_CTRL_WR_SET

#define SDRAMC_FLOW_CTRL_WR_SET   BIT(2)

SDRAMC_FLOW_CTRL_WR_STATUS

#define SDRAMC_FLOW_CTRL_WR_STATUS   BIT(18)

SDRAMC_INIT

#define SDRAMC_INIT   (0x0u)

SDRAMC_INIT_CFG_MRS

#define SDRAMC_INIT_CFG_MRS   BIT(1)

SDRAMC_INIT_CLK_OUT_EN

#define SDRAMC_INIT_CLK_OUT_EN   BIT(4)

SDRAMC_INIT_DDR_ASYNC_FLUSH_B

#define SDRAMC_INIT_DDR_ASYNC_FLUSH_B   BIT(2)

SDRAMC_INIT_DONE

#define SDRAMC_INIT_DONE   BIT(31)

SDRAMC_INIT_SDR_SYNC_FLUSH

#define SDRAMC_INIT_SDR_SYNC_FLUSH   BIT(3)

SDRAMC_INIT_SOFT_RESET

#define SDRAMC_INIT_SOFT_RESET   BIT(8)

SDRAMC_INIT_START

#define SDRAMC_INIT_START   BIT(0)

SDRAMC_INIT_WAIT_CONT

#define SDRAMC_INIT_WAIT_CONT   (0x50u)

SDRAMC_INIT_WAIT_CONT_200US

#define SDRAMC_INIT_WAIT_CONT_200US   (0u)

SDRAMC_INTERRUPT

#define SDRAMC_INTERRUPT   (0x28u)

SDRAMC_INTERRUPT_EN

#define SDRAMC_INTERRUPT_EN   (0x2Cu)

SDRAMC_MRD

#define SDRAMC_MRD   (0x68u)

SDRAMC_MRD_TMR_LSB

#define SDRAMC_MRD_TMR_LSB   (0u)

SDRAMC_NS_2_TICKS

#define SDRAMC_NS_2_TICKS	(		hz,
			ns
	)		(((hz) / 10000u * (ns) + 100000u) / 100000u)

SDRAMC_OPERATING_MODE

#define SDRAMC_OPERATING_MODE   (0x3Cu)

SDRAMC_OPERATING_MODE_A13_A9_LSB

#define SDRAMC_OPERATING_MODE_A13_A9_LSB   (16u)

SDRAMC_OPERATING_MODE_LSB

#define SDRAMC_OPERATING_MODE_LSB   (0u)

SDRAMC_RETURN_FC_GAP

#define SDRAMC_RETURN_FC_GAP   (0x5Cu)

SDRAMC_RETURN_FC_GAP_LSB

#define SDRAMC_RETURN_FC_GAP_LSB   (0u)

SDRAMC_SCH_WEIGHT

#define SDRAMC_SCH_WEIGHT   (0x30u)

SDRAMC_SCH_WEIGHT_BANKIDLE_W_LSB

#define SDRAMC_SCH_WEIGHT_BANKIDLE_W_LSB   (8u)

SDRAMC_SCH_WEIGHT_PAGE_W_LSB

#define SDRAMC_SCH_WEIGHT_PAGE_W_LSB   (16u)

SDRAMC_SCH_WEIGHT_QOS_W_LSB

#define SDRAMC_SCH_WEIGHT_QOS_W_LSB   (0u)

SDRAMC_SCH_WEIGHT_RW_W_LSB

#define SDRAMC_SCH_WEIGHT_RW_W_LSB   (24u)

SDRAMC_SDR_DQS_SHIFT

#define SDRAMC_SDR_DQS_SHIFT   (0xC4u)

SDRAMC_SDR_DQS_SHIFT_NUM_LSB

#define SDRAMC_SDR_DQS_SHIFT_NUM_LSB   (0u)

SDRAMC_TIMING_CNT_200CYCLE_LSB

#define SDRAMC_TIMING_CNT_200CYCLE_LSB   (16u)

SDRAMC_TIMING_REGS_PART1

#define SDRAMC_TIMING_REGS_PART1   (0x44u)

SDRAMC_TIMING_REGS_PART2

#define SDRAMC_TIMING_REGS_PART2   (0x48u)

SDRAMC_TIMING_REGS_PART3

#define SDRAMC_TIMING_REGS_PART3   (0x4Cu)

SDRAMC_TIMING_REGS_PART4

#define SDRAMC_TIMING_REGS_PART4   (0x64u)

SDRAMC_TIMING_TRAS_MAX_LSB

#define SDRAMC_TIMING_TRAS_MAX_LSB   (0u)

SDRAMC_TIMING_TRAS_MIN_LSB

#define SDRAMC_TIMING_TRAS_MIN_LSB   (0u)

SDRAMC_TIMING_TRC_LSB

#define SDRAMC_TIMING_TRC_LSB   (8u)

SDRAMC_TIMING_TRCD_LSB

#define SDRAMC_TIMING_TRCD_LSB   (24u)

SDRAMC_TIMING_TREFI_LSB

#define SDRAMC_TIMING_TREFI_LSB   (0u)

SDRAMC_TIMING_TRFC_LSB

#define SDRAMC_TIMING_TRFC_LSB   (16u)

SDRAMC_TIMING_TRP_LSB

#define SDRAMC_TIMING_TRP_LSB   (0u)

SDRAMC_TIMING_TRRD_LSB

#define SDRAMC_TIMING_TRRD_LSB   (8u)

SDRAMC_TIMING_TWR_LSB

#define SDRAMC_TIMING_TWR_LSB   (16u)

SDRAMC_TIMING_TWTR_LSB

#define SDRAMC_TIMING_TWTR_LSB   (24u)

SDRAMC_TIMING_TXSRD_LSB

#define SDRAMC_TIMING_TXSRD_LSB   (16u)

WCMD_ERR_INT_SET

#define WCMD_ERR_INT_SET   (0x74u)

WCMD_ERR_INT_SET_CLR

#define WCMD_ERR_INT_SET_CLR   BIT(0)

Typedef Documentation

gate_record_s

typedef struct gate_record gate_record_s

gate value record

sd_para_s

typedef struct sd_para sd_para_s

sdramc row column cs bank configuration

sdram_comm_config_t

typedef struct sdram_comm_config sdram_comm_config_t

sdramc commom configuration

sdram_config_t

typedef struct sdram_config sdram_config_t

sdramc private configuration

Enumeration Type Documentation

sdrv_sdramc_error

enum sdrv_sdramc_error

sdramc status error code.

Enumerator
SDRV_STATUS_SDRAMC_DLL_LOCK_ERR
SDRV_STATUS_SDRAMC_DLL_WAYS_ERR
SDRV_STATUS_SDRAMC_SET_DDR_CLK_ERR

Function Documentation

sdrv_get_sd_para()

struct sd_para * sdrv_get_sd_para

(

void

)

get sdram para

Returns

[out] sdram para

sdrv_sdramc_init()

int32_t sdrv_sdramc_init	(	addr_t	base,
		sdram_config_t *	conf
	)

sdramc init main function

1.config sdr/ddr register according to different mode 2.training and config dll value for sdr/ddr mode

Parameters

[in]	base	sdramc base register address
[in]	conf	sdramc config parameters

Returns

int32_t

Return values

0	success
other	failed

sdrv_set_sd_para()

void sdrv_set_sd_para

(

struct sd_para *

cs

)

save sdram para

Parameters

[in]

cs

sdram info

Variable Documentation

cs_p

struct sd_para cs_p

extern