sdrv_dma.h File Reference

#include <part.h>
#include "common.h"
#include "../source/dma/sdrv_dma_regdef.h"
#include "compiler.h"
#include "regs_base.h"
#include "sdrv_common.h"

Go to the source code of this file.

Data Structures
struct	sdrv_dma_mux_param_t
struct	sdrv_dma_linklist_descriptor_t
struct	sdrv_dma
struct	sdrv_dma_channel_config_t
struct	sdrv_dma_channel_t

Enumerations
enum	sdrv_dma_bus_width_e { SDRV_DMA_BUSWIDTH_1_BYTE = 1 , SDRV_DMA_BUSWIDTH_2_BYTES = 2 , SDRV_DMA_BUSWIDTH_4_BYTES = 4 , SDRV_DMA_BUSWIDTH_8_BYTES = 8 }
enum	sdrv_dma_burst_len_e {   SDRV_DMA_BURST_LEN_1 = 0 , SDRV_DMA_BURST_LEN_2 , SDRV_DMA_BURST_LEN_3 , SDRV_DMA_BURST_LEN_4 ,   SDRV_DMA_BURST_LEN_5 , SDRV_DMA_BURST_LEN_6 , SDRV_DMA_BURST_LEN_7 , SDRV_DMA_BURST_LEN_8 ,   SDRV_DMA_BURST_LEN_9 , SDRV_DMA_BURST_LEN_10 , SDRV_DMA_BURST_LEN_11 , SDRV_DMA_BURST_LEN_12 ,   SDRV_DMA_BURST_LEN_13 , SDRV_DMA_BURST_LEN_14 , SDRV_DMA_BURST_LEN_15 , SDRV_DMA_BURST_LEN_16 ,   SDRV_DMA_BURST_LEN_UNDEFINED }
enum	sdrv_dma_port_sel_e { SDRV_DMA_PORT_AXI64 = 0 , SDRV_DMA_PORT_AHB32 , SDRV_DMA_PROT_NOT_DEFINED }
enum	sdrv_dma_buffer_mode_e { SDRV_DMA_SINGLE_BUFFER = 0 , SDRV_DMA_DOUBLE_BUFFER , SDRV_DMA_CIRCULAR_BUFFER , SDRV_DMA_2D_BUFFER , SDRV_DMA_BUFFER_NOT_DEFINED }
enum	sdrv_dma_switch_event_ctrl_e { SDRV_DMA_SWT_EVT_CTL_STOP_WTH_INT = 0 , SDRV_DMA_SWT_EVT_CTL_SUSPEND_WTH_INT , SDRV_DMA_SWT_EVT_CTL_CONTINUE_WTH_INT , SDRV_DMA_SWT_EVT_CTL_CONTINUE_WTHOUT_INT , SDRV_DMA_SWT_EVT_CTL_UNDEFINED }
enum	sdrv_dma_trigger_mode_e { SDRV_DMA_TRIGGER_BY_HARDWARE = 0 , SDRV_DMA_TRIGGER_BY_SOFTWARE , SDRV_DMA_TRIGGER_BY_GTIMER , SDRV_DMA_TRIGGER_BY_INTERNAL_EVENT , SDRV_DMA_TRIGGER_MODE_NOT_DEFINED }
enum	sdrv_dma_loop_mode_e { SDRV_DMA_LOOP_MODE_0 = 0 , SDRV_DMA_LOOP_MODE_1 , SDRV_DMA_LOOP_MODE_2 , SDRV_DMA_LOOP_MODE_UNDEFINED }

Functions
static sdrv_dma_channel_ctrl_t *	sdrv_dma_get_channel_ctrl_base (sdrv_dma_ctrl_t *dma_base, sdrv_dma_channel_id_e channel)
static void	sdrv_dma_set_channel_sw_handshake (sdrv_dma_channel_ctrl_t *channel_base)
static void	sdrv_dma_set_channel_muxid (sdrv_dma_ctrl_t *dma_base, sdrv_dma_channel_id_e channel, uint32_t mux_id)
static void	sdrv_dma_set_channel_rd_outstanding (sdrv_dma_ctrl_t *dma_base, sdrv_dma_channel_id_e channel, uint8_t value)
static void	sdrv_dma_set_channel_wr_outstanding (sdrv_dma_ctrl_t *dma_base, sdrv_dma_channel_id_e channel, uint8_t value)
static void	sdrv_dma_set_channel_interrupt (sdrv_dma_ctrl_t *dma_base, sdrv_dma_channel_id_e channel, uint32_t int_type)
static void	sdrv_dma_reset_core_int_status (sdrv_dma_ctrl_t *dma_base)
static void	sdrv_dma_reset_fifo (sdrv_dma_ctrl_t *dma_base)
static void	sdrv_dma_set_channel_status (sdrv_dma_channel_ctrl_t *channel_base, sdrv_dma_channel_status_e status)
void	sdrv_dma_init_dmac (paddr_t base)
status_t	sdrv_dma_create_instance (sdrv_dma_t *dma_instance, paddr_t base)
status_t	sdrv_dma_init_channel_config (sdrv_dma_channel_config_t *config, sdrv_dma_t *instance)
status_t	sdrv_dma_init_channel (sdrv_dma_channel_t *channel, const sdrv_dma_channel_config_t *config)
status_t	sdrv_dma_start_channel_xfer (sdrv_dma_channel_t *channel)
status_t	sdrv_dma_stop_channel_xfer (sdrv_dma_channel_t *channel)
status_t	sdrv_dma_deinit_channel (sdrv_dma_channel_t *channel)
status_t	sdrv_dma_init_linklist_entry (sdrv_dma_linklist_descriptor_t *desc, const sdrv_dma_channel_config_t *config)
status_t	sdrv_dma_set_channel_source_address (sdrv_dma_channel_t *channel, paddr_t addr)
void	sdrv_dma_set_channel_buffer_size (sdrv_dma_channel_t *channel, sdrv_dma_loop_mode_e loop_mode, uint32_t total_size, uint32_t loop_size)
status_t	sdrv_dma_set_channel_destination_address (sdrv_dma_channel_t *channel, paddr_t addr)
status_t	sdrv_dma_set_channel_xfer_bytes (sdrv_dma_channel_t *channel, uint32_t xfer_bytes)
uint32_t	sdrv_dma_get_channel_xfer_bytes (sdrv_dma_channel_t *channel)
status_t	sdrv_dma_clear_channel_xfer_bytes (sdrv_dma_channel_t *channel)
uint32_t	sdrv_dma_get_channel_xfer_status (sdrv_dma_channel_t *channel)
status_t	sdrv_dma_clear_channel_xfer_status (sdrv_dma_channel_t *channel, uint32_t status)

Detailed Description

Copyright

Copyright (c) 2022 Semidrive Semiconductor. All rights reserved.

Macro Definition Documentation

SDRV_DMA_LIMIT_TIMES

#define SDRV_DMA_LIMIT_TIMES   5

SDRV_DMA_LP0_LPSIZE_MAX

#define SDRV_DMA_LP0_LPSIZE_MAX   (0x00FFFFFF)

SDRV_DMA_LP1_LP_COUNT_MAX

#define SDRV_DMA_LP1_LP_COUNT_MAX   (0X00000FFF)

SDRV_DMA_LP1_LPSIZE_MAX

#define SDRV_DMA_LP1_LPSIZE_MAX   (0X00000FFF)

SDRV_DMA_LP2_LPSIZE

#define SDRV_DMA_LP2_LPSIZE

(

n

)

((__builtin_ffs(n) - 1) & 0xf)

SDRV_DMA_LP2_LPSIZE_MAX

#define SDRV_DMA_LP2_LPSIZE_MAX   (0x000FFFFF)

SDRV_DMA_LP2_TT

#define SDRV_DMA_LP2_TT

(

n

)

((((n)-1) << 4) & 0xfffff0)

SDRV_DMA_MAD_CRC_REGISTERS

#define SDRV_DMA_MAD_CRC_REGISTERS   (7)

Typedef Documentation

sdrv_dma_irq_handler

typedef void(* sdrv_dma_irq_handler) (uint32_t status, uint32_t param, void *context)

DMA channel interrupt callback type.

sdrv_dma_t

typedef struct sdrv_dma sdrv_dma_t

DMA controller structure.

Enumeration Type Documentation

anonymous enum

anonymous enum

DMA status return code.

Enumerator
SDRV_DMA_INVALID_CHANNEL_ID
SDRV_DMA_UNSUPPORT_CONFIG
SDRV_DMA_INVALID_MUXID

sdrv_dma_addr_inc_e

enum sdrv_dma_addr_inc_e

DMA channel transfer address increase mode.

Enumerator
SDRV_DMA_ADDR_INC	Automatically increase DMA source or target address after each transaction, usually for memory buffers. Do not increase DMA source or target address after each transaction, usually for device registers.
SDRV_DMA_ADDR_NO_INC

sdrv_dma_buffer_mode_e

enum sdrv_dma_buffer_mode_e

The buffer mode used by different application scenarios.

MAD (Memory access description) - one transaction configuration include source address, target address,transfer mode,transfer length,link address,etc..

Buffer mode is related to transfer mode and loop mode (For details see sdrv_dma_loop_mode_e), when Single Mode selected,buffer mode should be set to SINGLE_BUFFER or 2D_BUFFER. when Continuous Mode selected,buffer mode should be set to DOUBLE_BUFFER or CIRCULAR_BUFFER.

Enumerator
SDRV_DMA_SINGLE_BUFFER	single buffer should be used with Single Mode. When the entire length data is transferred, DMA is terminated. double buffer should be used with Continuous Mode. DMA need two memory areas (IRAM, SDRAM), one memory address is filled in source address of MAD and the another is filled in link address of MAD. When one memory area is transferred,the another continues to be transferred. Set STATUS_ABORT or STATUS_STOP if you want to terminate DMA transfer.
SDRV_DMA_DOUBLE_BUFFER	circular buffer should be used with Continuous Mode. When the entire length data is transferred, DMA will continue to transfer from source address of MAD. Set STATUS_ABORT or STATUS_STOP if you want to terminate DMA transfer.
SDRV_DMA_CIRCULAR_BUFFER	2d buffer is similar to single buffer. The difference is that the entire length data can be transmitted at one handshake request regardless of LOOP_MODE_x. (For details see sdrv_dma_loop_mode_e)
SDRV_DMA_2D_BUFFER
SDRV_DMA_BUFFER_NOT_DEFINED

sdrv_dma_burst_len_e

enum sdrv_dma_burst_len_e

DMA channel burst length for each transaction.

This is actually the burst length, i.e. AXI AWLEN and ARLEN,for DMA burst transactions. for peripheral transactions,you should set burst length according to peripheral FIFO LEVEL.

Enumerator
SDRV_DMA_BURST_LEN_1	1 x bus_width per transaction
SDRV_DMA_BURST_LEN_2	2 x bus_width per transaction
SDRV_DMA_BURST_LEN_3	3 x bus_width per transaction
SDRV_DMA_BURST_LEN_4	4 x bus_width per transaction
SDRV_DMA_BURST_LEN_5	5 x bus_width per transaction
SDRV_DMA_BURST_LEN_6	6 x bus_width per transaction
SDRV_DMA_BURST_LEN_7	7 x bus_width per transaction
SDRV_DMA_BURST_LEN_8	8 x bus_width per transaction
SDRV_DMA_BURST_LEN_9	9 x bus_width per transaction
SDRV_DMA_BURST_LEN_10	10 x bus_width per transaction
SDRV_DMA_BURST_LEN_11	11 x bus_width per transaction
SDRV_DMA_BURST_LEN_12	12 x bus_width per transaction
SDRV_DMA_BURST_LEN_13	13 x bus_width per transaction
SDRV_DMA_BURST_LEN_14	14 x bus_width per transaction
SDRV_DMA_BURST_LEN_15	15 x bus_width per transaction
SDRV_DMA_BURST_LEN_16	16 x bus_width per transaction
SDRV_DMA_BURST_LEN_UNDEFINED

sdrv_dma_bus_width_e

enum sdrv_dma_bus_width_e

DMA channel data width for each transaction.

This is actually the burst size, i.e., AXI AWSIZE and ARSIZE, for DMA transactions. For memory to memory transactions, use 8 bytes width to get better throughput. However for peripheral transactions, you should set bus width according to hardware register data width.

Enumerator
SDRV_DMA_BUSWIDTH_1_BYTE	1 byte per transaction
SDRV_DMA_BUSWIDTH_2_BYTES	2 bytes per transaction
SDRV_DMA_BUSWIDTH_4_BYTES	4 bytes per transaction
SDRV_DMA_BUSWIDTH_8_BYTES	8 bytes per transaction

sdrv_dma_channel_id_e

enum sdrv_dma_channel_id_e

DMA Channel ID.

Enumerator
SDRV_DMA_CHANNEL_INVALID
SDRV_DMA_CHANNEL_0
SDRV_DMA_CHANNEL_1
SDRV_DMA_CHANNEL_2
SDRV_DMA_CHANNEL_3
SDRV_DMA_CHANNEL_4
SDRV_DMA_CHANNEL_5
SDRV_DMA_CHANNEL_6
SDRV_DMA_CHANNEL_7
SDRV_DMA_CHANNEL_8
SDRV_DMA_CHANNEL_9
SDRV_DMA_CHANNEL_10
SDRV_DMA_CHANNEL_11
SDRV_DMA_CHANNEL_12
SDRV_DMA_CHANNEL_13
SDRV_DMA_CHANNEL_14
SDRV_DMA_CHANNEL_15
SDRV_DMA_CHANNEL_16
SDRV_DMA_CHANNEL_17
SDRV_DMA_CHANNEL_18
SDRV_DMA_CHANNEL_19
SDRV_DMA_CHANNEL_20
SDRV_DMA_CHANNEL_21
SDRV_DMA_CHANNEL_22
SDRV_DMA_CHANNEL_23

sdrv_dma_channel_status_e

enum sdrv_dma_channel_status_e

DMA channel current status.

Enumerator
SDRV_DMA_CH_STATUS_STOP	transfer stopped
SDRV_DMA_CH_STATUS_FLUSH	next MAD config executed directly
SDRV_DMA_CH_STATUS_REQ_FLUSH	periphal handshake request cleared
SDRV_DMA_CH_STATUS_HALT	transfer halted
SDRV_DMA_CH_STATUS_ENABLE	transfer enabled
SDRV_DMA_CH_STATUS_RESUME	transfer resumed
SDRV_DMA_CH_STATUS_ABORT	transfer aborted

sdrv_dma_channle_ctrl_fsm_e

enum sdrv_dma_channle_ctrl_fsm_e

DMA channel control state machine status.

Enumerator
SDRV_DMA_CH_FSM_IDLE	DMA channel idle state
SDRV_DMA_CH_FSM_MAD_CHECK	DMA channel mad check state
SDRV_DMA_CH_FSM_POLL_OPD2	DMA channel poll opd2 state
SDRV_DMA_CH_FSM_DATA_TRANSFER	DMA channel data_transfer state
SDRV_DMA_CH_FSM_STOP	DMA channel stop state
SDRV_DMA_CH_FSM_HALT	DMA channel halt state
SDRV_DMA_CH_FSM_DONE	DMA channel done state

sdrv_dma_data_crc_mode_e

enum sdrv_dma_data_crc_mode_e

DMA Data CRC.

Enumerator
SDRV_DMA_NO_DATA_CRC	DMA Data crc disable
SDRV_DMA_DATA_CRC_SENSE	DMA Data crc calculated CRC value is stored in OPD
SDRV_DMA_DATA_CRC_VERIFY_WITH_OPD	DMA Data crc verification with OPD, mismatch CRC verification error interupt is generated
SDRV_DMA_DATA_CRC_VERIFY_BETWEEN_WR_RD	DMA Data crc verification between writing data and reading data, mismatch CRC verification error interupt is generated

sdrv_dma_data_crc_sel_e

enum sdrv_dma_data_crc_sel_e

DMA Data CRC Sel.

Enumerator
CRC32_802P3
CRC16_CCITT
CRC8_CCITT

sdrv_dma_interrupt_type_e

enum sdrv_dma_interrupt_type_e

DMA channel interrupt types.

Enumerator
SDRV_DMA_HANDSHAKE_E2E_COR_ERR	DMA Handshake e2e check correctable error
SDRV_DMA_HANDSHAKE_E2E_UNCOR_ERR	DMA Handshake e2e check uncorrectable error
SDRV_DMA_CHANNEL_FIFO_ECC_COR_ERR	Channel FIFO data ecc check correctable error
SDRV_DMA_CHANNEL_FIFO_ECC_UNCOR_ERR	Channel FIFO data ecc check uncorrectable error
SDRV_DMA_AHB_READ_ERR	AHB read response error
SDRV_DMA_AHB_WRITE_ERR	AHB write response error
SDRV_DMA_AXI_READ_ERR	AXI read response error
SDRV_DMA_AXI_WRITE_ERR	AXI write response error
SDRV_DMA_CHANNEL_LINK_ERR	Channel link error
SDRV_DMA_MAD_CRC_ERR	MAD crc error
SDRV_DMA_FIREWALL_RD_ERR	Firewall protection read error
SDRV_DMA_FIREWALL_WR_ERR	Firewall protection write error
SDRV_DMA_DATA_CRC_ERR	Data crc error
SDRV_DMA_PATTERN_DETECTED	Pattern detected DMA channel all MAD transfer completed
SDRV_DMA_LAST_MAD_DONE	DMA channel every MAD transfer completed (actually for Continuous and Liklist mode).
SDRV_DMA_EVERY_MAD_DONE
SDRV_DMA_CH_STOP	DMA channel stop
SDRV_DMA_CH_FLUSH	DMA channel flush
SDRV_DMA_CH_REQ_FLUSH	DMA channel requst flush DMA channel transfer halted
SDRV_DMA_CH_HALT	DMA channel transfer aborted
SDRV_DMA_CH_ABORT
SDRV_DMA_REQ_TIMEOUT	The handshake request timeout
SDRV_DMA_SWITCH_EVENT	In the loop mode enable with total size unfixed DMA channel handshake request completed
SDRV_DMA_HS_COMP
SDRV_DMA_PATTERN_POLL_MISMACTCH	In the pattern mode with 3'b101 or 3'b110, The pattern status for pattern poll mismatch
SDRV_DMA_AXI_OUTSTANDING_UTID_ERR	AXI read or write outstanding UTID error
SDRV_DMA_PROGRAMING_SEQUENCE_ERR	DMA programing sequence error

sdrv_dma_linklist_type_e

enum sdrv_dma_linklist_type_e

DMA channel linklist mad types.

Enumerator
SDRV_DMA_LINKLIST_NORMAL_MAD	DMA channel middle MAD DMA channel first MAD
SDRV_DMA_LINKLIST_FIRST_MAD	DMA channel last MAD
SDRV_DMA_LINKLIST_LAST_MAD

sdrv_dma_loop_mode_e

enum sdrv_dma_loop_mode_e

DMA channel transfer data mode in one handshake.

LOOP_MODE_0: when one handshake request, DMA transfers the entire length data then terminated according to MAD. LOOP_MODE_1: DMA transfers the specified length (burst length x bus_width) data through one handshake request. LOOP_MODE_2: DMA transfers the specified length (power of 2) data through one handshake request.

Enumerator
SDRV_DMA_LOOP_MODE_0	entire length data transaction
SDRV_DMA_LOOP_MODE_1	burst length data transaction
SDRV_DMA_LOOP_MODE_2	power of 2 length data transaction
SDRV_DMA_LOOP_MODE_UNDEFINED

sdrv_dma_mad_crc_mode_e

enum sdrv_dma_mad_crc_mode_e

DMA MAD CRC.

Enumerator
SDRV_DMA_NO_MAD_CRC	DMA MAD CRC Disable
SDRV_DMA_CHECK_CURR_MAD	DMA MAD CRC Check current mad
SDRV_DMA_CHECK_CURR_MAD_AND_PREVIOUS	DMA MAD CRC check LADR of previous MAD and current MAD(Except LADR of current MAD)

sdrv_dma_mux_direction_e

enum sdrv_dma_mux_direction_e

DMA channel mux direction.

Enumerator
SDRV_DMA_MUX_RD	only peripheral to memory
SDRV_DMA_MUX_WR	only memory to peripheral both peripheral to memory and memory to peripheral
SDRV_DMA_MUX_BOTH

sdrv_dma_port_sel_e

enum sdrv_dma_port_sel_e

The master port used by DMA source and target ports.

The DMA controller as a bus master, has both AXI64 port (for memory access) and AHB32 master port (for device register access). You can configure DMA channels to use different ports for different source and target addresses.

Enumerator
SDRV_DMA_PORT_AXI64	The AXI64 port, used when the source or target buffer is in normal memory (IRAM, SDRAM). The AHB32 port, used when the source or target buffer is peripheral register.
SDRV_DMA_PORT_AHB32
SDRV_DMA_PROT_NOT_DEFINED

sdrv_dma_status_e

enum sdrv_dma_status_e

DMA channel transfer status.

Enumerator
SDRV_DMA_COMPLETED	DMA channel will not accept requests
SDRV_DMA_BLOCK_DONE	DMA channel transfer every block done
SDRV_DMA_IN_PROGRESS	DMA channel in transmission
SDRV_DMA_PAUSED	DMA channel transfer paused
SDRV_DMA_ERR	DMA channel transfer error
SDRV_DMA_PENDING	DMA channel transfer pending

sdrv_dma_switch_event_ctrl_e

enum sdrv_dma_switch_event_ctrl_e

Hardware control after MAD completed just for LOOP_MODE_1.

When one transaction is completed according to MAD, DMA will trigger different control.

Enumerator
SDRV_DMA_SWT_EVT_CTL_STOP_WTH_INT	DMA will be stopped and trigger interrupt when MAD done. DMA will be halted and trigger interrupt when MAD done. If you need to continue to use it, you need to configure the resume register.
SDRV_DMA_SWT_EVT_CTL_SUSPEND_WTH_INT	DMA will be continued and trigger interrupt when MAD done. Such as linklist mode.
SDRV_DMA_SWT_EVT_CTL_CONTINUE_WTH_INT	DMA will be continued and not trigger interrupt when MAD done. Such as linklist mode.
SDRV_DMA_SWT_EVT_CTL_CONTINUE_WTHOUT_INT
SDRV_DMA_SWT_EVT_CTL_UNDEFINED

sdrv_dma_trigger_mode_e

enum sdrv_dma_trigger_mode_e

DMA channel transfer triggered by which mode.

Select appropriate trigger mode according to transfer type and transfer mode. Hardware trigger actually for peripheral transactions, Software trigger actually for memory transactions,Gtimer trigger actually use DMA internal timer for period transactions, Internal event trigger actually for linklist transactions.

Enumerator
SDRV_DMA_TRIGGER_BY_HARDWARE	for peripheral transaction
SDRV_DMA_TRIGGER_BY_SOFTWARE	for memory transaction
SDRV_DMA_TRIGGER_BY_GTIMER	for period transaction
SDRV_DMA_TRIGGER_BY_INTERNAL_EVENT	for linklist transaction
SDRV_DMA_TRIGGER_MODE_NOT_DEFINED

sdrv_dma_xfer_mode_e

enum sdrv_dma_xfer_mode_e

DMA channel transfer mode.

Enumerator
SDRV_DMA_TRANSFER_MODE_SINGLE	Single mode. Continuous mode.
SDRV_DMA_TRANSFER_MODE_CONTINUOUS	Link list mode.
SDRV_DMA_TRANSFER_MODE_LINKLIST	Channel link mode.
SDRV_DMA_TRANSFER_MODE_CHAN_LINK
SDRV_DMA_TRANSFER_MODE_NOT_DEFINED

sdrv_dma_xfer_type_e

enum sdrv_dma_xfer_type_e

DMA channel transfer types.

Enumerator
SDRV_DMA_DIR_MEM2MEM	memory to memory
SDRV_DMA_DIR_MEM2DEV	memory to device
SDRV_DMA_DIR_DEV2MEM	device to memory
SDRV_DMA_DIR_DEV2DEV	device to device
SDRV_DMA_DIR_REG2MEM	register to memory
SDRV_DMA_DIR_REG2DEV	register to device
SDRV_DMA_DIR_MEM2REG	memory to register
SDRV_DMA_DIR_DEV2REG	device to register
SDRV_DMA_DIR_NOT_DEFINED

Function Documentation

sdrv_dma_clear_channel_xfer_bytes()

status_t sdrv_dma_clear_channel_xfer_bytes

(

sdrv_dma_channel_t *

channel

)

Clear DMA channel transfered bytes counter.

This function clear transfered bytes counter.

Parameters

[in]

channel

DMA channel.

sdrv_dma_clear_channel_xfer_status()

status_t sdrv_dma_clear_channel_xfer_status	(	sdrv_dma_channel_t *	channel,
		uint32_t	status
	)

Clear DMA channel status.

This function clear channel current status.

Parameters

[in]	channel	DMA channel.
[in]	status	Channel status bitmask.

sdrv_dma_create_instance()

status_t sdrv_dma_create_instance	(	sdrv_dma_t *	dma_instance,
		paddr_t	base
	)

Create DMA controller instance.

This function create instance by dma controller base address.

Parameters

[in]	dma_instance	Pointer to DMA instance structure.
[in]	base	DMA controller base address.

sdrv_dma_deinit_channel()

status_t sdrv_dma_deinit_channel

(

sdrv_dma_channel_t *

channel

)

De-initialize the DMA channel.

This function reset channel registers to default value.

Parameters

[in]

channel

The DMA channel to de-initialize.

sdrv_dma_get_channel_ctrl_base()

static sdrv_dma_channel_ctrl_t * sdrv_dma_get_channel_ctrl_base ( sdrv_dma_ctrl_t *  dma_base, sdrv_dma_channel_id_e  channel  )

inlinestatic

get dma channel controller base address.

This function get dma channel base address by dma controller base address and channel id.

Parameters

[in]	dma_base	dma controller base address.
[in]	channel	dma channel id.

Return values

channel

controller base address.

sdrv_dma_get_channel_xfer_bytes()

uint32_t sdrv_dma_get_channel_xfer_bytes

(

sdrv_dma_channel_t *

channel

)

Get number of transfered bytes for the channel.

This function get transfered length in bytes.

Parameters

[in]

channel

DMA channel.

Returns

Number of transfered bytes.

sdrv_dma_get_channel_xfer_status()

uint32_t sdrv_dma_get_channel_xfer_status

(

sdrv_dma_channel_t *

channel

)

Get DMA channel status.

This function get channel current status.

Parameters

[in]

channel

DMA channel.

Returns

channel status.

sdrv_dma_init_channel()

status_t sdrv_dma_init_channel	(	sdrv_dma_channel_t *	channel,
		const sdrv_dma_channel_config_t *	config
	)

Initialize DMA channel.

This function set configuration to channel.

Parameters

[in]	channel	The channel to initialize.
[in]	config	DMA channel configuration.

Returns

True if the DMA channel is initialized successfully.

sdrv_dma_init_channel_config()

status_t sdrv_dma_init_channel_config	(	sdrv_dma_channel_config_t *	config,
		sdrv_dma_t *	instance
	)

Initialize default configuration for DMA channel.

This function get channel default configuration.

Parameters

[in]	config	DMA channel configuration to initialize.
[in]	dma_instance	DMA controller instance.

sdrv_dma_init_dmac()

void sdrv_dma_init_dmac

(

paddr_t

base

)

Initialize the DMA controller.

This function initialize dma controller with reset status and fifo.

Parameters

[in]

base

DMA controller base address.

sdrv_dma_init_linklist_entry()

status_t sdrv_dma_init_linklist_entry	(	sdrv_dma_linklist_descriptor_t *	desc,
		const sdrv_dma_channel_config_t *	config
	)

Initialize DMA link list descriptor.

This function initializes a DMA link list descriptor, using specified channel configuration.

Parameters

[in]	desc	Link list descriptor.
[in]	config	DMA channel config.

Returns

sdrv_dma_reset_core_int_status()

static void sdrv_dma_reset_core_int_status ( sdrv_dma_ctrl_t *  dma_base )

inlinestatic

reset dma interrupt type.

This function reset dma controller interrupt status.

Parameters

[in]

dma_base

dma controller base address.

sdrv_dma_reset_fifo()

static void sdrv_dma_reset_fifo ( sdrv_dma_ctrl_t *  dma_base )

inlinestatic

reset dma fifo.

This function reset dma controller fifo.

Parameters

[in]

dma_base

dma controller base address.

sdrv_dma_set_channel_buffer_size()

void sdrv_dma_set_channel_buffer_size	(	sdrv_dma_channel_t *	channel,
		sdrv_dma_loop_mode_e	loop_mode,
		uint32_t	total_size,
		uint32_t	loop_size
	)

set dma channel single transmit buffer size

This is an unsafe interface. The parameters filled in need to be calculated by yourself, and there is no verification inside the function.

Parameters

channel	dma channel ptr
loop_mode	loop mode
total_size	total bytes
loop_size	every handshake transmic bytes(The loop mode 0 does not take effect)

Returns

sdrv_dma_set_channel_destination_address()

status_t sdrv_dma_set_channel_destination_address	(	sdrv_dma_channel_t *	channel,
		paddr_t	addr
	)

Set DMA channel target address.

This function set target address to channel.

Parameters

[in]	channel	DMA channel.
[in]	addr	target address.

sdrv_dma_set_channel_interrupt()

static void sdrv_dma_set_channel_interrupt ( sdrv_dma_ctrl_t *  dma_base, sdrv_dma_channel_id_e  channel, uint32_t  int_type  )

inlinestatic

set dma channel interrupt type.

This function set dma channel interrupt type.

Parameters

[in]	dma_base	dma controller base address.
[in]	channel	dma channel id.
[in]	int_type	interrupt type.

sdrv_dma_set_channel_muxid()

static void sdrv_dma_set_channel_muxid ( sdrv_dma_ctrl_t *  dma_base, sdrv_dma_channel_id_e  channel, uint32_t  mux_id  )

inlinestatic

set dma channel mux id.

This function set mux id for periphal transactions.

Parameters

[in]	dma_base	dma controller base address.
[in]	channel	dma channel id.
[in]	mux_id	dma channel mux id.

sdrv_dma_set_channel_rd_outstanding()

static void sdrv_dma_set_channel_rd_outstanding ( sdrv_dma_ctrl_t *  dma_base, sdrv_dma_channel_id_e  channel, uint8_t  value  )

inlinestatic

set dma channel read outstanding.

This function set read outstanding for memory transactions to get better performance.

Parameters

[in]	dma_base	dma controller base address.
[in]	channel	dma channel id.
[in]	value	read outstanding value.

sdrv_dma_set_channel_source_address()

status_t sdrv_dma_set_channel_source_address	(	sdrv_dma_channel_t *	channel,
		paddr_t	addr
	)

Set DMA channel source address.

This function set source address to channel.

Parameters

[in]	channel	DMA channel.
[in]	addr	source address.

sdrv_dma_set_channel_status()

static void sdrv_dma_set_channel_status ( sdrv_dma_channel_ctrl_t *  channel_base, sdrv_dma_channel_status_e  status  )

inlinestatic

set dma channel status.

Parameters

[in]	channel_base	dma channel controller base address.
[in]	status	dma channel status.

sdrv_dma_set_channel_sw_handshake()

static void sdrv_dma_set_channel_sw_handshake ( sdrv_dma_channel_ctrl_t *  channel_base )

inlinestatic

set dma channel software handshake.

This function set software handshake for memory transactions.

Parameters

[in]

channel_base

dma channel controller base address.

sdrv_dma_set_channel_wr_outstanding()

static void sdrv_dma_set_channel_wr_outstanding ( sdrv_dma_ctrl_t *  dma_base, sdrv_dma_channel_id_e  channel, uint8_t  value  )

inlinestatic

set dma channel write outstanding.

This function set write outstanding for memory transactions to get better performance.

Parameters

[in]	dma_base	dma controller base address.
[in]	channel	dma channel id.
[in]	value	write outstanding value.

sdrv_dma_set_channel_xfer_bytes()

status_t sdrv_dma_set_channel_xfer_bytes	(	sdrv_dma_channel_t *	channel,
		uint32_t	xfer_bytes
	)

Set transfer length in bytes for the channel.

This function set transfer length in one transaction.

Parameters

[in]	channel	DMA channel.
[in]	xfer_bytes	transfer bytes.

sdrv_dma_start_channel_xfer()

status_t sdrv_dma_start_channel_xfer

(

sdrv_dma_channel_t *

channel

)

Start DMA transaction.

This function start transfer.

Parameters

[in]

channel

The DMA channel to start.

sdrv_dma_stop_channel_xfer()

status_t sdrv_dma_stop_channel_xfer

(

sdrv_dma_channel_t *

channel

)

Stop DMA transaction.

This function stop transfer.

Parameters

[in]

channel

The DMA channel to stop.