sdrv_sdhci.h File Reference

#include <reg.h>
#include <udelay/udelay.h>
#include <FreeRTOS.h>
#include <queue.h>
#include <semphr.h>
#include <task.h>
#include <irq.h>
#include <timers.h>
#include "sdrv_common.h"

Go to the source code of this file.

Data Structures
struct	host_caps
struct	mmc_data
struct	mmc_command
struct	sdhci_host
struct	sdhci_ops
struct	desc_entry_a32
struct	desc_entry_a64

Functions
void	sdrv_sdhci_init (struct sdhci_host *host)
status_t	sdrv_sdhci_send_command (struct sdhci_host *host, struct mmc_command *cmd)
status_t	sdrv_sdhci_set_bus_width (struct sdhci_host *host, uint16_t width)
status_t	sdrv_sdhci_execute_tuning (struct sdhci_host *host, uint32_t opcode, uint32_t bus_width)
uint32_t	sdrv_sdhci_clk_supply (struct sdhci_host *host, uint32_t type)
void	sdrv_sdhci_set_uhs_mode (struct sdhci_host *host, uint32_t mode)
status_t	sdrv_sdhci_reset (struct sdhci_host *host, uint8_t mask)
void	sdrv_sdhci_start_tuning (struct sdhci_host *host)
void	sdrv_sdhci_reset_tuning (struct sdhci_host *host)
void	sdrv_sdhci_abort_tuning (struct sdhci_host *host)
status_t	sdrv_sdhci_tuning_sequence (struct sdhci_host *host, uint32_t opcode, uint32_t bus_width)

Detailed Description

Copyright

Copyright (c) 2022 Semidrive Semiconductor. All rights reserved.

Macro Definition Documentation

ADMA_DESC_LIST_SIZE

#define ADMA_DESC_LIST_SIZE   (64)

BIT

#define BIT

(

nr

)

(1U << (nr))

desc_entry

#define desc_entry   desc_entry_a32

DETAIL_PRINTF

#define DETAIL_PRINTF	(		level,
			x...
	)

Value:

{                                                                           \
    ssdk_printf(level, "[%s|%d|%s]\n",__FILE__,__LINE__,__func__);          \
    ssdk_printf(level,x);                                                   \
}

FV_ADMA2_ATTR_LEN

#define FV_ADMA2_ATTR_LEN

(

v

)

((((v)&0xffffU) << 16) | ((((v)&0x3ff0000U)) >> 10))

MMC_BUS_WIDTH_1BIT

#define MMC_BUS_WIDTH_1BIT   0

MMC_BUS_WIDTH_4BIT

#define MMC_BUS_WIDTH_4BIT   1

MMC_BUS_WIDTH_8BIT

#define MMC_BUS_WIDTH_8BIT   2

MMC_CMD_RETRIES

#define MMC_CMD_RETRIES   0x3

MMC_DATA_BUS_WIDTH_1BIT

#define MMC_DATA_BUS_WIDTH_1BIT   0

MMC_DATA_BUS_WIDTH_4BIT

#define MMC_DATA_BUS_WIDTH_4BIT   1

MMC_DATA_BUS_WIDTH_8BIT

#define MMC_DATA_BUS_WIDTH_8BIT   2

MMC_DATA_DDR_BUS_WIDTH_4BIT

#define MMC_DATA_DDR_BUS_WIDTH_4BIT   5

MMC_DATA_DDR_BUS_WIDTH_8BIT

#define MMC_DATA_DDR_BUS_WIDTH_8BIT   6

readhw

#define readhw

(

a

)

(*REG16(a))

REG_READ16

#define REG_READ16	(		host,
			a
	)		readhw(((host)->base) + (a))

REG_READ32

#define REG_READ32	(		host,
			a
	)		readl(((host)->base) + (a))

REG_READ8

#define REG_READ8	(		host,
			a
	)		readb(((host)->base) + (a))

REG_RMW32

#define REG_RMW32	(		host,
			a,
			s,
			w,
			v
	)		RMWREG32((((host)->base) + (a)), (s), (w), (v))

REG_WRITE16

#define REG_WRITE16	(		host,
			v,
			a
	)		writehw((v), (((host)->base) + (a)))

REG_WRITE32

#define REG_WRITE32	(		host,
			v,
			a
	)		writel((v), (((host)->base) + (a)))

REG_WRITE8

#define REG_WRITE8	(		host,
			v,
			a
	)		writeb((v), (((host)->base) + (a)))

SDCC_HC_BUS_OFF

#define SDCC_HC_BUS_OFF   BIT(1)

SDCC_HC_BUS_ON

#define SDCC_HC_BUS_ON   BIT(0)

SDCC_HC_BUS_ON_OFF_SUCC

#define SDCC_HC_BUS_ON_OFF_SUCC   BIT(0)

SDCC_HC_INT_CARD_INSERT

#define SDCC_HC_INT_CARD_INSERT   BIT(6)

SDCC_HC_INT_CARD_REMOVE

#define SDCC_HC_INT_CARD_REMOVE   BIT(7)

SDCC_HC_IO_SIG_HIGH

#define SDCC_HC_IO_SIG_HIGH   BIT(3)

SDCC_HC_IO_SIG_LOW

#define SDCC_HC_IO_SIG_LOW   BIT(2)

SDCC_HC_IO_SIG_SUCC

#define SDCC_HC_IO_SIG_SUCC   BIT(2)

SDCC_HC_PWR_CTRL_INT

#define SDCC_HC_PWR_CTRL_INT   0xF

SDHC_SDCLK_UP_BIT_MASK

#define SDHC_SDCLK_UP_BIT_MASK   0x300

SDHCI_1_8_VOL_MASK

#define SDHCI_1_8_VOL_MASK   0x04000000

SDHCI_1_8_VOL_SET

#define SDHCI_1_8_VOL_SET   BIT(3)

SDHCI_3_0_VOL_MASK

#define SDHCI_3_0_VOL_MASK   0x02000000

SDHCI_3_3_VOL_MASK

#define SDHCI_3_3_VOL_MASK   0x01000000

SDHCI_8BIT_WIDTH_MASK

#define SDHCI_8BIT_WIDTH_MASK   0x00040000

SDHCI_ADM_ADDR_REG

#define SDHCI_ADM_ADDR_REG   (0x058)

SDHCI_ADM_ERR_REG

#define SDHCI_ADM_ERR_REG   (0x054)

SDHCI_ADMA23_SEL

#define SDHCI_ADMA23_SEL   (BIT(3) | BIT(4))

SDHCI_ADMA2_26BIT_LEN_MODE

#define SDHCI_ADMA2_26BIT_LEN_MODE   BIT(10)

SDHCI_ADMA2_DESC_16BIT_LEN_LSB

#define SDHCI_ADMA2_DESC_16BIT_LEN_LSB   (16)

SDHCI_ADMA2_DESC_26BIT_LEN_LSB

#define SDHCI_ADMA2_DESC_26BIT_LEN_LSB   (6)

SDHCI_ADMA2_DESC_LINE_SZ_V4

#define SDHCI_ADMA2_DESC_LINE_SZ_V4   0x1000000

SDHCI_ADMA2_MAX_TRANS_SZ_V4

#define SDHCI_ADMA2_MAX_TRANS_SZ_V4   (0xFFFFFFFF * 512)

SDHCI_ADMA2_SEL

#define SDHCI_ADMA2_SEL   BIT(4)

SDHCI_ADMA_32BIT

#define SDHCI_ADMA_32BIT   BIT(4)

SDHCI_ADMA_64BIT

#define SDHCI_ADMA_64BIT   (BIT(3) | BIT(4))

SDHCI_ADMA_64BIT_V4

#define SDHCI_ADMA_64BIT_V4   BIT(13)

SDHCI_ADMA_DATA_VALID

#define SDHCI_ADMA_DATA_VALID   SDHCI_ADMA_TRANS_DATA | SDHCI_ADMA_TRANS_VALID

SDHCI_ADMA_DATA_VALID_END

#define SDHCI_ADMA_DATA_VALID_END   SDHCI_ADMA_TRANS_DATA | SDHCI_ADMA_TRANS_VALID | SDHCI_ADMA_TRANS_END

SDHCI_ADMA_DESC_LINE_SZ

#define SDHCI_ADMA_DESC_LINE_SZ   0x10000

SDHCI_ADMA_MASK

#define SDHCI_ADMA_MASK   BIT(9)

SDHCI_ADMA_MAX_TRANS_SZ

#define SDHCI_ADMA_MAX_TRANS_SZ   (0xFFFFFFFFF * 512)

SDHCI_ADMA_NOP_END_VALID

#define SDHCI_ADMA_NOP_END_VALID   SDHCI_ADMA_TRANS_END | SDHCI_ADMA_TRANS_VALID

SDHCI_ADMA_SEL_MASK

#define SDHCI_ADMA_SEL_MASK   (BIT(3) | BIT(4))

SDHCI_ADMA_TRANS_DATA

#define SDHCI_ADMA_TRANS_DATA   BIT(5)

SDHCI_ADMA_TRANS_END

#define SDHCI_ADMA_TRANS_END   BIT(1)

SDHCI_ADMA_TRANS_INT

#define SDHCI_ADMA_TRANS_INT   BIT(2)

SDHCI_ADMA_TRANS_VALID

#define SDHCI_ADMA_TRANS_VALID   BIT(0)

SDHCI_ARGUMENT_REG

#define SDHCI_ARGUMENT_REG   (0x008)

SDHCI_ASYNC_MODE

#define SDHCI_ASYNC_MODE   (1)

SDHCI_AUTO_CMD12_EN

#define SDHCI_AUTO_CMD12_EN   BIT(2)

SDHCI_AUTO_CMD12_MASK

#define SDHCI_AUTO_CMD12_MASK   BIT(8)

SDHCI_AUTO_CMD23_EN

#define SDHCI_AUTO_CMD23_EN   BIT(3)

SDHCI_AUTO_CMD_ERR

#define SDHCI_AUTO_CMD_ERR   (0x03C)

SDHCI_BLK_ADMA_MASK

#define SDHCI_BLK_ADMA_MASK   0x00080000

SDHCI_BLK_CNT_EN

#define SDHCI_BLK_CNT_EN   BIT(1)

SDHCI_BLK_CNT_REG

#define SDHCI_BLK_CNT_REG   (0x006)

SDHCI_BLK_LEN_BIT

#define SDHCI_BLK_LEN_BIT   16

SDHCI_BLK_LEN_MASK

#define SDHCI_BLK_LEN_MASK   0x00030000

SDHCI_BLKSZ_REG

#define SDHCI_BLKSZ_REG   (0x004)

SDHCI_BUF_DATA

#define SDHCI_BUF_DATA   (0x020)

SDHCI_BUS_PWR_EN

#define SDHCI_BUS_PWR_EN   BIT(0)

SDHCI_BUS_VOL_SEL

#define SDHCI_BUS_VOL_SEL   1

SDHCI_BUS_WITDH_1BIT

#define SDHCI_BUS_WITDH_1BIT   (0)

SDHCI_BUS_WITDH_4BIT

#define SDHCI_BUS_WITDH_4BIT   BIT(1)

SDHCI_BUS_WITDH_8BIT

#define SDHCI_BUS_WITDH_8BIT   BIT(5)

SDHCI_CAP_ADDR_64BIT_V3

#define SDHCI_CAP_ADDR_64BIT_V3   BIT(28)

SDHCI_CAP_ADDR_64BIT_V4

#define SDHCI_CAP_ADDR_64BIT_V4   BIT(27)

SDHCI_CAPS_REG1

#define SDHCI_CAPS_REG1   (0x040)

SDHCI_CAPS_REG2

#define SDHCI_CAPS_REG2   (0x044)

SDHCI_CLK_100MHZ

#define SDHCI_CLK_100MHZ   100000000

SDHCI_CLK_200MHZ

#define SDHCI_CLK_200MHZ   200000000

SDHCI_CLK_25MHZ

#define SDHCI_CLK_25MHZ   25000000

SDHCI_CLK_400KHZ

#define SDHCI_CLK_400KHZ   400000

SDHCI_CLK_400MHZ

#define SDHCI_CLK_400MHZ   400000000

SDHCI_CLK_50MHZ

#define SDHCI_CLK_50MHZ   50000000

SDHCI_CLK_CTRL_REG

#define SDHCI_CLK_CTRL_REG   (0x02C)

SDHCI_CLK_DIS

#define SDHCI_CLK_DIS   (0 << 2)

SDHCI_CLK_EN

#define SDHCI_CLK_EN   BIT(2)

SDHCI_CLK_MAX_DIV

#define SDHCI_CLK_MAX_DIV   2046

SDHCI_CLK_PLL_EN

#define SDHCI_CLK_PLL_EN   BIT(3)

SDHCI_CLK_RATE_BIT

#define SDHCI_CLK_RATE_BIT   8

SDHCI_CLK_RATE_MASK

#define SDHCI_CLK_RATE_MASK   0x0000FF00

SDHCI_CLK_STABLE

#define SDHCI_CLK_STABLE   BIT(1)

SDHCI_CLK_STABLE_MASK

#define SDHCI_CLK_STABLE_MASK   BIT(1)

SDHCI_CMD_ACT

#define SDHCI_CMD_ACT   BIT(0)

SDHCI_CMD_CMD_IDX_BIT

#define SDHCI_CMD_CMD_IDX_BIT   8

SDHCI_CMD_CMD_TYPE_BIT

#define SDHCI_CMD_CMD_TYPE_BIT   6

SDHCI_CMD_CRC_CHECK_BIT

#define SDHCI_CMD_CRC_CHECK_BIT   3

SDHCI_CMD_CRC_MASK

#define SDHCI_CMD_CRC_MASK   BIT(1)

SDHCI_CMD_DATA_PRESENT_BIT

#define SDHCI_CMD_DATA_PRESENT_BIT   5

SDHCI_CMD_END_BIT_MASK

#define SDHCI_CMD_END_BIT_MASK   BIT(2)

SDHCI_CMD_ERR_MASK

#define SDHCI_CMD_ERR_MASK

Value:

    (SDHCI_CMD_TIMEOUT_MASK | SDHCI_CMD_CRC_MASK | SDHCI_CMD_END_BIT_MASK |     \
     SDHCI_CMD_IDX_MASK | SDHCI_AUTO_CMD12_MASK)

SDHCI_CMD_EVENT_FLAG

#define SDHCI_CMD_EVENT_FLAG   0x1u

SDHCI_CMD_IDX_CHECK_BIT

#define SDHCI_CMD_IDX_CHECK_BIT   4

SDHCI_CMD_IDX_MASK

#define SDHCI_CMD_IDX_MASK   BIT(3)

SDHCI_CMD_REG

#define SDHCI_CMD_REG   (0x00E)

SDHCI_CMD_RESP_NONE

#define SDHCI_CMD_RESP_NONE   0

SDHCI_CMD_RESP_R1

#define SDHCI_CMD_RESP_R1   BIT(0)

SDHCI_CMD_RESP_R1B

#define SDHCI_CMD_RESP_R1B   BIT(1)

SDHCI_CMD_RESP_R2

#define SDHCI_CMD_RESP_R2   BIT(2)

SDHCI_CMD_RESP_R3

#define SDHCI_CMD_RESP_R3   BIT(3)

SDHCI_CMD_RESP_R6

#define SDHCI_CMD_RESP_R6   BIT(6)

SDHCI_CMD_RESP_R7

#define SDHCI_CMD_RESP_R7   BIT(7)

SDHCI_CMD_RESP_TYPE_SEL_BIT

#define SDHCI_CMD_RESP_TYPE_SEL_BIT   0

SDHCI_CMD_SW_TIMEOUT

#define SDHCI_CMD_SW_TIMEOUT   0x100

SDHCI_CMD_SW_TIMEOUT_MASK

#define SDHCI_CMD_SW_TIMEOUT_MASK   BIT(16)

SDHCI_CMD_TIMEOUT

#define SDHCI_CMD_TIMEOUT   0xE

SDHCI_CMD_TIMEOUT_MASK

#define SDHCI_CMD_TIMEOUT_MASK   BIT(0)

SDHCI_CUR_LIM_MASK

#define SDHCI_CUR_LIM_MASK   BIT(7)

SDHCI_DAT_ACT

#define SDHCI_DAT_ACT   BIT(1)

SDHCI_DAT_CRC_MASK

#define SDHCI_DAT_CRC_MASK   BIT(5)

SDHCI_DAT_END_BIT_MASK

#define SDHCI_DAT_END_BIT_MASK   BIT(6)

SDHCI_DAT_SW_TIMEOUT_MASK

#define SDHCI_DAT_SW_TIMEOUT_MASK   BIT(17)

SDHCI_DAT_TIMEOUT_MASK

#define SDHCI_DAT_TIMEOUT_MASK   BIT(4)

SDHCI_DATA_COMPLETE_EVENT_FLAG

#define SDHCI_DATA_COMPLETE_EVENT_FLAG   0x1u

SDHCI_DATA_ERR_MASK

#define SDHCI_DATA_ERR_MASK

Value:

    (SDHCI_DAT_TIMEOUT_MASK | SDHCI_DAT_CRC_MASK | SDHCI_DAT_END_BIT_MASK |     \
     SDHCI_ADMA_MASK)

SDHCI_DATA_EVENT_FLAG

#define SDHCI_DATA_EVENT_FLAG   0x1u

SDHCI_DATA_SW_TIMEOUT

#define SDHCI_DATA_SW_TIMEOUT   0x1000

SDHCI_DDR50_MODE_MASK

#define SDHCI_DDR50_MODE_MASK   BIT(2)

SDHCI_DMA_EN

#define SDHCI_DMA_EN   BIT(0)

SDHCI_EMMC_DDR52_MODE

#define SDHCI_EMMC_DDR52_MODE   0x4

SDHCI_EMMC_HISPEED_MODE

#define SDHCI_EMMC_HISPEED_MODE   0x1

SDHCI_EMMC_HS200_MODE

#define SDHCI_EMMC_HS200_MODE   0x3

SDHCI_EMMC_HS400_MODE

#define SDHCI_EMMC_HS400_MODE   0x7

SDHCI_EMMC_LEGACY_MODE

#define SDHCI_EMMC_LEGACY_MODE   0x0

SDHCI_EMMC_VOL_1_8

#define SDHCI_EMMC_VOL_1_8   5

SDHCI_EMMC_VOL_3_0

#define SDHCI_EMMC_VOL_3_0   6

SDHCI_ERR_INT_SIG_EN

#define SDHCI_ERR_INT_SIG_EN   0xFFFF

SDHCI_ERR_INT_SIG_EN_REG

#define SDHCI_ERR_INT_SIG_EN_REG   (0x03A)

SDHCI_ERR_INT_STAT_MASK

#define SDHCI_ERR_INT_STAT_MASK   0x8000

SDHCI_ERR_INT_STS_EN

#define SDHCI_ERR_INT_STS_EN   0xFFFF

SDHCI_ERR_INT_STS_EN_REG

#define SDHCI_ERR_INT_STS_EN_REG   (0x036)

SDHCI_ERR_INT_STS_REG

#define SDHCI_ERR_INT_STS_REG   (0x032)

SDHCI_EXEC_TUNING

#define SDHCI_EXEC_TUNING   BIT(6)

SDHCI_HC_MODE_DIS

#define SDHCI_HC_MODE_DIS   (0 << 1)

SDHCI_HC_MODE_EN

#define SDHCI_HC_MODE_EN   BIT(0)

SDHCI_HIGH_SPEED_EN

#define SDHCI_HIGH_SPEED_EN   BIT(2)

SDHCI_HOST_CTRL1_REG

#define SDHCI_HOST_CTRL1_REG   (0x028)

SDHCI_HOST_CTRL2_REG

#define SDHCI_HOST_CTRL2_REG   (0x03E)

SDHCI_HW_TUNING_MIN_COUNT

#define SDHCI_HW_TUNING_MIN_COUNT   40

SDHCI_INHIBIT_COUNT

#define SDHCI_INHIBIT_COUNT   0x100

SDHCI_INT_ABORT_MASK

#define SDHCI_INT_ABORT_MASK

Value:

    (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | SDHCI_INT_END_BIT |                   \
    SDHCI_INT_INDEX)

SDHCI_INT_ACMD12ERR

#define SDHCI_INT_ACMD12ERR   BIT(24)

SDHCI_INT_ADMA_ERROR

#define SDHCI_INT_ADMA_ERROR   BIT(25)

SDHCI_INT_BLK_GAP

#define SDHCI_INT_BLK_GAP   BIT(2)

SDHCI_INT_BUS_POWER

#define SDHCI_INT_BUS_POWER   BIT(23)

SDHCI_INT_CARD_INSERT

#define SDHCI_INT_CARD_INSERT   BIT(6)

SDHCI_INT_CARD_INT

#define SDHCI_INT_CARD_INT   BIT(8)

SDHCI_INT_CARD_REMOVE

#define SDHCI_INT_CARD_REMOVE   BIT(7)

SDHCI_INT_CLK_EN

#define SDHCI_INT_CLK_EN   BIT(0)

SDHCI_INT_CMD_MASK

#define SDHCI_INT_CMD_MASK

Value:

    (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |                  \
     SDHCI_INT_END_BIT | SDHCI_INT_INDEX | SDHCI_INT_ACMD12ERR)

SDHCI_INT_CQE

#define SDHCI_INT_CQE   BIT(14)

SDHCI_INT_CRC

#define SDHCI_INT_CRC   BIT(17)

SDHCI_INT_DATA_AVAIL

#define SDHCI_INT_DATA_AVAIL   BIT(5)

SDHCI_INT_DATA_CRC

#define SDHCI_INT_DATA_CRC   BIT(21)

SDHCI_INT_DATA_END

#define SDHCI_INT_DATA_END   BIT(1)

SDHCI_INT_DATA_END_BIT

#define SDHCI_INT_DATA_END_BIT   BIT(22)

SDHCI_INT_DATA_MASK

#define SDHCI_INT_DATA_MASK

Value:

    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | SDHCI_INT_DATA_AVAIL |           \
     SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC |     \
     SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | SDHCI_INT_BLK_GAP)

SDHCI_INT_DATA_TIMEOUT

#define SDHCI_INT_DATA_TIMEOUT   BIT(20)

SDHCI_INT_DMA_END

#define SDHCI_INT_DMA_END   BIT(3)

SDHCI_INT_END_BIT

#define SDHCI_INT_END_BIT   BIT(18)

SDHCI_INT_ERROR

#define SDHCI_INT_ERROR   BIT(15)

SDHCI_INT_ERROR_MASK

#define SDHCI_INT_ERROR_MASK   0xFFFF8000

SDHCI_INT_INDEX

#define SDHCI_INT_INDEX   BIT(19)

SDHCI_INT_NORMAL_MASK

#define SDHCI_INT_NORMAL_MASK   0x00007FFF

SDHCI_INT_RESPONSE

#define SDHCI_INT_RESPONSE   BIT(0)

SDHCI_INT_RETUNE

#define SDHCI_INT_RETUNE   BIT(12)

SDHCI_INT_SPACE_AVAIL

#define SDHCI_INT_SPACE_AVAIL   BIT(4)

SDHCI_INT_STS_CMD_COMPLETE

#define SDHCI_INT_STS_CMD_COMPLETE   BIT(0)

SDHCI_INT_STS_TRANS_COMPLETE

#define SDHCI_INT_STS_TRANS_COMPLETE   BIT(1)

SDHCI_INT_TIMEOUT

#define SDHCI_INT_TIMEOUT   BIT(16)

SDHCI_MAX_CMD_RETRY

#define SDHCI_MAX_CMD_RETRY   5000000

SDHCI_MAX_TRANS_RETRY

#define SDHCI_MAX_TRANS_RETRY   10000000

SDHCI_MMC_BLK_SZ

#define SDHCI_MMC_BLK_SZ   512

SDHCI_MMC_BLK_SZ_BIT

#define SDHCI_MMC_BLK_SZ_BIT   0

SDHCI_MMC_CUR_BLK_CNT_BIT

#define SDHCI_MMC_CUR_BLK_CNT_BIT   16

SDHCI_MMC_READ

#define SDHCI_MMC_READ   1

SDHCI_MMC_RETRY

#define SDHCI_MMC_RETRY

SDHCI_MMC_WRITE

#define SDHCI_MMC_WRITE   0

SDHCI_NRML_INT_SIG_EN

#define SDHCI_NRML_INT_SIG_EN   0x003B

SDHCI_NRML_INT_SIG_EN_REG

#define SDHCI_NRML_INT_SIG_EN_REG   (0x038)

SDHCI_NRML_INT_STS_EN

#define SDHCI_NRML_INT_STS_EN   0x003B

SDHCI_NRML_INT_STS_EN_REG

#define SDHCI_NRML_INT_STS_EN_REG   (0x034)

SDHCI_NRML_INT_STS_REG

#define SDHCI_NRML_INT_STS_REG   (0x030)

SDHCI_PREP_CMD

#define SDHCI_PREP_CMD	(		c,
			f
	)		((((c)&0xff) << 8) | ((f)&0xff))

SDHCI_PRESENT_STATE_DAT_1BIT_MASK

#define SDHCI_PRESENT_STATE_DAT_1BIT_MASK   (SDHCI_PSTATE_DAT_3_0_MASK & 0x00100000)

SDHCI_PRESENT_STATE_DAT_4BIT_MASK

#define SDHCI_PRESENT_STATE_DAT_4BIT_MASK   (SDHCI_PSTATE_DAT_3_0_MASK)

SDHCI_PRESENT_STATE_DAT_8BIT_MASK

#define SDHCI_PRESENT_STATE_DAT_8BIT_MASK   (SDHCI_PSTATE_DAT_3_0_MASK | SDHCI_PSTATE_DAT_7_4_MASK)

SDHCI_PRESENT_STATE_DAT_MASK

#define SDHCI_PRESENT_STATE_DAT_MASK   (SDHCI_PSTATE_DAT_3_0_MASK | SDHCI_PSTATE_DAT_7_4_MASK)

SDHCI_PRESENT_STATE_REG

#define SDHCI_PRESENT_STATE_REG   (0x024)

SDHCI_PSTATE_CMD_INHIBIT_DAT_MASK

#define SDHCI_PSTATE_CMD_INHIBIT_DAT_MASK   BIT(1)

SDHCI_PSTATE_CMD_INHIBIT_MASK

#define SDHCI_PSTATE_CMD_INHIBIT_MASK   BIT(0)

SDHCI_PSTATE_DAT_3_0_MASK

#define SDHCI_PSTATE_DAT_3_0_MASK   0x00f00000

SDHCI_PSTATE_DAT_7_4_MASK

#define SDHCI_PSTATE_DAT_7_4_MASK   0x000000f0

SDHCI_PWR_CTRL_REG

#define SDHCI_PWR_CTRL_REG   (0x029)

SDHCI_READ_MODE

#define SDHCI_READ_MODE   BIT(4)

SDHCI_RESET_MAX_TIMEOUT

#define SDHCI_RESET_MAX_TIMEOUT   0x64

SDHCI_RESET_REG

#define SDHCI_RESET_REG   (0x02F)

SDHCI_RESP_LSHIFT

#define SDHCI_RESP_LSHIFT   8

SDHCI_RESP_REG

#define SDHCI_RESP_REG   (0x010)

SDHCI_RESP_RSHIFT

#define SDHCI_RESP_RSHIFT   24

SDHCI_SAMPLE_CLK_SEL

#define SDHCI_SAMPLE_CLK_SEL   BIT(7)

SDHCI_SDCLK_FREQ_MASK

#define SDHCI_SDCLK_FREQ_MASK   0xFF

SDHCI_SDCLK_FREQ_SEL

#define SDHCI_SDCLK_FREQ_SEL   8

SDHCI_SDCLK_UP_BIT_SEL

#define SDHCI_SDCLK_UP_BIT_SEL   6

SDHCI_SDMASA_BLKCNT_REG

#define SDHCI_SDMASA_BLKCNT_REG   (0x000)

SDHCI_SDR104_MODE_MASK

#define SDHCI_SDR104_MODE_MASK   BIT(1)

SDHCI_SDR50_MODE_MASK

#define SDHCI_SDR50_MODE_MASK   BIT(0)

SDHCI_SOFT_RESET

#define SDHCI_SOFT_RESET   BIT(0)

SDHCI_SPEC_VER4_NUM

#define SDHCI_SPEC_VER4_NUM   (0x3)

SDHCI_SPEC_VERSION_REG

#define SDHCI_SPEC_VERSION_REG   (0xFE)

SDHCI_STATE_CMD_DAT_MASK

#define SDHCI_STATE_CMD_DAT_MASK   0x0003

SDHCI_STATE_CMD_MASK

#define SDHCI_STATE_CMD_MASK   BIT(0)

SDHCI_STATE_DAT_MASK

#define SDHCI_STATE_DAT_MASK   BIT(1)

SDHCI_SWITCH_CMD

#define SDHCI_SWITCH_CMD   6

SDHCI_SYNC_MODE

#define SDHCI_SYNC_MODE   (0)

SDHCI_TIMEOUT_REG

#define SDHCI_TIMEOUT_REG   (0x02E)

SDHCI_TRANS_COUNT_MAX

#define SDHCI_TRANS_COUNT_MAX   0x10

SDHCI_TRANS_MODE_REG

#define SDHCI_TRANS_MODE_REG   (0x00C)

SDHCI_TRANS_MULTI

#define SDHCI_TRANS_MULTI   BIT(5)

SDHCI_TRANS_SINGLE

#define SDHCI_TRANS_SINGLE   (0 << 5)

SDHCI_TUNE_CLK_STOP_EN_MASK

#define SDHCI_TUNE_CLK_STOP_EN_MASK   BIT(16)

SDHCI_TUNE_SWIN_TH_VAL_LSB

#define SDHCI_TUNE_SWIN_TH_VAL_LSB   (24)

SDHCI_TUNE_SWIN_TH_VAL_MASK

#define SDHCI_TUNE_SWIN_TH_VAL_MASK   0xFF

SDHCI_UHS_DDR50_MODE

#define SDHCI_UHS_DDR50_MODE   0x4

SDHCI_UHS_MODE_MASK

#define SDHCI_UHS_MODE_MASK   0x0007

UHS macros.

SDHCI_UHS_SDR104_MODE

#define SDHCI_UHS_SDR104_MODE   0x3

SDHCI_UHS_SDR12_MODE

#define SDHCI_UHS_SDR12_MODE   0x0

SDHCI_UHS_SDR25_MODE

#define SDHCI_UHS_SDR25_MODE   0x1

SDHCI_UHS_SDR50_MODE

#define SDHCI_UHS_SDR50_MODE   0x2

SDHCI_VENDER_AT_CTRL_REG

#define SDHCI_VENDER_AT_CTRL_REG   (0x40)

SDHCI_VENDOR_BASE_REG

#define SDHCI_VENDOR_BASE_REG   (0xE8)

SDHCI_VER4_ENABLE

#define SDHCI_VER4_ENABLE   BIT(12)

SDHCI_VOL_1_8

#define SDHCI_VOL_1_8   5

SDHCI_VOL_3_0

#define SDHCI_VOL_3_0   6

SDHCI_VOL_3_3

#define SDHCI_VOL_3_3   7

SOFT_RESET_CMD

#define SOFT_RESET_CMD   BIT(1)

SOFT_RESET_DATA

#define SOFT_RESET_DATA   BIT(2)

writehw

#define writehw	(		v,
			a
	)		(*REG16(a) = (v))

Enumeration Type Documentation

sdhci_card_type

enum sdhci_card_type

Card types for sdhci.

Enumerator
SDHCI_EMMC_CARD
SDHCI_SD_CARD
SDHCI_UHS2_CARD
SDHCI_SDIO_CARD
SDHCI_CARD_TYPE_ABORT

sdhci_cmd_type

enum sdhci_cmd_type

Command types for sdhci.

Enumerator
SDHCI_CMD_TYPE_NORMAL
SDHCI_CMD_TYPE_SUSPEND
SDHCI_CMD_TYPE_RESUME
SDHCI_CMD_TYPE_ABORT

sdhci_resp_type

enum sdhci_resp_type

Response type values for sdhci.

Enumerator
SDHCI_CMD_RESP_NONE
SDHCI_CMD_RESP_136
SDHCI_CMD_RESP_48
SDHCI_CMD_RESP_48_BUSY

Function Documentation

sdrv_sdhci_abort_tuning()

void sdrv_sdhci_abort_tuning

(

struct sdhci_host *

host

)

sdhci abort tuning

Parameters

[in]

host

sdhci host structure

sdrv_sdhci_clk_supply()

uint32_t sdrv_sdhci_clk_supply	(	struct sdhci_host *	host,
		uint32_t	type
	)

sdhci clk supply

Parameters

[in]	host	sdhci host structure
[in]	type	clk supply type

Returns

uint32_t

Return values

0	success
other	failed

sdrv_sdhci_execute_tuning()

status_t sdrv_sdhci_execute_tuning	(	struct sdhci_host *	host,
		uint32_t	opcode,
		uint32_t	bus_width
	)

sdhci execute tuning

start sdhci tuning and execute sdhci tuning sequence

Parameters

[in]	host	sdhci host structure
[in]	opcode	tuning opcode
[in]	bus_width	mmc bus witdh

Returns

uint32_t

Return values

0	success
other	failed

sdrv_sdhci_init()

void sdrv_sdhci_init

(

struct sdhci_host *

host

)

initialize the controller.

Parameters

[in]

host

sdhci host structure

reset the controller, read the capabilities register and set initial bus width

sdrv_sdhci_reset()

status_t sdrv_sdhci_reset	(	struct sdhci_host *	host,
		uint8_t	mask
	)

Soft reset for the controller.

Parameters

[in]	host	sdhci host structure
[in]	mask	write to reset register

sdrv_sdhci_reset_tuning()

void sdrv_sdhci_reset_tuning

(

struct sdhci_host *

host

)

sdhci reset tuning

Parameters

[in]

host

sdhci host structure

sdrv_sdhci_send_command()

status_t sdrv_sdhci_send_command	(	struct sdhci_host *	host,
		struct mmc_command *	cmd
	)

sdhci send command

prepare the command register and run the command

Parameters

[in]	host	sdhci host structure
[in]	cmd	mmc command structure

reset the controller, read the capabilities register and set initial bus width

Returns

uint32_t

Return values

0	success
other	failed

sdrv_sdhci_set_bus_width()

status_t sdrv_sdhci_set_bus_width	(	struct sdhci_host *	host,
		uint16_t	width
	)

set the bus width for controller

Parameters

[in]	host	sdhci host structure
[in]	width	mmc bus witdh

Returns

uint8_t

Return values

0	success
other	failed

sdrv_sdhci_set_uhs_mode()

void sdrv_sdhci_set_uhs_mode	(	struct sdhci_host *	host,
		uint32_t	mode
	)

sdhci clk supply

sdhci set uhs mode, needs to be used together with set clock api

Parameters

[in]	host	sdhci host structure
[in]	mode	UHS mode

sdrv_sdhci_start_tuning()

void sdrv_sdhci_start_tuning

(

struct sdhci_host *

host

)

start tuning

Parameters

[in]

host

sdhci host structure

sdrv_sdhci_tuning_sequence()

status_t sdrv_sdhci_tuning_sequence	(	struct sdhci_host *	host,
		uint32_t	opcode,
		uint32_t	bus_width
	)

sdhci clk supply

Parameters

[in]	host	sdhci host structure
[in]	opcode	tuning opcode
[in]	bus_width	Bus width used

Returns

uint32_t

Return values

0	success
other	failed

sdrv_sdhci_wait_for_bit()

static status_t sdrv_sdhci_wait_for_bit ( struct sdhci_host *  host, addr_t  reg, uint16_t  mask, bool  clear, uint32_t  ms  )

inlinestatic

sdhci wait for bit mask