g2dlite_reg.h File Reference

Go to the source code of this file.

Detailed Description

Copyright

Copyright (c) 2022 Semidrive Semiconductor. All rights reserved.

Macro Definition Documentation

AFLU_EN_MASK

#define AFLU_EN_MASK   0x1 << AFLU_EN_SHIFT

AFLU_EN_SHIFT

#define AFLU_EN_SHIFT   7

ALPHA_BLD_BYPS_MASK

#define ALPHA_BLD_BYPS_MASK   0x1 << ALPHA_BLD_BYPS_SHIFT

ALPHA_BLD_BYPS_SHIFT

#define ALPHA_BLD_BYPS_SHIFT   0

ALPHA_BLD_IDX_MASK

#define ALPHA_BLD_IDX_MASK   0xF << ALPHA_BLD_IDX_SHIFT

ALPHA_BLD_IDX_SHIFT

#define ALPHA_BLD_IDX_SHIFT   16

AP_AP_STRIDE

#define AP_AP_STRIDE   REG(0x902c)

AP_BADDR_H_H

#define AP_BADDR_H_H   REG(0x9010)

AP_BADDR_H_MASK

#define AP_BADDR_H_MASK   0xFFFFFFFF << AP_BADDR_H_SHIFT

AP_BADDR_H_SHIFT

#define AP_BADDR_H_SHIFT   0

AP_BADDR_L_L

#define AP_BADDR_L_L   REG(0x900c)

AP_BADDR_L_MASK

#define AP_BADDR_L_MASK   0xFFFFFFFF << AP_BADDR_L_SHIFT

AP_BADDR_L_SHIFT

#define AP_BADDR_L_SHIFT   0

AP_FRM_CTRL_ENDIAN_CTRL_MASK

#define AP_FRM_CTRL_ENDIAN_CTRL_MASK   0x7 << AP_FRM_CTRL_ENDIAN_CTRL_SHIFT

AP_FRM_CTRL_ENDIAN_CTRL_SHIFT

#define AP_FRM_CTRL_ENDIAN_CTRL_SHIFT   16

AP_FRM_CTRL_FAST_CP_MODE_MASK

#define AP_FRM_CTRL_FAST_CP_MODE_MASK   0x1 << AP_FRM_CTRL_FAST_CP_MODE_SHIFT

AP_FRM_CTRL_FAST_CP_MODE_SHIFT

#define AP_FRM_CTRL_FAST_CP_MODE_SHIFT   0

AP_FRM_CTRL_ROT_MASK

#define AP_FRM_CTRL_ROT_MASK   0x7 << AP_FRM_CTRL_ROT_SHIFT

AP_FRM_CTRL_ROT_SHIFT

#define AP_FRM_CTRL_ROT_SHIFT   8

AP_FRM_FRM_CTRL

#define AP_FRM_FRM_CTRL   REG(0x9004)

AP_FRM_FRM_OFFSET

#define AP_FRM_FRM_OFFSET   REG(0x9040)

AP_FRM_FRM_SIZE

#define AP_FRM_FRM_SIZE   REG(0x9008)

AP_FRM_OFFSET_X_MASK

#define AP_FRM_OFFSET_X_MASK   0xFFFF << AP_FRM_OFFSET_X_SHIFT

AP_FRM_OFFSET_X_SHIFT

#define AP_FRM_OFFSET_X_SHIFT   0

AP_FRM_OFFSET_Y_MASK

#define AP_FRM_OFFSET_Y_MASK   0xFFFF << AP_FRM_OFFSET_Y_SHIFT

AP_FRM_OFFSET_Y_SHIFT

#define AP_FRM_OFFSET_Y_SHIFT   16

AP_FRM_SIZE_HEIGHT_MASK

#define AP_FRM_SIZE_HEIGHT_MASK   0xFFFFUL << AP_FRM_SIZE_HEIGHT_SHIFT

AP_FRM_SIZE_HEIGHT_SHIFT

#define AP_FRM_SIZE_HEIGHT_SHIFT   16

AP_FRM_SIZE_WIDTH_MASK

#define AP_FRM_SIZE_WIDTH_MASK   0xFFFF << AP_FRM_SIZE_WIDTH_SHIFT

AP_FRM_SIZE_WIDTH_SHIFT

#define AP_FRM_SIZE_WIDTH_SHIFT   0

AP_PIX_COMP_BPA_MASK

#define AP_PIX_COMP_BPA_MASK   0xF << AP_PIX_COMP_BPA_SHIFT

AP_PIX_COMP_BPA_SHIFT

#define AP_PIX_COMP_BPA_SHIFT   0

AP_PIX_PIX_COMP

#define AP_PIX_PIX_COMP   REG(0x9000)

AP_SDW_CTRL_CTRL

#define AP_SDW_CTRL_CTRL   REG(0x9f00)

AP_SDW_CTRL_TRIG_MASK

#define AP_SDW_CTRL_TRIG_MASK   0x1 << AP_SDW_CTRL_TRIG_SHIFT

AP_SDW_CTRL_TRIG_SHIFT

#define AP_SDW_CTRL_TRIG_SHIFT   0

AP_STRIDE_MASK

#define AP_STRIDE_MASK   0x3FFFF << AP_STRIDE_SHIFT

AP_STRIDE_SHIFT

#define AP_STRIDE_SHIFT   0

BADDR_H_U_MASK

#define BADDR_H_U_MASK   0xFF << BADDR_H_U_SHIFT

BADDR_H_U_SHIFT

#define BADDR_H_U_SHIFT   0

BADDR_H_V_MASK

#define BADDR_H_V_MASK   0xFF << BADDR_H_V_SHIFT

BADDR_H_V_SHIFT

#define BADDR_H_V_SHIFT   0

BADDR_H_Y_MASK

#define BADDR_H_Y_MASK   0xFF << BADDR_H_Y_SHIFT

BADDR_H_Y_SHIFT

#define BADDR_H_Y_SHIFT   0

BADDR_L_U_MASK

#define BADDR_L_U_MASK   0xFFFFFFFF << BADDR_L_U_SHIFT

BADDR_L_U_SHIFT

#define BADDR_L_U_SHIFT   0

BADDR_L_V_MASK

#define BADDR_L_V_MASK   0xFFFFFFFF << BADDR_L_V_SHIFT

BADDR_L_V_SHIFT

#define BADDR_L_V_SHIFT   0

BADDR_L_Y_MASK

#define BADDR_L_Y_MASK   0xFFFFFFFF << BADDR_L_Y_SHIFT

BADDR_L_Y_SHIFT

#define BADDR_L_Y_SHIFT   0

BG_A_MASK

#define BG_A_MASK   0xFF << BG_A_SHIFT

BG_A_SEL_MASK

#define BG_A_SEL_MASK   0x1 << BG_A_SEL_SHIFT

BG_A_SEL_SHIFT

#define BG_A_SEL_SHIFT   2

BG_A_SHIFT

#define BG_A_SHIFT   8

BG_COLOR_B_MASK

#define BG_COLOR_B_MASK   0x3FF << BG_COLOR_B_SHIFT

BG_COLOR_B_SHIFT

#define BG_COLOR_B_SHIFT   0

BG_COLOR_G_MASK

#define BG_COLOR_G_MASK   0x3FF << BG_COLOR_G_SHIFT

BG_COLOR_G_SHIFT

#define BG_COLOR_G_SHIFT   10

BG_COLOR_R_MASK

#define BG_COLOR_R_MASK   0x3FF << BG_COLOR_R_SHIFT

BG_COLOR_R_SHIFT

#define BG_COLOR_R_SHIFT   20

BG_EN_MASK

#define BG_EN_MASK   0x1 << BG_EN_SHIFT

BG_EN_SHIFT

#define BG_EN_SHIFT   1

BPA_MASK

#define BPA_MASK   0xF << BPA_SHIFT

BPA_SHIFT

#define BPA_SHIFT   0

BPU_MASK

#define BPU_MASK   0xF << BPU_SHIFT

BPU_SHIFT

#define BPU_SHIFT   16

BPV_MASK

#define BPV_MASK   0xF << BPV_SHIFT

BPV_SHIFT

#define BPV_SHIFT   24

BPY_MASK

#define BPY_MASK   0x1F << BPY_SHIFT

BPY_SHIFT

#define BPY_SHIFT   8

CANVAS_COLOR_B_MASK

#define CANVAS_COLOR_B_MASK   0x3FF << CANVAS_COLOR_B_SHIFT

CANVAS_COLOR_B_SHIFT

#define CANVAS_COLOR_B_SHIFT   0

CANVAS_COLOR_G_MASK

#define CANVAS_COLOR_G_MASK   0x3FF << CANVAS_COLOR_G_SHIFT

CANVAS_COLOR_G_SHIFT

#define CANVAS_COLOR_G_SHIFT   10

CANVAS_COLOR_R_MASK

#define CANVAS_COLOR_R_MASK   0x3FF << CANVAS_COLOR_R_SHIFT

CANVAS_COLOR_R_SHIFT

#define CANVAS_COLOR_R_SHIFT   20

CHN_COUNT

#define CHN_COUNT   5

CHN_JMP

#define CHN_JMP   0x20

CLUT_A_BYPASS_MASK

#define CLUT_A_BYPASS_MASK   0x1 << CLUT_A_BYPASS_SHIFT

CLUT_A_BYPASS_SHIFT

#define CLUT_A_BYPASS_SHIFT   16

CLUT_A_CTRL

#define CLUT_A_CTRL   REG(0x5200)

CLUT_A_DEPTH_MASK

#define CLUT_A_DEPTH_MASK   0xF << CLUT_A_DEPTH_SHIFT

CLUT_A_DEPTH_SHIFT

#define CLUT_A_DEPTH_SHIFT   0

CLUT_A_HAS_ALPHA_MASK

#define CLUT_A_HAS_ALPHA_MASK   0x1 << CLUT_A_HAS_ALPHA_SHIFT

CLUT_A_HAS_ALPHA_SHIFT

#define CLUT_A_HAS_ALPHA_SHIFT   18

CLUT_A_OFFSET_MASK

#define CLUT_A_OFFSET_MASK   0xFF << CLUT_A_OFFSET_SHIFT

CLUT_A_OFFSET_SHIFT

#define CLUT_A_OFFSET_SHIFT   8

CLUT_A_SEL_MASK

#define CLUT_A_SEL_MASK   0x1 << CLUT_A_SEL_SHIFT

CLUT_A_SEL_SHIFT

#define CLUT_A_SEL_SHIFT   0

CLUT_A_Y_SEL_MASK

#define CLUT_A_Y_SEL_MASK   0x1 << CLUT_A_Y_SEL_SHIFT

CLUT_A_Y_SEL_SHIFT

#define CLUT_A_Y_SEL_SHIFT   17

CLUT_READ_CTRL

#define CLUT_READ_CTRL   REG(0x5210)

CLUT_U_BYPASS_MASK

#define CLUT_U_BYPASS_MASK   0x1 << CLUT_U_BYPASS_SHIFT

CLUT_U_BYPASS_SHIFT

#define CLUT_U_BYPASS_SHIFT   16

CLUT_U_CTRL

#define CLUT_U_CTRL   REG(0x5208)

CLUT_U_DEPTH_MASK

#define CLUT_U_DEPTH_MASK   0xF << CLUT_U_DEPTH_SHIFT

CLUT_U_DEPTH_SHIFT

#define CLUT_U_DEPTH_SHIFT   0

CLUT_U_OFFSET_MASK

#define CLUT_U_OFFSET_MASK   0xFF << CLUT_U_OFFSET_SHIFT

CLUT_U_OFFSET_SHIFT

#define CLUT_U_OFFSET_SHIFT   8

CLUT_U_SEL_MASK

#define CLUT_U_SEL_MASK   0x1 << CLUT_U_SEL_SHIFT

CLUT_U_SEL_SHIFT

#define CLUT_U_SEL_SHIFT   2

CLUT_U_Y_SEL_MASK

#define CLUT_U_Y_SEL_MASK   0x1 << CLUT_U_Y_SEL_SHIFT

CLUT_U_Y_SEL_SHIFT

#define CLUT_U_Y_SEL_SHIFT   17

CLUT_V_BYPASS_MASK

#define CLUT_V_BYPASS_MASK   0x1 << CLUT_V_BYPASS_SHIFT

CLUT_V_BYPASS_SHIFT

#define CLUT_V_BYPASS_SHIFT   16

CLUT_V_CTRL

#define CLUT_V_CTRL   REG(0x520c)

CLUT_V_DEPTH_MASK

#define CLUT_V_DEPTH_MASK   0xF << CLUT_V_DEPTH_SHIFT

CLUT_V_DEPTH_SHIFT

#define CLUT_V_DEPTH_SHIFT   0

CLUT_V_OFFSET_MASK

#define CLUT_V_OFFSET_MASK   0xFF << CLUT_V_OFFSET_SHIFT

CLUT_V_OFFSET_SHIFT

#define CLUT_V_OFFSET_SHIFT   8

CLUT_V_SEL_MASK

#define CLUT_V_SEL_MASK   0x1 << CLUT_V_SEL_SHIFT

CLUT_V_SEL_SHIFT

#define CLUT_V_SEL_SHIFT   3

CLUT_V_Y_SEL_MASK

#define CLUT_V_Y_SEL_MASK   0x1 << CLUT_V_Y_SEL_SHIFT

CLUT_V_Y_SEL_SHIFT

#define CLUT_V_Y_SEL_SHIFT   17

CLUT_Y_BYPASS_MASK

#define CLUT_Y_BYPASS_MASK   0x1 << CLUT_Y_BYPASS_SHIFT

CLUT_Y_BYPASS_SHIFT

#define CLUT_Y_BYPASS_SHIFT   16

CLUT_Y_CTRL

#define CLUT_Y_CTRL   REG(0x5204)

CLUT_Y_DEPTH_MASK

#define CLUT_Y_DEPTH_MASK   0xF << CLUT_Y_DEPTH_SHIFT

CLUT_Y_DEPTH_SHIFT

#define CLUT_Y_DEPTH_SHIFT   0

CLUT_Y_OFFSET_MASK

#define CLUT_Y_OFFSET_MASK   0xFF << CLUT_Y_OFFSET_SHIFT

CLUT_Y_OFFSET_SHIFT

#define CLUT_Y_OFFSET_SHIFT   8

CLUT_Y_SEL_MASK

#define CLUT_Y_SEL_MASK   0x1 << CLUT_Y_SEL_SHIFT

CLUT_Y_SEL_SHIFT

#define CLUT_Y_SEL_SHIFT   1

FRM_HEIGHT_MASK

#define FRM_HEIGHT_MASK   0xFFFFUL << FRM_HEIGHT_SHIFT

FRM_HEIGHT_SHIFT

#define FRM_HEIGHT_SHIFT   16

FRM_WIDTH_MASK

#define FRM_WIDTH_MASK   0xFFFF << FRM_WIDTH_SHIFT

FRM_WIDTH_SHIFT

#define FRM_WIDTH_SHIFT   0

FRM_X_MASK

#define FRM_X_MASK   0xFFFFUL << FRM_X_SHIFT

FRM_X_SHIFT

#define FRM_X_SHIFT   0

FRM_Y_MASK

#define FRM_Y_MASK   0xFFFFUL << FRM_Y_SHIFT

FRM_Y_SHIFT

#define FRM_Y_SHIFT   16

FSTART_SEL_MASK

#define FSTART_SEL_MASK   0x7 << FSTART_SEL_SHIFT

FSTART_SEL_SHIFT

#define FSTART_SEL_SHIFT   4

G2DLITE_CMDFILE_ADDR_H_ADDR_MASK

#define G2DLITE_CMDFILE_ADDR_H_ADDR_MASK    0xFF << G2DLITE_CMDFILE_ADDR_H_ADDR_SHIFT

G2DLITE_CMDFILE_ADDR_H_ADDR_SHIFT

#define G2DLITE_CMDFILE_ADDR_H_ADDR_SHIFT   0

G2DLITE_CMDFILE_ADDR_H_H

#define G2DLITE_CMDFILE_ADDR_H_H   REG(0x14)

G2DLITE_CMDFILE_ADDR_L_ADDR_MASK

#define G2DLITE_CMDFILE_ADDR_L_ADDR_MASK    0x3FFFFFFF << G2DLITE_CMDFILE_ADDR_L_ADDR_SHIFT

G2DLITE_CMDFILE_ADDR_L_ADDR_SHIFT

#define G2DLITE_CMDFILE_ADDR_L_ADDR_SHIFT   2

G2DLITE_CMDFILE_ADDR_L_L

#define G2DLITE_CMDFILE_ADDR_L_L   REG(0x10)

G2DLITE_CMDFILE_CFG_CFG

#define G2DLITE_CMDFILE_CFG_CFG   REG(0x1c)

G2DLITE_CMDFILE_CFG_CMD_DMA_EN_MASK

#define G2DLITE_CMDFILE_CFG_CMD_DMA_EN_MASK    1 << G2DLITE_CMDFILE_CFG_CMD_DMA_EN_SHIFT

G2DLITE_CMDFILE_CFG_CMD_DMA_EN_SHIFT

#define G2DLITE_CMDFILE_CFG_CMD_DMA_EN_SHIFT   3

G2DLITE_CMDFILE_CFG_ENDIAN_CTRL_MASK

#define G2DLITE_CMDFILE_CFG_ENDIAN_CTRL_MASK    0x7 << G2DLITE_CMDFILE_CFG_ENDIAN_CTRL_SHIFT

G2DLITE_CMDFILE_CFG_ENDIAN_CTRL_SHIFT

#define G2DLITE_CMDFILE_CFG_ENDIAN_CTRL_SHIFT   0

G2DLITE_CMDFILE_LEN_FILE_LEN_MASK

#define G2DLITE_CMDFILE_LEN_FILE_LEN_MASK    0xFFFF << G2DLITE_CMDFILE_LEN_FILE_LEN_SHIFT

G2DLITE_CMDFILE_LEN_FILE_LEN_SHIFT

#define G2DLITE_CMDFILE_LEN_FILE_LEN_SHIFT   0

G2DLITE_CMDFILE_LEN_LEN

#define G2DLITE_CMDFILE_LEN_LEN   REG(0x18)

G2DLITE_CTRL

#define G2DLITE_CTRL   REG(0x0)

G2DLITE_EN_MASK

#define G2DLITE_EN_MASK   1 << G2DLITE_EN_SHIFT

G2DLITE_EN_SHIFT

#define G2DLITE_EN_SHIFT   0

G2DLITE_FLC_CTRL

#define G2DLITE_FLC_CTRL   REG(0x4)

G2DLITE_FLC_TRIG_MASK

#define G2DLITE_FLC_TRIG_MASK   1 << G2DLITE_FLC_TRIG_SHIFT

G2DLITE_FLC_TRIG_SHIFT

#define G2DLITE_FLC_TRIG_SHIFT   0

G2DLITE_GP_CROP_BYPASS_MASK

#define G2DLITE_GP_CROP_BYPASS_MASK   0x1 << G2DLITE_GP_CROP_BYPASS_SHIFT

G2DLITE_GP_CROP_BYPASS_SHIFT

#define G2DLITE_GP_CROP_BYPASS_SHIFT   0

G2DLITE_GP_CROP_CTRL

#define G2DLITE_GP_CROP_CTRL   REG(0x2100)

G2DLITE_GP_CROP_PAR_ERR

#define G2DLITE_GP_CROP_PAR_ERR   REG(0x2120)

G2DLITE_GP_CROP_PAR_STATUS_MASK

#define G2DLITE_GP_CROP_PAR_STATUS_MASK   0x1 << G2DLITE_GP_CROP_PAR_STATUS_SHIFT

G2DLITE_GP_CROP_PAR_STATUS_SHIFT

#define G2DLITE_GP_CROP_PAR_STATUS_SHIFT   0

G2DLITE_GP_CROP_SIZE_H_MASK

#define G2DLITE_GP_CROP_SIZE_H_MASK   0xFFFF << G2DLITE_GP_CROP_SIZE_H_SHIFT

G2DLITE_GP_CROP_SIZE_H_SHIFT

#define G2DLITE_GP_CROP_SIZE_H_SHIFT   0

G2DLITE_GP_CROP_SIZE_SIZE

#define G2DLITE_GP_CROP_SIZE_SIZE   REG(0x2108)

G2DLITE_GP_CROP_SIZE_V_MASK

#define G2DLITE_GP_CROP_SIZE_V_MASK   0xFFFFUL << G2DLITE_GP_CROP_SIZE_V_SHIFT

G2DLITE_GP_CROP_SIZE_V_SHIFT

#define G2DLITE_GP_CROP_SIZE_V_SHIFT   16

G2DLITE_GP_CROP_UL_POS_POS

#define G2DLITE_GP_CROP_UL_POS_POS   REG(0x2104)

G2DLITE_GP_CROP_UL_POS_X_MASK

#define G2DLITE_GP_CROP_UL_POS_X_MASK   0xFFFF << G2DLITE_GP_CROP_UL_POS_X_SHIFT

G2DLITE_GP_CROP_UL_POS_X_SHIFT

#define G2DLITE_GP_CROP_UL_POS_X_SHIFT   0

G2DLITE_GP_CROP_UL_POS_Y_MASK

#define G2DLITE_GP_CROP_UL_POS_Y_MASK   0xFFFF << G2DLITE_GP_CROP_UL_POS_Y_SHIFT

G2DLITE_GP_CROP_UL_POS_Y_SHIFT

#define G2DLITE_GP_CROP_UL_POS_Y_SHIFT   16

G2DLITE_GP_FRM_CTRL

#define G2DLITE_GP_FRM_CTRL   REG(0x2004)

G2DLITE_GP_FRM_OFFSET

#define G2DLITE_GP_FRM_OFFSET   REG(0x2040)

G2DLITE_GP_FRM_SIZE

#define G2DLITE_GP_FRM_SIZE   REG(0x2008)

G2DLITE_GP_PIX_COMP

#define G2DLITE_GP_PIX_COMP   REG(0x2000)

G2DLITE_GP_U_BADDR_H

#define G2DLITE_GP_U_BADDR_H   REG(0x2018)

G2DLITE_GP_U_BADDR_L

#define G2DLITE_GP_U_BADDR_L   REG(0x2014)

G2DLITE_GP_U_STRIDE

#define G2DLITE_GP_U_STRIDE   REG(0x2030)

G2DLITE_GP_V_BADDR_H

#define G2DLITE_GP_V_BADDR_H   REG(0x2020)

G2DLITE_GP_V_BADDR_L

#define G2DLITE_GP_V_BADDR_L   REG(0x201c)

G2DLITE_GP_V_STRIDE

#define G2DLITE_GP_V_STRIDE   REG(0x2034)

G2DLITE_GP_Y_BADDR_H

#define G2DLITE_GP_Y_BADDR_H   REG(0x2010)

G2DLITE_GP_Y_BADDR_L

#define G2DLITE_GP_Y_BADDR_L   REG(0x200c)

G2DLITE_GP_Y_STRIDE

#define G2DLITE_GP_Y_STRIDE   REG(0x202c)

G2DLITE_GP_YUVUP_BYPASS_MASK

#define G2DLITE_GP_YUVUP_BYPASS_MASK   0x1 << G2DLITE_GP_YUVUP_BYPASS_SHIFT

G2DLITE_GP_YUVUP_BYPASS_SHIFT

#define G2DLITE_GP_YUVUP_BYPASS_SHIFT   0

G2DLITE_GP_YUVUP_CTRL

#define G2DLITE_GP_YUVUP_CTRL   REG(0x2044)

G2DLITE_GP_YUVUP_EN_MASK

#define G2DLITE_GP_YUVUP_EN_MASK   0x1UL << G2DLITE_GP_YUVUP_EN_SHIFT

G2DLITE_GP_YUVUP_EN_SHIFT

#define G2DLITE_GP_YUVUP_EN_SHIFT   31

G2DLITE_GP_YUVUP_FILTER_MODE_MASK

#define G2DLITE_GP_YUVUP_FILTER_MODE_MASK    0x1 << G2DLITE_GP_YUVUP_FILTER_MODE_SHIFT

G2DLITE_GP_YUVUP_FILTER_MODE_SHIFT

#define G2DLITE_GP_YUVUP_FILTER_MODE_SHIFT   3

G2DLITE_GP_YUVUP_HOFSET_MASK

#define G2DLITE_GP_YUVUP_HOFSET_MASK   0x3 << G2DLITE_GP_YUVUP_HOFSET_SHIFT

G2DLITE_GP_YUVUP_HOFSET_SHIFT

#define G2DLITE_GP_YUVUP_HOFSET_SHIFT   4

G2DLITE_GP_YUVUP_UPH_BYPASS_MASK

#define G2DLITE_GP_YUVUP_UPH_BYPASS_MASK    0x1 << G2DLITE_GP_YUVUP_UPH_BYPASS_SHIFT

G2DLITE_GP_YUVUP_UPH_BYPASS_SHIFT

#define G2DLITE_GP_YUVUP_UPH_BYPASS_SHIFT   1

G2DLITE_GP_YUVUP_UPV_BYPASS_MASK

#define G2DLITE_GP_YUVUP_UPV_BYPASS_MASK    0x1 << G2DLITE_GP_YUVUP_UPV_BYPASS_SHIFT

G2DLITE_GP_YUVUP_UPV_BYPASS_SHIFT

#define G2DLITE_GP_YUVUP_UPV_BYPASS_SHIFT   2

G2DLITE_GP_YUVUP_VOFSET_MASK

#define G2DLITE_GP_YUVUP_VOFSET_MASK   0x3 << G2DLITE_GP_YUVUP_VOFSET_SHIFT

G2DLITE_GP_YUVUP_VOFSET_SHIFT

#define G2DLITE_GP_YUVUP_VOFSET_SHIFT   6

G2DLITE_INT_MASK_FRM_DONE_MASK

#define G2DLITE_INT_MASK_FRM_DONE_MASK   1 << G2DLITE_INT_MASK_FRM_DONE_SHIFT

G2DLITE_INT_MASK_FRM_DONE_SHIFT

#define G2DLITE_INT_MASK_FRM_DONE_SHIFT   6

G2DLITE_INT_MASK_MASK

#define G2DLITE_INT_MASK_MASK   REG(0x20)

G2DLITE_INT_MASK_MLC_MASK

#define G2DLITE_INT_MASK_MLC_MASK   1 << G2DLITE_INT_MASK_MLC_SHIFT

G2DLITE_INT_MASK_MLC_SHIFT

#define G2DLITE_INT_MASK_MLC_SHIFT   2

G2DLITE_INT_MASK_RDMA_MASK

#define G2DLITE_INT_MASK_RDMA_MASK   1 << G2DLITE_INT_MASK_RDMA_SHIFT

G2DLITE_INT_MASK_RDMA_SHIFT

#define G2DLITE_INT_MASK_RDMA_SHIFT   0

G2DLITE_INT_MASK_RLE_0_MASK

#define G2DLITE_INT_MASK_RLE_0_MASK   1 << G2DLITE_INT_MASK_RLE_0_SHIFT

G2DLITE_INT_MASK_RLE_0_SHIFT

#define G2DLITE_INT_MASK_RLE_0_SHIFT   1

G2DLITE_INT_MASK_RLE_1_MASK

#define G2DLITE_INT_MASK_RLE_1_MASK   1 << G2DLITE_INT_MASK_RLE_1_SHIFT

G2DLITE_INT_MASK_RLE_1_SHIFT

#define G2DLITE_INT_MASK_RLE_1_SHIFT   3

G2DLITE_INT_MASK_TASK_DONE_MASK

#define G2DLITE_INT_MASK_TASK_DONE_MASK   1 << G2DLITE_INT_MASK_TASK_DONE_SHIFT

G2DLITE_INT_MASK_TASK_DONE_SHIFT

#define G2DLITE_INT_MASK_TASK_DONE_SHIFT   5

G2DLITE_INT_MASK_WDMA_MASK

#define G2DLITE_INT_MASK_WDMA_MASK   1 << G2DLITE_INT_MASK_WDMA_SHIFT

G2DLITE_INT_MASK_WDMA_SHIFT

#define G2DLITE_INT_MASK_WDMA_SHIFT   4

G2DLITE_INT_STATUS

#define G2DLITE_INT_STATUS   REG(0x24)

G2DLITE_SIZE_H_MASK

#define G2DLITE_SIZE_H_MASK   0xFFFF << G2DLITE_SIZE_H_SHIFT

G2DLITE_SIZE_H_SHIFT

#define G2DLITE_SIZE_H_SHIFT   0

G2DLITE_SIZE_SIZE

#define G2DLITE_SIZE_SIZE   REG(0xc)

G2DLITE_SIZE_V_MASK

#define G2DLITE_SIZE_V_MASK   0xFFFFUL << G2DLITE_SIZE_V_SHIFT

G2DLITE_SIZE_V_SHIFT

#define G2DLITE_SIZE_V_SHIFT   16

G2DLITE_SP_FRM_CTRL

#define G2DLITE_SP_FRM_CTRL   REG(0x5004)

G2DLITE_SP_FRM_OFFSET

#define G2DLITE_SP_FRM_OFFSET   REG(0x5040)

G2DLITE_SP_FRM_SIZE

#define G2DLITE_SP_FRM_SIZE   REG(0x5008)

G2DLITE_SP_PIX_COMP

#define G2DLITE_SP_PIX_COMP   REG(0x5000)

G2DLITE_SP_Y_BADDR_H

#define G2DLITE_SP_Y_BADDR_H   REG(0x5010)

G2DLITE_SP_Y_BADDR_L

#define G2DLITE_SP_Y_BADDR_L   REG(0x500c)

G2DLITE_SP_Y_STRIDE

#define G2DLITE_SP_Y_STRIDE   REG(0x502c)

G2DLITE_SPEED_ADJ_ADJ

#define G2DLITE_SPEED_ADJ_ADJ   REG(0x30)

G2DLITE_SPEED_ADJ_EN_MASK

#define G2DLITE_SPEED_ADJ_EN_MASK   1 << G2DLITE_SPEED_ADJ_EN_SHIFT

G2DLITE_SPEED_ADJ_EN_SHIFT

#define G2DLITE_SPEED_ADJ_EN_SHIFT   31

G2DLITE_SPEED_ADJ_INC_MASK

#define G2DLITE_SPEED_ADJ_INC_MASK   0x3FF << G2DLITE_SPEED_ADJ_INC_SHIFT

G2DLITE_SPEED_ADJ_INC_SHIFT

#define G2DLITE_SPEED_ADJ_INC_SHIFT   0

G2DLITE_SW_RST_MASK

#define G2DLITE_SW_RST_MASK   1UL << G2DLITE_SW_RST_SHIFT

G2DLITE_SW_RST_SHIFT

#define G2DLITE_SW_RST_SHIFT   31

GP_CSC_ALPHA_MASK

#define GP_CSC_ALPHA_MASK   0x1 << GP_CSC_ALPHA_SHIFT

GP_CSC_ALPHA_SHIFT

#define GP_CSC_ALPHA_SHIFT   2

GP_CSC_BYPASS_MASK

#define GP_CSC_BYPASS_MASK   0x1 << GP_CSC_BYPASS_SHIFT

GP_CSC_BYPASS_SHIFT

#define GP_CSC_BYPASS_SHIFT   0

GP_CSC_COEF1_A00_MASK

#define GP_CSC_COEF1_A00_MASK   0x3FFF << GP_CSC_COEF1_A00_SHIFT

GP_CSC_COEF1_A00_SHIFT

#define GP_CSC_COEF1_A00_SHIFT   0

GP_CSC_COEF1_A01_MASK

#define GP_CSC_COEF1_A01_MASK   0x3FFF << GP_CSC_COEF1_A01_SHIFT

GP_CSC_COEF1_A01_SHIFT

#define GP_CSC_COEF1_A01_SHIFT   16

GP_CSC_COEF2_A02_MASK

#define GP_CSC_COEF2_A02_MASK   0x3FFF << GP_CSC_COEF2_A02_SHIFT

GP_CSC_COEF2_A02_SHIFT

#define GP_CSC_COEF2_A02_SHIFT   0

GP_CSC_COEF2_A10_MASK

#define GP_CSC_COEF2_A10_MASK   0x3FFF << GP_CSC_COEF2_A10_SHIFT

GP_CSC_COEF2_A10_SHIFT

#define GP_CSC_COEF2_A10_SHIFT   16

GP_CSC_COEF3_A11_MASK

#define GP_CSC_COEF3_A11_MASK   0x3FFF << GP_CSC_COEF3_A11_SHIFT

GP_CSC_COEF3_A11_SHIFT

#define GP_CSC_COEF3_A11_SHIFT   0

GP_CSC_COEF3_A12_MASK

#define GP_CSC_COEF3_A12_MASK   0x3FFF << GP_CSC_COEF3_A12_SHIFT

GP_CSC_COEF3_A12_SHIFT

#define GP_CSC_COEF3_A12_SHIFT   16

GP_CSC_COEF4_A20_MASK

#define GP_CSC_COEF4_A20_MASK   0x3FFF << GP_CSC_COEF4_A20_SHIFT

GP_CSC_COEF4_A20_SHIFT

#define GP_CSC_COEF4_A20_SHIFT   0

GP_CSC_COEF4_A21_MASK

#define GP_CSC_COEF4_A21_MASK   0x3FFF << GP_CSC_COEF4_A21_SHIFT

GP_CSC_COEF4_A21_SHIFT

#define GP_CSC_COEF4_A21_SHIFT   16

GP_CSC_COEF5_A22_MASK

#define GP_CSC_COEF5_A22_MASK   0x3FFF << GP_CSC_COEF5_A22_SHIFT

GP_CSC_COEF5_A22_SHIFT

#define GP_CSC_COEF5_A22_SHIFT   0

GP_CSC_COEF5_B0_MASK

#define GP_CSC_COEF5_B0_MASK   0x3FFF << GP_CSC_COEF5_B0_SHIFT

GP_CSC_COEF5_B0_SHIFT

#define GP_CSC_COEF5_B0_SHIFT   16

GP_CSC_COEF6_B1_MASK

#define GP_CSC_COEF6_B1_MASK   0x3FFF << GP_CSC_COEF6_B1_SHIFT

GP_CSC_COEF6_B1_SHIFT

#define GP_CSC_COEF6_B1_SHIFT   0

GP_CSC_COEF6_B2_MASK

#define GP_CSC_COEF6_B2_MASK   0x3FFF << GP_CSC_COEF6_B2_SHIFT

GP_CSC_COEF6_B2_SHIFT

#define GP_CSC_COEF6_B2_SHIFT   16

GP_CSC_COEF7_C0_MASK

#define GP_CSC_COEF7_C0_MASK   0x3FF << GP_CSC_COEF7_C0_SHIFT

GP_CSC_COEF7_C0_SHIFT

#define GP_CSC_COEF7_C0_SHIFT   0

GP_CSC_COEF7_C1_MASK

#define GP_CSC_COEF7_C1_MASK   0x3FF << GP_CSC_COEF7_C1_SHIFT

GP_CSC_COEF7_C1_SHIFT

#define GP_CSC_COEF7_C1_SHIFT   16

GP_CSC_COEF8_C2_MASK

#define GP_CSC_COEF8_C2_MASK   0x3FF << GP_CSC_COEF8_C2_SHIFT

GP_CSC_COEF8_C2_SHIFT

#define GP_CSC_COEF8_C2_SHIFT   0

GP_CSC_COEF_COEF1

#define GP_CSC_COEF_COEF1   REG(0x2204)

GP_CSC_COEF_COEF2

#define GP_CSC_COEF_COEF2   REG(0x2208)

GP_CSC_COEF_COEF3

#define GP_CSC_COEF_COEF3   REG(0x220c)

GP_CSC_COEF_COEF4

#define GP_CSC_COEF_COEF4   REG(0x2210)

GP_CSC_COEF_COEF5

#define GP_CSC_COEF_COEF5   REG(0x2214)

GP_CSC_COEF_COEF6

#define GP_CSC_COEF_COEF6   REG(0x2218)

GP_CSC_COEF_COEF7

#define GP_CSC_COEF_COEF7   REG(0x221c)

GP_CSC_COEF_COEF8

#define GP_CSC_COEF_COEF8   REG(0x2220)

GP_CSC_CTRL

#define GP_CSC_CTRL   REG(0x2200)

GP_CSC_SBUP_CONV_MASK

#define GP_CSC_SBUP_CONV_MASK   0x1 << GP_CSC_SBUP_CONV_SHIFT

GP_CSC_SBUP_CONV_SHIFT

#define GP_CSC_SBUP_CONV_SHIFT   1

GP_HS_CTRL_APB_RD_MASK

#define GP_HS_CTRL_APB_RD_MASK   1 << GP_HS_CTRL_APB_RD_SHIFT

GP_HS_CTRL_APB_RD_SHIFT

#define GP_HS_CTRL_APB_RD_SHIFT   4

GP_HS_CTRL_FILTER_EN_A_MASK

#define GP_HS_CTRL_FILTER_EN_A_MASK   1 << GP_HS_CTRL_FILTER_EN_A_SHIFT

GP_HS_CTRL_FILTER_EN_A_SHIFT

#define GP_HS_CTRL_FILTER_EN_A_SHIFT   0

GP_HS_CTRL_FILTER_EN_U_MASK

#define GP_HS_CTRL_FILTER_EN_U_MASK   1 << GP_HS_CTRL_FILTER_EN_U_SHIFT

GP_HS_CTRL_FILTER_EN_U_SHIFT

#define GP_HS_CTRL_FILTER_EN_U_SHIFT   2

GP_HS_CTRL_FILTER_EN_V_MASK

#define GP_HS_CTRL_FILTER_EN_V_MASK   1 << GP_HS_CTRL_FILTER_EN_V_SHIFT

GP_HS_CTRL_FILTER_EN_V_SHIFT

#define GP_HS_CTRL_FILTER_EN_V_SHIFT   3

GP_HS_CTRL_FILTER_EN_Y_MASK

#define GP_HS_CTRL_FILTER_EN_Y_MASK   1 << GP_HS_CTRL_FILTER_EN_Y_SHIFT

GP_HS_CTRL_FILTER_EN_Y_SHIFT

#define GP_HS_CTRL_FILTER_EN_Y_SHIFT   1

GP_HS_CTRL_NOR_PARA_MASK

#define GP_HS_CTRL_NOR_PARA_MASK   0xF << GP_HS_CTRL_NOR_PARA_SHIFT

GP_HS_CTRL_NOR_PARA_SHIFT

#define GP_HS_CTRL_NOR_PARA_SHIFT   8

GP_HS_HS_CTRL

#define GP_HS_HS_CTRL   REG(0x2300)

GP_HS_HS_INI

#define GP_HS_HS_INI   REG(0x2304)

GP_HS_HS_RATIO

#define GP_HS_HS_RATIO   REG(0x2308)

GP_HS_HS_WIDTH

#define GP_HS_HS_WIDTH   REG(0x230c)

GP_HS_INI_FRA_MASK

#define GP_HS_INI_FRA_MASK   0x7FFFF << GP_HS_INI_FRA_SHIFT

GP_HS_INI_FRA_SHIFT

#define GP_HS_INI_FRA_SHIFT   0

GP_HS_INI_POLA_MASK

#define GP_HS_INI_POLA_MASK   1 << GP_HS_INI_POLA_SHIFT

GP_HS_INI_POLA_SHIFT

#define GP_HS_INI_POLA_SHIFT   19

GP_HS_RATIO_FRA_MASK

#define GP_HS_RATIO_FRA_MASK   0x7FFFF << GP_HS_RATIO_FRA_SHIFT

GP_HS_RATIO_FRA_SHIFT

#define GP_HS_RATIO_FRA_SHIFT   0

GP_HS_RATIO_INT_MASK

#define GP_HS_RATIO_INT_MASK   0x7 << GP_HS_RATIO_INT_SHIFT

GP_HS_RATIO_INT_SHIFT

#define GP_HS_RATIO_INT_SHIFT   19

GP_HS_WIDTH_OUT_MASK

#define GP_HS_WIDTH_OUT_MASK   0xFFFF << GP_HS_WIDTH_OUT_SHIFT

GP_HS_WIDTH_OUT_SHIFT

#define GP_HS_WIDTH_OUT_SHIFT   0

GP_RE_RE_STATUS

#define GP_RE_RE_STATUS   REG(0x2414)

GP_RE_STATUS_U_FRAME_END_MASK

#define GP_RE_STATUS_U_FRAME_END_MASK   1 << GP_RE_STATUS_U_FRAME_END_SHIFT

GP_RE_STATUS_U_FRAME_END_SHIFT

#define GP_RE_STATUS_U_FRAME_END_SHIFT   1

GP_RE_STATUS_V_FRAME_END_MASK

#define GP_RE_STATUS_V_FRAME_END_MASK   1 << GP_RE_STATUS_V_FRAME_END_SHIFT

GP_RE_STATUS_V_FRAME_END_SHIFT

#define GP_RE_STATUS_V_FRAME_END_SHIFT   2

GP_RE_STATUS_Y_FRAME_END_MASK

#define GP_RE_STATUS_Y_FRAME_END_MASK   1 << GP_RE_STATUS_Y_FRAME_END_SHIFT

GP_RE_STATUS_Y_FRAME_END_SHIFT

#define GP_RE_STATUS_Y_FRAME_END_SHIFT   0

GP_SDW_CTRL_CTRL

#define GP_SDW_CTRL_CTRL   REG(0x2f00)

GP_SDW_CTRL_TRIG_MASK

#define GP_SDW_CTRL_TRIG_MASK   1 << GP_SDW_CTRL_TRIG_SHIFT

GP_SDW_CTRL_TRIG_SHIFT

#define GP_SDW_CTRL_TRIG_SHIFT   0

GP_VS_CTRL_NORM_MASK

#define GP_VS_CTRL_NORM_MASK   0xF << GP_VS_CTRL_NORM_SHIFT

GP_VS_CTRL_NORM_SHIFT

#define GP_VS_CTRL_NORM_SHIFT   4

GP_VS_CTRL_PARITY_MASK

#define GP_VS_CTRL_PARITY_MASK   1 << GP_VS_CTRL_PARITY_SHIFT

GP_VS_CTRL_PARITY_SHIFT

#define GP_VS_CTRL_PARITY_SHIFT   3

GP_VS_CTRL_PXL_MODE_MASK

#define GP_VS_CTRL_PXL_MODE_MASK   1 << GP_VS_CTRL_PXL_MODE_SHIFT

GP_VS_CTRL_PXL_MODE_SHIFT

#define GP_VS_CTRL_PXL_MODE_SHIFT   2

GP_VS_CTRL_VS_MODE_MASK

#define GP_VS_CTRL_VS_MODE_MASK   0x3 << GP_VS_CTRL_VS_MODE_SHIFT

GP_VS_CTRL_VS_MODE_SHIFT

#define GP_VS_CTRL_VS_MODE_SHIFT   0

GP_VS_INC_INC_E_INIT_PHASE_MASK

#define GP_VS_INC_INC_E_INIT_PHASE_MASK    0X3FFFF << GP_VS_INC_INC_E_INIT_PHASE_SHIFT

GP_VS_INC_INC_E_INIT_PHASE_SHIFT

#define GP_VS_INC_INC_E_INIT_PHASE_SHIFT   0

GP_VS_INC_INC_E_INIT_POS_MASK

#define GP_VS_INC_INC_E_INIT_POS_MASK   0x3 << GP_VS_INC_INC_E_INIT_POS_SHIFT

GP_VS_INC_INC_E_INIT_POS_SHIFT

#define GP_VS_INC_INC_E_INIT_POS_SHIFT   18

GP_VS_INC_INC_MASK

#define GP_VS_INC_INC_MASK   0x1FFFFF << GP_VS_INC_INC_SHIFT

GP_VS_INC_INC_SHIFT

#define GP_VS_INC_INC_SHIFT   0

GP_VS_RESV_VSIZE_MASK

#define GP_VS_RESV_VSIZE_MASK   0xFFFF << GP_VS_RESV_VSIZE_SHIFT

GP_VS_RESV_VSIZE_SHIFT

#define GP_VS_RESV_VSIZE_SHIFT   0

GP_VS_VS_CTRL

#define GP_VS_VS_CTRL   REG(0x2400)

GP_VS_VS_INC

#define GP_VS_VS_INC   REG(0x2408)

GP_VS_VS_INC_INC_E

#define GP_VS_VS_INC_INC_E   REG(0x240c)

GP_VS_VS_INC_INC_O

#define GP_VS_VS_INC_INC_O   REG(0x2410)

GP_VS_VS_RESV

#define GP_VS_VS_RESV   REG(0x2404)

LAYER_OUT_IDX_MASK

#define LAYER_OUT_IDX_MASK   0xF << LAYER_OUT_IDX_SHIFT

LAYER_OUT_IDX_SHIFT

#define LAYER_OUT_IDX_SHIFT   0

MLC_BG_AFLU_AFLU_TIME

#define MLC_BG_AFLU_AFLU_TIME   REG(0x7228)

MLC_BG_AFLU_TIMER_MASK

#define MLC_BG_AFLU_TIMER_MASK   0xFFFFFFFF << MLC_BG_AFLU_TIMER_SHIFT

MLC_BG_AFLU_TIMER_SHIFT

#define MLC_BG_AFLU_TIMER_SHIFT   0

MLC_BG_COLOR

#define MLC_BG_COLOR   REG(0x7224)

MLC_BG_CTRL

#define MLC_BG_CTRL   REG(0x7220)

MLC_CANVAS_COLOR

#define MLC_CANVAS_COLOR   REG(0x7230)

MLC_CLK_CLK_RATIO

#define MLC_CLK_CLK_RATIO   REG(0x7234)

MLC_CLK_RATIO_MASK

#define MLC_CLK_RATIO_MASK   0xFFFF << MLC_CLK_RATIO_SHIFT

MLC_CLK_RATIO_SHIFT

#define MLC_CLK_RATIO_SHIFT   0

MLC_INT_MASK

#define MLC_INT_MASK   REG(0x7240)

MLC_INT_STATUS

#define MLC_INT_STATUS   REG(0x7244)

MLC_LAYER_COUNT

#define MLC_LAYER_COUNT   2

MLC_LAYER_JMP

#define MLC_LAYER_JMP   0x30

MLC_MASK_ERR_L_0_MASK

#define MLC_MASK_ERR_L_0_MASK   0x1 << MLC_MASK_ERR_L_0_SHIFT

MLC_MASK_ERR_L_0_SHIFT

#define MLC_MASK_ERR_L_0_SHIFT   7

MLC_MASK_ERR_L_1_MASK

#define MLC_MASK_ERR_L_1_MASK   0x1 << MLC_MASK_ERR_L_1_SHIFT

MLC_MASK_ERR_L_1_SHIFT

#define MLC_MASK_ERR_L_1_SHIFT   8

MLC_MASK_ERR_L_2_MASK

#define MLC_MASK_ERR_L_2_MASK   0x1 << MLC_MASK_ERR_L_2_SHIFT

MLC_MASK_ERR_L_2_SHIFT

#define MLC_MASK_ERR_L_2_SHIFT   9

MLC_MASK_ERR_L_3_MASK

#define MLC_MASK_ERR_L_3_MASK   0x1 << MLC_MASK_ERR_L_3_SHIFT

MLC_MASK_ERR_L_3_SHIFT

#define MLC_MASK_ERR_L_3_SHIFT   10

MLC_MASK_ERR_L_4_MASK

#define MLC_MASK_ERR_L_4_MASK   0x1 << MLC_MASK_ERR_L_4_SHIFT

MLC_MASK_ERR_L_4_SHIFT

#define MLC_MASK_ERR_L_4_SHIFT   11

MLC_MASK_ERR_L_5_MASK

#define MLC_MASK_ERR_L_5_MASK   0x1 << MLC_MASK_ERR_L_5_SHIFT

MLC_MASK_ERR_L_5_SHIFT

#define MLC_MASK_ERR_L_5_SHIFT   12

MLC_MASK_FLU_L_0_MASK

#define MLC_MASK_FLU_L_0_MASK   0x1 << MLC_MASK_FLU_L_0_SHIFT

MLC_MASK_FLU_L_0_SHIFT

#define MLC_MASK_FLU_L_0_SHIFT   1

MLC_MASK_FLU_L_1_MASK

#define MLC_MASK_FLU_L_1_MASK   0x1 << MLC_MASK_FLU_L_1_SHIFT

MLC_MASK_FLU_L_1_SHIFT

#define MLC_MASK_FLU_L_1_SHIFT   2

MLC_MASK_FLU_L_2_MASK

#define MLC_MASK_FLU_L_2_MASK   0x1 << MLC_MASK_FLU_L_2_SHIFT

MLC_MASK_FLU_L_2_SHIFT

#define MLC_MASK_FLU_L_2_SHIFT   3

MLC_MASK_FLU_L_3_MASK

#define MLC_MASK_FLU_L_3_MASK   0x1 << MLC_MASK_FLU_L_3_SHIFT

MLC_MASK_FLU_L_3_SHIFT

#define MLC_MASK_FLU_L_3_SHIFT   4

MLC_MASK_FLU_L_4_MASK

#define MLC_MASK_FLU_L_4_MASK   0x1 << MLC_MASK_FLU_L_4_SHIFT

MLC_MASK_FLU_L_4_SHIFT

#define MLC_MASK_FLU_L_4_SHIFT   5

MLC_MASK_FLU_L_5_MASK

#define MLC_MASK_FLU_L_5_MASK   0x1 << MLC_MASK_FLU_L_5_SHIFT

MLC_MASK_FLU_L_5_SHIFT

#define MLC_MASK_FLU_L_5_SHIFT   6

MLC_MASK_FRM_END_MASK

#define MLC_MASK_FRM_END_MASK   0x1 << MLC_MASK_FRM_END_SHIFT

MLC_MASK_FRM_END_SHIFT

#define MLC_MASK_FRM_END_SHIFT   0

MLC_PATH_COUNT

#define MLC_PATH_COUNT   3

MLC_PATH_CTRL_

#define MLC_PATH_CTRL_

(

i

)

(REG(0x7200) + MLC_PATH_JMP * i)

MLC_PATH_JMP

#define MLC_PATH_JMP   0x4

MLC_S_CROP_E_L_0_MASK

#define MLC_S_CROP_E_L_0_MASK   0x1 << MLC_S_CROP_E_L_0_SHIFT

MLC_S_CROP_E_L_0_SHIFT

#define MLC_S_CROP_E_L_0_SHIFT   16

MLC_S_CROP_E_L_1_MASK

#define MLC_S_CROP_E_L_1_MASK   0x1 << MLC_S_CROP_E_L_1_SHIFT

MLC_S_CROP_E_L_1_SHIFT

#define MLC_S_CROP_E_L_1_SHIFT   17

MLC_S_CROP_E_L_2_MASK

#define MLC_S_CROP_E_L_2_MASK   0x1 << MLC_S_CROP_E_L_2_SHIFT

MLC_S_CROP_E_L_2_SHIFT

#define MLC_S_CROP_E_L_2_SHIFT   18

MLC_S_CROP_E_L_3_MASK

#define MLC_S_CROP_E_L_3_MASK   0x1 << MLC_S_CROP_E_L_3_SHIFT

MLC_S_CROP_E_L_3_SHIFT

#define MLC_S_CROP_E_L_3_SHIFT   19

MLC_S_CROP_E_L_4_MASK

#define MLC_S_CROP_E_L_4_MASK   0x1 << MLC_S_CROP_E_L_4_SHIFT

MLC_S_CROP_E_L_4_SHIFT

#define MLC_S_CROP_E_L_4_SHIFT   20

MLC_S_CROP_E_L_5_MASK

#define MLC_S_CROP_E_L_5_MASK   0x1 << MLC_S_CROP_E_L_5_SHIFT

MLC_S_CROP_E_L_5_SHIFT

#define MLC_S_CROP_E_L_5_SHIFT   21

MLC_S_E_L_0_MASK

#define MLC_S_E_L_0_MASK   0x1 << MLC_S_E_L_0_SHIFT

MLC_S_E_L_0_SHIFT

#define MLC_S_E_L_0_SHIFT   7

MLC_S_E_L_1_MASK

#define MLC_S_E_L_1_MASK   0x1 << MLC_S_E_L_1_SHIFT

MLC_S_E_L_1_SHIFT

#define MLC_S_E_L_1_SHIFT   8

MLC_S_E_L_2_MASK

#define MLC_S_E_L_2_MASK   0x1 << MLC_S_E_L_2_SHIFT

MLC_S_E_L_2_SHIFT

#define MLC_S_E_L_2_SHIFT   9

MLC_S_E_L_3_MASK

#define MLC_S_E_L_3_MASK   0x1 << MLC_S_E_L_3_SHIFT

MLC_S_E_L_3_SHIFT

#define MLC_S_E_L_3_SHIFT   10

MLC_S_E_L_4_MASK

#define MLC_S_E_L_4_MASK   0x1 << MLC_S_E_L_4_SHIFT

MLC_S_E_L_4_SHIFT

#define MLC_S_E_L_4_SHIFT   11

MLC_S_E_L_5_MASK

#define MLC_S_E_L_5_MASK   0x1 << MLC_S_E_L_5_SHIFT

MLC_S_E_L_5_SHIFT

#define MLC_S_E_L_5_SHIFT   12

MLC_S_FLU_L_0_MASK

#define MLC_S_FLU_L_0_MASK   0x1 << MLC_S_FLU_L_0_SHIFT

MLC_S_FLU_L_0_SHIFT

#define MLC_S_FLU_L_0_SHIFT   1

MLC_S_FLU_L_1_MASK

#define MLC_S_FLU_L_1_MASK   0x1 << MLC_S_FLU_L_1_SHIFT

MLC_S_FLU_L_1_SHIFT

#define MLC_S_FLU_L_1_SHIFT   2

MLC_S_FLU_L_2_MASK

#define MLC_S_FLU_L_2_MASK   0x1 << MLC_S_FLU_L_2_SHIFT

MLC_S_FLU_L_2_SHIFT

#define MLC_S_FLU_L_2_SHIFT   3

MLC_S_FLU_L_3_MASK

#define MLC_S_FLU_L_3_MASK   0x1 << MLC_S_FLU_L_3_SHIFT

MLC_S_FLU_L_3_SHIFT

#define MLC_S_FLU_L_3_SHIFT   4

MLC_S_FLU_L_4_MASK

#define MLC_S_FLU_L_4_MASK   0x1 << MLC_S_FLU_L_4_SHIFT

MLC_S_FLU_L_4_SHIFT

#define MLC_S_FLU_L_4_SHIFT   5

MLC_S_FLU_L_5_MASK

#define MLC_S_FLU_L_5_MASK   0x1 << MLC_S_FLU_L_5_SHIFT

MLC_S_FLU_L_5_SHIFT

#define MLC_S_FLU_L_5_SHIFT   6

MLC_S_FRM_END_MASK

#define MLC_S_FRM_END_MASK   0x1 << MLC_S_FRM_END_SHIFT

MLC_S_FRM_END_SHIFT

#define MLC_S_FRM_END_SHIFT   0

MLC_S_SLOWD_L_0_MASK

#define MLC_S_SLOWD_L_0_MASK   0x1 << MLC_S_SLOWD_L_0_SHIFT

MLC_S_SLOWD_L_0_SHIFT

#define MLC_S_SLOWD_L_0_SHIFT   22

MLC_S_SLOWD_L_1_MASK

#define MLC_S_SLOWD_L_1_MASK   0x1 << MLC_S_SLOWD_L_1_SHIFT

MLC_S_SLOWD_L_1_SHIFT

#define MLC_S_SLOWD_L_1_SHIFT   23

MLC_S_SLOWD_L_2_MASK

#define MLC_S_SLOWD_L_2_MASK   0x1 << MLC_S_SLOWD_L_2_SHIFT

MLC_S_SLOWD_L_2_SHIFT

#define MLC_S_SLOWD_L_2_SHIFT   24

MLC_S_SLOWD_L_3_MASK

#define MLC_S_SLOWD_L_3_MASK   0x1 << MLC_S_SLOWD_L_3_SHIFT

MLC_S_SLOWD_L_3_SHIFT

#define MLC_S_SLOWD_L_3_SHIFT   25

MLC_S_SLOWD_L_4_MASK

#define MLC_S_SLOWD_L_4_MASK   0x1 << MLC_S_SLOWD_L_4_SHIFT

MLC_S_SLOWD_L_4_SHIFT

#define MLC_S_SLOWD_L_4_SHIFT   26

MLC_S_SLOWD_L_5_MASK

#define MLC_S_SLOWD_L_5_MASK   0x1 << MLC_S_SLOWD_L_5_SHIFT

MLC_S_SLOWD_L_5_SHIFT

#define MLC_S_SLOWD_L_5_SHIFT   27

MLC_SF_AFLU_AFLU_TIME_

#define MLC_SF_AFLU_AFLU_TIME_

(

i

)

(REG(0x702c) + MLC_LAYER_JMP * i)

MLC_SF_AFLU_EN_MASK

#define MLC_SF_AFLU_EN_MASK   0x1 << MLC_SF_AFLU_EN_SHIFT

MLC_SF_AFLU_EN_SHIFT

#define MLC_SF_AFLU_EN_SHIFT   4

MLC_SF_AFLU_PSEL_MASK

#define MLC_SF_AFLU_PSEL_MASK   0x1 << MLC_SF_AFLU_PSEL_SHIFT

MLC_SF_AFLU_PSEL_SHIFT

#define MLC_SF_AFLU_PSEL_SHIFT   5

MLC_SF_AFLU_TIMER_MASK

#define MLC_SF_AFLU_TIMER_MASK   0xFFFFFFFF << MLC_SF_AFLU_TIMER_SHIFT

MLC_SF_AFLU_TIMER_SHIFT

#define MLC_SF_AFLU_TIMER_SHIFT   0

MLC_SF_CKEY_ALPHA_A_MASK

#define MLC_SF_CKEY_ALPHA_A_MASK   0xFF << MLC_SF_CKEY_ALPHA_A_SHIFT

MLC_SF_CKEY_ALPHA_A_SHIFT

#define MLC_SF_CKEY_ALPHA_A_SHIFT   0

MLC_SF_CKEY_B_LV_

#define MLC_SF_CKEY_B_LV_

(

i

)

(REG(0x7028) + MLC_LAYER_JMP * i)

MLC_SF_CKEY_CKEY_ALPHA_

#define MLC_SF_CKEY_CKEY_ALPHA_

(

i

)

(REG(0x701c) + MLC_LAYER_JMP * i)

MLC_SF_CKEY_EN_MASK

#define MLC_SF_CKEY_EN_MASK   0x1 << MLC_SF_CKEY_EN_SHIFT

MLC_SF_CKEY_EN_SHIFT

#define MLC_SF_CKEY_EN_SHIFT   3

MLC_SF_CKEY_G_LV_

#define MLC_SF_CKEY_G_LV_

(

i

)

(REG(0x7024) + MLC_LAYER_JMP * i)

MLC_SF_CKEY_LV_DN_MASK

#define MLC_SF_CKEY_LV_DN_MASK   0x3FF << MLC_SF_CKEY_LV_DN_SHIFT

MLC_SF_CKEY_LV_DN_SHIFT

#define MLC_SF_CKEY_LV_DN_SHIFT   0

MLC_SF_CKEY_LV_UP_MASK

#define MLC_SF_CKEY_LV_UP_MASK   0x3FF << MLC_SF_CKEY_LV_UP_SHIFT

MLC_SF_CKEY_LV_UP_SHIFT

#define MLC_SF_CKEY_LV_UP_SHIFT   16

MLC_SF_CKEY_R_LV_

#define MLC_SF_CKEY_R_LV_

(

i

)

(REG(0x7020) + MLC_LAYER_JMP * i)

MLC_SF_CROP_EN_MASK

#define MLC_SF_CROP_EN_MASK   0x1 << MLC_SF_CROP_EN_SHIFT

MLC_SF_CROP_EN_SHIFT

#define MLC_SF_CROP_EN_SHIFT   1

MLC_SF_CROP_END_MASK

#define MLC_SF_CROP_END_MASK   0xFFFF << MLC_SF_CROP_END_SHIFT

MLC_SF_CROP_END_SHIFT

#define MLC_SF_CROP_END_SHIFT   16

MLC_SF_CROP_H_POS_

#define MLC_SF_CROP_H_POS_

(

i

)

(REG(0x7010) + MLC_LAYER_JMP * i)

MLC_SF_CROP_START_MASK

#define MLC_SF_CROP_START_MASK   0xFFFF << MLC_SF_CROP_START_SHIFT

MLC_SF_CROP_START_SHIFT

#define MLC_SF_CROP_START_SHIFT   0

MLC_SF_CROP_V_POS_

#define MLC_SF_CROP_V_POS_

(

i

)

(REG(0x7014) + MLC_LAYER_JMP * i)

MLC_SF_CTRL_

#define MLC_SF_CTRL_

(

i

)

(REG(0x7000) + MLC_LAYER_JMP * i)

MLC_SF_EN_MASK

#define MLC_SF_EN_MASK   0x1 << MLC_SF_EN_SHIFT

MLC_SF_EN_SHIFT

#define MLC_SF_EN_SHIFT   0

MLC_SF_G_ALPHA_A_MASK

#define MLC_SF_G_ALPHA_A_MASK   0xFF << MLC_SF_G_ALPHA_A_SHIFT

MLC_SF_G_ALPHA_A_SHIFT

#define MLC_SF_G_ALPHA_A_SHIFT   0

MLC_SF_G_ALPHA_EN_MASK

#define MLC_SF_G_ALPHA_EN_MASK   0x1 << MLC_SF_G_ALPHA_EN_SHIFT

MLC_SF_G_ALPHA_EN_SHIFT

#define MLC_SF_G_ALPHA_EN_SHIFT   2

MLC_SF_G_G_ALPHA_

#define MLC_SF_G_G_ALPHA_

(

i

)

(REG(0x7018) + MLC_LAYER_JMP * i)

MLC_SF_H_H_SPOS_

#define MLC_SF_H_H_SPOS_

(

i

)

(REG(0x7004) + MLC_LAYER_JMP * i)

MLC_SF_H_SPOS_H_MASK

#define MLC_SF_H_SPOS_H_MASK   0x1FFFF << MLC_SF_H_SPOS_H_SHIFT

MLC_SF_H_SPOS_H_SHIFT

#define MLC_SF_H_SPOS_H_SHIFT   0

MLC_SF_PROT_VAL_MASK

#define MLC_SF_PROT_VAL_MASK   0x3F << MLC_SF_PROT_VAL_SHIFT

MLC_SF_PROT_VAL_SHIFT

#define MLC_SF_PROT_VAL_SHIFT   8

MLC_SF_SF_SIZE_

#define MLC_SF_SF_SIZE_

(

i

)

(REG(0x700c) + MLC_LAYER_JMP * i)

MLC_SF_SIZE_H_MASK

#define MLC_SF_SIZE_H_MASK   0xFFFF << MLC_SF_SIZE_H_SHIFT

MLC_SF_SIZE_H_SHIFT

#define MLC_SF_SIZE_H_SHIFT   0

MLC_SF_SIZE_V_MASK

#define MLC_SF_SIZE_V_MASK   0xFFFFUL << MLC_SF_SIZE_V_SHIFT

MLC_SF_SIZE_V_SHIFT

#define MLC_SF_SIZE_V_SHIFT   16

MLC_SF_SLOWDOWN_EN_MASK

#define MLC_SF_SLOWDOWN_EN_MASK   0x1 << MLC_SF_SLOWDOWN_EN_SHIFT

MLC_SF_SLOWDOWN_EN_SHIFT

#define MLC_SF_SLOWDOWN_EN_SHIFT   6

MLC_SF_V_SPOS_V_MASK

#define MLC_SF_V_SPOS_V_MASK   0x1FFFF << MLC_SF_V_SPOS_V_SHIFT

MLC_SF_V_SPOS_V_SHIFT

#define MLC_SF_V_SPOS_V_SHIFT   0

MLC_SF_V_V_SPOS_

#define MLC_SF_V_V_SPOS_

(

i

)

(REG(0x7008) + MLC_LAYER_JMP * i)

MLC_SF_VPOS_PROT_EN_MASK

#define MLC_SF_VPOS_PROT_EN_MASK   0x1 << MLC_SF_VPOS_PROT_EN_SHIFT

MLC_SF_VPOS_PROT_EN_SHIFT

#define MLC_SF_VPOS_PROT_EN_SHIFT   7

PD_DES_IDX_MASK

#define PD_DES_IDX_MASK   0x7 << PD_DES_IDX_SHIFT

PD_DES_IDX_SHIFT

#define PD_DES_IDX_SHIFT   8

PD_MODE_MASK

#define PD_MODE_MASK   0x1F << PD_MODE_SHIFT

PD_MODE_SHIFT

#define PD_MODE_SHIFT   20

PD_OUT_IDX_MASK

#define PD_OUT_IDX_MASK   0x7 << PD_OUT_IDX_SHIFT

PD_OUT_IDX_SHIFT

#define PD_OUT_IDX_SHIFT   12

PD_OUT_SEL_MASK

#define PD_OUT_SEL_MASK   0x1 << PD_OUT_SEL_SHIFT

PD_OUT_SEL_SHIFT

#define PD_OUT_SEL_SHIFT   28

PD_SRC_IDX_MASK

#define PD_SRC_IDX_MASK   0x7 << PD_SRC_IDX_SHIFT

PD_SRC_IDX_SHIFT

#define PD_SRC_IDX_SHIFT   4

PIPE_COMP_SWAP_MASK

#define PIPE_COMP_SWAP_MASK   0xF << PIPE_COMP_SWAP_SHIFT

PIPE_COMP_SWAP_SHIFT

#define PIPE_COMP_SWAP_SHIFT   12

PIPE_ENDIAN_CTRL_MASK

#define PIPE_ENDIAN_CTRL_MASK   0x7 << PIPE_ENDIAN_CTRL_SHIFT

PIPE_ENDIAN_CTRL_SHIFT

#define PIPE_ENDIAN_CTRL_SHIFT   16

PIPE_FMT_MASK

#define PIPE_FMT_MASK   0x3 << PIPE_FMT_SHIFT

PIPE_FMT_SHIFT

#define PIPE_FMT_SHIFT   0

PIPE_MODE_MASK

#define PIPE_MODE_MASK   0x7 << PIPE_MODE_SHIFT

PIPE_MODE_SHIFT

#define PIPE_MODE_SHIFT   2

PIPE_RGB_YUV_MASK

#define PIPE_RGB_YUV_MASK   1 << PIPE_RGB_YUV_SHIFT

PIPE_RGB_YUV_SHIFT

#define PIPE_RGB_YUV_SHIFT   8

PIPE_ROT_MASK

#define PIPE_ROT_MASK   0x7 << PIPE_ROT_SHIFT

PIPE_ROT_SHIFT

#define PIPE_ROT_SHIFT   9

PIPE_UV_MODE_MASK

#define PIPE_UV_MODE_MASK   0x3 << PIPE_UV_MODE_SHIFT

PIPE_UV_MODE_SHIFT

#define PIPE_UV_MODE_SHIFT   5

PIPE_UV_SWAP_MASK

#define PIPE_UV_SWAP_MASK   1 << PIPE_UV_SWAP_SHIFT

PIPE_UV_SWAP_SHIFT

#define PIPE_UV_SWAP_SHIFT   7

PMA_EN_MASK

#define PMA_EN_MASK   0x1 << PMA_EN_SHIFT

PMA_EN_SHIFT

#define PMA_EN_SHIFT   29

RDMA_AXI_CTRL_CACHE_MASK

#define RDMA_AXI_CTRL_CACHE_MASK   0xF << RDMA_AXI_CTRL_CACHE_SHIFT

RDMA_AXI_CTRL_CACHE_SHIFT

#define RDMA_AXI_CTRL_CACHE_SHIFT   0

RDMA_AXI_CTRL_CTRL_

#define RDMA_AXI_CTRL_CTRL_

(

i

)

(REG(0x1018) + CHN_JMP * i)

RDMA_AXI_CTRL_PORT_MASK

#define RDMA_AXI_CTRL_PORT_MASK   0x3 << RDMA_AXI_CTRL_PORT_SHIFT

RDMA_AXI_CTRL_PORT_SHIFT

#define RDMA_AXI_CTRL_PORT_SHIFT   4

RDMA_AXI_USER_MASK

#define RDMA_AXI_USER_MASK   0xFFFFF << RDMA_AXI_USER_SHIFT

RDMA_AXI_USER_SHIFT

#define RDMA_AXI_USER_SHIFT   0

RDMA_AXI_USER_USER_

#define RDMA_AXI_USER_USER_

(

i

)

(REG(0x1014) + CHN_JMP * i)

RDMA_BURST_BURST_

#define RDMA_BURST_BURST_

(

i

)

(REG(0x1010) + CHN_JMP * i)

RDMA_BURST_LEN_MASK

#define RDMA_BURST_LEN_MASK   0x7 << RDMA_BURST_LEN_SHIFT

RDMA_BURST_LEN_SHIFT

#define RDMA_BURST_LEN_SHIFT   0

RDMA_BURST_MODE_MASK

#define RDMA_BURST_MODE_MASK   1 << RDMA_BURST_MODE_SHIFT

RDMA_BURST_MODE_SHIFT

#define RDMA_BURST_MODE_SHIFT   3

RDMA_CFIFO_DEP_MASK

#define RDMA_CFIFO_DEP_MASK   0xFFFF << RDMA_CFIFO_DEP_SHIFT

RDMA_CFIFO_DEP_SHIFT

#define RDMA_CFIFO_DEP_SHIFT   16

RDMA_CFIFO_DEPTH_DEPTH_

#define RDMA_CFIFO_DEPTH_DEPTH_

(

i

)

(REG(0x1008) + CHN_JMP * i)

RDMA_CFIFO_DEPTH_MASK

#define RDMA_CFIFO_DEPTH_MASK   (0xFFFF << RDMA_CFIFO_DEPTH_SHIFT)

RDMA_CFIFO_DEPTH_SHIFT

#define RDMA_CFIFO_DEPTH_SHIFT   0

RDMA_CFIFO_EMPTY

#define RDMA_CFIFO_EMPTY   REG(0x150c)

RDMA_CFIFO_FULL

#define RDMA_CFIFO_FULL   REG(0x1508)

RDMA_CH_0_MASK

#define RDMA_CH_0_MASK   1UL << RDMA_CH_0_SHIFT

RDMA_CH_0_SHIFT

#define RDMA_CH_0_SHIFT   0

RDMA_CH_1_MASK

#define RDMA_CH_1_MASK   1UL << RDMA_CH_1_SHIFT

RDMA_CH_1_SHIFT

#define RDMA_CH_1_SHIFT   1

RDMA_CH_2_MASK

#define RDMA_CH_2_MASK   1UL << RDMA_CH_2_SHIFT

RDMA_CH_2_SHIFT

#define RDMA_CH_2_SHIFT   2

RDMA_CH_3_MASK

#define RDMA_CH_3_MASK   1UL << RDMA_CH_3_SHIFT

RDMA_CH_3_SHIFT

#define RDMA_CH_3_SHIFT   3

RDMA_CH_4_MASK

#define RDMA_CH_4_MASK   1UL << RDMA_CH_4_SHIFT

RDMA_CH_4_SHIFT

#define RDMA_CH_4_SHIFT   4

RDMA_CH_IDLE

#define RDMA_CH_IDLE   REG(0x1510)

RDMA_CH_PRIO_P0_MASK

#define RDMA_CH_PRIO_P0_MASK   0x3f << RDMA_CH_PRIO_P0_SHIFT

RDMA_CH_PRIO_P0_SHIFT

#define RDMA_CH_PRIO_P0_SHIFT   0

RDMA_CH_PRIO_P1_MASK

#define RDMA_CH_PRIO_P1_MASK   0x3f << RDMA_CH_PRIO_P1_SHIFT

RDMA_CH_PRIO_P1_SHIFT

#define RDMA_CH_PRIO_P1_SHIFT   8

RDMA_CH_PRIO_PRIO_

#define RDMA_CH_PRIO_PRIO_

(

i

)

(REG(0x100c) + CHN_JMP * i)

RDMA_CH_PRIO_SCHE_MASK

#define RDMA_CH_PRIO_SCHE_MASK   0x3f << RDMA_CH_PRIO_SCHE_SHIFT

RDMA_CH_PRIO_SCHE_SHIFT

#define RDMA_CH_PRIO_SCHE_SHIFT   16

RDMA_CTRL_ARB_SEL_MASK

#define RDMA_CTRL_ARB_SEL_MASK   1 << RDMA_CTRL_ARB_SEL_SHIFT

RDMA_CTRL_ARB_SEL_SHIFT

#define RDMA_CTRL_ARB_SEL_SHIFT   0

RDMA_CTRL_CFG_LOAD_MASK

#define RDMA_CTRL_CFG_LOAD_MASK   1 << RDMA_CTRL_CFG_LOAD_SHIFT

RDMA_CTRL_CFG_LOAD_SHIFT

#define RDMA_CTRL_CFG_LOAD_SHIFT   1

RDMA_CTRL_CTRL

#define RDMA_CTRL_CTRL   REG(0x1400)

RDMA_DEBUG_CTRL

#define RDMA_DEBUG_CTRL   REG(0x1540)

RDMA_DEBUG_STA

#define RDMA_DEBUG_STA   REG(0x1544)

RDMA_DFIFO_DEP_MASK

#define RDMA_DFIFO_DEP_MASK   0xFFFF << RDMA_DFIFO_DEP_SHIFT

RDMA_DFIFO_DEP_SHIFT

#define RDMA_DFIFO_DEP_SHIFT   0

RDMA_DFIFO_DEPTH_DEPTH_

#define RDMA_DFIFO_DEPTH_DEPTH_

(

i

)

(REG(0x1004) + CHN_JMP * i)

RDMA_DFIFO_DEPTH_MASK

#define RDMA_DFIFO_DEPTH_MASK   (0xFFFF << RDMA_DFIFO_DEPTH_SHIFT)

RDMA_DFIFO_DEPTH_SHIFT

#define RDMA_DFIFO_DEPTH_SHIFT   0

RDMA_DFIFO_EMPTY

#define RDMA_DFIFO_EMPTY   REG(0x1504)

RDMA_DFIFO_FULL

#define RDMA_DFIFO_FULL   REG(0x1500)

RDMA_DFIFO_WML_MASK

#define RDMA_DFIFO_WML_MASK   (0xFFFF << RDMA_DFIFO_WML_SHIFT)

RDMA_DFIFO_WML_SHIFT

#define RDMA_DFIFO_WML_SHIFT   0

RDMA_DFIFO_WML_WML_

#define RDMA_DFIFO_WML_WML_

(

i

)

(REG(0x1000) + CHN_JMP * i)

RDMA_INT_MASK

#define RDMA_INT_MASK   REG(0x1520)

RDMA_INT_STATUS

#define RDMA_INT_STATUS   REG(0x1524)

RDMA_SEL_MASK

#define RDMA_SEL_MASK   0x1F << RDMA_SEL_SHIFT

RDMA_SEL_SHIFT

#define RDMA_SEL_SHIFT   0

REG

#define REG

(

x

)

(x)

RLE_A_CHECK_SUM_ST

#define RLE_A_CHECK_SUM_ST   REG(0x513c)

RLE_CTRL

#define RLE_CTRL   REG(0x5120)

RLE_DATA_SIZE_MASK

#define RLE_DATA_SIZE_MASK   0x3 << RLE_DATA_SIZE_SHIFT

RLE_DATA_SIZE_SHIFT

#define RLE_DATA_SIZE_SHIFT   1

RLE_EN_MASK

#define RLE_EN_MASK   0x1 << RLE_EN_SHIFT

RLE_EN_SHIFT

#define RLE_EN_SHIFT   0

RLE_INT_A_ERR_MASK

#define RLE_INT_A_ERR_MASK   0x1 << RLE_INT_A_ERR_SHIFT

RLE_INT_A_ERR_SHIFT

#define RLE_INT_A_ERR_SHIFT   0

RLE_INT_MASK

#define RLE_INT_MASK   REG(0x5140)

RLE_INT_STATUS

#define RLE_INT_STATUS   REG(0x5144)

RLE_INT_U_ERR_MASK

#define RLE_INT_U_ERR_MASK   0x1 << RLE_INT_U_ERR_SHIFT

RLE_INT_U_ERR_SHIFT

#define RLE_INT_U_ERR_SHIFT   2

RLE_INT_V_ERR_MASK

#define RLE_INT_V_ERR_MASK   0x1 << RLE_INT_V_ERR_SHIFT

RLE_INT_V_ERR_SHIFT

#define RLE_INT_V_ERR_SHIFT   3

RLE_INT_Y_ERR_MASK

#define RLE_INT_Y_ERR_MASK   0x1 << RLE_INT_Y_ERR_SHIFT

RLE_INT_Y_ERR_SHIFT

#define RLE_INT_Y_ERR_SHIFT   1

RLE_U_CHECK_SUM_ST

#define RLE_U_CHECK_SUM_ST   REG(0x5134)

RLE_V_CHECK_SUM_ST

#define RLE_V_CHECK_SUM_ST   REG(0x5138)

RLE_Y_CHECK_SUM_ST

#define RLE_Y_CHECK_SUM_ST   REG(0x5130)

RLE_Y_CHECK_SUM_Y_MASK

#define RLE_Y_CHECK_SUM_Y_MASK   0xFFFFFFFF << RLE_Y_CHECK_SUM_Y_SHIFT

RLE_Y_CHECK_SUM_Y_SHIFT

#define RLE_Y_CHECK_SUM_Y_SHIFT   0

RLE_Y_LEN_Y_MASK

#define RLE_Y_LEN_Y_MASK   0xFFFFFF << RLE_Y_LEN_Y_SHIFT

RLE_Y_LEN_Y_SHIFT

#define RLE_Y_LEN_Y_SHIFT   0

RLE_Y_Y_CHECK_SUM

#define RLE_Y_Y_CHECK_SUM   REG(0x5110)

RLE_Y_Y_LEN

#define RLE_Y_Y_LEN   REG(0x5100)

SP_SDW_CTRL_CTRL

#define SP_SDW_CTRL_CTRL   REG(0x5f00)

SP_SDW_CTRL_TRIG_MASK

#define SP_SDW_CTRL_TRIG_MASK   0x1 << SP_SDW_CTRL_TRIG_SHIFT

SP_SDW_CTRL_TRIG_SHIFT

#define SP_SDW_CTRL_TRIG_SHIFT   0

STRIDE_U_MASK

#define STRIDE_U_MASK   0x3FFFFUL << STRIDE_U_SHIFT

STRIDE_U_SHIFT

#define STRIDE_U_SHIFT   0

STRIDE_V_MASK

#define STRIDE_V_MASK   0x3FFFFUL << STRIDE_V_SHIFT

STRIDE_V_SHIFT

#define STRIDE_V_SHIFT   0

STRIDE_Y_MASK

#define STRIDE_Y_MASK   0x3FFFFUL << STRIDE_Y_SHIFT

STRIDE_Y_SHIFT

#define STRIDE_Y_SHIFT   0

WCHN_COUNT

#define WCHN_COUNT   3

WCHN_JUMP

#define WCHN_JUMP   0x20

WDMA_AXI_CTRL_BUFAB_CFG_MASK

#define WDMA_AXI_CTRL_BUFAB_CFG_MASK   1 << WDMA_AXI_CTRL_BUFAB_CFG_SHFIT

WDMA_AXI_CTRL_BUFAB_CFG_SHFIT

#define WDMA_AXI_CTRL_BUFAB_CFG_SHFIT   6

WDMA_AXI_CTRL_CACHE_MASK

#define WDMA_AXI_CTRL_CACHE_MASK   0xF << WDMA_AXI_CTRL_CACHE_SHIFT

WDMA_AXI_CTRL_CACHE_SHIFT

#define WDMA_AXI_CTRL_CACHE_SHIFT   0

WDMA_AXI_CTRL_CHN_RST_MASK

#define WDMA_AXI_CTRL_CHN_RST_MASK   1 << WDMA_AXI_CTRL_CHN_RST_SHIFT

WDMA_AXI_CTRL_CHN_RST_SHIFT

#define WDMA_AXI_CTRL_CHN_RST_SHIFT   7

WDMA_AXI_CTRL_CTRL_

#define WDMA_AXI_CTRL_CTRL_

(

i

)

(REG(0xa018) + WCHN_JUMP * i)

WDMA_AXI_CTRL_PROT_MASK

#define WDMA_AXI_CTRL_PROT_MASK   0x3 << WDMA_AXI_CTRL_PROT_SHIFT

WDMA_AXI_CTRL_PROT_SHIFT

#define WDMA_AXI_CTRL_PROT_SHIFT   4

WDMA_AXI_USER_MASK

#define WDMA_AXI_USER_MASK   0xFFFFF << WDMA_AXI_USER_SHIFT

WDMA_AXI_USER_SHIFT

#define WDMA_AXI_USER_SHIFT   0

WDMA_AXI_USER_USER_

#define WDMA_AXI_USER_USER_

(

i

)

(REG(0xa014) + WCHN_JUMP * i)

WDMA_BURST_BURST_

#define WDMA_BURST_BURST_

(

i

)

(REG(0xa010) + WCHN_JUMP * i)

WDMA_BURST_LEN_MASK

#define WDMA_BURST_LEN_MASK   0x7 << WDMA_BURST_LEN_SHIFT

WDMA_BURST_LEN_SHIFT

#define WDMA_BURST_LEN_SHIFT   0

WDMA_BURST_MODE_MASK

#define WDMA_BURST_MODE_MASK   1 << WDMA_BURST_MODE_SHIFT

WDMA_BURST_MODE_SHIFT

#define WDMA_BURST_MODE_SHIFT   3

WDMA_CFIFO_DEPTH_DEPTH_

#define WDMA_CFIFO_DEPTH_DEPTH_

(

i

)

(REG(0xa008) + WCHN_JUMP * i)

WDMA_CFIFO_DEPTH_MASK

#define WDMA_CFIFO_DEPTH_MASK   0xFFFF << WDMA_CFIFO_DEPTH_SHIFT

WDMA_CFIFO_DEPTH_SHIFT

#define WDMA_CFIFO_DEPTH_SHIFT   0

WDMA_CFIFO_EMPTY_CH_0_MASK

#define WDMA_CFIFO_EMPTY_CH_0_MASK   1 << WDMA_CFIFO_EMPTY_CH_0_SHIFT

WDMA_CFIFO_EMPTY_CH_0_SHIFT

#define WDMA_CFIFO_EMPTY_CH_0_SHIFT   0

WDMA_CFIFO_EMPTY_CH_1_MASK

#define WDMA_CFIFO_EMPTY_CH_1_MASK   1 << WDMA_CFIFO_EMPTY_CH_1_SHIFT

WDMA_CFIFO_EMPTY_CH_1_SHIFT

#define WDMA_CFIFO_EMPTY_CH_1_SHIFT   1

WDMA_CFIFO_EMPTY_CH_2_MASK

#define WDMA_CFIFO_EMPTY_CH_2_MASK   1 << WDMA_CFIFO_EMPTY_CH_2_SHIFT

WDMA_CFIFO_EMPTY_CH_2_SHIFT

#define WDMA_CFIFO_EMPTY_CH_2_SHIFT   2

WDMA_CFIFO_EMPTY_EMPTY

#define WDMA_CFIFO_EMPTY_EMPTY   REG(0xa50c)

WDMA_CFIFO_FULL_CH_0_MASK

#define WDMA_CFIFO_FULL_CH_0_MASK   1 << WDMA_CFIFO_FULL_CH_0_SHFIT

WDMA_CFIFO_FULL_CH_0_SHFIT

#define WDMA_CFIFO_FULL_CH_0_SHFIT   0

WDMA_CFIFO_FULL_CH_1_MASK

#define WDMA_CFIFO_FULL_CH_1_MASK   1 << WDMA_CFIFO_FULL_CH_1_SHFIT

WDMA_CFIFO_FULL_CH_1_SHFIT

#define WDMA_CFIFO_FULL_CH_1_SHFIT   1

WDMA_CFIFO_FULL_CH_2_MASK

#define WDMA_CFIFO_FULL_CH_2_MASK   1 << WDMA_CFIFO_FULL_CH_2_SHFIT

WDMA_CFIFO_FULL_CH_2_SHFIT

#define WDMA_CFIFO_FULL_CH_2_SHFIT   2

WDMA_CFIFO_FULL_FULL

#define WDMA_CFIFO_FULL_FULL   REG(0xa508)

WDMA_CH_IDLE_CH_0_MASK

#define WDMA_CH_IDLE_CH_0_MASK   1 << WDMA_CH_IDLE_CH_0_SHIFT

WDMA_CH_IDLE_CH_0_SHIFT

#define WDMA_CH_IDLE_CH_0_SHIFT   0

WDMA_CH_IDLE_CH_1_MASK

#define WDMA_CH_IDLE_CH_1_MASK   1 << WDMA_CH_IDLE_CH_1_SHIFT

WDMA_CH_IDLE_CH_1_SHIFT

#define WDMA_CH_IDLE_CH_1_SHIFT   1

WDMA_CH_IDLE_CH_2_MASK

#define WDMA_CH_IDLE_CH_2_MASK   1 << WDMA_CH_IDLE_CH_2_SHIFT

WDMA_CH_IDLE_CH_2_SHIFT

#define WDMA_CH_IDLE_CH_2_SHIFT   2

WDMA_CH_IDLE_IDLE

#define WDMA_CH_IDLE_IDLE   REG(0xa510)

WDMA_CH_PRIO_P0_MASK

#define WDMA_CH_PRIO_P0_MASK   0x3F << WDMA_CH_PRIO_P0_SHIFT

WDMA_CH_PRIO_P0_SHIFT

#define WDMA_CH_PRIO_P0_SHIFT   0

WDMA_CH_PRIO_P1_MASK

#define WDMA_CH_PRIO_P1_MASK   0x3F << WDMA_CH_PRIO_P1_SHIFT

WDMA_CH_PRIO_P1_SHIFT

#define WDMA_CH_PRIO_P1_SHIFT   8

WDMA_CH_PRIO_PRIO_

#define WDMA_CH_PRIO_PRIO_

(

i

)

(REG(0xa00c) + WCHN_JUMP * i)

WDMA_CH_PRIO_SCHE_MASK

#define WDMA_CH_PRIO_SCHE_MASK   0x3F << WDMA_CH_PRIO_SCHE_SHIFT

WDMA_CH_PRIO_SCHE_SHIFT

#define WDMA_CH_PRIO_SCHE_SHIFT   16

WDMA_CTRL_ARB_SEL_MASK

#define WDMA_CTRL_ARB_SEL_MASK   1 << WDMA_CTRL_ARB_SEL_SHIFT

WDMA_CTRL_ARB_SEL_SHIFT

#define WDMA_CTRL_ARB_SEL_SHIFT   0

WDMA_CTRL_CFG_LOAD_MASK

#define WDMA_CTRL_CFG_LOAD_MASK   1 << WDMA_CTRL_CFG_LOAD_SHIFT

WDMA_CTRL_CFG_LOAD_SHIFT

#define WDMA_CTRL_CFG_LOAD_SHIFT   1

WDMA_CTRL_CTRL

#define WDMA_CTRL_CTRL   REG(0xa400)

WDMA_DEBUG_CTRL_CTRL

#define WDMA_DEBUG_CTRL_CTRL   REG(0xa540)

WDMA_DEBUG_CTRL_DEBUG_SEL_MASK

#define WDMA_DEBUG_CTRL_DEBUG_SEL_MASK   0x1F << WDMA_DEBUG_CTRL_DEBUG_SEL_SHIFT

WDMA_DEBUG_CTRL_DEBUG_SEL_SHIFT

#define WDMA_DEBUG_CTRL_DEBUG_SEL_SHIFT   0

WDMA_DEBUG_STA_CFIFO_DEP_MASK

#define WDMA_DEBUG_STA_CFIFO_DEP_MASK   0xFFFF << WDMA_DEBUG_STA_CFIFO_DEP_SHIFT

WDMA_DEBUG_STA_CFIFO_DEP_SHIFT

#define WDMA_DEBUG_STA_CFIFO_DEP_SHIFT   16

WDMA_DEBUG_STA_DFIFO_DEP_MASK

#define WDMA_DEBUG_STA_DFIFO_DEP_MASK   0xFFFF << WDMA_DEBUG_STA_DFIFO_DEP_SHIFT

WDMA_DEBUG_STA_DFIFO_DEP_SHIFT

#define WDMA_DEBUG_STA_DFIFO_DEP_SHIFT   0

WDMA_DEBUG_STA_STA

#define WDMA_DEBUG_STA_STA   REG(0xa544)

WDMA_DFIFO_DEPTH_DEPTH_

#define WDMA_DFIFO_DEPTH_DEPTH_

(

i

)

(REG(0xa004) + WCHN_JUMP * i)

WDMA_DFIFO_DEPTH_MASK

#define WDMA_DFIFO_DEPTH_MASK   0xFFFF << WDMA_DFIFO_DEPTH_SHIFT

WDMA_DFIFO_DEPTH_SHIFT

#define WDMA_DFIFO_DEPTH_SHIFT   0

WDMA_DFIFO_EMPTY_CH_0_MASK

#define WDMA_DFIFO_EMPTY_CH_0_MASK   1 << WDMA_DFIFO_EMPTY_CH_0_SHIFT

WDMA_DFIFO_EMPTY_CH_0_SHIFT

#define WDMA_DFIFO_EMPTY_CH_0_SHIFT   0

WDMA_DFIFO_EMPTY_CH_1_MASK

#define WDMA_DFIFO_EMPTY_CH_1_MASK   1 << WDMA_DFIFO_EMPTY_CH_1_SHIFT

WDMA_DFIFO_EMPTY_CH_1_SHIFT

#define WDMA_DFIFO_EMPTY_CH_1_SHIFT   1

WDMA_DFIFO_EMPTY_CH_2_MASK

#define WDMA_DFIFO_EMPTY_CH_2_MASK   1 << WDMA_DFIFO_EMPTY_CH_2_SHIFT

WDMA_DFIFO_EMPTY_CH_2_SHIFT

#define WDMA_DFIFO_EMPTY_CH_2_SHIFT   2

WDMA_DFIFO_EMPTY_EMPTY

#define WDMA_DFIFO_EMPTY_EMPTY   REG(0xa504)

WDMA_DFIFO_FULL_CH_0_MASK

#define WDMA_DFIFO_FULL_CH_0_MASK   1 << WDMA_DFIFO_FULL_CH_0_SHIFT

WDMA_DFIFO_FULL_CH_0_SHIFT

#define WDMA_DFIFO_FULL_CH_0_SHIFT   0

WDMA_DFIFO_FULL_CH_1_MASK

#define WDMA_DFIFO_FULL_CH_1_MASK   1 << WDMA_DFIFO_FULL_CH_1_SHIFT

WDMA_DFIFO_FULL_CH_1_SHIFT

#define WDMA_DFIFO_FULL_CH_1_SHIFT   1

WDMA_DFIFO_FULL_CH_2_MASK

#define WDMA_DFIFO_FULL_CH_2_MASK   1 << WDMA_DFIFO_FULL_CH_2_SHIFT

WDMA_DFIFO_FULL_CH_2_SHIFT

#define WDMA_DFIFO_FULL_CH_2_SHIFT   2

WDMA_DFIFO_FULL_FULL

#define WDMA_DFIFO_FULL_FULL   REG(0xa500)

WDMA_DFIFO_WML_MASK

#define WDMA_DFIFO_WML_MASK   0xFFFF << WDMA_DFIFO_WML_SHIFT

WDMA_DFIFO_WML_SHIFT

#define WDMA_DFIFO_WML_SHIFT   0

WDMA_DFIFO_WML_WML_

#define WDMA_DFIFO_WML_WML_

(

i

)

(REG(0xa000) + WCHN_JUMP * i)

WDMA_INT_MASK_ERR_CH_0_MASK

#define WDMA_INT_MASK_ERR_CH_0_MASK   1 << WDMA_INT_MASK_ERR_CH_0_SHIFT

WDMA_INT_MASK_ERR_CH_0_SHIFT

#define WDMA_INT_MASK_ERR_CH_0_SHIFT   0

WDMA_INT_MASK_ERR_CH_1_MASK

#define WDMA_INT_MASK_ERR_CH_1_MASK   1 << WDMA_INT_MASK_ERR_CH_1_SHIFT

WDMA_INT_MASK_ERR_CH_1_SHIFT

#define WDMA_INT_MASK_ERR_CH_1_SHIFT   1

WDMA_INT_MASK_ERR_CH_2_MASK

#define WDMA_INT_MASK_ERR_CH_2_MASK   1 << WDMA_INT_MASK_ERR_CH_2_SHIFT

WDMA_INT_MASK_ERR_CH_2_SHIFT

#define WDMA_INT_MASK_ERR_CH_2_SHIFT   2

WDMA_INT_MASK_MASK

#define WDMA_INT_MASK_MASK   REG(0xa520)

WDMA_INT_STATUS_ERR_CH_0_MASK

#define WDMA_INT_STATUS_ERR_CH_0_MASK   1 << WDMA_INT_STATUS_ERR_CH_0_SHIFT

WDMA_INT_STATUS_ERR_CH_0_SHIFT

#define WDMA_INT_STATUS_ERR_CH_0_SHIFT   0

WDMA_INT_STATUS_ERR_CH_1_MASK

#define WDMA_INT_STATUS_ERR_CH_1_MASK   1 << WDMA_INT_STATUS_ERR_CH_1_SHIFT

WDMA_INT_STATUS_ERR_CH_1_SHIFT

#define WDMA_INT_STATUS_ERR_CH_1_SHIFT   1

WDMA_INT_STATUS_ERR_CH_2_MASK

#define WDMA_INT_STATUS_ERR_CH_2_MASK   1 << WDMA_INT_STATUS_ERR_CH_2_SHIFT

WDMA_INT_STATUS_ERR_CH_2_SHIFT

#define WDMA_INT_STATUS_ERR_CH_2_SHIFT   2

WDMA_INT_STATUS_STATUS

#define WDMA_INT_STATUS_STATUS   REG(0xa524)

WP_CSC_COEF1_A00_MASK

#define WP_CSC_COEF1_A00_MASK   0x3FFF << WP_CSC_COEF1_A00_SHIFT

WP_CSC_COEF1_A00_SHIFT

#define WP_CSC_COEF1_A00_SHIFT   0

WP_CSC_COEF1_A01_MASK

#define WP_CSC_COEF1_A01_MASK   0x3FFF << WP_CSC_COEF1_A01_SHIFT

WP_CSC_COEF1_A01_SHIFT

#define WP_CSC_COEF1_A01_SHIFT   16

WP_CSC_COEF2_A02_MASK

#define WP_CSC_COEF2_A02_MASK   0x3FFF << WP_CSC_COEF2_A02_SHIFT

WP_CSC_COEF2_A02_SHIFT

#define WP_CSC_COEF2_A02_SHIFT   0

WP_CSC_COEF2_A10_MASK

#define WP_CSC_COEF2_A10_MASK   0x3FFF << WP_CSC_COEF2_A10_SHIFT

WP_CSC_COEF2_A10_SHIFT

#define WP_CSC_COEF2_A10_SHIFT   16

WP_CSC_COEF3_A11_MASK

#define WP_CSC_COEF3_A11_MASK   0x3FFF << WP_CSC_COEF3_A11_SHIFT

WP_CSC_COEF3_A11_SHIFT

#define WP_CSC_COEF3_A11_SHIFT   0

WP_CSC_COEF3_A12_MASK

#define WP_CSC_COEF3_A12_MASK   0x3FFF << WP_CSC_COEF3_A12_SHIFT

WP_CSC_COEF3_A12_SHIFT

#define WP_CSC_COEF3_A12_SHIFT   16

WP_CSC_COEF4_A20_MASK

#define WP_CSC_COEF4_A20_MASK   0x3FFF << WP_CSC_COEF4_A20_SHIFT

WP_CSC_COEF4_A20_SHIFT

#define WP_CSC_COEF4_A20_SHIFT   0

WP_CSC_COEF4_A21_MASK

#define WP_CSC_COEF4_A21_MASK   0x3FFF << WP_CSC_COEF4_A21_SHIFT

WP_CSC_COEF4_A21_SHIFT

#define WP_CSC_COEF4_A21_SHIFT   16

WP_CSC_COEF5_A22_MASK

#define WP_CSC_COEF5_A22_MASK   0x3FFF << WP_CSC_COEF5_A22_SHIFT

WP_CSC_COEF5_A22_SHIFT

#define WP_CSC_COEF5_A22_SHIFT   0

WP_CSC_COEF5_B0_MASK

#define WP_CSC_COEF5_B0_MASK   0x3FFF << WP_CSC_COEF5_B0_SHIFT

WP_CSC_COEF5_B0_SHIFT

#define WP_CSC_COEF5_B0_SHIFT   16

WP_CSC_COEF6_B1_MASK

#define WP_CSC_COEF6_B1_MASK   0x3FFF << WP_CSC_COEF6_B1_SHIFT

WP_CSC_COEF6_B1_SHIFT

#define WP_CSC_COEF6_B1_SHIFT   0

WP_CSC_COEF6_B2_MASK

#define WP_CSC_COEF6_B2_MASK   0x3FFF << WP_CSC_COEF6_B2_SHIFT

WP_CSC_COEF6_B2_SHIFT

#define WP_CSC_COEF6_B2_SHIFT   16

WP_CSC_COEF7_C0_MASK

#define WP_CSC_COEF7_C0_MASK   0x3FF << WP_CSC_COEF7_C0_SHIFT

WP_CSC_COEF7_C0_SHIFT

#define WP_CSC_COEF7_C0_SHIFT   0

WP_CSC_COEF7_C1_MASK

#define WP_CSC_COEF7_C1_MASK   0x3FF << WP_CSC_COEF7_C1_SHIFT

WP_CSC_COEF7_C1_SHIFT

#define WP_CSC_COEF7_C1_SHIFT   16

WP_CSC_COEF8_C2_MASK

#define WP_CSC_COEF8_C2_MASK   0x3FF << WP_CSC_COEF8_C2_SHIFT

WP_CSC_COEF8_C2_SHIFT

#define WP_CSC_COEF8_C2_SHIFT   0

WP_CSC_COEF_COEF1

#define WP_CSC_COEF_COEF1   REG(0xb044)

WP_CSC_COEF_COEF2

#define WP_CSC_COEF_COEF2   REG(0xb048)

WP_CSC_COEF_COEF3

#define WP_CSC_COEF_COEF3   REG(0xb04c)

WP_CSC_COEF_COEF4

#define WP_CSC_COEF_COEF4   REG(0xb050)

WP_CSC_COEF_COEF5

#define WP_CSC_COEF_COEF5   REG(0xb054)

WP_CSC_COEF_COEF6

#define WP_CSC_COEF_COEF6   REG(0xb058)

WP_CSC_COEF_COEF7

#define WP_CSC_COEF_COEF7   REG(0xb05c)

WP_CSC_COEF_COEF8

#define WP_CSC_COEF_COEF8   REG(0xb060)

WP_CSC_CTRL_ALPHA_MASK

#define WP_CSC_CTRL_ALPHA_MASK   1 << WP_CSC_CTRL_ALPHA_SHIFT

WP_CSC_CTRL_ALPHA_SHIFT

#define WP_CSC_CTRL_ALPHA_SHIFT   2

WP_CSC_CTRL_BYPASS_MASK

#define WP_CSC_CTRL_BYPASS_MASK   1 << WP_CSC_CTRL_BYPASS_SHIFT

WP_CSC_CTRL_BYPASS_SHIFT

#define WP_CSC_CTRL_BYPASS_SHIFT   0

WP_CSC_CTRL_CTRL

#define WP_CSC_CTRL_CTRL   REG(0xb040)

WP_CSC_CTRL_SBUP_CONV_MASK

#define WP_CSC_CTRL_SBUP_CONV_MASK   1 << WP_CSC_CTRL_SBUP_CONV_SHIFT

WP_CSC_CTRL_SBUP_CONV_SHIFT

#define WP_CSC_CTRL_SBUP_CONV_SHIFT   1

WP_CTRL_CTRL

#define WP_CTRL_CTRL   REG(0xb000)

WP_CTRL_FRM_MODE_MASK

#define WP_CTRL_FRM_MODE_MASK   1 << WP_CTRL_FRM_MODE_SHIFT

WP_CTRL_FRM_MODE_SHIFT

#define WP_CTRL_FRM_MODE_SHIFT   0

WP_CTRL_HFLIP_MASK

#define WP_CTRL_HFLIP_MASK   1 << WP_CTRL_HFLIP_SHIFT

WP_CTRL_HFLIP_SHIFT

#define WP_CTRL_HFLIP_SHIFT   2

WP_CTRL_PACK_ENDIAN_CTRL_MASK

#define WP_CTRL_PACK_ENDIAN_CTRL_MASK   0x7 << WP_CTRL_PACK_ENDIAN_CTRL_SHIFT

WP_CTRL_PACK_ENDIAN_CTRL_SHIFT

#define WP_CTRL_PACK_ENDIAN_CTRL_SHIFT   16

WP_CTRL_PACK_ROUND_MASK

#define WP_CTRL_PACK_ROUND_MASK   1 << WP_CTRL_PACK_ROUND_SHIFT

WP_CTRL_PACK_ROUND_SHIFT

#define WP_CTRL_PACK_ROUND_SHIFT   12

WP_CTRL_PXL_MODE_MASK

#define WP_CTRL_PXL_MODE_MASK   1 << WP_CTRL_PXL_MODE_SHIFT

WP_CTRL_PXL_MODE_SHIFT

#define WP_CTRL_PXL_MODE_SHIFT   9

WP_CTRL_REFORGE_BYPS_MASK

#define WP_CTRL_REFORGE_BYPS_MASK   1 << WP_CTRL_REFORGE_BYPS_SHIFT

WP_CTRL_REFORGE_BYPS_SHIFT

#define WP_CTRL_REFORGE_BYPS_SHIFT   8

WP_CTRL_ROT_EN_MASK

#define WP_CTRL_ROT_EN_MASK   1 << WP_CTRL_ROT_EN_SHIFT

WP_CTRL_ROT_EN_SHIFT

#define WP_CTRL_ROT_EN_SHIFT   1

WP_CTRL_STR_FMT_MASK

#define WP_CTRL_STR_FMT_MASK   0x3 << WP_CTRL_STR_FMT_SHIFT

WP_CTRL_STR_FMT_SHIFT

#define WP_CTRL_STR_FMT_SHIFT   4

WP_CTRL_TILE_TYPE_MASK

#define WP_CTRL_TILE_TYPE_MASK   0x3 << WP_CTRL_TILE_TYPE_SHIFT

WP_CTRL_TILE_TYPE_SHIFT

#define WP_CTRL_TILE_TYPE_SHIFT   10

WP_CTRL_UV_MODE_MASK

#define WP_CTRL_UV_MODE_MASK   0x3 << WP_CTRL_UV_MODE_SHIFT

WP_CTRL_UV_MODE_SHIFT

#define WP_CTRL_UV_MODE_SHIFT   6

WP_CTRL_VFLIP_MASK

#define WP_CTRL_VFLIP_MASK   1 << WP_CTRL_VFLIP_SHIFT

WP_CTRL_VFLIP_SHIFT

#define WP_CTRL_VFLIP_SHIFT   3

WP_PIX_COMP_BPA_MASK

#define WP_PIX_COMP_BPA_MASK   0xF << WP_PIX_COMP_BPA_SHIFT

WP_PIX_COMP_BPA_SHIFT

#define WP_PIX_COMP_BPA_SHIFT   0

WP_PIX_COMP_BPU_MASK

#define WP_PIX_COMP_BPU_MASK   0xF << WP_PIX_COMP_BPU_SHIFT

WP_PIX_COMP_BPU_SHIFT

#define WP_PIX_COMP_BPU_SHIFT   16

WP_PIX_COMP_BPV_MASK

#define WP_PIX_COMP_BPV_MASK   0xF << WP_PIX_COMP_BPV_SHIFT

WP_PIX_COMP_BPV_SHIFT

#define WP_PIX_COMP_BPV_SHIFT   24

WP_PIX_COMP_BPY_MASK

#define WP_PIX_COMP_BPY_MASK   0x1F << WP_PIX_COMP_BPY_SHIFT

WP_PIX_COMP_BPY_SHIFT

#define WP_PIX_COMP_BPY_SHIFT   8

WP_PIX_COMP_COMP

#define WP_PIX_COMP_COMP   REG(0xb004)

WP_U_BADDR_H_H

#define WP_U_BADDR_H_H   REG(0xb01c)

WP_U_BADDR_H_U_MASK

#define WP_U_BADDR_H_U_MASK   0xFF << WP_U_BADDR_H_U_SHIFT

WP_U_BADDR_H_U_SHIFT

#define WP_U_BADDR_H_U_SHIFT   0

WP_U_BADDR_L_L

#define WP_U_BADDR_L_L   REG(0xb018)

WP_U_BADDR_L_U_MASK

#define WP_U_BADDR_L_U_MASK   0xFFFFFFFF << WP_U_BADDR_L_U_SHIFT

WP_U_BADDR_L_U_SHIFT

#define WP_U_BADDR_L_U_SHIFT   0

WP_U_STRIDE_STRIDE

#define WP_U_STRIDE_STRIDE   REG(0xb02c)

WP_U_STRIDE_U_MASK

#define WP_U_STRIDE_U_MASK   0x3FFFF << WP_U_STRIDE_U_SHIFT

WP_U_STRIDE_U_SHIFT

#define WP_U_STRIDE_U_SHIFT   0

WP_V_BADDR_H_H

#define WP_V_BADDR_H_H   REG(0xb024)

WP_V_BADDR_H_V_MASK

#define WP_V_BADDR_H_V_MASK   0xFF << WP_V_BADDR_H_V_SHIFT

WP_V_BADDR_H_V_SHIFT

#define WP_V_BADDR_H_V_SHIFT   0

WP_V_BADDR_L_L

#define WP_V_BADDR_L_L   REG(0xb020)

WP_V_BADDR_L_V_MASK

#define WP_V_BADDR_L_V_MASK   0xFFFFFFFF << WP_V_BADDR_L_V_SHIFT

WP_V_BADDR_L_V_SHIFT

#define WP_V_BADDR_L_V_SHIFT   0

WP_V_STRIDE_STRIDE

#define WP_V_STRIDE_STRIDE   REG(0xb030)

WP_V_STRIDE_V_MASK

#define WP_V_STRIDE_V_MASK   0x3FFFF << WP_V_STRIDE_V_SHIFT

WP_V_STRIDE_V_SHIFT

#define WP_V_STRIDE_V_SHIFT   0

WP_Y_BADDR_H_H

#define WP_Y_BADDR_H_H   REG(0xb014)

WP_Y_BADDR_H_Y_MASK

#define WP_Y_BADDR_H_Y_MASK   0xFF << WP_Y_BADDR_H_Y_SHIFT

WP_Y_BADDR_H_Y_SHIFT

#define WP_Y_BADDR_H_Y_SHIFT   0

WP_Y_BADDR_L_L

#define WP_Y_BADDR_L_L   REG(0xb010)

WP_Y_BADDR_L_Y_MASK

#define WP_Y_BADDR_L_Y_MASK   0xFFFFFFFF << WP_Y_BADDR_L_Y_SHIFT

WP_Y_BADDR_L_Y_SHIFT

#define WP_Y_BADDR_L_Y_SHIFT   0

WP_Y_STRIDE_STRIDE

#define WP_Y_STRIDE_STRIDE   REG(0xb028)

WP_Y_STRIDE_Y_MASK

#define WP_Y_STRIDE_Y_MASK   0x3FFFF << WP_Y_STRIDE_Y_SHIFT

WP_Y_STRIDE_Y_SHIFT

#define WP_Y_STRIDE_Y_SHIFT   0

WP_YUVDOWN_CTRL_BYPASS_MASK

#define WP_YUVDOWN_CTRL_BYPASS_MASK   1 << WP_YUVDOWN_CTRL_BYPASS_SHIFT

WP_YUVDOWN_CTRL_BYPASS_SHIFT

#define WP_YUVDOWN_CTRL_BYPASS_SHIFT   8

WP_YUVDOWN_CTRL_CTRL

#define WP_YUVDOWN_CTRL_CTRL   REG(0xb008)

WP_YUVDOWN_CTRL_H_FILTER_TYPE_MASK

#define WP_YUVDOWN_CTRL_H_FILTER_TYPE_MASK    0x3 << WP_YUVDOWN_CTRL_H_FILTER_TYPE_SHIFT

WP_YUVDOWN_CTRL_H_FILTER_TYPE_SHIFT

#define WP_YUVDOWN_CTRL_H_FILTER_TYPE_SHIFT   0

WP_YUVDOWN_CTRL_H_INI_OFST_MASK

#define WP_YUVDOWN_CTRL_H_INI_OFST_MASK   0x3 << WP_YUVDOWN_CTRL_H_INI_OFST_SHIFT

WP_YUVDOWN_CTRL_H_INI_OFST_SHIFT

#define WP_YUVDOWN_CTRL_H_INI_OFST_SHIFT   2

WP_YUVDOWN_CTRL_V_BYPASS_MASK

#define WP_YUVDOWN_CTRL_V_BYPASS_MASK   1 << WP_YUVDOWN_CTRL_V_BYPASS_SHIFT

WP_YUVDOWN_CTRL_V_BYPASS_SHIFT

#define WP_YUVDOWN_CTRL_V_BYPASS_SHIFT   9

WP_YUVDOWN_CTRL_V_FILTER_TYPE_MASK

#define WP_YUVDOWN_CTRL_V_FILTER_TYPE_MASK    0x3 << WP_YUVDOWN_CTRL_V_FILTER_TYPE_SHIFT

WP_YUVDOWN_CTRL_V_FILTER_TYPE_SHIFT

#define WP_YUVDOWN_CTRL_V_FILTER_TYPE_SHIFT   4

WP_YUVDOWN_CTRL_V_INI_OFST_MASK

#define WP_YUVDOWN_CTRL_V_INI_OFST_MASK   0x3 << WP_YUVDOWN_CTRL_V_INI_OFST_SHIFT

WP_YUVDOWN_CTRL_V_INI_OFST_SHIFT

#define WP_YUVDOWN_CTRL_V_INI_OFST_SHIFT   6