sdrv_i2s.h

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#ifndef SDRV_I2S_DRIVER_H_
#define SDRV_I2S_DRIVER_H_
 
#include <debug.h>
#include <reg.h>
#include <stdbool.h>
#include <types.h>
 
#include "sdrv_ckgen.h"
#include "sdrv_common.h"
#include "sdrv_dma.h"
#define SDRV_I2S_DAIFMT_FORMAT_MASK 0x0f
 
/* i2s standard phillips interface mode */
#define SDRV_I2S_DAIFMT_STANDARD_PHILLIPS 1
/* i2s left justified interface mode */
#define SDRV_I2S_DAIFMT_LEFT_JUSTIFIED 2
/* i2s right justified interface mode */
#define SDRV_I2S_DAIFMT_RIGHT_JUSTIFIED 3
/* i2s dsp mode-A */
#define SDRV_I2S_DAIFMT_DSP_A 4
/* i2s dsp mode-B */
#define SDRV_I2S_DAIFMT_DSP_B 5
 
/* transfer control mode master or slave */
#define SDRV_I2S_DAIFMT_MASTER_MASK (0x0f0)
#define SDRV_I2S_DAIFMT_CODEC_SLAVE (1 << 4)
#define SDRV_I2S_DAIFMT_CODEC_MASTER (2 << 4)
 
#define SDRV_I2S_DAIFMT_INV_MASK 0x0f00
#define SDRV_I2S_DAIFMT_INV_OFFSET 8
/* normal bit clock + frame */
#define SDRV_I2S_DAIFMT_NB_NF (0 << SDRV_I2S_DAIFMT_INV_OFFSET)
/* normal BCLK + inv FRM */
#define SDRV_I2S_DAIFMT_NB_IF (SDRV_I2S_DAIFMT_INV_OFFSET)
 
/* invert BCLK + nor FRM  */
#define SDRV_I2S_DAIFMT_IB_NF (3 << SDRV_I2S_DAIFMT_INV_OFFSET)
 
/* invert BCLK + FRM */
#define SDRV_I2S_DAIFMT_IB_IF (4 << SDRV_I2S_DAIFMT_INV_OFFSET)
 
#define SDRV_I2S_XFER_NUM_BUFFERS (4U)
#define SDRV_I2S_CHNNELS_COUNT 2
#define SDRV_I2S_CHNNELS_BYTES (SDRV_I2S_SAMPLE_WIDTH_16BITS / 8)
#define SDRV_I2S_DMA_PERIOD_FRAME_SIZE 1024 * 4
#define SDRV_I2S_DMA_PERIOD_BYTES                                              \
    SDRV_I2S_DMA_PERIOD_FRAME_SIZE *SDRV_I2S_CHNNELS_COUNT                     \
        *SDRV_I2S_CHNNELS_BYTES
#define SDRV_I2S_DMA_PERIOD_COUNT 2
#define SDRV_I2S_DMA_BUF_TOTAL_SIZE                                            \
    SDRV_I2S_DMA_PERIOD_SIZE *SDRV_I2S_DMA_PERIOD_COUNT
 
#define SDRV_I2S_SEL_CHNULL 0x00
#define SDRV_I2S_SEL_DATALINE0 (0x01 << 0)
#define SDRV_I2S_SEL_DATALINE1 (0x01 << 1)
#define SDRV_I2S_SEL_DATALINE2 (0x01 << 2)
#define SDRV_I2S_SEL_DATALINE3 (0x01 << 3)
#define SDRV_I2S_SEL_DATALINE4 (0x01 << 4)
#define SDRV_I2S_SEL_DATALINE5 (0x01 << 5)
#define SDRV_I2S_SEL_DATALINE6 (0x01 << 6)
#define SDRV_I2S_SEL_DATALINE7 (0x01 << 7)
 
typedef enum i2s_channel {
    SDRV_I2S_CHANNEL_NUM_MONO = 1,
    SDRV_I2S_CHANNEL_NUM_STEREO = 2,
    SDRV_I2S_CHANNEL_NUM_3CHANS = 3,
    SDRV_I2S_CHANNEL_NUM_4CHANS = 4,
    SDRV_I2S_CHANNEL_NUM_5CHANS = 5,
    SDRV_I2S_CHANNEL_NUM_6CHANS = 6,
    SDRV_I2S_CHANNEL_NUM_7CHANS = 7,
    SDRV_I2S_CHANNEL_NUM_8CHANS = 8,
    SDRV_I2S_CHANNEL_NUM_9CHANS = 9,
    SDRV_I2S_CHANNEL_NUM_10CHANS = 10,
    SDRV_I2S_CHANNEL_NUM_11CHANS = 11,
    SDRV_I2S_CHANNEL_NUM_12CHANS = 12,
    SDRV_I2S_CHANNEL_NUM_13CHANS = 13,
    SDRV_I2S_CHANNEL_NUM_14CHANS = 14,
    SDRV_I2S_CHANNEL_NUM_15CHANS = 15,
    SDRV_I2S_CHANNEL_NUM_16CHANS = 16,
} sdrv_i2s_channel_t;
 
typedef enum sdrv_i2s_sample_rate {
    SDRV_I2S_SR_NO_INIT = 0,
    SDRV_I2S_SR_5512 = 5512,
    SDRV_I2S_SR_8000 = 8000,
    SDRV_I2S_SR_11025 = 11025,
    SDRV_I2S_SR_16000 = 16000,
    SDRV_I2S_SR_22050 = 22050,
    SDRV_I2S_SR_32000 = 32000,
    SDRV_I2S_SR_44100 = 44100,
    SDRV_I2S_SR_48000 = 48000,
    SDRV_I2S_SR_64000 = 64000,
    SDRV_I2S_SR_88200 = 88200,
    SDRV_I2S_SR_96000 = 96000,
    SDRV_I2S_SR_176400 = 176400,
    SDRV_I2S_SR_192000 = 192000,
} sdrv_i2s_sample_rate_t;
 
typedef enum sdrv_i2s_sample_width {
    SDRV_I2S_SAMPLE_WIDTH_8BITS = 8,
    SDRV_I2S_SAMPLE_WIDTH_16BITS = 16,
    SDRV_I2S_SAMPLE_WIDTH_24BITS = 24,
    SDRV_I2S_SAMPLE_WIDTH_32BITS = 32,
} sdrv_i2s_sample_width_t;
 
typedef enum sdrv_i2s_slot_width {
    SDRV_I2S_SLOT_WIDTH_8BITS = 8,
    SDRV_I2S_SLOT_WIDTH_16BITS = 16,
    SDRV_I2S_SLOT_WIDTH_24BITS = 24,
    SDRV_I2S_SLOT_WIDTH_32BITS = 32,
} sdrv_i2s_slot_width_t;
 
typedef enum {
    SDRV_I2S_STREAM_PLAYBACK = 0,
    SDRV_I2S_STREAM_CAPTURE,
    SDRV_I2S_STREAM_MAX,
} sdrv_i2s_stream_type_t;
 
typedef enum sdrv_i2s_clk_sync_type {
    SDRV_I2S_CLK_TX_SYNC = 0,
    SDRV_I2S_CLK_RX_SYNC,
    SDRV_I2S_CLK_TX_RX_ASYNC,
} sdrv_i2s_clk_sync_type_t;
 
typedef struct sdrv_i2s_dma_buf {
    uint8_t *addr;         
    uint32_t buffer_bytes; 
    uint32_t period_bytes; 
    uint32_t periods;      
    uint32_t appl_ptr; 
    uint32_t hw_ptr;   
    uint32_t boundary; 
} sdrv_i2s_dma_buf_t;
 
typedef enum sdrv_i2s_status {
    SDRV_I2S_STATUS_SUCCESS = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_COMMON, 0),
    SDRV_I2S_STATUS_FAIL = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_I2S, 1),
    SDRV_I2S_STATUS_INVALID_PARAMS =
        SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_I2S, 2),
    SDRV_I2S_STATUS_OVERRUN = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_I2S, 3),
    SDRV_I2S_STATUS_UNDERRUN = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_I2S, 4),
} sdrv_i2s_status_t;
 
typedef struct sdrv_i2s_transfer {
    uint8_t *data;   
    uint32_t length; 
    uint8_t id;      
} sdrv_i2s_transfer_t;
 
/* @brief sdrv i2s transfer callback function. */
typedef void (*sdrv_i2s_callback)(sdrv_i2s_transfer_t *transfer, void *context,
                                  sdrv_i2s_status_t state);
 
typedef struct sdrv_i2s_params {
    uint32_t fmt;                         
    sdrv_i2s_channel_t channels;          
    sdrv_i2s_sample_width_t sample_width; 
    sdrv_i2s_sample_rate_t sample_rate;   
    unsigned int period_bytes;        
    unsigned int periods;             
    sdrv_i2s_channel_t slots;         
    sdrv_i2s_slot_width_t slot_width; /* slot data width */
    unsigned int tx_slot_mask; 
    unsigned int rx_slot_mask; 
    bool usedma;               
    uint8_t *dma_buff;         
} sdrv_i2s_params_t;
 
typedef enum sdrv_i2s_mclk_dir {
    SDRV_I2S_MCLK_IN = 0, 
    SDRV_I2S_MCLK_OUT,    
} sdrv_i2s_mclk_dir_t;
 
typedef enum sdrv_i2s_mclk_sel {
    SDRV_I2S_MCLK_NULL = 0,
    SDRV_I2S_MCLK_0,
    SDRV_I2S_MCLK_1,
} sdrv_i2s_mclk_sel_t;
 
typedef struct sdrv_i2s_config {
    paddr_t base;           
    int id;                 
    uint32_t irq;           
    sdrv_ckgen_node_t *clk; 
    paddr_t dma_base;       
    sdrv_dma_channel_id_e
        tx_channel_id; 
    sdrv_dma_channel_id_e
        rx_channel_id; 
    sdrv_i2s_clk_sync_type_t sync_mode; 
    uint8_t tx_chsel;                   
    uint8_t rx_chsel;                   
    sdrv_i2s_mclk_dir_t mclk_dir;       
    sdrv_i2s_mclk_sel_t mclk_sel;       
} sdrv_i2s_config_t;
 
typedef struct sdrv_i2s_dma_data {
    paddr_t addr;                    
    sdrv_dma_bus_width_e addr_width; 
    unsigned int maxburst;           
    unsigned int fifo_size;          
} sdrv_i2s_dma_data_t;
 
typedef struct sdrv_i2s_stream {
    sdrv_i2s_params_t params;
    bool active;
    bool clk_enable;
    bool pack_mode;
    unsigned threshold;
 
    sdrv_i2s_transfer_t queue[SDRV_I2S_XFER_NUM_BUFFERS];
    uint8_t queue_appl; 
    uint8_t queue_hw;   
    sdrv_i2s_callback callback;
    void *context;
    sdrv_dma_t dma_instance;
    sdrv_dma_channel_t dma_channel;
    sdrv_i2s_dma_data_t dma_data;
    sdrv_i2s_dma_buf_t dma_buf;
} sdrv_i2s_stream_t;
 
typedef struct sdrv_i2s {
    sdrv_i2s_config_t *cfg;      
    uint32_t clk_rate;           
    sdrv_i2s_stream_t stream[2]; 
} sdrv_i2s_t;
 
sdrv_i2s_status_t sdrv_i2s_init(sdrv_i2s_t *i2s, sdrv_i2s_config_t *cfg);
 
sdrv_i2s_status_t sdrv_i2s_get_default_params(sdrv_i2s_t *i2s,
                                              sdrv_i2s_params_t *params,
                                              sdrv_i2s_stream_type_t type);
 
sdrv_i2s_status_t sdrv_i2s_set_params(sdrv_i2s_t *i2s,
                                      sdrv_i2s_params_t *params,
                                      sdrv_i2s_stream_type_t type);
sdrv_i2s_status_t sdrv_i2s_create_transfer(sdrv_i2s_t *i2s,
                                           sdrv_i2s_callback callback,
                                           void *context,
                                           sdrv_i2s_stream_type_t type);
sdrv_i2s_status_t sdrv_i2s_submit_transfer(sdrv_i2s_t *i2s,
                                           sdrv_i2s_transfer_t *transfer,
                                           sdrv_i2s_stream_type_t type);
sdrv_i2s_status_t sdrv_i2s_start(sdrv_i2s_t *i2s, sdrv_i2s_stream_type_t type);
 
sdrv_i2s_status_t sdrv_i2s_stop(sdrv_i2s_t *i2s, sdrv_i2s_stream_type_t type);
 
#endif /* SDRV_I2S_DRIVER_H_ */