SemiDrive SSDK Appication Program Interface PTG3.0
Data Structures | Functions
sdrv_ckgen.h File Reference
#include <sdrv_common.h>
#include <lib/list.h>
#include <types.h>
#include <part.h>
#include <sdrv_rtc.h>

Go to the source code of this file.

Data Structures

struct  sdrv_ckgen_node
 
struct  sdrv_ckgen_slice_node
 
struct  sdrv_ckgen_cg_node
 
struct  sdrv_pll_node
 
struct  sdrv_ckgen_rate_config_node
 
struct  sdrv_ckgen_rate_config
 
struct  sdrv_ckgen_bus_config_node
 
struct  sdrv_ckgen_bus_config
 
struct  sdrv_ckgen_gating_config_node
 
struct  sdrv_ckgen_gating_config
 
struct  sdrv_ckgen_ip_clock_config_node
 
struct  sdrv_ckgen_ip_clock_config
 
struct  sdrv_ckgen_config
 
struct  sdrv_clk
 
struct  sdrv_clk_config
 
struct  sdrv_ckgen_xcg_set
 

Functions

status_t sdrv_clktree_dump (sdrv_clk_config_t *clk_config, sdrv_clk_t *clk_node)
 
int sdrv_xtal24m_enable (sdrv_ckgen_node_t *ckgen, bool enable)
 
int sdrv_xtal24m_from_active_crystal (sdrv_ckgen_node_t *ckgen)
 
int sdrv_fs24m_change_src (sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src)
 
uint32_t sdrv_ckgen_get_fs32k_real_frequency (sdrv_ckgen_node_t *ckgen)
 
int sdrv_xtal32k_enable (sdrv_ckgen_node_t *ckgen, bool enable)
 
int sdrv_xtal32k_enable_nowait (sdrv_ckgen_node_t *ckgen, bool enable)
 
bool sdrv_xtal32k_get_ready_status (sdrv_ckgen_node_t *ckgen)
 
int sdrv_xtal32k_from_active_crystal (sdrv_ckgen_node_t *ckgen)
 
int sdrv_fs32k_change_src (sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src)
 
int sdrv_fs32k_change_src_nowait (sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src)
 
bool sdrv_fs32k_get_src_active_status (sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src)
 
int sdrv_fs32k_lpvd_power_ctrl (sdrv_ckgen_node_t *ckgen, bool power_on)
 
status_t sdrv_pll_set_rate (sdrv_ckgen_node_t *ckgen, uint32_t rate)
 
status_t sdrv_pll_set_rate_with_dsm (sdrv_ckgen_node_t *ckgen, uint32_t rate, bool dsm_en)
 
uint32_t sdrv_pll_get_rate (sdrv_ckgen_node_t *ckgen)
 
status_t sdrv_pll_is_locked (sdrv_ckgen_node_t *ckgen)
 
status_t sdrv_pll_set_ssc_amplitude (sdrv_ckgen_node_t *ckgen, sdrv_ckgen_ssc_amplitude_e amplitude)
 
status_t sdrv_pll_set_ssc_frequency (sdrv_ckgen_node_t *ckgen, sdrv_ckgen_ssc_freq_e ssc_freq)
 
status_t sdrv_pll_set_ssc_mode (sdrv_ckgen_node_t *ckgen, sdrv_ckgen_ssc_mode_e ssc_mode)
 
status_t sdrv_ckgen_set_rate (sdrv_ckgen_node_t *ckgen, uint32_t rate)
 
uint32_t sdrv_ckgen_get_rate (sdrv_ckgen_node_t *ckgen)
 
status_t sdrv_ckgen_bus_set_rate (sdrv_ckgen_node_t *ckgen, uint32_t rate, sdrv_ckgen_bus_post_div_e div)
 
uint32_t sdrv_ckgen_bus_get_rate (sdrv_ckgen_node_t *ckgen, sdrv_ckgen_bus_out_type_e clk_out)
 
status_t sdrv_ckgen_cg_mask (sdrv_ckgen_node_t *ckgen, bool mask)
 
status_t sdrv_ckgen_set_gate (sdrv_ckgen_node_t *ckgen, sdrv_ckgen_lp_mode_e lp_mode, bool gating)
 
status_t sdrv_ckgen_clock_config (sdrv_ckgen_node_t *ckgen, bool enable)
 
status_t sdrv_ckgen_ip_clock_enable (const sdrv_ckgen_node_t *ckgen_ip[], sdrv_ckgen_lp_mode_e mode, bool enable)
 
status_t sdrv_ckgen_set_pll_power (sdrv_ckgen_node_t *ckgen, sdrv_ckgen_lp_mode_e lp_mode, bool power_down)
 
status_t sdrv_ckgen_is_gated (sdrv_ckgen_node_t *ckgen)
 
status_t sdrv_ckgen_slice_gated (sdrv_ckgen_node_t *ckgen)
 
status_t sdrv_ckgen_xcg_type_set (sdrv_ckgen_xcg_set_t *xcg, sdrv_ckgen_lp_mode_e mode, bool gate)
 
status_t sdrv_ckgen_init (sdrv_ckgen_config_t *config)
 

Detailed Description

Copyright
Copyright (c) 2020 Semidrive Semiconductor. All rights reserved.

Macro Definition Documentation

◆ CLK_MHZ

#define CLK_MHZ (   x)    ((x) * 1000 * 1000)

◆ CLK_NODE

#define CLK_NODE (   node)    (sdrv_ckgen_node_t *)&(node.clk_node)

◆ CONFIG_CKGEN_PARENTS_NUM

#define CONFIG_CKGEN_PARENTS_NUM   5

◆ RTC_SS_ACCESS_END

#define RTC_SS_ACCESS_END ( )

◆ RTC_SS_ACCESS_START

#define RTC_SS_ACCESS_START ( )

Typedef Documentation

◆ sdrv_ckgen_bus_config_node_t

typedef struct sdrv_ckgen_bus_config_node sdrv_ckgen_bus_config_node_t

Clock rate config for Bus node.

◆ sdrv_ckgen_bus_config_t

typedef struct sdrv_ckgen_bus_config sdrv_ckgen_bus_config_t

Clock rate config lists for Bus node.

◆ sdrv_ckgen_bus_out_type_e

typedef enum sdrv_ckgen_bus_out_type sdrv_ckgen_bus_out_type_e

Config bus slice node output type. For SF/SP BUS, clk_out_m for core, clk_out_n for AXI, clk_out_p for APB For AP domain bus, clk_out_m not used, clk_out_n for AXI, clk_out_p for APB.

◆ sdrv_ckgen_bus_post_div_e

typedef enum sdrv_ckgen_bus_post_div sdrv_ckgen_bus_post_div_e

Bus slice post divide ratio.

◆ sdrv_ckgen_cg_node_t

typedef struct sdrv_ckgen_cg_node sdrv_ckgen_cg_node_t

Abstract xcg node for driver operate.

◆ sdrv_ckgen_config_t

typedef struct sdrv_ckgen_config sdrv_ckgen_config_t

Initialize clock config for system setup.

◆ sdrv_ckgen_gating_config_node_t

typedef struct sdrv_ckgen_gating_config_node sdrv_ckgen_gating_config_node_t

Gate config for xcg node.

◆ sdrv_ckgen_gating_config_t

typedef struct sdrv_ckgen_gating_config sdrv_ckgen_gating_config_t

Gate config list for XCG node.

◆ sdrv_ckgen_ip_clock_config_node_t

typedef struct sdrv_ckgen_ip_clock_config_node sdrv_ckgen_ip_clock_config_node_t

IP clock enable/disable config node.

◆ sdrv_ckgen_ip_clock_config_t

typedef struct sdrv_ckgen_ip_clock_config sdrv_ckgen_ip_clock_config_t

IP clock enable or disable config.

◆ sdrv_ckgen_lp_mode_e

typedef enum sdrv_ckgen_lp_mode sdrv_ckgen_lp_mode_e

Low power mode for clock config.

◆ sdrv_ckgen_node_t

typedef struct sdrv_ckgen_node sdrv_ckgen_node_t

Abstract clock common node for driver operate.

◆ sdrv_ckgen_rate_config_node_t

typedef struct sdrv_ckgen_rate_config_node sdrv_ckgen_rate_config_node_t

Clock rate config for IP/Core/PLL node.

◆ sdrv_ckgen_rate_config_t

typedef struct sdrv_ckgen_rate_config sdrv_ckgen_rate_config_t

Clock rate config lists for IP/Core/PLL node.

◆ sdrv_ckgen_slice_node_t

typedef struct sdrv_ckgen_slice_node sdrv_ckgen_slice_node_t

Abstract clock slice node for driver operate.

◆ sdrv_ckgen_ssc_amplitude_e

typedef enum sdrv_ckgen_ssc_amplitude sdrv_ckgen_ssc_amplitude_e

PLL Spread amplitude.

◆ sdrv_ckgen_ssc_freq_e

typedef enum sdrv_ckgen_ssc_freq sdrv_ckgen_ssc_freq_e

PLL Spread Modulation frequency.

◆ sdrv_ckgen_ssc_mode_e

typedef enum sdrv_ckgen_ssc_mode sdrv_ckgen_ssc_mode_e

PLL Spread mode.

◆ sdrv_ckgen_type_e

typedef enum sdrv_ckgen_type sdrv_ckgen_type_e

Clock node type.

◆ sdrv_ckgen_xcg_set_t

typedef struct sdrv_ckgen_xcg_set sdrv_ckgen_xcg_set_t

CKGEN XCG List.

◆ sdrv_clk_config_t

typedef struct sdrv_clk_config sdrv_clk_config_t

System default total clock node list.

◆ sdrv_clk_t

typedef struct sdrv_clk sdrv_clk_t

Definition for clock tree node.

◆ sdrv_fs_src_type_e

typedef enum sdrv_fs_src_type sdrv_fs_src_type_e

Function Safe clock source.

◆ sdrv_pll_node_t

typedef struct sdrv_pll_node sdrv_pll_node_t

Abstract pll node for driver operate.

Enumeration Type Documentation

◆ sdrv_ckgen_bus_out_type

enum sdrv_ckgen_bus_out_type

Config bus slice node output type. For SF/SP BUS, clk_out_m for core, clk_out_n for AXI, clk_out_p for APB For AP domain bus, clk_out_m not used, clk_out_n for AXI, clk_out_p for APB.

Enumerator
CKGEN_BUS_CLK_OUT 

use clk_in4, no divide as output clock

CKGEN_BUS_CLK_OUT_M 

output clock divided by div_m_num

CKGEN_BUS_CLK_OUT_N 

output clock divided by div_n_num

CKGEN_BUS_CLK_OUT_P 

output clock divided by div_p_num

CKGEN_BUS_CLK_OUT_Q 

output clock divided by div_q_num

◆ sdrv_ckgen_bus_post_div

enum sdrv_ckgen_bus_post_div

Bus slice post divide ratio.

Enumerator
CKGEN_BUS_DIV_4_2_1 

divm/divn/divp = 4/2/1

CKGEN_BUS_DIV_2_2_1 

divm/divn/divp = 2/2/1

◆ sdrv_ckgen_error

enum sdrv_ckgen_error

CKGEN status error code.

Enumerator
SDRV_CKGEN_POINTER_IS_NULL 
SDRV_CKGEN_XTAL24M_NOT_READY 
SDRV_CKGEN_FS24M_WAIT_ACTIVE_TIMEOUT 
SDRV_CKGEN_XTAL32K_NOT_READY 
SDRV_CKGEN_FS32K_WAIT_ACTIVE_TIMEOUT 
SDRV_CKGEN_PLL_NOT_LOCK 
SDRV_CKGEN_PLL_RATE_WRONG 
SDRV_CKGEN_PLL_LVDS_DIV2_CHG_BUSY 
SDRV_CKGEN_PLL_LVDS_DIV7_CHG_BUSY 
SDRV_CKGEN_PLL_LVDS_CKGEN_CHG_BUSY 
SDRV_CKGEN_PLL_NOT_DSM_MODE 
SDRV_CKGEN_SLICE_TYPE_ERROR 
SDRV_CKGEN_SLICE_NO_SUITABLE_PARENT 
SDRV_CKGEN_SLICE_MAIN_STATUS_ERROR 
SDRV_CKGEN_SLICE_PRE_STATUS_ERROR 
SDRV_CKGEN_SLICE_D0_ACTIVE_ERROR 
SDRV_CKGEN_SLICE_POST_D0_ACTIVE_ERROR 
SDRV_CKGEN_SLICE_DIV_CHG_BUSY 
SDRV_CKGEN_BEYOND_MAX_DIVIDER 
SDRV_CKGEN_FREQUENCY_INCORRECT 
SDRV_CKGEN_CONSTRUCT_CLKTREE_FAILED 
SDRV_CKGEN_PARENT_NODE_NULL 
SDRV_CKGEN_BEYOND_MAX_AXI_RATE 
SDRV_CKGEN_CLOCK_SET_TIMEOUT 

◆ sdrv_ckgen_lp_mode

enum sdrv_ckgen_lp_mode

Low power mode for clock config.

Enumerator
CKGEN_RUN_MODE 

CKGEN RUN MODE

CKGEN_HIB_MODE 

CKGEN HIBERNATE MODE

CKGEN_SLP_MODE 

CKGEN SLEEP MODE

◆ sdrv_ckgen_ssc_amplitude

enum sdrv_ckgen_ssc_amplitude

PLL Spread amplitude.

Enumerator
CKGEN_SSC_0P0_PERCENT 

SSC_DEP 0.0%

CKGEN_SSC_0P1_PERCENT 

SSC_DEP 0.1%

CKGEN_SSC_0P2_PERCENT 

SSC_DEP 0.2%

CKGEN_SSC_0P3_PERCENT 

SSC_DEP 0.3%

CKGEN_SSC_0P4_PERCENT 

SSC_DEP 0.4%

CKGEN_SSC_0P5_PERCENT 

SSC_DEP 0.5%

CKGEN_SSC_0P6_PERCENT 

SSC_DEP 0.6%

CKGEN_SSC_0P7_PERCENT 

SSC_DEP 0.7%

CKGEN_SSC_0P8_PERCENT 

SSC_DEP 0.8%

CKGEN_SSC_0P9_PERCENT 

SSC_DEP 0.9%

CKGEN_SSC_1P0_PERCENT 

SSC_DEP 1.0%

CKGEN_SSC_1P1_PERCENT 

SSC_DEP 1.1%

CKGEN_SSC_1P2_PERCENT 

SSC_DEP 1.2%

CKGEN_SSC_1P3_PERCENT 

SSC_DEP 1.3%

CKGEN_SSC_1P4_PERCENT 

SSC_DEP 1.4%

CKGEN_SSC_1P5_PERCENT 

SSC_DEP 1.5%

CKGEN_SSC_1P6_PERCENT 

SSC_DEP 1.6%

CKGEN_SSC_1P7_PERCENT 

SSC_DEP 1.7%

CKGEN_SSC_1P8_PERCENT 

SSC_DEP 1.8%

CKGEN_SSC_1P9_PERCENT 

SSC_DEP 1.9%

CKGEN_SSC_2P0_PERCENT 

SSC_DEP 2.0%

CKGEN_SSC_2P1_PERCENT 

SSC_DEP 2.1%

CKGEN_SSC_2P2_PERCENT 

SSC_DEP 2.2%

CKGEN_SSC_2P3_PERCENT 

SSC_DEP 2.3%

CKGEN_SSC_2P4_PERCENT 

SSC_DEP 2.4%

CKGEN_SSC_2P5_PERCENT 

SSC_DEP 2.5%

CKGEN_SSC_2P6_PERCENT 

SSC_DEP 2.6%

CKGEN_SSC_2P7_PERCENT 

SSC_DEP 2.7%

CKGEN_SSC_2P8_PERCENT 

SSC_DEP 2.8%

CKGEN_SSC_2P9_PERCENT 

SSC_DEP 2.9%

CKGEN_SSC_3P0_PERCENT 

SSC_DEP 3.0%

CKGEN_SSC_3P1_PERCENT 

SSC_DEP 3.1%

◆ sdrv_ckgen_ssc_freq

enum sdrv_ckgen_ssc_freq

PLL Spread Modulation frequency.

Enumerator
CKGEN_FREF_DIV_507 

For 16MHz ref. It's 31.5KHz

CKGEN_FREF_DIV_761 

For 24MHz ref. It's 31.5KHz

CKGEN_FREF_DIV_793 

For 25MHz ref. It's 31.5KHz

CKGEN_FREF_DIV_857 

For 27MHz ref. It's 31.5KHz

◆ sdrv_ckgen_ssc_mode

enum sdrv_ckgen_ssc_mode

PLL Spread mode.

Enumerator
CKGEN_NO_SSC 

PLL no spread

CKGEN_DOWN_SPREADING 

PLL down spread

CKGEN_CENTER_SPREADING 

PLL center spread

◆ sdrv_ckgen_type

enum sdrv_ckgen_type

Clock node type.

Enumerator
CKGEN_IP_SLICE_TYPE 

ip slice type

CKGEN_SF_BUS_SLICE_TYPE 

sf/sp bus slice type

CKGEN_BUS_SLICE_TYPE 

except sf/sp bus slice type

CKGEN_CORE_SLICE_TYPE 

core slice type

CKGEN_PCG_TYPE 

PCG type

CKGEN_BCG_TYPE 

BCG type

CKGEN_CCG_TYPE 

CCG type

CKGEN_PLL_CG_TYPE 

PLL CG type

CKGEN_XTAL_CG_TYPE 

XTAL CG type

CKGEN_PLL_CTRL_TYPE 

PLL CTRL type

CKGEN_PLL_LVDS_TYPE 

PLL LVDS type

CKGEN_RC24M_TYPE 

RC24M type

CKGEN_FS24M_TYPE 

FS24M type

CKGEN_RC32K_TYPE 

RC32K type

CKGEN_FS32K_TYPE 

FS32K type

◆ sdrv_fs_src_type

enum sdrv_fs_src_type

Function Safe clock source.

Enumerator
FS_SRC_RC 

RC oscillator

FS_SRC_XTAL 

XTAL oscillator

Function Documentation

◆ sdrv_ckgen_bus_get_rate()

uint32_t sdrv_ckgen_bus_get_rate ( sdrv_ckgen_node_t *  ckgen,
sdrv_ckgen_bus_out_type_e  clk_out 
)

Get clock rate for Bus slice node.

This function can get Bus slice clock rate, it can get clk_in4 clock directly without divide, or Clk_out_m/Clk_out_n/Clk_out_p/Clk_out_q divided by m/n/p/q.

Parameters
[in]ckgenckgen node type can be CKGEN_SF_BUS_SLICE_TYPE or CKGEN_BUS_SLICE_TYPE.
[in]clk_outClk_out/Clk_out_m/Clk_out_n/Clk_out_p/Clk_out_q.
Returns
clock rate.

◆ sdrv_ckgen_bus_set_rate()

status_t sdrv_ckgen_bus_set_rate ( sdrv_ckgen_node_t *  ckgen,
uint32_t  rate,
sdrv_ckgen_bus_post_div_e  div 
)

Config clock rate for Bus slice node.

This function configure expected clock rate for specific ckgen BUS slice node, since bus slice can output clock direct, or clock divide by m/n/p/q, and their ratio only has two option, one is 4:2:1, other is 2:2:1. Clk_out_m is for core clock rate, Clk_out_n is for AXI bus clock rate, Clk_out_p is for APB bus clock rate.

Parameters
[in]ckgenckgen node type can be CKGEN_SF_BUS_SLICE_TYPE or CKGEN_BUS_SLICE_TYPE.
[in]rateclock rate to be set for Clk_out_m.
[in]divm/n/p,q ratio select.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_ckgen_cg_mask()

status_t sdrv_ckgen_cg_mask ( sdrv_ckgen_node_t *  ckgen,
bool  mask 
)

Set CG NODE whether participate in low power handshake.

This function config CG Node lowpower mask bit. If set to mask, cg status is ignored under low power handshake. Otherwize, cg status is considerd into low power handshake.

Parameters
[in]ckgenckgen node type can be CG NODE.
[in]masktrue or false.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_ckgen_clock_config()

status_t sdrv_ckgen_clock_config ( sdrv_ckgen_node_t *  ckgen,
bool  enable 
)

Config clock enable or disable in run mode.

This function configure clock gating status in run mode.

Parameters
[in]ckgenckgen node type can be CG NODE.
[in]enableclock enable or disable.
Returns
0 represents success, otherwise failed.

◆ sdrv_ckgen_get_fs32k_real_frequency()

uint32_t sdrv_ckgen_get_fs32k_real_frequency ( sdrv_ckgen_node_t *  ckgen)

Get FS32K real output clock frequency.

This function use FS24M to check FS32K clock frequency. So you must make sure FS24M is accurate. If you want check RC32K frequency, first change FS32K source to RC, then call this function. If you want check XTAL32K frequency, first change FS32K source to XTAL, then call this function.

Parameters
[in]ckgenckgen node type must be CKGEN_FS24M_TYPE.
Returns
Real FS32K output frequency.

◆ sdrv_ckgen_get_rate()

uint32_t sdrv_ckgen_get_rate ( sdrv_ckgen_node_t *  ckgen)

Get clock rate for Core/IP slice node.

This function get clock rate for CORE or IP slice node.

Parameters
[in]ckgenckgen node type can be CKGEN_IP_SLICE_TYPE or CKGEN_CORE_SLICE_TYPE.
Returns
CORE/IP clock rate.

◆ sdrv_ckgen_init()

status_t sdrv_ckgen_init ( sdrv_ckgen_config_t *  config)

System clock initialize.

This function initialize all system clock as pre-defined. It will change core clock to 24M, then config PLL, after PLL is locked, config BUS and CORE to expect rate. After that config IP clock if defined, and enable or disable clock gate.

Parameters
[in]configpre-defined clock config list.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_ckgen_ip_clock_enable()

status_t sdrv_ckgen_ip_clock_enable ( const sdrv_ckgen_node_t *  ckgen_ip[],
sdrv_ckgen_lp_mode_e  mode,
bool  enable 
)

Config IP clock enable/disable in run/sleep/hibernate mode.

This function config all xcg belongs to this IP in run/sleep/hibernate mode.

Parameters
[in]ckgen_ipCG Node list belongs to this IP.
[in]modeRun/Sleep/Hibernate.
[in]enableclock enable or disable.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_ckgen_is_gated()

status_t sdrv_ckgen_is_gated ( sdrv_ckgen_node_t *  ckgen)

Get ckgen xcg node gating status.

This function check whether xcg node is gated.

Parameters
[in]ckgenckgen node type can be CG NODE.
Returns
true represents clock is gated, false represents clock is active, negative is error code.

◆ sdrv_ckgen_set_gate()

status_t sdrv_ckgen_set_gate ( sdrv_ckgen_node_t *  ckgen,
sdrv_ckgen_lp_mode_e  lp_mode,
bool  gating 
)

Config xcg status under run/sleep/hibernate mode.

This function configure clock gating status in run/sleep/hibernate mode, when system enter run/sleep/hibernate mode, hardware auto enable or disable clock as configured.

Parameters
[in]ckgenckgen node type can be CG NODE.
[in]lp_modeRun/Sleep/Hibernate.
[in]gatinggating enable or disable.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_ckgen_set_pll_power()

status_t sdrv_ckgen_set_pll_power ( sdrv_ckgen_node_t *  ckgen,
sdrv_ckgen_lp_mode_e  lp_mode,
bool  power_down 
)

Config PLL power down under run/sleep/hibernate mode.

This function config enable or disable PLL power under run/sleep/hibernate mode.

Parameters
[in]ckgenckgen node type can be CKGEN_PLL_CG_TYPE.
[in]lp_modeRun/Sleep/Hibernate.
[in]power_downpower down enable or disable.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_ckgen_set_rate()

status_t sdrv_ckgen_set_rate ( sdrv_ckgen_node_t *  ckgen,
uint32_t  rate 
)

Config clock rate for Core/IP slice node.

This function configures expected clock rate for specific ckgen node, it will search all his parent nodes, and select a closest clock rate at last.

Parameters
[in]ckgenckgen node type can be CKGEN_IP_SLICE_TYPE or CKGEN_CORE_SLICE_TYPE.
[in]rateexpected clock rate.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_ckgen_slice_gated()

status_t sdrv_ckgen_slice_gated ( sdrv_ckgen_node_t *  ckgen)

Get slice node gating status.

This function check whether slice node is gated.

Parameters
[in]ckgenckgen node type can be IP/Core/Bus slice.
Returns
true represents clock is gated, false represents clock is active, negative is error code.

◆ sdrv_ckgen_xcg_type_set()

status_t sdrv_ckgen_xcg_type_set ( sdrv_ckgen_xcg_set_t *  xcg,
sdrv_ckgen_lp_mode_e  mode,
bool  gate 
)

Config All xcg gate or active.

This function config PCG/BCG/CCG all gate or active.

Parameters
[in]xcgxcg info.
[in]moderun mode.
[in]gatetrue or false.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_clktree_dump()

status_t sdrv_clktree_dump ( sdrv_clk_config_t *  clk_config,
sdrv_clk_t *  clk_node 
)

Dump system clock tree.

Parameters
[in]clk_configsystem total clock node list.
[in]clk_nodethe root clock node begin to dump, if set NULL means dump all clock.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_fs24m_change_src()

int sdrv_fs24m_change_src ( sdrv_ckgen_node_t *  ckgen,
sdrv_fs_src_type_e  src 
)

Config FS24M clock source.

This function select FS24M clock source, RC oscillator or XTAL oscillator.

Parameters
[in]ckgenckgen node type must be CKGEN_FS24M_TYPE.
[in]srcRC oscillator or XTAL oscillator
Returns
true represents success, false represents fail.

◆ sdrv_fs32k_change_src()

int sdrv_fs32k_change_src ( sdrv_ckgen_node_t *  ckgen,
sdrv_fs_src_type_e  src 
)

Config FS32K clock source.

This function select FS32K clock source, RC oscillator or XTAL oscillator.

Parameters
[in]ckgenckgen node type must be CKGEN_FS32K_TYPE.
[in]srcRC oscillator or XTAL oscillator
Returns
true represents success, false represents fail.

◆ sdrv_fs32k_change_src_nowait()

int sdrv_fs32k_change_src_nowait ( sdrv_ckgen_node_t *  ckgen,
sdrv_fs_src_type_e  src 
)

Config FS32K clock source without wait active status.

This function select FS32K clock source, RC oscillator or XTAL oscillator.

Parameters
[in]ckgenckgen node type must be CKGEN_FS32K_TYPE.
[in]srcRC oscillator or XTAL oscillator
Returns
true represents success, false represents fail.

◆ sdrv_fs32k_get_src_active_status()

bool sdrv_fs32k_get_src_active_status ( sdrv_ckgen_node_t *  ckgen,
sdrv_fs_src_type_e  src 
)

Get FS32K clock source active status.

This function get FS32K clock source, RC oscillator or XTAL oscillator, active status.

Parameters
[in]ckgenckgen node type must be CKGEN_FS32K_TYPE.
[in]srcRC oscillator or XTAL oscillator
Returns
true represents clock source as FS32K

◆ sdrv_fs32k_lpvd_power_ctrl()

int sdrv_fs32k_lpvd_power_ctrl ( sdrv_ckgen_node_t *  ckgen,
bool  power_on 
)

Control low power voltage detector power on or down.

Parameters
[in]ckgenckgen node type must be CKGEN_FS32K_TYPE.
[in]power_onTrue or False.
Returns
true represents success, false represents fail.

◆ sdrv_pll_get_rate()

uint32_t sdrv_pll_get_rate ( sdrv_ckgen_node_t *  ckgen)

Get PLL rate.

This function get clock rate for specific PLL.

Parameters
[in]ckgenckgen node type can be CKGEN_PLL_CTRL_TYPE or CKGEN_PLL_LVDS_TYPE.
Returns
pll clock rate.

◆ sdrv_pll_is_locked()

status_t sdrv_pll_is_locked ( sdrv_ckgen_node_t *  ckgen)

Get PLL lock detector status.

This function check whether pll is locked.

Parameters
[in]ckgenckgen node type can be CKGEN_PLL_CTRL_TYPE.
Returns
true represets locked, false represents unlocked, negative is error code.

◆ sdrv_pll_set_rate()

status_t sdrv_pll_set_rate ( sdrv_ckgen_node_t *  ckgen,
uint32_t  rate 
)

Config PLL rate.

This function config clock rate for specific PLL.

Parameters
[in]ckgenckgen node type can be CKGEN_PLL_CTRL_TYPE or CKGEN_PLL_LVDS_TYPE.
[in]rateclock rate to be set.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_pll_set_rate_with_dsm()

status_t sdrv_pll_set_rate_with_dsm ( sdrv_ckgen_node_t *  ckgen,
uint32_t  rate,
bool  dsm_en 
)

Config PLL rate with delta-sigma modulator enable config.

This function config clock rate for specific PLL, and when rate configed work as integer pll, it's up to user whether enable fractional.

Parameters
[in]ckgenckgen node type can be CKGEN_PLL_CTRL_TYPE or CKGEN_PLL_LVDS_TYPE.
[in]rateclock rate to be set.
[in]dsm_endsm enable or not.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_pll_set_ssc_amplitude()

status_t sdrv_pll_set_ssc_amplitude ( sdrv_ckgen_node_t *  ckgen,
sdrv_ckgen_ssc_amplitude_e  amplitude 
)

Set PLL spread amplitude.

This function set SSC amplitude for specific pll.

Parameters
[in]ckgenckgen node only can be CKGEN_PLL_CTRL_TYPE.
[in]amplitudeSSC amplitude 0-31 represents 0.0% - 3.1%.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_pll_set_ssc_frequency()

status_t sdrv_pll_set_ssc_frequency ( sdrv_ckgen_node_t *  ckgen,
sdrv_ckgen_ssc_freq_e  ssc_freq 
)

Set PLL spread frequency.

This function set SSC frequency for specific pll.

Parameters
[in]ckgenckgen node only can be CKGEN_PLL_CTRL_TYPE.
[in]ssc_freqSSC modulation frequency.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_pll_set_ssc_mode()

status_t sdrv_pll_set_ssc_mode ( sdrv_ckgen_node_t *  ckgen,
sdrv_ckgen_ssc_mode_e  ssc_mode 
)

Set PLL spread mode.

This function set SSC mode for specific pll. This function will check PLL work mode first, if pll config DSM_DISABLE, set spread mode will failed.

Parameters
[in]ckgenckgen node only can be CKGEN_PLL_CTRL_TYPE.
[in]ssc_modeSSC mode.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_xtal24m_enable()

int sdrv_xtal24m_enable ( sdrv_ckgen_node_t *  ckgen,
bool  enable 
)

Config XTAL24M oscillator.

This function enable or disable xtal24m oscillator.

Parameters
[in]ckgenckgen node type must be CKGEN_FS24M_TYPE.
[in]enabletrue represents enable oscillator, false represents disable oscillator.
Returns
true represents success, false represents fail.

◆ sdrv_xtal24m_from_active_crystal()

int sdrv_xtal24m_from_active_crystal ( sdrv_ckgen_node_t *  ckgen)

Config XTAL24M oscillator.

This function config 24M clock from external active crystal.

Parameters
[in]ckgenckgen node type must be CKGEN_FS24M_TYPE.
Returns
true represents success, false represents fail.

◆ sdrv_xtal32k_enable()

int sdrv_xtal32k_enable ( sdrv_ckgen_node_t *  ckgen,
bool  enable 
)

Config XTAL32K oscillator.

This function enable or disable xtal32k oscillator.

Parameters
[in]ckgenckgen node type must be CKGEN_FS32K_TYPE.
[in]enabletrue represents enable oscillator, false represents disable oscillator.
Returns
true represents success, false represents fail.

◆ sdrv_xtal32k_enable_nowait()

int sdrv_xtal32k_enable_nowait ( sdrv_ckgen_node_t *  ckgen,
bool  enable 
)

Config XTAL32K oscillator.

This function enable or disable xtal32k oscillator without wait ready status.

Parameters
[in]ckgenckgen node type must be CKGEN_FS32K_TYPE.
[in]enabletrue represents enable oscillator, false represents disable oscillator.
Returns
true represents success, false represents fail.

◆ sdrv_xtal32k_from_active_crystal()

int sdrv_xtal32k_from_active_crystal ( sdrv_ckgen_node_t *  ckgen)

Config XTAL32K oscillator.

This function config 32k clock from external active crystal.

Parameters
[in]ckgenckgen node type must be CKGEN_FS32K_TYPE.
Returns
true represents success, false represents fail.

◆ sdrv_xtal32k_get_ready_status()

bool sdrv_xtal32k_get_ready_status ( sdrv_ckgen_node_t *  ckgen)

Get xtal32k ready status.

This function get xtal32k ready status.

Parameters
[in]ckgenckgen node type must be CKGEN_FS32K_TYPE.
Returns
true represents xtal32k ready, false represents xtal32 not ready.
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