sdrv_epwm.h

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#ifndef SDRV_EPWM_DRV_H_
#define SDRV_EPWM_DRV_H_
 
#include "../source/epwm/sdrv_epwm_reg.h"
 
#if CONFIG_E3L
#if ((CONFIG_E3106) || (CONFIG_E3104))
#define EPWM_SOURCE_CLK 150
#else
#define EPWM_SOURCE_CLK 198
#endif
#else
#define EPWM_SOURCE_CLK 250
#endif
 
#define EPWM_FIFO_A_OFFSET (0xc0U)
#define EPWM_FIFO_B_OFFSET (0xc4U)
#define EPWM_FIFO_C_OFFSET (0xc8U)
#define EPWM_FIFO_D_OFFSET (0xccU)
#define EPWM_CNT_G0_OVF_OFFSET (0x104U)
#define EPWM_CNT_G1_OVF_OFFSET (0x124U)
#define EPWM_INT_STA_EN (0x3f << 0 | 0xf << 20)
#define EPWM_COR_ERR_INT_STA_EN (0xf << 0 | 0xffff << 8)
#define EPWM_UNC_ERR_INT_STA_EN (0xf << 0 | 0xffff << 8)
 
#define EPWM_BM_INT_EN_CHN_D_DMA_REQ_SHIFT (23U)
#define EPWM_BM_INT_EN_CHN_C_DMA_REQ_SHIFT (22U)
#define EPWM_BM_INT_EN_CHN_B_DMA_REQ_SHIFT (21U)
#define EPWM_BM_INT_EN_CHN_A_DMA_REQ_SHIFT (20U)
#define EPWM_BM_INT_EN_CNT_G1_OVF_SHIFT (5U)
#define EPWM_BM_INT_EN_CNT_G0_OVF_SHIFT (4U)
#define EPWM_BM_INT_EN_CMP_D_SHIFT (3U)
#define EPWM_BM_INT_EN_CMP_C_SHIFT (2U)
#define EPWM_BM_INT_EN_CMP_B_SHIFT (1U)
#define EPWM_BM_INT_EN_CMP_A_SHIFT (0U)
 
#define EPWM_BM_ERR_INT_STA_CMP_D_REG_UPD_TWICE_SHIFT (23U)
#define EPWM_BM_ERR_INT_STA_CMP_C_REG_UPD_TWICE_SHIFT (22U)
#define EPWM_BM_ERR_INT_STA_CMP_B_REG_UPD_TWICE_SHIFT (21U)
#define EPWM_BM_ERR_INT_STA_CMP_A_REG_UPD_TWICE_SHIFT (20U)
#define EPWM_BM_ERR_INT_STA_CMP_D_REG_NO_UPD_SHIFT (19U)
#define EPWM_BM_ERR_INT_STA_CMP_C_REG_NO_UPD_SHIFT (18U)
#define EPWM_BM_ERR_INT_STA_CMP_B_REG_NO_UPD_SHIFT (17U)
#define EPWM_BM_ERR_INT_STA_CMP_A_REG_NO_UPD_SHIFT (16U)
#define EPWM_BM_ERR_INT_STA_CMP_D_FAULT_EVENT_SHIFT (15U)
#define EPWM_BM_ERR_INT_STA_CMP_C_FAULT_EVENT_SHIFT (14U)
#define EPWM_BM_ERR_INT_STA_CMP_B_FAULT_EVENT_SHIFT (13U)
#define EPWM_BM_ERR_INT_STA_CMP_A_FAULT_EVENT_SHIFT (12U)
#define EPWM_BM_ERR_INT_STA_CMP_D0_FAULT_SHIFT (11U)
#define EPWM_BM_ERR_INT_STA_CMP_C0_FAULT_SHIFT (10U)
#define EPWM_BM_ERR_INT_STA_CMP_B0_FAULT_SHIFT (9U)
#define EPWM_BM_ERR_INT_STA_CMP_A0_FAULT_SHIFT (8U)
#define EPWM_BM_ERR_INT_STA_FIFO_D_UNDERRUN_SHIFT (3U)
#define EPWM_BM_ERR_INT_STA_FIFO_C_UNDERRUN_SHIFT (2U)
#define EPWM_BM_ERR_INT_STA_FIFO_B_UNDERRUN_SHIFT (1U)
#define EPWM_BM_ERR_INT_STA_FIFO_A_UNDERRUN_SHIFT (0U)
 
#define EPWM_BM_CHN_D_DMA_REQ (1 << EPWM_BM_INT_EN_CHN_D_DMA_REQ_SHIFT)
#define EPWM_BM_CHN_C_DMA_REQ (1 << EPWM_BM_INT_EN_CHN_C_DMA_REQ_SHIFT)
#define EPWM_BM_CHN_B_DMA_REQ (1 << EPWM_BM_INT_EN_CHN_B_DMA_REQ_SHIFT)
#define EPWM_BM_CHN_A_DMA_REQ (1 << EPWM_BM_INT_EN_CHN_A_DMA_REQ_SHIFT)
#define EPWM_BM_CNT_G0_OVF (1 << EPWM_BM_INT_EN_CNT_G0_OVF_SHIFT)
#define EPWM_BM_CNT_G1_OVF (1 << EPWM_BM_INT_EN_CNT_G1_OVF_SHIFT)
#define EPWM_BM_CMP_D (1 << EPWM_BM_INT_EN_CMP_D_SHIFT)
#define EPWM_BM_CMP_C (1 << EPWM_BM_INT_EN_CMP_C_SHIFT)
#define EPWM_BM_CMP_B (1 << EPWM_BM_INT_EN_CMP_B_SHIFT)
#define EPWM_BM_CMP_A (1 << EPWM_BM_INT_EN_CMP_A_SHIFT)
 
#define EPWM_BM_CMP_D_REG_UPD_TWICE                                            \
    (1 << EPWM_BM_ERR_INT_STA_CMP_D_REG_UPD_TWICE_SHIFT)
#define EPWM_BM_CMP_C_REG_UPD_TWICE                                            \
    (1 << EPWM_BM_ERR_INT_STA_CMP_C_REG_UPD_TWICE_SHIFT)
#define EPWM_BM_CMP_B_REG_UPD_TWICE                                            \
    (1 << EPWM_BM_ERR_INT_STA_CMP_B_REG_UPD_TWICE_SHIFT)
#define EPWM_BM_CMP_A_REG_UPD_TWICE                                            \
    (1 << EPWM_BM_ERR_INT_STA_CMP_A_REG_UPD_TWICE_SHIFT)
#define EPWM_BM_CMP_D_REG_NO_UPD                                               \
    (1 << EPWM_BM_ERR_INT_STA_CMP_D_REG_NO_UPD_SHIFT)
#define EPWM_BM_CMP_C_REG_NO_UPD                                               \
    (1 << EPWM_BM_ERR_INT_STA_CMP_C_REG_NO_UPD_SHIFT)
#define EPWM_BM_CMP_B_REG_NO_UPD                                               \
    (1 << EPWM_BM_ERR_INT_STA_CMP_B_REG_NO_UPD_SHIFT)
#define EPWM_BM_CMP_A_REG_NO_UPD                                               \
    (1 << EPWM_BM_ERR_INT_STA_CMP_A_REG_NO_UPD_SHIFT)
#define EPWM_BM_CMP_D_FAULT_EVENT                                              \
    (1 << EPWM_BM_ERR_INT_STA_CMP_D_FAULT_EVENT_SHIFT)
#define EPWM_BM_CMP_C_FAULT_EVENT                                              \
    (1 << EPWM_BM_ERR_INT_STA_CMP_C_FAULT_EVENT_SHIFT)
#define EPWM_BM_CMP_B_FAULT_EVENT                                              \
    (1 << EPWM_BM_ERR_INT_STA_CMP_B_FAULT_EVENT_SHIFT)
#define EPWM_BM_CMP_A_FAULT_EVENT                                              \
    (1 << EPWM_BM_ERR_INT_STA_CMP_A_FAULT_EVENT_SHIFT)
#define EPWM_BM_CMP_D0_FAULT (1 << EPWM_BM_ERR_INT_STA_CMP_D0_FAULT_SHIFT)
#define EPWM_BM_CMP_C0_FAULT (1 << EPWM_BM_ERR_INT_STA_CMP_C0_FAULT_SHIFT)
#define EPWM_BM_CMP_B0_FAULT (1 << EPWM_BM_ERR_INT_STA_CMP_B0_FAULT_SHIFT)
#define EPWM_BM_CMP_A0_FAULT (1 << EPWM_BM_ERR_INT_STA_CMP_A0_FAULT_SHIFT)
#define EPWM_BM_FIFO_D_UNDERRUN (1 << EPWM_BM_ERR_INT_STA_FIFO_D_UNDERRUN_SHIFT)
#define EPWM_BM_FIFO_C_UNDERRUN (1 << EPWM_BM_ERR_INT_STA_FIFO_C_UNDERRUN_SHIFT)
#define EPWM_BM_FIFO_B_UNDERRUN (1 << EPWM_BM_ERR_INT_STA_FIFO_B_UNDERRUN_SHIFT)
#define EPWM_BM_FIFO_A_UNDERRUN (1 << EPWM_BM_ERR_INT_STA_FIFO_A_UNDERRUN_SHIFT)
 
#if CONFIG_E3L
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_D_CMP11 (0x01U << 15U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_D_CMP10 (0x01U << 14U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_D_CMP01 (0x01U << 13U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_D_CMP00 (0x01U << 12U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_C_CMP11 (0x01U << 11U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_C_CMP10 (0x01U << 10U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_C_CMP01 (0x01U << 9U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_C_CMP00 (0x01U << 8U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_B_CMP11 (0x01U << 7U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_B_CMP10 (0x01U << 6U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_B_CMP01 (0x01U << 5U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_B_CMP00 (0x01U << 4U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_A_CMP11 (0x01U << 3U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_A_CMP10 (0x01U << 2U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_A_CMP01 (0x01U << 1U)
#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_A_CMP00 (0x01U << 0U)
#endif
 
typedef enum epwm_cmp_cfg_con_mode {
    EPWM_CONSECUTIVE_MODE,
    EPWM_ONLY_EXECUTE_ONE_TIME,
} epwm_cmp_cfg_con_mode_e;
 
typedef enum epwm_cmp_out_mode {
    EPWM_ONLY_COMP0_OUTPUT,
    EPWM_BOTH_COMP0_AND_COMP1_OUTPUT,
} epwm_cmp_out_mode_e;
 
typedef enum epwm_cfg_ctrl_dma_trig_sel {
    EPWM_CMP_A_CE = 1 << 0,
    EPWM_CMP_B_CE = 1 << 1,
    EPWM_CMP_C_CE = 1 << 2,
    EPWM_CMP_D_CE = 1 << 3,
    EPWM_CNT_G0_CE = 1 << 4,
    EPWM_CNT_G1_CE = 1 << 5,
} epwm_cfg_ctrl_dma_trig_sel_e;
 
typedef struct epwm_multi_cmp_val {
    uint32_t cmp00_val; 
    uint32_t cmp01_val; 
    uint32_t cmp10_val; 
    uint32_t cmp11_val; 
} epwm_multi_cmp_val_t;
 
typedef struct epwm_eid_val {
    uint8_t eid00; 
    uint8_t eid01; 
    uint8_t eid10; 
    uint8_t eid11; 
} epwm_eid_val_t;
 
typedef struct epwm_dual_duty_state {
    uint32_t left_point;  
    uint32_t right_point; 
} epwm_dual_duty_state_t;
 
typedef struct epwm_fs_state {
    bool cmp0_fs_state; 
    bool cmp1_fs_state; 
} epwm_fs_state_t;
 
typedef struct epwm_dma_cfg {
    bool dma_enable;  
    uint8_t fifo_wml; 
} epwm_dma_cfg_t;
 
typedef struct pwm_status {
    uint32_t period; 
    uint32_t duty1;  
    uint32_t duty2;  
} pwm_state_t;
 
typedef struct sdrv_epwm_controller sdrv_epwm_controller_t;
 
typedef void (*pwm_callback_t)(void *arg, uint32_t irq_status);
 
typedef struct epwm_cmp_cfg {
    sdrv_epwm_cnt_gx_e cmp_cnt_sel;
    epwm_cmp_out_mode_e chnl_out_mode;
    epwm_cmp_cfg_con_mode_e con_mode;
    sdrv_epwm_cmp_mode_e cmp_mode;
    sdrv_epwm_cmp_event_out_t out_mode;
    sdrv_epwm_cmp_pulse_wid0_t cmp_pulse_wid0;
    sdrv_epwm_cmp_pulse_wid1_t cmp_pulse_wid1;
    uint8_t refresh_intval;
    bool audio_enable;
    epwm_dma_cfg_t dma_cfg;
    bool sw_rld_mode;
#if CONFIG_E3L
    bool center_align_mode;
#endif
} epwm_cmp_cfg_t;
 
typedef struct sdrv_epwm {
    paddr_t base;
    pwm_callback_t cb;
    epwm_cmp_cfg_t cmp_cfg;
    sdrv_epwm_channel_e chnl;
    epwm_dual_duty_state_t pre_duty;
    sdrv_epwm_controller_t *controller;
} sdrv_epwm_t;
 
/* sdrv epwm controller module */
struct sdrv_epwm_controller {
    uint32_t base;
    uint8_t irq;
    uint32_t irq_id;
    sdrv_epwm_clk_config_src_clk_sel_e clk_src;
    uint16_t clk_div;
    sdrv_epwm_t *epwm_bank[SDRV_EPWM_CHANNEL_NR];
};
 
uint32_t sdrv_epwm_ns_to_val(uint32_t clk, uint32_t ns, uint32_t div);
 
uint32_t sdrv_epwm_ns_to_val_1(uint32_t clk, uint32_t ns, uint32_t div);
 
uint32_t sdrv_epwm_val_to_ns(uint32_t clk, uint32_t val, uint32_t div);
 
void sdrv_epwm_cmp_en(sdrv_epwm_t *dev, bool en);
 
void sdrv_epwm_cnt_en(sdrv_epwm_t *dev, bool en);
 
void sdrv_epwm_start(sdrv_epwm_t *dev);
 
void sdrv_epwm_stop(sdrv_epwm_t *dev);
 
void sdrv_epwm_cnt_ovf_upd(sdrv_epwm_t *dev, uint32_t period);
 
status_t sdrv_epwm_cmp_val_upd(sdrv_epwm_t *dev, const pwm_state_t *state);
 
status_t sdrv_epwm_config(sdrv_epwm_t *dev, const pwm_state_t *state);
 
uint8_t sdrv_epwm_set_callback(sdrv_epwm_t *dev, pwm_callback_t callback);
 
status_t sdrv_epwm_multi_cmp_mode(sdrv_epwm_t *dev, pwm_state_t *state,
                                  epwm_multi_cmp_val_t *multi_cmp);
 
void sdrv_epwm_cnt_clr_cfg(sdrv_epwm_t *dev,
                           sdrv_epwm_event_trigger_mode_e cnt_clr_trig_sel,
                           sdrv_epwm_input_sel_trig_e clr_sel);
 
void sdrv_epwm_cnt_ovf_upd_cfg(sdrv_epwm_t *dev,
                               sdrv_epwm_cnt_cfg_set_upd_sel_e set_mode_sel,
                               sdrv_epwm_event_trigger_mode_e cnt_set_trig_sel,
                               sdrv_epwm_input_sel_trig_e set_sel);
 
void sdrv_epwm_sw_trig(sdrv_epwm_t *dev, sdrv_epwm_sw_trig_ctrl_e trig);
 
void sdrv_epwm_dti(sdrv_epwm_t *dev, sdrv_epwm_cmp_prefin_pol_t *prefin_pol,
                   const uint32_t dti_val);
 
void sdrv_epwm_sse(sdrv_epwm_t *dev, sdrv_epwm_cmp_sse_ctrl_t *sse_cfg,
                   uint32_t sse_reg_val);
 
void sdrv_epwm_mfc(sdrv_epwm_t *dev, uint8_t val);
 
void sdrv_epwm_cmp_data_format(
    sdrv_epwm_t *dev, sdrv_epwm_chn_dma_ctrl_cmp_x_dat_format_e dat_format);
 
void sdrv_epwm_cmp_dither(sdrv_epwm_t *dev, uint8_t clip_rslt,
                          uint16_t init_offset);
 
void sdrv_epwm_cmp_multi_chnl(sdrv_epwm_t *dev, bool full_en);
 
void sdrv_epwm_ce_ctrl(sdrv_epwm_t *dev, bool src_sel);
 
void sdrv_epwm_ce_dma_trig(sdrv_epwm_t *dev, uint8_t sel_trig);
 
void sdrv_epwm_fault_flt(sdrv_epwm_t *dev, sdrv_epwm_fault_flt_t *flt_cfg);
 
void sdrv_epwm_fault_event(sdrv_epwm_t *dev, uint8_t fault_src,
                           sdrv_epwm_cmp_fault_event_ctrl_t *fault_cfg,
                           epwm_fs_state_t *fs_state);
 
void sdrv_epwm_fault_event_clr(sdrv_epwm_t *dev, uint8_t fault_src);
 
void sdrv_epwm_cnt_ovf_dir_upd(sdrv_epwm_t *dev, uint32_t period_cnt);
 
void sdrv_epwm_cmp_bcd_update(sdrv_epwm_t *dev, uint32_t left_point,
                              uint32_t right_point);
 
void sdrv_epwm_cmp_val_upd_bcd(sdrv_epwm_t *dev, uint32_t left_point,
                               uint32_t right_point);
 
void sdrv_epwm_cmp_val_upd_a(sdrv_epwm_t *dev, uint32_t trig_point);
 
void sdrv_epwm_cmp_sw_rld(sdrv_epwm_t *dev);
 
void sdrv_epwm_cmp_input(sdrv_epwm_t *dev, sdrv_epwm_input_sel_t *input_sel,
                         uint8_t set_trig, uint8_t clr_trig);
 
void sdrv_epwm_cmp_a_eid(sdrv_epwm_t *dev, epwm_eid_val_t *eid_val);
 
void sdrv_epwm_init_sta(sdrv_epwm_t *dev, bool cmp0_init, bool cmp1_init);
 
void sdrv_epwm_val_chnl_bcd_upd_split(sdrv_epwm_t *dev,
                                      sdrv_epwm_output_e subchnl,
                                      uint32_t left_point,
                                      uint32_t right_point);
 
void sdrv_epwm_val_chnl_bcd_upd_split_both(sdrv_epwm_t *dev,
                                           uint32_t cmp0_left_point,
                                           uint32_t cmp0_right_point,
                                           uint32_t cmp1_left_point,
                                           uint32_t cmp1_right_point);
 
#if CONFIG_E3L
void sdrv_epwm_center_align_mode_en(sdrv_epwm_t *dev, bool en);
 
void sdrv_epwm_cmp_center_align_val_upd_bcd(sdrv_epwm_t *dev,
                                            uint32_t cmp_point);
 
#endif
 
#endif