SemiDrive SSDK Appication Program Interface PTG3.0
Data Structures | Functions
sdrv_xtrg.h File Reference
#include <compiler.h>
#include <reg.h>
#include <types.h>
#include "part.h"

Go to the source code of this file.

Data Structures

struct  sdrv_xtrg_sig_group
 
struct  sdrv_xtrg_config
 
struct  sdrv_xtrg
 
struct  sdrv_xtrg_swt_config
 
struct  sdrv_xtrg_sse5_config
 
struct  sdrv_xtrg_smon_config
 
struct  sdrv_xtrg_swdt_event_check_config
 
struct  sdrv_xtrg_swdt_pulse_check_config
 
struct  sdrv_xtrg_swdt_config
 
struct  sdrv_xtrg_io_filter_config
 
struct  sdrv_xtrg_tmux_drt_config
 
struct  sdrv_xtrg_tmux_indrt_config
 
struct  sdrv_xtrg_dma_config
 
struct  sdrv_xtrg_smon_cmp_err_config
 

Functions

int sdrv_xtrg_irq_handler (uint32_t irq, void *ctrl)
 
void sdrv_xtrg_init (sdrv_xtrg_t *ctrl, xtrg_callback_t callback, void *para)
 
void sdrv_xtrg_deinit (sdrv_xtrg_t *ctrl)
 
void sdrv_xtrg_int_enable (sdrv_xtrg_t *ctrl, sdrv_xtrg_irq_status_e int_id)
 
void sdrv_xtrg_int_disable (sdrv_xtrg_t *ctrl, sdrv_xtrg_irq_status_e int_id)
 
void sdrv_xtrg_sync_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_config_t *cfg, bool enable)
 
void sdrv_xtrg_io_filter_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_io_filter_config_t *io_filter_cfg, bool enable)
 
int sdrv_xtrg_swt_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_swt_config_t *swt_cfg)
 
void sdrv_xtrg_sse5_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_sse5_config_t *sse5_cfg, bool enable)
 
void sdrv_xtrg_smux_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_config_t *cfg)
 
void sdrv_xtrg_io_out_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_config_t *cfg, bool enable)
 
void sdrv_xtrg_syncmux_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_config_t *cfg)
 
void sdrv_xtrg_tmux0_drt_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_tmux_drt_config_t *tmux_drt_cfg)
 
void sdrv_xtrg_tmux0_indrt_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_tmux_indrt_config_t *tmux_indrt_cfg)
 
void sdrv_xtrg_smon_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_smon_config_t *smon_cfg, bool enable)
 
void sdrv_xtrg_swdt_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_swdt_config_t *swdt_cfg, bool enable)
 
void sdrv_xtrg_dma_config (sdrv_xtrg_t *ctrl, const sdrv_xtrg_dma_config_t *config, bool enable)
 
uint32_t sdrv_xtrg_adc_rslt (sdrv_xtrg_t *ctrl, sdrv_xtrg_tmux_sel_e tmux_id, sdrv_xtrg_adc_sel_e adc_id)
 
uint32_t sdrv_xtrg_acmp_rslt (sdrv_xtrg_t *ctrl, sdrv_xtrg_tmux_sel_e tmux_id, sdrv_xtrg_acmp_sel_e acmp_id)
 
void sdrv_xtrg_fault_source_config (sdrv_xtrg_t *ctrl, uint32_t fault_id, bool enable)
 
void sdrv_xtrg_smon_cmp_err_config (sdrv_xtrg_t *ctrl, sdrv_xtrg_smon_cmp_err_config_t *xtrg_smon_cmp_err_config, bool enable)
 
uint32_t sdrv_xtrg_read_smon_cmp_err_status (sdrv_xtrg_t *ctrl)
 
void sdrv_xtrg_tmux_done_monitor_cnt_config (sdrv_xtrg_t *ctrl, uint8_t timeOutValue)
 

Detailed Description

Copyright
Copyright (c) 2021 Semidrive Semiconductor. All rights reserved.

Macro Definition Documentation

◆ ACMP_SAMPLE

#define ACMP_SAMPLE (   ACMP)    (SIG_o_START + 72 + (ACMP))

◆ ACMPO

#define ACMPO (   ACMP_ID)    (SIG_i_START + 63 + (ACMP_ID))

◆ ADC_DONE

#define ADC_DONE (   ADC_ID)    (SIG_i_START + 60 + (ADC_ID))

◆ DMA_CODE_INJ

#define DMA_CODE_INJ   (0xFE4)

◆ DMAC0_CTRL

#define DMAC0_CTRL   (0xB00)

◆ DMAC1_CTRL

#define DMAC1_CTRL   (0xB04)

◆ EPWM_CLK

#define EPWM_CLK (   EPWM)    (SIG_o_START + 68 + (EPWM))

◆ EPWM_CLR_I

#define EPWM_CLR_I (   EPWM_ID)    (SYNC_i_START + 16 + (EPWM_ID))

◆ EPWM_CLR_O

#define EPWM_CLR_O (   EPWM)    (SYNC_o_START + 16 + (EPWM))

◆ EPWM_CMP0

#define EPWM_CMP0 (   EPWM_ID)    (TRG_i_START + 4 + (EPWM_ID))

◆ EPWM_CMP_A1

#define EPWM_CMP_A1 (   EPWM_ID)    (SIG_i_START + 32 + 7 * (EPWM_ID) + 0)

◆ EPWM_CMP_B0

#define EPWM_CMP_B0 (   EPWM_ID)    (SIG_i_START + 32 + 7 * (EPWM_ID) + 1)

◆ EPWM_CMP_B1

#define EPWM_CMP_B1 (   EPWM_ID)    (SIG_i_START + 32 + 7 * (EPWM_ID) + 2)

◆ EPWM_CMP_C0

#define EPWM_CMP_C0 (   EPWM_ID)    (SIG_i_START + 32 + 7 * (EPWM_ID) + 3)

◆ EPWM_CMP_C1

#define EPWM_CMP_C1 (   EPWM_ID)    (SIG_i_START + 32 + 7 * (EPWM_ID) + 4)

◆ EPWM_CMP_D0

#define EPWM_CMP_D0 (   EPWM_ID)    (SIG_i_START + 32 + 7 * (EPWM_ID) + 5)

◆ EPWM_CMP_D1

#define EPWM_CMP_D1 (   EPWM_ID)    (SIG_i_START + 32 + 7 * (EPWM_ID) + 6)

◆ EPWM_EID

#define EPWM_EID (   EPWM)    (TID_i_START + 32 + (EPWM)*8)

◆ EPWM_FAULT

#define EPWM_FAULT (   EPWM,
  CHNL 
)    (SIG_o_START + 52 + (EPWM)*4 + (CHNL))

◆ EPWM_SET_I

#define EPWM_SET_I (   EPWM_ID)    (SYNC_i_START + 12 + (EPWM_ID))

◆ EPWM_SET_O

#define EPWM_SET_O (   EPWM)    (SYNC_o_START + 12 + (EPWM))

◆ ETIMER_CLK

#define ETIMER_CLK (   ETMR)    (SIG_o_START + 48 + (ETMR))

◆ ETIMER_CLR_I

#define ETIMER_CLR_I (   ETMR_ID)    (SYNC_i_START + 8 + (ETMR_ID))

◆ ETIMER_CLR_O

#define ETIMER_CLR_O (   ETMR)    (SYNC_o_START + 8 + (ETMR))

◆ ETIMER_CMP0

#define ETIMER_CMP0 (   ETMR_ID)    (TRG_i_START + (ETMR_ID))

◆ ETIMER_CMP_A1

#define ETIMER_CMP_A1 (   ETMR_ID)    (SIG_i_START + 7 * (ETMR_ID) + 0)

◆ ETIMER_CMP_B0

#define ETIMER_CMP_B0 (   ETMR_ID)    (SIG_i_START + 7 * (ETMR_ID) + 1)

◆ ETIMER_CMP_B1

#define ETIMER_CMP_B1 (   ETMR_ID)    (SIG_i_START + 7 * (ETMR_ID) + 2)

◆ ETIMER_CMP_C0

#define ETIMER_CMP_C0 (   ETMR_ID)    (SIG_i_START + 7 * (ETMR_ID) + 3)

◆ ETIMER_CMP_C1

#define ETIMER_CMP_C1 (   ETMR_ID)    (SIG_i_START + 7 * (ETMR_ID) + 4)

◆ ETIMER_CMP_D0

#define ETIMER_CMP_D0 (   ETMR_ID)    (SIG_i_START + 7 * (ETMR_ID) + 5)

◆ ETIMER_CMP_D1

#define ETIMER_CMP_D1 (   ETMR_ID)    (SIG_i_START + 7 * (ETMR_ID) + 6)

◆ ETIMER_CPT0

#define ETIMER_CPT0 (   ETMR,
  CHNL 
)    (SIG_o_START + ETMR * 8 + (CHNL))

◆ ETIMER_DIR

#define ETIMER_DIR (   ETMR_ID)    (SIG_i_START + 28 + (ETMR_ID))

◆ ETIMER_EID

#define ETIMER_EID (   ETMR)    (TID_i_START + (ETMR)*8)

◆ ETIMER_FAULT

#define ETIMER_FAULT (   ETMR,
  CHNL 
)    (SIG_o_START + 32 + (ETMR)*4 + (CHNL))

◆ ETIMER_SET_I

#define ETIMER_SET_I (   ETMR_ID)    (SYNC_i_START + 4 + (ETMR_ID))

◆ ETIMER_SET_O

#define ETIMER_SET_O (   ETMR)    (SYNC_o_START + 4 + (ETMR))

◆ ETIMER_SNAP_SHOT_I

#define ETIMER_SNAP_SHOT_I (   ETMR_ID)    (SYNC_i_START + (ETMR_ID))

◆ ETIMER_SNAP_SHOT_O

#define ETIMER_SNAP_SHOT_O (   ETMR)    (SYNC_o_START + (ETMR))

◆ FAULT_EVENT_CLR

#define FAULT_EVENT_CLR   (0xD14)

◆ FAULT_EVENT_RED_ERR_INJ

#define FAULT_EVENT_RED_ERR_INJ   (0xFA4)

◆ FAULT_SOURCE_EN

#define FAULT_SOURCE_EN (   fault_id)    (0xD00 + (fault_id) / 32 * 4)

◆ FAULT_SOURCE_EN0

#define FAULT_SOURCE_EN0   (0xD00)

◆ FAULT_SOURCE_EN1

#define FAULT_SOURCE_EN1   (0xD04)

◆ FAULT_SOURCE_EN2

#define FAULT_SOURCE_EN2   (0xD08)

◆ FAULT_SOURCE_EN3

#define FAULT_SOURCE_EN3   (0xD0C)

◆ FAULT_SOURCE_EN4

#define FAULT_SOURCE_EN4   (0xD10)

◆ FUNC_COR_ERR_INT_SIG_EN

#define FUNC_COR_ERR_INT_SIG_EN   (0x18)

◆ FUNC_ERR_INT_STA

#define FUNC_ERR_INT_STA   (0x10)

◆ FUNC_ERR_INT_STA_EN

#define FUNC_ERR_INT_STA_EN   (0x14)

◆ FUNC_INT_SIG_EN

#define FUNC_INT_SIG_EN   (0x8)

◆ FUNC_INT_STA

#define FUNC_INT_STA   (0x0)

◆ FUNC_INT_STA_EN

#define FUNC_INT_STA_EN   (0x4)

◆ FUNC_INT_STA_MASK

#define FUNC_INT_STA_MASK (   int_id)    (0x1 << FUNC_INT_STA_SHIFT(int_id))

◆ FUNC_INT_STA_SHIFT

#define FUNC_INT_STA_SHIFT (   int_id)    (int_id)

◆ FUNC_IO_COR_ERR0_INT_SIG_EN

#define FUNC_IO_COR_ERR0_INT_SIG_EN   (0x28)

◆ FUNC_IO_COR_ERR1_INT_SIG_EN

#define FUNC_IO_COR_ERR1_INT_SIG_EN   (0x38)

◆ FUNC_IO_ERR0_INT_STA

#define FUNC_IO_ERR0_INT_STA   (0x20)

◆ FUNC_IO_ERR0_INT_STA_EN

#define FUNC_IO_ERR0_INT_STA_EN   (0x24)

◆ FUNC_IO_ERR1_INT_STA

#define FUNC_IO_ERR1_INT_STA   (0x30)

◆ FUNC_IO_ERR1_INT_STA_EN

#define FUNC_IO_ERR1_INT_STA_EN   (0x34)

◆ FUNC_IO_UNC_ERR0_INT_SIG_EN

#define FUNC_IO_UNC_ERR0_INT_SIG_EN   (0x2C)

◆ FUNC_IO_UNC_ERR1_INT_SIG_EN

#define FUNC_IO_UNC_ERR1_INT_SIG_EN   (0x3C)

◆ FUNC_SEQ_COR_ERR_INT_SIG_EN

#define FUNC_SEQ_COR_ERR_INT_SIG_EN   (0x68)

◆ FUNC_SEQ_ERR_INT_STA

#define FUNC_SEQ_ERR_INT_STA   (0x60)

◆ FUNC_SEQ_ERR_INT_STA_EN

#define FUNC_SEQ_ERR_INT_STA_EN   (0x64)

◆ FUNC_SEQ_UNC_ERR_INT_SIG_EN

#define FUNC_SEQ_UNC_ERR_INT_SIG_EN   (0x6C)

◆ FUNC_SMON_CMP_COR_ERR_INT_SIG_EN

#define FUNC_SMON_CMP_COR_ERR_INT_SIG_EN   (0x48)

◆ FUNC_SMON_CMP_ERR_INT_STA

#define FUNC_SMON_CMP_ERR_INT_STA   (0x40)

◆ FUNC_SMON_CMP_ERR_INT_STA_EN

#define FUNC_SMON_CMP_ERR_INT_STA_EN   (0x44)

◆ FUNC_SMON_CMP_UNC_ERR_INT_SIG_EN

#define FUNC_SMON_CMP_UNC_ERR_INT_SIG_EN   (0x4C)

◆ FUNC_UNC_ERR_INT_SIG_EN

#define FUNC_UNC_ERR_INT_SIG_EN   (0x1C)

◆ FUSA_COR_ERR_INT_SIG_EN

#define FUSA_COR_ERR_INT_SIG_EN   (0x78)

◆ FUSA_COR_ERR_INT_STA

#define FUSA_COR_ERR_INT_STA   (0x70)

◆ FUSA_COR_ERR_INT_STA_EN

#define FUSA_COR_ERR_INT_STA_EN   (0x74)

◆ FUSA_UNC_ERR_INT_SIG_EN

#define FUSA_UNC_ERR_INT_SIG_EN   (0x84)

◆ FUSA_UNC_ERR_INT_STA

#define FUSA_UNC_ERR_INT_STA   (0x7C)

◆ FUSA_UNC_ERR_INT_STA_EN

#define FUSA_UNC_ERR_INT_STA_EN   (0x80)

◆ INT_ERR_INJ

#define INT_ERR_INJ   (0xFF0)

◆ IO_ERR_INJ

#define IO_ERR_INJ   (0xF30)

◆ IO_FLAT

#define IO_FLAT (   io)    (0x210 + (io)*4)

◆ IO_FLT_ERR_INJ

#define IO_FLT_ERR_INJ   (0xF2C)

◆ IO_i

#define IO_i (   IO)    (IO_i_START + (IO))

◆ IO_i_NR

#define IO_i_NR   64

◆ IO_i_START

#define IO_i_START   (SDRV_XTRG_IO_i_GROUP << XTRG_i_GROUP_SHIFT)

◆ IO_o

#define IO_o (   IO)    (IO_o_START + (IO))

◆ IO_o_NR

#define IO_o_NR   64

◆ IO_O_SEL

#define IO_O_SEL (   io_o)    (0x540 + (io_o)*4)

◆ IO_o_START

#define IO_o_START   (SDRV_XTRG_IO_o_GROUP << XTRG_i_GROUP_SHIFT)

◆ IO_OUT_EN

#define IO_OUT_EN (   io_o)    (0x670 + (io_o) / 32 * 4)

◆ IO_SYNC_DIS

#define IO_SYNC_DIS   (0x200)

◆ IO_SYNC_ERR_INJ0

#define IO_SYNC_ERR_INJ0   (0xF24)

◆ REG_PARITY_ERR_INT_SIG_EN

#define REG_PARITY_ERR_INT_SIG_EN   (0x90)

◆ REG_PARITY_ERR_INT_STAT

#define REG_PARITY_ERR_INT_STAT   (0x88)

◆ REG_PARITY_ERR_INT_STAT_EN

#define REG_PARITY_ERR_INT_STAT_EN   (0x8C)

◆ SELFTEST_MODE

#define SELFTEST_MODE   (0xFFC)

◆ SEM_FAULT

#define SEM_FAULT   (SIG_i_START + 67)

◆ SIG_i_NR

#define SIG_i_NR   68

◆ SIG_i_START

#define SIG_i_START   (SDRV_XTRG_SIG_i_GROUP << XTRG_i_GROUP_SHIFT)

◆ SIG_o_NR

#define SIG_o_NR   76

◆ SIG_O_SEL

#define SIG_O_SEL (   sig_o)    (0x410 + (sig_o)*4)

◆ SIG_o_START

#define SIG_o_START   (SDRV_XTRG_SIG_o_GROUP << XTRG_i_GROUP_SHIFT)

◆ SIG_SYNC_DIS

#define SIG_SYNC_DIS   (0x104)

◆ SIG_SYNC_ERR_INJ

#define SIG_SYNC_ERR_INJ (   num)    (0xF10 + num * 4)

◆ SMON_EN

#define SMON_EN   (0x8FC)

◆ SMON_ERR_INJ

#define SMON_ERR_INJ   (0xF34)

◆ SMON_FIRST_MUX_SELECT

#define SMON_FIRST_MUX_SELECT (   smon_id)    (0x900 + smon_id * 8)

◆ SMON_SECOND_MUX_SELECT

#define SMON_SECOND_MUX_SELECT (   smon_id)    (0x904 + smon_id * 8)

◆ SSE_CTRL

#define SSE_CTRL (   sse)    (SSE_IN_0_3_SEL(sse) + 0xc)

◆ SSE_IN_0_3_SEL

#define SSE_IN_0_3_SEL (   sse)    (0x310 + 0x10 * (sse))

◆ SSE_IN_4_SEL

#define SSE_IN_4_SEL (   sse)    (SSE_IN_0_3_SEL(sse) + 0x4)

◆ SSE_REG

#define SSE_REG (   sse)    (SSE_IN_0_3_SEL(sse) + 0x8)

◆ SSIG

#define SSIG (   SSIG)    (SSIG_START + (SSIG))

◆ SSIG_NR

#define SSIG_NR   16

◆ SSIG_START

#define SSIG_START   (SDRV_XTRG_SSIG_GROUP << XTRG_i_GROUP_SHIFT)

◆ SW_TRG_CTRL

#define SW_TRG_CTRL   (0xc00)

◆ SW_TRG_PULSE_WIDTH

#define SW_TRG_PULSE_WIDTH (   swt)    (0xc10 + (swt) / 2 * 4)

◆ SW_TRG_STATUS

#define SW_TRG_STATUS   (0xc04)

◆ SWDT_COR_ERR_INT_SIG_EN

#define SWDT_COR_ERR_INT_SIG_EN   (0x58)

◆ SWDT_ERR_INT_STA

#define SWDT_ERR_INT_STA   (0x50)

◆ SWDT_ERR_INT_STA_EN

#define SWDT_ERR_INT_STA_EN   (0x54)

◆ SWDT_EVENT_CHECK

#define SWDT_EVENT_CHECK (   swdt_id)    (SWDT_IN_SEL(swdt_id) + 4)

◆ SWDT_IN_SEL

#define SWDT_IN_SEL (   swdt_id)    (0xA00 + swdt_id * 0x10)

◆ SWDT_PULSE_CHECK

#define SWDT_PULSE_CHECK (   swdt_id)    (SWDT_IN_SEL(swdt_id) + 8)

◆ SWDT_PULSE_CHECK_WINDOW

#define SWDT_PULSE_CHECK_WINDOW (   swdt_id)    (SWDT_IN_SEL(swdt_id) + 0xC)

◆ SWDT_UNC_ERR_INT_SIG_EN

#define SWDT_UNC_ERR_INT_SIG_EN   (0x5C)

◆ SWT_i_NR

#define SWT_i_NR   8

◆ SWT_i_START

#define SWT_i_START   (SDRV_XTRG_SWT_i_GROUP << XTRG_i_GROUP_SHIFT)

◆ SYNC_i_NR

#define SYNC_i_NR   20

◆ SYNC_i_START

#define SYNC_i_START   (SDRV_XTRG_SYNC_i_GROUP << XTRG_i_GROUP_SHIFT)

◆ SYNC_o_NR

#define SYNC_o_NR   20

◆ SYNC_O_SEL

#define SYNC_O_SEL (   sync_o)    (0x680 + (sync_o)*4)

◆ SYNC_o_START

#define SYNC_o_START   (SDRV_XTRG_SYNC_o_GROUP << XTRG_i_GROUP_SHIFT)

◆ SYNC_SYNC_DIS

#define SYNC_SYNC_DIS   (0x110)

◆ SYNC_SYNC_ERR_INJ

#define SYNC_SYNC_ERR_INJ   (0xF20)

◆ TID_i_NR

#define TID_i_NR   64

◆ TID_i_START

#define TID_i_START   (SDRV_XTRG_TID_i_GROUP << XTRG_i_GROUP_SHIFT)

◆ TMUX0_DRT_CTRL

#define TMUX0_DRT_CTRL (   drt_id)    (0x6d0 + (drt_id)*0x18)

◆ TMUX0_DRT_DECODE_SEL

#define TMUX0_DRT_DECODE_SEL (   drt_id,
  sel 
)    (TMUX0_DRT_CTRL(drt_id) + (sel)*4)

◆ TMUX0_INDRT_CTRL

#define TMUX0_INDRT_CTRL (   drt_id)    (0x790 + (drt_id)*0x28)

◆ TMUX0_INDRT_DECODE_SEL

#define TMUX0_INDRT_DECODE_SEL (   drt_id,
  sel 
)    (TMUX0_INDRT_CTRL(drt_id) + (sel)*4)

◆ TMUX0_INDRT_TID_POOL

#define TMUX0_INDRT_TID_POOL (   drt_id,
  sel 
)     (TMUX0_INDRT_CTRL(drt_id) + (sel)*4 + 0x8)

◆ TMUX_ACMP_RSLT

#define TMUX_ACMP_RSLT (   acmp_id,
  tmux_id 
)    (0xE80 + (acmp_id)*4 + (tmux_id)*0x10)

◆ TMUX_ADC_RSLT

#define TMUX_ADC_RSLT (   adc_id,
  tmux_id 
)    (0xE00 + (adc_id)*4 + (tmux_id)*0xC)

◆ TMUX_ARB_LSP_ERR_INJ

#define TMUX_ARB_LSP_ERR_INJ   (0xF90)

◆ TMUX_DEC_CMP_ERR_INJ

#define TMUX_DEC_CMP_ERR_INJ (   n)    (0xF50 + 4 * (n))

◆ TMUX_DEC_EN

#define TMUX_DEC_EN   (0x8D0)

◆ TMUX_TRG_SYNC_ERR_INJ

#define TMUX_TRG_SYNC_ERR_INJ   (0xF38)

◆ TRG_i_NR

#define TRG_i_NR   8

◆ TRG_i_START

#define TRG_i_START   (SDRV_XTRG_TRG_i_GROUP << XTRG_i_GROUP_SHIFT)

◆ TRG_SYNC_DIS

#define TRG_SYNC_DIS   (0x100)

◆ TRG_SYNC_ERR_INJ

#define TRG_SYNC_ERR_INJ   (0xF00)

◆ TUMX_DONE_MONITOR_CNT

#define TUMX_DONE_MONITOR_CNT   (0x8E0)

◆ XTRG_i_GROUP

#define XTRG_i_GROUP (   SIG)    (sdrv_xtrg_i_group_e)((SIG) >> XTRG_i_GROUP_SHIFT)

◆ XTRG_i_GROUP_SHIFT

#define XTRG_i_GROUP_SHIFT   28

xTRG signals.

◆ XTRG_i_SIG

#define XTRG_i_SIG (   SIG)    ((SIG)&0x0FFFFFFFul)

◆ XTRG_SWT

#define XTRG_SWT (   swt)    (SWT_i_START + (swt))

Typedef Documentation

◆ sdrv_xtrg_acmp_sel_e

typedef enum sdrv_xtrg_acmp_sel sdrv_xtrg_acmp_sel_e

tmux acmp sel.

◆ sdrv_xtrg_adc_sel_e

typedef enum sdrv_xtrg_adc_sel sdrv_xtrg_adc_sel_e

tmux adc sel.

◆ sdrv_xtrg_config_t

typedef struct sdrv_xtrg_config sdrv_xtrg_config_t

XTRG configurations.

◆ sdrv_xtrg_dma_config_t

typedef struct sdrv_xtrg_dma_config sdrv_xtrg_dma_config_t

DMA configuration.

◆ sdrv_xtrg_dma_sel_e

typedef enum sdrv_xtrg_dma_sel sdrv_xtrg_dma_sel_e

DMA sel.

◆ sdrv_xtrg_dma_ssig_mode_e

typedef enum sdrv_xtrg_dma_ssig_mode sdrv_xtrg_dma_ssig_mode_e

Edge detect mode for dma.

◆ sdrv_xtrg_edge_e

typedef enum sdrv_xtrg_edge sdrv_xtrg_edge_e

Edge detect mode for I/O filter and SSE5.

◆ sdrv_xtrg_err_sel_e

typedef enum sdrv_xtrg_err_sel sdrv_xtrg_err_sel_e

SMON cmp err sem signal mode select.

◆ sdrv_xtrg_event_trigger_mode_e

typedef enum sdrv_xtrg_event_trigger_mode sdrv_xtrg_event_trigger_mode_e

event trigger mode.

◆ sdrv_xtrg_i_group_e

typedef enum sdrv_xtrg_i_group sdrv_xtrg_i_group_e

xTRG signal groups, including input (i) and output (o) signals.

◆ sdrv_xtrg_io_filter_config_t

typedef struct sdrv_xtrg_io_filter_config sdrv_xtrg_io_filter_config_t

I/O Filter configuration.

◆ sdrv_xtrg_irq_status_e

typedef enum sdrv_xtrg_irq_status sdrv_xtrg_irq_status_e

xTRG interrupt event.

◆ sdrv_xtrg_pulse_check_edge_e

typedef enum sdrv_xtrg_pulse_check_edge sdrv_xtrg_pulse_check_edge_e

Pulse signal width edge.

◆ sdrv_xtrg_pulse_check_mode_e

typedef enum sdrv_xtrg_pulse_check_mode sdrv_xtrg_pulse_check_mode_e

Pulse signal width check.

◆ sdrv_xtrg_sig_group_t

typedef struct sdrv_xtrg_sig_group sdrv_xtrg_sig_group_t

◆ sdrv_xtrg_smon_cmp_err_config_t

typedef struct sdrv_xtrg_smon_cmp_err_config sdrv_xtrg_smon_cmp_err_config_t

SMON cmp err config struct.

◆ sdrv_xtrg_smon_cmp_err_e

typedef enum sdrv_xtrg_smon_cmp_err sdrv_xtrg_smon_cmp_err_e

smon cmp err signal select.

◆ sdrv_xtrg_smon_config_t

typedef struct sdrv_xtrg_smon_config sdrv_xtrg_smon_config_t

SMON configuration structure.

◆ sdrv_xtrg_smon_sel_e

typedef enum sdrv_xtrg_smon_sel sdrv_xtrg_smon_sel_e

SMON sel.

◆ sdrv_xtrg_sse5_config_t

typedef struct sdrv_xtrg_sse5_config sdrv_xtrg_sse5_config_t

SSE5 configuration structure.

◆ sdrv_xtrg_ssm_sel_e

typedef enum sdrv_xtrg_ssm_sel sdrv_xtrg_ssm_sel_e

ssm sel.

◆ sdrv_xtrg_swdt_check_mode_e

typedef enum sdrv_xtrg_swdt_check_mode sdrv_xtrg_swdt_check_mode_e

swdt check mode.

◆ sdrv_xtrg_swdt_config_t

typedef struct sdrv_xtrg_swdt_config sdrv_xtrg_swdt_config_t

swdt conifg.

◆ sdrv_xtrg_swdt_event_check_config_t

typedef struct sdrv_xtrg_swdt_event_check_config sdrv_xtrg_swdt_event_check_config_t

SWDT event check configuration structure.

◆ sdrv_xtrg_swdt_pulse_check_config_t

typedef struct sdrv_xtrg_swdt_pulse_check_config sdrv_xtrg_swdt_pulse_check_config_t

SWDT pulse check configuration structure.

◆ sdrv_xtrg_swdt_sel_e

typedef enum sdrv_xtrg_swdt_sel sdrv_xtrg_swdt_sel_e

swdt sel.

◆ sdrv_xtrg_swt_config_t

typedef struct sdrv_xtrg_swt_config sdrv_xtrg_swt_config_t

Software Triggers config.

◆ sdrv_xtrg_swt_event_e

typedef enum sdrv_xtrg_swt_event sdrv_xtrg_swt_event_e

Software Triggers events.

◆ sdrv_xtrg_swt_sel_e

typedef enum sdrv_xtrg_swt_sel sdrv_xtrg_swt_sel_e

Software Triggers sel.

◆ sdrv_xtrg_t

typedef struct sdrv_xtrg sdrv_xtrg_t

◆ sdrv_xtrg_tmux0_drt_sel_e

typedef enum sdrv_xtrg_tmux0_drt_sel sdrv_xtrg_tmux0_drt_sel_e

tmux0 drt sel.

◆ sdrv_xtrg_tmux0_indrt_sel_e

typedef enum sdrv_xtrg_tmux0_indrt_sel sdrv_xtrg_tmux0_indrt_sel_e

tmux0 indrt sel.

◆ sdrv_xtrg_tmux_drt_config_t

typedef struct sdrv_xtrg_tmux_drt_config sdrv_xtrg_tmux_drt_config_t

Trigger Mux (tmux) configuration.

◆ sdrv_xtrg_tmux_indrt_config_t

typedef struct sdrv_xtrg_tmux_indrt_config sdrv_xtrg_tmux_indrt_config_t

Trigger Mux (tmux) configuration.

◆ sdrv_xtrg_tmux_sel_e

typedef enum sdrv_xtrg_tmux_sel sdrv_xtrg_tmux_sel_e

tmux index sel.

◆ xtrg_callback_t

typedef void(* xtrg_callback_t) (sdrv_xtrg_t *ctrl, sdrv_xtrg_irq_status_e status, void *para)

XTRG callback function.

Enumeration Type Documentation

◆ sdrv_xtrg_acmp_sel

enum sdrv_xtrg_acmp_sel

tmux acmp sel.

Enumerator
SDRV_XTRG_ACMP0 
SDRV_XTRG_ACMP1 
SDRV_XTRG_ACMP2 
SDRV_XTRG_ACMP3 

◆ sdrv_xtrg_adc_sel

enum sdrv_xtrg_adc_sel

tmux adc sel.

Enumerator
SDRV_XTRG_ADC0 
SDRV_XTRG_ADC1 
SDRV_XTRG_ADC2 

◆ sdrv_xtrg_dma_sel

enum sdrv_xtrg_dma_sel

DMA sel.

Enumerator
SDRV_XTRG_DMA0 
SDRV_XTRG_DMA1 

◆ sdrv_xtrg_dma_ssig_mode

enum sdrv_xtrg_dma_ssig_mode

Edge detect mode for dma.

Enumerator
SDRV_XTRG_SSIG_POSEDGE 
SDRV_XTRG_SSIG_NEGEDGE 

◆ sdrv_xtrg_edge

enum sdrv_xtrg_edge

Edge detect mode for I/O filter and SSE5.

Enumerator
SDRV_XTRG_POSEDGE 
SDRV_XTRG_NEGEDGE 
SDRV_XTRG_BOTHEDGE 

◆ sdrv_xtrg_err_sel

enum sdrv_xtrg_err_sel

SMON cmp err sem signal mode select.

Enumerator
SDRV_SMON_COR_ERROR 
SDRV_SMON_UNC_ERROR 
SDRV_SMON_NULL 

◆ sdrv_xtrg_event_trigger_mode

enum sdrv_xtrg_event_trigger_mode

event trigger mode.

Enumerator
SDRV_XTRG_EVENT_TRIGGER_MODE_POSEDGE 
SDRV_XTRG_EVENT_TRIGGER_MODE_NEGEDGE 
SDRV_XTRG_EVENT_TRIGGER_MODE_TOGGLE 
SDRV_XTRG_EVENT_TRIGGER_MODE_HIGH 
SDRV_XTRG_EVENT_TRIGGER_MODE_LOW 

◆ sdrv_xtrg_i_group

enum sdrv_xtrg_i_group

xTRG signal groups, including input (i) and output (o) signals.

Enumerator
SDRV_XTRG_SWT_i_GROUP 
SDRV_XTRG_TRG_i_GROUP 
SDRV_XTRG_SIG_i_GROUP 
SDRV_XTRG_SYNC_i_GROUP 
SDRV_XTRG_IO_i_GROUP 
SDRV_XTRG_TID_i_GROUP 
SDRV_XTRG_SIG_o_GROUP 
SDRV_XTRG_IO_o_GROUP 
SDRV_XTRG_SYNC_o_GROUP 
SDRV_XTRG_SSIG_GROUP 

◆ sdrv_xtrg_irq_status

enum sdrv_xtrg_irq_status

xTRG interrupt event.

Enumerator
SDRV_FAULT_EVENT 
SDRV_TMUX0_DONE_EVENT 
SDRV_TMUX1_DONE_EVENT 
SDRV_TMUX2_DONE_EVENT 
SDRV_TMUX3_DONE_EVENT 
SDRV_TMUX4_DONE_EVENT 
SDRV_TMUX5_DONE_EVENT 
SDRV_TMUX6_DONE_EVENT 
SDRV_TMUX7_DONE_EVENT 

◆ sdrv_xtrg_pulse_check_edge

enum sdrv_xtrg_pulse_check_edge

Pulse signal width edge.

Enumerator
SDRV_XTRG_PULSE_CHECK_POSITIVE_PULSE 
SDRV_XTRG_PULSE_CHECK_NEGATIVE_PULSE 

◆ sdrv_xtrg_pulse_check_mode

enum sdrv_xtrg_pulse_check_mode

Pulse signal width check.

Enumerator
SDRV_XTRG_PULSE_CHECK_MODE_BETWEEN_WINDOW 
SDRV_XTRG_PULSE_CHECK_MODE_MORE_OR_LESS_WINDOW 

◆ sdrv_xtrg_smon_cmp_err

enum sdrv_xtrg_smon_cmp_err

smon cmp err signal select.

Enumerator
SDRV_XTRG_SMON_CMP_ERR0 
SDRV_XTRG_SMON_CMP_ERR1 
SDRV_XTRG_SMON_CMP_ERR2 
SDRV_XTRG_SMON_CMP_ERR3 
SDRV_XTRG_SMON_CMP_ERR4 
SDRV_XTRG_SMON_CMP_ERR5 
SDRV_XTRG_SMON_CMP_ERR6 
SDRV_XTRG_SMON_CMP_ERR7 
SDRV_XTRG_SMON_CMP_ERR8 
SDRV_XTRG_SMON_CMP_ERR9 
SDRV_XTRG_SMON_CMP_ERR10 
SDRV_XTRG_SMON_CMP_ERR11 
SDRV_XTRG_SMON_CMP_ERR12 
SDRV_XTRG_SMON_CMP_ERR13 
SDRV_XTRG_SMON_CMP_ERR14 
SDRV_XTRG_SMON_CMP_ERR15 
SDRV_XTRG_SMON_CMP_ERR16 
SDRV_XTRG_SMON_CMP_ERR17 
SDRV_XTRG_SMON_CMP_ERR18 
SDRV_XTRG_SMON_CMP_ERR19 
SDRV_XTRG_SMON_CMP_ERR20 
SDRV_XTRG_SMON_CMP_ERR21 
SDRV_XTRG_SMON_CMP_ERR22 
SDRV_XTRG_SMON_CMP_ERR23 
SDRV_XTRG_SMON_CMP_ERR24 
SDRV_XTRG_SMON_CMP_ERR25 
SDRV_XTRG_SMON_CMP_ERR26 
SDRV_XTRG_SMON_CMP_ERR27 
SDRV_XTRG_SMON_CMP_ERR28 
SDRV_XTRG_SMON_CMP_ERR29 
SDRV_XTRG_SMON_CMP_ERR30 
SDRV_XTRG_SMON_CMP_ERR31 

◆ sdrv_xtrg_smon_sel

enum sdrv_xtrg_smon_sel

SMON sel.

Enumerator
SDRV_XTRG_SMON0 
SDRV_XTRG_SMON1 
SDRV_XTRG_SMON2 
SDRV_XTRG_SMON3 
SDRV_XTRG_SMON4 
SDRV_XTRG_SMON5 
SDRV_XTRG_SMON6 
SDRV_XTRG_SMON7 
SDRV_XTRG_SMON8 
SDRV_XTRG_SMON9 
SDRV_XTRG_SMON10 
SDRV_XTRG_SMON11 
SDRV_XTRG_SMON12 
SDRV_XTRG_SMON13 
SDRV_XTRG_SMON14 
SDRV_XTRG_SMON15 
SDRV_XTRG_SMON16 
SDRV_XTRG_SMON17 
SDRV_XTRG_SMON18 
SDRV_XTRG_SMON19 
SDRV_XTRG_SMON20 
SDRV_XTRG_SMON21 
SDRV_XTRG_SMON22 
SDRV_XTRG_SMON23 
SDRV_XTRG_SMON24 
SDRV_XTRG_SMON25 
SDRV_XTRG_SMON26 
SDRV_XTRG_SMON27 
SDRV_XTRG_SMON28 
SDRV_XTRG_SMON29 
SDRV_XTRG_SMON30 
SDRV_XTRG_SMON31 

◆ sdrv_xtrg_ssm_sel

enum sdrv_xtrg_ssm_sel

ssm sel.

Enumerator
SDRV_XTRG_SSM0 
SDRV_XTRG_SSM1 
SDRV_XTRG_SSM2 
SDRV_XTRG_SSM3 
SDRV_XTRG_SSM4 
SDRV_XTRG_SSM5 
SDRV_XTRG_SSM6 
SDRV_XTRG_SSM7 
SDRV_XTRG_SSM8 
SDRV_XTRG_SSM9 
SDRV_XTRG_SSM10 
SDRV_XTRG_SSM11 
SDRV_XTRG_SSM12 
SDRV_XTRG_SSM13 
SDRV_XTRG_SSM14 
SDRV_XTRG_SSM15 

◆ sdrv_xtrg_swdt_check_mode

enum sdrv_xtrg_swdt_check_mode

swdt check mode.

Enumerator
SDRV_XTRG_SWDT_PULSE_CHECK 
SDRV_XTRG_SWDT_EVENT_CHECK 

◆ sdrv_xtrg_swdt_sel

enum sdrv_xtrg_swdt_sel

swdt sel.

Enumerator
SDRV_XTRG_SWDT0 
SDRV_XTRG_SWDT1 
SDRV_XTRG_SWDT2 
SDRV_XTRG_SWDT3 

◆ sdrv_xtrg_swt_event

enum sdrv_xtrg_swt_event

Software Triggers events.

Enumerator
SDRV_XTRG_SWT_EVENT_SET 
SDRV_XTRG_SWT_EVENT_CLEAR 
SDRV_XTRG_SWT_EVENT_TRIGGER 
SDRV_XTRG_SWT_EVENT_PULSE 

◆ sdrv_xtrg_swt_sel

enum sdrv_xtrg_swt_sel

Software Triggers sel.

Enumerator
SDRV_XTRG_SWT0 
SDRV_XTRG_SWT1 
SDRV_XTRG_SWT2 
SDRV_XTRG_SWT3 
SDRV_XTRG_SWT4 
SDRV_XTRG_SWT5 
SDRV_XTRG_SWT6 
SDRV_XTRG_SWT7 

◆ sdrv_xtrg_tmux0_drt_sel

enum sdrv_xtrg_tmux0_drt_sel

tmux0 drt sel.

Enumerator
SDRV_XTRG_TMUX0_DRT0 
SDRV_XTRG_TMUX0_DRT1 
SDRV_XTRG_TMUX0_DRT2 
SDRV_XTRG_TMUX0_DRT3 
SDRV_XTRG_TMUX0_DRT4 
SDRV_XTRG_TMUX0_DRT5 
SDRV_XTRG_TMUX0_DRT6 
SDRV_XTRG_TMUX0_DRT7 

◆ sdrv_xtrg_tmux0_indrt_sel

enum sdrv_xtrg_tmux0_indrt_sel

tmux0 indrt sel.

Enumerator
SDRV_XTRG_TMUX0_INDRT0 
SDRV_XTRG_TMUX0_INDRT1 
SDRV_XTRG_TMUX0_INDRT2 
SDRV_XTRG_TMUX0_INDRT3 
SDRV_XTRG_TMUX0_INDRT4 
SDRV_XTRG_TMUX0_INDRT5 
SDRV_XTRG_TMUX0_INDRT6 
SDRV_XTRG_TMUX0_INDRT7 

◆ sdrv_xtrg_tmux_sel

enum sdrv_xtrg_tmux_sel

tmux index sel.

Enumerator
SDRV_XTRG_TMUX0 
SDRV_XTRG_TMUX1 
SDRV_XTRG_TMUX2 
SDRV_XTRG_TMUX3 
SDRV_XTRG_TMUX4 
SDRV_XTRG_TMUX5 
SDRV_XTRG_TMUX6 
SDRV_XTRG_TMUX7 

Function Documentation

◆ sdrv_xtrg_acmp_rslt()

uint32_t sdrv_xtrg_acmp_rslt ( sdrv_xtrg_t *  ctrl,
sdrv_xtrg_tmux_sel_e  tmux_id,
sdrv_xtrg_acmp_sel_e  acmp_id 
)

Read tmux acmp result.

Parameters
[in]ctrlxTRG controller.
[in]tmux_idxTRG tmux index.
[in]acmp_idxTRG acmp index.
Returns
acmp result

◆ sdrv_xtrg_adc_rslt()

uint32_t sdrv_xtrg_adc_rslt ( sdrv_xtrg_t *  ctrl,
sdrv_xtrg_tmux_sel_e  tmux_id,
sdrv_xtrg_adc_sel_e  adc_id 
)

Read tmux adc result.

Parameters
[in]ctrlxTRG controller.
[in]tmux_idxTRG tmux index.
[in]adc_idxTRG adc index.
Returns
adc result

◆ sdrv_xtrg_deinit()

void sdrv_xtrg_deinit ( sdrv_xtrg_t *  ctrl)

Deinit XTRG.

Parameters
[in]ctrlxTRG controller.

◆ sdrv_xtrg_dma_config()

void sdrv_xtrg_dma_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_dma_config_t *  config,
bool  enable 
)

Enable or disable DMA0/1.

Parameters
[in]ctrlxTRG controller.
[in]configxTRG dma configuration.
[in]enableEnable or disable dma.

◆ sdrv_xtrg_fault_source_config()

void sdrv_xtrg_fault_source_config ( sdrv_xtrg_t *  ctrl,
uint32_t  fault_id,
bool  enable 
)

sdrv xtrg fault source enable.

Parameters
[in]ctrlxTRG controller.
[in]fault_idxTRG fault source id.

◆ sdrv_xtrg_init()

void sdrv_xtrg_init ( sdrv_xtrg_t *  ctrl,
xtrg_callback_t  callback,
void *  para 
)

Init XTRG.

Parameters
[in]ctrlxTRG controller.

◆ sdrv_xtrg_int_disable()

void sdrv_xtrg_int_disable ( sdrv_xtrg_t *  ctrl,
sdrv_xtrg_irq_status_e  int_id 
)

sdrv xtrg int disable.

Parameters
[in]ctrlxTRG controller
[in]int_idint id

◆ sdrv_xtrg_int_enable()

void sdrv_xtrg_int_enable ( sdrv_xtrg_t *  ctrl,
sdrv_xtrg_irq_status_e  int_id 
)

sdrv xtrg int enable.

Parameters
[in]ctrlxTRG controller.
[in]int_idint id

◆ sdrv_xtrg_io_filter_config()

void sdrv_xtrg_io_filter_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_io_filter_config_t *  io_filter_cfg,
bool  enable 
)

Configure I/O filters.

Parameters
[in]ctrlxTRG controller.
[in]cfgThe input signal to enable or disable debouncing
[in]io_filter_cfgI/O filter configuration.

◆ sdrv_xtrg_io_out_config()

void sdrv_xtrg_io_out_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_config_t *  cfg,
bool  enable 
)

Configure IO output, muxing SSIG_i,TRG_i,SIG_i,IO_i to IO_o.

Parameters
[in]ctrlxTRG controler.
[in]cfgxTRG configuration.
[in]enableEnable or disable io out.

◆ sdrv_xtrg_irq_handler()

int sdrv_xtrg_irq_handler ( uint32_t  irq,
void *  ctrl 
)

XTRG irp handler.

Parameters
[in]irqxTRG irq.
[in]ctrlxTRG controller

◆ sdrv_xtrg_read_smon_cmp_err_status()

uint32_t sdrv_xtrg_read_smon_cmp_err_status ( sdrv_xtrg_t *  ctrl)

sdrv xtrg read fault status.

Parameters
[in]ctrlxTRG controller.

◆ sdrv_xtrg_smon_cmp_err_config()

void sdrv_xtrg_smon_cmp_err_config ( sdrv_xtrg_t *  ctrl,
sdrv_xtrg_smon_cmp_err_config_t *  xtrg_smon_cmp_err_config,
bool  enable 
)

Smon cmp err config.

Parameters
[in]ctrlxTRG controller.
[in]xtrg_smon_cmp_err_configSmon cmp err config.
[in]enableEnable or disable err signal.

◆ sdrv_xtrg_smon_config()

void sdrv_xtrg_smon_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_smon_config_t *  smon_cfg,
bool  enable 
)

Configure SMON (Signal Monitor). The SMON monitors the input and output signal groups First level select 32 input signals and 32 output signals. Second level select inputs from output of 1st level.

Parameters
[in]ctrlxTRG controller.
[in]smon_cfgsmon configuration.
[in]enableEnable or disable smon.

◆ sdrv_xtrg_smux_config()

void sdrv_xtrg_smux_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_config_t *  cfg 
)

Configure signal mux, muxing input signals to SIG_o or IO_o.

The smux module muxes SSIG, TRG_i, SIG_i, and I/O inputs to SIG_o and I/O outputs.

Parameters
[in]ctrlxTRG controller.
[in]cfgxTRG configuration.

◆ sdrv_xtrg_sse5_config()

void sdrv_xtrg_sse5_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_sse5_config_t *  sse5_cfg,
bool  enable 
)

Enable or disable SSE5. ctrl.

Parameters
[in]ctrlxTRG controller.
[in]sse5_cfgxTRG sse configuration.
[in]enableEnable or disable sse5.

◆ sdrv_xtrg_swdt_config()

void sdrv_xtrg_swdt_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_swdt_config_t *  swdt_cfg,
bool  enable 
)

Configure SWDT Pulse Check.(Signal Watch Dog Timer).

Parameters
[in]ctrlxTRG controller.
[in]swdt_cfgswdt configuration.
[in]enableEnable or disable swdt.

◆ sdrv_xtrg_swt_config()

int sdrv_xtrg_swt_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_swt_config_t *  swt_cfg 
)

Config SWT (software trigger).

Parameters
[in]ctrlxTRG controller.
[in]swt_cfgswt configuration.

◆ sdrv_xtrg_sync_config()

void sdrv_xtrg_sync_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_config_t *  cfg,
bool  enable 
)

Enable or disable input signal synchronization.

SIG_i, TRG_i, SYNC_i and IO_i signals are synchronized to timer clock domain by default. This function enable or disable signal synchronizations.

Parameters
[in]ctrlxTRG controller.
[in]cfgxTRG configuration.
[in]enableEnable or disable synchronization.

◆ sdrv_xtrg_syncmux_config()

void sdrv_xtrg_syncmux_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_config_t *  cfg 
)

Configure syncmux, muxing input sync signals to SYNC_o.

The syncmux module muxes SWT_i, SSIG and SYNC_i inputs to SYNC_o outputs.

Parameters
[in]ctrlxTRG controller.
[in]cfgxTRG configuration.

◆ sdrv_xtrg_tmux0_drt_config()

void sdrv_xtrg_tmux0_drt_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_tmux_drt_config_t *  tmux_drt_cfg 
)

Configure syncmux, muxing input sync signals to SYNC_o.

The syncmux module muxes SWT_i, SSIG and SYNC_i inputs to SYNC_o outputs.

Parameters
[in]ctrlxTRG controller.
[in]tmux_drt_cfgxTRG tmux direct configuration.

◆ sdrv_xtrg_tmux0_indrt_config()

void sdrv_xtrg_tmux0_indrt_config ( sdrv_xtrg_t *  ctrl,
const sdrv_xtrg_tmux_indrt_config_t *  tmux_indrt_cfg 
)

Configure the Trigger Mux (tmux) indrt modules..

The tmux muxes TRG_i, SSIG signals to ADC and ACMP modules, with specified TID. There are 8 "drt" decoders, whose TID comes from TID_i, and 8 "indrt" decoders, whose TID comes from xTRG internel TID pool.

Parameters
[in]ctrlxTRG controller.
[in]tmux_indrtxTRG tmux indirect configuration.

◆ sdrv_xtrg_tmux_done_monitor_cnt_config()

void sdrv_xtrg_tmux_done_monitor_cnt_config ( sdrv_xtrg_t *  ctrl,
uint8_t  timeOutValue 
)

sdrv set up timeout value from ADC

Parameters
[in]xtrgdev base.
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