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551
devices/E3106/clock_default_cfg.c
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551
devices/E3106/clock_default_cfg.c
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/**
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* @file clock_default_cfg.c
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* @brief Semidrive clock default config file.
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*
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* This file supply a example clock config for use, it contain all IP,
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* you can pick up some of them in your application. Futhermore, you can modify
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* rate as you want.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#include <sdrv_ckgen.h>
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#include <clock_ip.h>
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#include <compiler.h>
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/**
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* @brief g_pre_bus_config contains soc pre config bus clock.
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* Optional, we can change BUS to XTAL24M before PLL configuration.
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*/
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__WEAK const sdrv_ckgen_bus_config_t g_pre_bus_config = {
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.config_num = 0,
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};
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/**
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* @brief g_pll_config contains PLL rate config.
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*
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*/
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__WEAK const sdrv_ckgen_rate_config_t g_pll_config = {
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.config_num = 3,
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.config_nodes[0].clk_node = CLK_NODE(g_pll1_root),
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.config_nodes[0].rate = 500000000,
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.config_nodes[1].clk_node = CLK_NODE(g_pll2_root),
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.config_nodes[1].rate = 400000000,
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.config_nodes[2].clk_node = CLK_NODE(g_pll3_root),
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.config_nodes[2].rate = 600000000,
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};
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/**
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* @brief g_bus_config contains all bus core rate config.
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*
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*/
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__WEAK const sdrv_ckgen_bus_config_t g_bus_config = {
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.config_num = 2,
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/* SF core 300M, and AXI bus 150M, APB bus 75M */
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.config_nodes[0].clk_node = CLK_NODE(g_ckgen_bus_cr5_sf),
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.config_nodes[0].rate = 300000000,
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.config_nodes[0].post_div = CKGEN_BUS_DIV_4_2_1,
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/* AP bus 150M */
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.config_nodes[1].clk_node = CLK_NODE(g_ckgen_bus_ap_bus),
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.config_nodes[1].rate = 150000000,
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.config_nodes[1].post_div = CKGEN_BUS_DIV_4_2_1,
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};
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/**
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* @brief g_ip_config contains all IP rate config.
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*
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*/
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__WEAK const sdrv_ckgen_rate_config_t g_ip_config = {
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.config_num = 28,
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.config_nodes[0].clk_node = CLK_NODE(g_ckgen_ip_i2c_sf_1_to_3),
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.config_nodes[0].rate = 133300000,
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.config_nodes[1].clk_node = CLK_NODE(g_ckgen_ip_i2c_sf_4_to_6),
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.config_nodes[1].rate = 133300000,
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.config_nodes[2].clk_node = CLK_NODE(g_ckgen_ip_spi_sf_1_to_3),
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.config_nodes[2].rate = 133300000,
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.config_nodes[3].clk_node = CLK_NODE(g_ckgen_ip_spi_sf_4_to_6),
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.config_nodes[3].rate = 133300000,
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.config_nodes[4].clk_node = CLK_NODE(g_ckgen_ip_uart_sf_1_to_6),
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.config_nodes[4].rate = 83300000,
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.config_nodes[5].clk_node = CLK_NODE(g_ckgen_ip_uart_sf_7_to_12),
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.config_nodes[5].rate = 83300000,
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.config_nodes[6].clk_node = CLK_NODE(g_ckgen_ip_enet1_tx),
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.config_nodes[6].rate = 250000000,
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.config_nodes[7].clk_node = CLK_NODE(g_ckgen_ip_enet1_rmii),
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.config_nodes[7].rate = 50000000,
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.config_nodes[8].clk_node = CLK_NODE(g_ckgen_ip_enet1_phy_ref),
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.config_nodes[8].rate = 125000000,
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.config_nodes[9].clk_node = CLK_NODE(g_ckgen_ip_enet1_timer_sec),
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.config_nodes[9].rate = 500000000,
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.config_nodes[10].clk_node = CLK_NODE(g_ckgen_ip_i2s_mclk0),
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.config_nodes[10].rate = 133300000,
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.config_nodes[11].clk_node = CLK_NODE(g_ckgen_ip_xspi1a),
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.config_nodes[11].rate = 200000000,
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.config_nodes[12].clk_node = CLK_NODE(g_ckgen_ip_xspi1b),
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.config_nodes[12].rate = 200000000,
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.config_nodes[13].clk_node = CLK_NODE(g_ckgen_ip_saci2_clk),
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.config_nodes[13].rate = 100000000,
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.config_nodes[14].clk_node = CLK_NODE(g_ckgen_ip_saci2_pdm_clk),
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.config_nodes[14].rate = 100000000,
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.config_nodes[15].clk_node = CLK_NODE(g_ckgen_ip_xtrg),
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.config_nodes[15].rate = 150000000,
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.config_nodes[16].clk_node = CLK_NODE(g_ckgen_ip_etmr1),
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.config_nodes[16].rate = 150000000,
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.config_nodes[17].clk_node = CLK_NODE(g_ckgen_ip_etmr2),
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.config_nodes[17].rate = 150000000,
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.config_nodes[18].clk_node = CLK_NODE(g_ckgen_ip_epwm1),
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.config_nodes[18].rate = 150000000,
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.config_nodes[19].clk_node = CLK_NODE(g_ckgen_ip_epwm2),
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.config_nodes[19].rate = 150000000,
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.config_nodes[20].clk_node = CLK_NODE(g_ckgen_ip_sehc1),
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.config_nodes[20].rate = 300000000,
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.config_nodes[21].clk_node = CLK_NODE(g_ckgen_ip_can),
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.config_nodes[21].rate = 80000000,
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.config_nodes[22].clk_node = CLK_NODE(g_ckgen_ip_adc1),
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.config_nodes[22].rate = 150000000,
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.config_nodes[23].clk_node = CLK_NODE(g_ckgen_ip_adc2),
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.config_nodes[23].rate = 150000000,
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.config_nodes[24].clk_node = CLK_NODE(g_ckgen_ip_adc3),
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.config_nodes[24].rate = 150000000,
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.config_nodes[25].clk_node = CLK_NODE(g_ckgen_ip_acmp),
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.config_nodes[25].rate = 150000000,
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.config_nodes[26].clk_node = CLK_NODE(g_ckgen_ip_ioc),
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.config_nodes[26].rate = 200000000,
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.config_nodes[27].clk_node = CLK_NODE(g_ckgen_ip_pt_sns_sf),
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.config_nodes[27].rate = 100000,
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};
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/**
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* @brief g_enable_config contains IP clock enable/disable config
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*
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*/
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__WEAK const sdrv_ckgen_ip_clock_config_t g_enable_config = {
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.config_num = 58,
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.config_nodes[0].ip_nodes = g_ckgen_adc1,
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.config_nodes[0].mode = CKGEN_RUN_MODE,
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.config_nodes[0].enable = false,
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.config_nodes[1].ip_nodes = g_ckgen_adc2,
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.config_nodes[1].mode = CKGEN_RUN_MODE,
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.config_nodes[1].enable = false,
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.config_nodes[2].ip_nodes = g_ckgen_adc3,
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.config_nodes[2].mode = CKGEN_RUN_MODE,
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.config_nodes[2].enable = false,
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.config_nodes[3].ip_nodes = g_ckgen_acmp1,
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.config_nodes[3].mode = CKGEN_RUN_MODE,
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.config_nodes[3].enable = false,
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.config_nodes[4].ip_nodes = g_ckgen_acmp2,
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.config_nodes[4].mode = CKGEN_RUN_MODE,
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.config_nodes[4].enable = false,
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.config_nodes[5].ip_nodes = g_ckgen_btm1,
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.config_nodes[5].mode = CKGEN_RUN_MODE,
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.config_nodes[5].enable = false,
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.config_nodes[6].ip_nodes = g_ckgen_btm2,
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.config_nodes[6].mode = CKGEN_RUN_MODE,
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.config_nodes[6].enable = false,
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.config_nodes[7].ip_nodes = g_ckgen_btm3,
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.config_nodes[7].mode = CKGEN_RUN_MODE,
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.config_nodes[7].enable = false,
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.config_nodes[8].ip_nodes = g_ckgen_btm4,
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.config_nodes[8].mode = CKGEN_RUN_MODE,
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.config_nodes[8].enable = false,
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.config_nodes[9].ip_nodes = g_ckgen_canfd16,
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.config_nodes[9].mode = CKGEN_RUN_MODE,
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.config_nodes[9].enable = false,
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.config_nodes[10].ip_nodes = g_ckgen_canfd21,
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.config_nodes[10].mode = CKGEN_RUN_MODE,
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.config_nodes[10].enable = false,
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.config_nodes[11].ip_nodes = g_ckgen_canfd23,
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.config_nodes[11].mode = CKGEN_RUN_MODE,
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.config_nodes[11].enable = false,
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.config_nodes[12].ip_nodes = g_ckgen_canfd3,
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.config_nodes[12].mode = CKGEN_RUN_MODE,
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.config_nodes[12].enable = false,
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.config_nodes[13].ip_nodes = g_ckgen_canfd4,
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.config_nodes[13].mode = CKGEN_RUN_MODE,
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.config_nodes[13].enable = false,
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.config_nodes[14].ip_nodes = g_ckgen_canfd5,
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.config_nodes[14].mode = CKGEN_RUN_MODE,
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.config_nodes[14].enable = false,
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.config_nodes[15].ip_nodes = g_ckgen_canfd6,
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.config_nodes[15].mode = CKGEN_RUN_MODE,
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.config_nodes[15].enable = false,
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.config_nodes[16].ip_nodes = g_ckgen_canfd7,
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.config_nodes[16].mode = CKGEN_RUN_MODE,
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.config_nodes[16].enable = false,
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.config_nodes[17].ip_nodes = g_ckgen_dma_sf,
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.config_nodes[17].mode = CKGEN_RUN_MODE,
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.config_nodes[17].enable = false,
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.config_nodes[18].ip_nodes = g_ckgen_enet1,
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.config_nodes[18].mode = CKGEN_RUN_MODE,
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.config_nodes[18].enable = false,
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.config_nodes[19].ip_nodes = g_ckgen_epwm1,
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.config_nodes[19].mode = CKGEN_RUN_MODE,
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.config_nodes[19].enable = false,
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.config_nodes[20].ip_nodes = g_ckgen_epwm2,
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.config_nodes[20].mode = CKGEN_RUN_MODE,
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.config_nodes[20].enable = false,
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.config_nodes[21].ip_nodes = g_ckgen_etmr1,
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.config_nodes[21].mode = CKGEN_RUN_MODE,
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.config_nodes[21].enable = false,
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.config_nodes[22].ip_nodes = g_ckgen_etmr2,
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.config_nodes[22].mode = CKGEN_RUN_MODE,
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.config_nodes[22].enable = false,
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.config_nodes[23].ip_nodes = g_ckgen_i2c3,
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.config_nodes[23].mode = CKGEN_RUN_MODE,
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.config_nodes[23].enable = false,
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.config_nodes[24].ip_nodes = g_ckgen_i2c4,
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.config_nodes[24].mode = CKGEN_RUN_MODE,
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.config_nodes[24].enable = false,
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.config_nodes[25].ip_nodes = g_ckgen_i2c5,
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.config_nodes[25].mode = CKGEN_RUN_MODE,
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.config_nodes[25].enable = false,
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.config_nodes[26].ip_nodes = g_ckgen_i2c6,
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.config_nodes[26].mode = CKGEN_RUN_MODE,
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.config_nodes[26].enable = false,
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.config_nodes[27].ip_nodes = g_ckgen_ioc,
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.config_nodes[27].mode = CKGEN_RUN_MODE,
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.config_nodes[27].enable = false,
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.config_nodes[28].ip_nodes = g_ckgen_pt_sns_sf_ana,
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.config_nodes[28].mode = CKGEN_RUN_MODE,
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.config_nodes[28].enable = false,
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.config_nodes[29].ip_nodes = g_ckgen_pt_sns_sf_dig,
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.config_nodes[29].mode = CKGEN_RUN_MODE,
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.config_nodes[29].enable = false,
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.config_nodes[30].ip_nodes = g_ckgen_saci2,
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.config_nodes[30].mode = CKGEN_RUN_MODE,
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.config_nodes[30].enable = false,
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.config_nodes[31].ip_nodes = g_ckgen_sehc1,
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.config_nodes[31].mode = CKGEN_RUN_MODE,
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.config_nodes[31].enable = false,
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.config_nodes[32].ip_nodes = g_ckgen_seip,
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.config_nodes[32].mode = CKGEN_RUN_MODE,
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.config_nodes[32].enable = false,
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.config_nodes[33].ip_nodes = g_ckgen_spi1,
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.config_nodes[33].mode = CKGEN_RUN_MODE,
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.config_nodes[33].enable = false,
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.config_nodes[34].ip_nodes = g_ckgen_spi2,
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.config_nodes[34].mode = CKGEN_RUN_MODE,
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.config_nodes[34].enable = false,
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.config_nodes[35].ip_nodes = g_ckgen_spi3,
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.config_nodes[35].mode = CKGEN_RUN_MODE,
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.config_nodes[35].enable = false,
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.config_nodes[36].ip_nodes = g_ckgen_spi4,
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.config_nodes[36].mode = CKGEN_RUN_MODE,
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.config_nodes[36].enable = false,
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.config_nodes[37].ip_nodes = g_ckgen_spi5,
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.config_nodes[37].mode = CKGEN_RUN_MODE,
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.config_nodes[37].enable = false,
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.config_nodes[38].ip_nodes = g_ckgen_spi6,
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.config_nodes[38].mode = CKGEN_RUN_MODE,
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.config_nodes[38].enable = false,
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.config_nodes[39].ip_nodes = g_ckgen_uart1,
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.config_nodes[39].mode = CKGEN_RUN_MODE,
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.config_nodes[39].enable = false,
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.config_nodes[40].ip_nodes = g_ckgen_uart2,
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.config_nodes[40].mode = CKGEN_RUN_MODE,
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.config_nodes[40].enable = false,
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.config_nodes[41].ip_nodes = g_ckgen_uart3,
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.config_nodes[41].mode = CKGEN_RUN_MODE,
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.config_nodes[41].enable = false,
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.config_nodes[42].ip_nodes = g_ckgen_uart4,
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.config_nodes[42].mode = CKGEN_RUN_MODE,
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.config_nodes[42].enable = false,
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.config_nodes[43].ip_nodes = g_ckgen_uart5,
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.config_nodes[43].mode = CKGEN_RUN_MODE,
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.config_nodes[43].enable = false,
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.config_nodes[44].ip_nodes = g_ckgen_uart6,
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.config_nodes[44].mode = CKGEN_RUN_MODE,
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.config_nodes[44].enable = false,
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.config_nodes[45].ip_nodes = g_ckgen_uart7,
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.config_nodes[45].mode = CKGEN_RUN_MODE,
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.config_nodes[45].enable = false,
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.config_nodes[46].ip_nodes = g_ckgen_uart8,
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.config_nodes[46].mode = CKGEN_RUN_MODE,
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.config_nodes[46].enable = false,
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.config_nodes[47].ip_nodes = g_ckgen_uart9,
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.config_nodes[47].mode = CKGEN_RUN_MODE,
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.config_nodes[47].enable = false,
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.config_nodes[48].ip_nodes = g_ckgen_uart10,
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.config_nodes[48].mode = CKGEN_RUN_MODE,
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.config_nodes[48].enable = false,
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.config_nodes[49].ip_nodes = g_ckgen_uart11,
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.config_nodes[49].mode = CKGEN_RUN_MODE,
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.config_nodes[49].enable = false,
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.config_nodes[50].ip_nodes = g_ckgen_uart12,
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.config_nodes[50].mode = CKGEN_RUN_MODE,
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.config_nodes[50].enable = false,
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.config_nodes[51].ip_nodes = g_ckgen_usb,
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.config_nodes[51].mode = CKGEN_RUN_MODE,
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.config_nodes[51].enable = false,
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.config_nodes[52].ip_nodes = g_ckgen_wdt1,
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.config_nodes[52].mode = CKGEN_RUN_MODE,
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.config_nodes[52].enable = false,
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.config_nodes[53].ip_nodes = g_ckgen_wdt8,
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.config_nodes[53].mode = CKGEN_RUN_MODE,
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.config_nodes[53].enable = false,
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.config_nodes[54].ip_nodes = g_ckgen_xspi1a,
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.config_nodes[54].mode = CKGEN_RUN_MODE,
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.config_nodes[54].enable = false,
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.config_nodes[55].ip_nodes = g_ckgen_xspi1b,
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.config_nodes[55].mode = CKGEN_RUN_MODE,
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.config_nodes[55].enable = false,
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.config_nodes[56].ip_nodes = g_ckgen_xspi_slv,
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.config_nodes[56].mode = CKGEN_RUN_MODE,
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.config_nodes[56].enable = false,
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.config_nodes[57].ip_nodes = g_ckgen_xtrg,
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.config_nodes[57].mode = CKGEN_RUN_MODE,
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.config_nodes[57].enable = false,
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};
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#if CONFIG_CLK_DUMP
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__WEAK sdrv_clk_config_t g_clk_config = {
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.config_num = 37,
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.config_nodes[0].ckgen_ref = CLK_NODE(g_rc_32k),
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.config_nodes[0].name = "rc32k",
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.config_nodes[1].ckgen_ref = CLK_NODE(g_fs_32k),
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.config_nodes[1].name = "fs32k",
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.config_nodes[2].ckgen_ref = CLK_NODE(g_rc_24m),
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.config_nodes[2].name = "rc24m",
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|
||||
.config_nodes[3].ckgen_ref = CLK_NODE(g_fs_24m),
|
||||
.config_nodes[3].name = "fs24m",
|
||||
|
||||
.config_nodes[4].ckgen_ref = CLK_NODE(g_pll1_root),
|
||||
.config_nodes[4].name = "pll1",
|
||||
|
||||
.config_nodes[5].ckgen_ref = CLK_NODE(g_pll2_root),
|
||||
.config_nodes[5].name = "pll2",
|
||||
|
||||
.config_nodes[6].ckgen_ref = CLK_NODE(g_pll3_root),
|
||||
.config_nodes[6].name = "pll3",
|
||||
|
||||
.config_nodes[7].ckgen_ref = CLK_NODE(g_ckgen_bus_cr5_sf),
|
||||
.config_nodes[7].name = "cr5_sf",
|
||||
|
||||
.config_nodes[8].ckgen_ref = CLK_NODE(g_ckgen_ip_i2c_sf_1_to_3),
|
||||
.config_nodes[8].name = "i2c_sf_1_to_3",
|
||||
|
||||
.config_nodes[9].ckgen_ref = CLK_NODE(g_ckgen_ip_i2c_sf_4_to_6),
|
||||
.config_nodes[9].name = "i2c_sf_4_to_6",
|
||||
|
||||
.config_nodes[10].ckgen_ref = CLK_NODE(g_ckgen_ip_spi_sf_1_to_3),
|
||||
.config_nodes[10].name = "spi_sf_1_to_3",
|
||||
|
||||
.config_nodes[11].ckgen_ref = CLK_NODE(g_ckgen_ip_spi_sf_4_to_6),
|
||||
.config_nodes[11].name = "spi_sf_4_to_6",
|
||||
|
||||
.config_nodes[12].ckgen_ref = CLK_NODE(g_ckgen_ip_uart_sf_1_to_6),
|
||||
.config_nodes[12].name = "uart_sf_1_to_6",
|
||||
|
||||
.config_nodes[13].ckgen_ref = CLK_NODE(g_ckgen_ip_uart_sf_7_to_12),
|
||||
.config_nodes[13].name = "uart_sf_7_to_12",
|
||||
|
||||
.config_nodes[14].ckgen_ref = CLK_NODE(g_ckgen_ip_enet1_tx),
|
||||
.config_nodes[14].name = "enet1_tx",
|
||||
|
||||
.config_nodes[15].ckgen_ref = CLK_NODE(g_ckgen_ip_enet1_rmii),
|
||||
.config_nodes[15].name = "enet1_rmii",
|
||||
|
||||
.config_nodes[16].ckgen_ref = CLK_NODE(g_ckgen_ip_enet1_phy_ref),
|
||||
.config_nodes[16].name = "enet1_phy_ref",
|
||||
|
||||
.config_nodes[17].ckgen_ref = CLK_NODE(g_ckgen_ip_enet1_timer_sec),
|
||||
.config_nodes[17].name = "enet1_timer_sec",
|
||||
|
||||
.config_nodes[18].ckgen_ref = CLK_NODE(g_ckgen_ip_i2s_mclk0),
|
||||
.config_nodes[18].name = "i2s_mclk0",
|
||||
|
||||
.config_nodes[19].ckgen_ref = CLK_NODE(g_ckgen_ip_xspi1a),
|
||||
.config_nodes[19].name = "xspi1a",
|
||||
|
||||
.config_nodes[20].ckgen_ref = CLK_NODE(g_ckgen_ip_xspi1b),
|
||||
.config_nodes[20].name = "xspi1b",
|
||||
|
||||
.config_nodes[21].ckgen_ref = CLK_NODE(g_ckgen_ip_saci2_clk),
|
||||
.config_nodes[21].name = "saci2_clk",
|
||||
|
||||
.config_nodes[22].ckgen_ref = CLK_NODE(g_ckgen_ip_saci2_pdm_clk),
|
||||
.config_nodes[22].name = "saci2_pdm_clk",
|
||||
|
||||
.config_nodes[23].ckgen_ref = CLK_NODE(g_ckgen_ip_xtrg),
|
||||
.config_nodes[23].name = "xtrg",
|
||||
|
||||
.config_nodes[24].ckgen_ref = CLK_NODE(g_ckgen_ip_etmr1),
|
||||
.config_nodes[24].name = "etmr1",
|
||||
|
||||
.config_nodes[25].ckgen_ref = CLK_NODE(g_ckgen_ip_etmr2),
|
||||
.config_nodes[25].name = "etmr2",
|
||||
|
||||
.config_nodes[26].ckgen_ref = CLK_NODE(g_ckgen_ip_epwm1),
|
||||
.config_nodes[26].name = "epwm1",
|
||||
|
||||
.config_nodes[27].ckgen_ref = CLK_NODE(g_ckgen_ip_epwm2),
|
||||
.config_nodes[27].name = "epwm2",
|
||||
|
||||
.config_nodes[28].ckgen_ref = CLK_NODE(g_ckgen_ip_sehc1),
|
||||
.config_nodes[28].name = "sehc1",
|
||||
|
||||
.config_nodes[29].ckgen_ref = CLK_NODE(g_ckgen_ip_can),
|
||||
.config_nodes[29].name = "can",
|
||||
|
||||
.config_nodes[30].ckgen_ref = CLK_NODE(g_ckgen_ip_adc1),
|
||||
.config_nodes[30].name = "adc1",
|
||||
|
||||
.config_nodes[31].ckgen_ref = CLK_NODE(g_ckgen_ip_adc2),
|
||||
.config_nodes[31].name = "adc2",
|
||||
|
||||
.config_nodes[32].ckgen_ref = CLK_NODE(g_ckgen_ip_adc3),
|
||||
.config_nodes[32].name = "adc3",
|
||||
|
||||
.config_nodes[33].ckgen_ref = CLK_NODE(g_ckgen_ip_acmp),
|
||||
.config_nodes[33].name = "acmp",
|
||||
|
||||
.config_nodes[34].ckgen_ref = CLK_NODE(g_ckgen_ip_ioc),
|
||||
.config_nodes[34].name = "ioc",
|
||||
|
||||
.config_nodes[35].ckgen_ref = CLK_NODE(g_ckgen_ip_pt_sns_sf),
|
||||
.config_nodes[35].name = "pt_sns_sf",
|
||||
|
||||
.config_nodes[36].ckgen_ref = CLK_NODE(g_ckgen_bus_ap_bus),
|
||||
.config_nodes[36].name = "ap_bus",
|
||||
};
|
||||
|
||||
#endif /* CONFIG_CLK_DUMP */
|
||||
|
||||
#if CONFIG_RTC_SS_DYNAMIC_PCLK
|
||||
|
||||
static uint32_t g_rtc_ss_pclk_ref = 0;
|
||||
|
||||
int sdrv_rtc_ss_pclk_enable(void)
|
||||
{
|
||||
int ret = SDRV_STATUS_OK;
|
||||
irq_state_t state;
|
||||
|
||||
state = arch_irq_save();
|
||||
|
||||
if (++g_rtc_ss_pclk_ref == 1) {
|
||||
ret = sdrv_ckgen_clock_config(CLK_NODE(g_ckgen_gating_rtc_pclk), true);
|
||||
SDRV_RTC_REG_PARITY_ERR_ENABLE();
|
||||
}
|
||||
|
||||
arch_irq_restore(state);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int sdrv_rtc_ss_pclk_disable(void)
|
||||
{
|
||||
int ret = SDRV_STATUS_OK;
|
||||
irq_state_t state;
|
||||
|
||||
state = arch_irq_save();
|
||||
|
||||
if (g_rtc_ss_pclk_ref) {
|
||||
g_rtc_ss_pclk_ref--;
|
||||
}
|
||||
|
||||
if (!g_rtc_ss_pclk_ref) {
|
||||
SDRV_RTC_REG_PARITY_ERR_DISABLE();
|
||||
ret = sdrv_ckgen_clock_config(CLK_NODE(g_ckgen_gating_rtc_pclk), false);
|
||||
}
|
||||
|
||||
arch_irq_restore(state);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_RTC_SS_DYNAMIC_PCLK */
|
||||
2744
devices/E3106/clock_ip.c
Normal file
2744
devices/E3106/clock_ip.c
Normal file
File diff suppressed because it is too large
Load Diff
114
devices/E3106/device_init.c
Normal file
114
devices/E3106/device_init.c
Normal file
@@ -0,0 +1,114 @@
|
||||
/**
|
||||
* @file device_init.c
|
||||
* @brief Semidrive device ealryinit.
|
||||
*
|
||||
* @copyright Copyright (c) 2022 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <sdrv_ckgen.h>
|
||||
#include <sdrv_power.h>
|
||||
#include <regs_base.h>
|
||||
#include <reg.h>
|
||||
#include <param.h>
|
||||
|
||||
#ifndef APB_ACMP4_BASE
|
||||
/* Analog Compare (ACMP) 4 */
|
||||
#define APB_ACMP4_BASE (0xF0AC0000ul)
|
||||
#endif
|
||||
|
||||
#ifndef APB_ACMP3_BASE
|
||||
/* Analog Compare (ACMP) 3 */
|
||||
#define APB_ACMP3_BASE (0xF0AB0000ul)
|
||||
#endif
|
||||
|
||||
extern const sdrv_ckgen_node_t **g_ckgen_unused[];
|
||||
|
||||
static const sdrv_ckgen_xcg_set_t g_xcg_info[] = {
|
||||
{APB_CKGEN_SF_BASE, CKGEN_PCG_TYPE, 207},
|
||||
{APB_CKGEN_SF_BASE, CKGEN_BCG_TYPE, 8},
|
||||
{APB_CKGEN_SF_BASE, CKGEN_CCG_TYPE, 1},
|
||||
};
|
||||
|
||||
static const mcu_power_e g_unused_power[] = {
|
||||
MCU_POWER_ACMP3,
|
||||
MCU_POWER_ACMP4,
|
||||
MCU_POWER_END
|
||||
};
|
||||
|
||||
static int mcu_unused_ip_cglist_mask(const sdrv_ckgen_node_t *ckgen_ip[], bool mask)
|
||||
{
|
||||
sdrv_ckgen_node_t *node;
|
||||
uint32_t i = 0;
|
||||
int ret = 0;
|
||||
|
||||
while (ckgen_ip[i] && !ret) {
|
||||
node = (sdrv_ckgen_node_t *)ckgen_ip[i];
|
||||
ret = sdrv_ckgen_cg_mask(node, mask);
|
||||
i++;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mcu_unused_power_pre_config(const mcu_power_e *powers)
|
||||
{
|
||||
uint32_t i = 0;
|
||||
|
||||
while (powers[i] != MCU_POWER_END) {
|
||||
switch (powers[i]) {
|
||||
case MCU_POWER_ACMP3:
|
||||
RMWREG32(APB_ACMP3_BASE + 0xBC, 0, 1, 1);
|
||||
RMWREG32(APB_ACMP3_BASE + 0xBC, 1, 1, 1);
|
||||
break;
|
||||
|
||||
case MCU_POWER_ACMP4:
|
||||
RMWREG32(APB_ACMP4_BASE + 0xBC, 0, 1, 1);
|
||||
RMWREG32(APB_ACMP4_BASE + 0xBC, 1, 1, 1);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
static int mcu_unused_ip_config(void)
|
||||
{
|
||||
uint32_t i = 0;
|
||||
int ret = 0;
|
||||
|
||||
mcu_unused_power_pre_config(g_unused_power);
|
||||
|
||||
while (g_ckgen_unused[i]) {
|
||||
ret = sdrv_ckgen_ip_clock_enable(g_ckgen_unused[i], CKGEN_HIB_MODE, false);
|
||||
ret = sdrv_ckgen_ip_clock_enable(g_ckgen_unused[i], CKGEN_SLP_MODE, false);
|
||||
ret = sdrv_ckgen_ip_clock_enable(g_ckgen_unused[i], CKGEN_RUN_MODE, false);
|
||||
ret = mcu_unused_ip_cglist_mask(g_ckgen_unused[i], true);
|
||||
i++;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sdrv_xcg_runmode_active(const sdrv_ckgen_xcg_set_t *infos, uint32_t size)
|
||||
{
|
||||
for (uint32_t i = 0; i < size; i++) {
|
||||
sdrv_ckgen_xcg_type_set((sdrv_ckgen_xcg_set_t *)&infos[i], CKGEN_RUN_MODE, false);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief initializes the device.
|
||||
*
|
||||
* This function initializes the device before call main function.
|
||||
*/
|
||||
void device_init(void)
|
||||
{
|
||||
sdrv_xcg_runmode_active(g_xcg_info, ARRAY_SIZE(g_xcg_info));
|
||||
|
||||
mcu_unused_ip_config();
|
||||
}
|
||||
BIN
devices/E3106/dloader/e3_176_ref_norflash.bin
Normal file
BIN
devices/E3106/dloader/e3_176_ref_norflash.bin
Normal file
Binary file not shown.
BIN
devices/E3106/dloader/e3_master_slave_slave_a_norflash.bin
Normal file
BIN
devices/E3106/dloader/e3_master_slave_slave_a_norflash.bin
Normal file
Binary file not shown.
BIN
devices/E3106/dloader/e3_master_slave_slave_b_norflash.bin
Normal file
BIN
devices/E3106/dloader/e3_master_slave_slave_b_norflash.bin
Normal file
Binary file not shown.
BIN
devices/E3106/flashloader/flashloader_norflash.out
Normal file
BIN
devices/E3106/flashloader/flashloader_norflash.out
Normal file
Binary file not shown.
39
devices/E3106/flashloader/iar_flashmacro.mac
Normal file
39
devices/E3106/flashloader/iar_flashmacro.mac
Normal file
@@ -0,0 +1,39 @@
|
||||
tcm_init(tcma_base, tcmb_base)
|
||||
{
|
||||
__var actlr;
|
||||
|
||||
actlr = __jtagCP15ReadReg(1, 0, 0, 1);
|
||||
actlr &= ~((1 << 25) | (1 << 26) | (1 << 27));
|
||||
__jtagCP15WriteReg(1, 0, 0, 1, actlr);
|
||||
__jtagCP15WriteReg(9, 1, 0, 1, tcma_base | 1);
|
||||
__jtagCP15WriteReg(9, 1, 0, 0, tcmb_base | 1);
|
||||
}
|
||||
|
||||
mpu_disable()
|
||||
{
|
||||
__var sctlr;
|
||||
sctlr = __jtagCP15ReadReg(1, 0, 0, 0);
|
||||
sctlr &= ~(1 << 0);
|
||||
__jtagCP15WriteReg(1, 0, 0, 0, sctlr);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserFlashInit()
|
||||
*********************************************************************/
|
||||
execUserFlashInit()
|
||||
{
|
||||
__message "------------------------------ execUserFlashInit ---------------------------------";
|
||||
mpu_disable();
|
||||
|
||||
tcm_init(0x4E0000, 0x4F0000);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserFlashReset()
|
||||
*********************************************************************/
|
||||
execUserFlashReset()
|
||||
{
|
||||
__message "------------------------------ execUserFlashReset ---------------------------------";
|
||||
/* Disable MPU*/
|
||||
__jtagCP15WriteReg(1, 0, 0, 0, 0x08E7087A);
|
||||
}
|
||||
9
devices/E3106/flashloader/init_before_download.txt
Normal file
9
devices/E3106/flashloader/init_before_download.txt
Normal file
@@ -0,0 +1,9 @@
|
||||
h
|
||||
WCP15Ex 0 1 0 0 0x08E7087A
|
||||
WCP15Ex 0 1 0 1 0x00000020
|
||||
WCP15Ex 0 9 1 1 0x4E0001
|
||||
WCP15Ex 0 9 1 0 0x4F0001
|
||||
w4 0x4E0000 0xBE00BE00
|
||||
setpc 0x4E0000
|
||||
wreg CPSR 0x3F
|
||||
q
|
||||
@@ -0,0 +1,13 @@
|
||||
h
|
||||
WCP15Ex 0 1 0 0 0x08E7087A
|
||||
WCP15Ex 0 1 0 1 0x00000020
|
||||
WCP15Ex 0 9 1 1 0x4E0001
|
||||
WCP15Ex 0 9 1 0 0x4F0001
|
||||
exec EnableEraseAllFlashBanks
|
||||
Erase 0x100C0000 0x100C1000 noreset
|
||||
Erase 0x104C0000 0x104C1000 noreset
|
||||
Erase 0x108C0000 0x108C1000 noreset
|
||||
w4 0x4E0000 0xBE00BE00
|
||||
setpc 0x4E0000
|
||||
wreg CPSR 0x3F
|
||||
q
|
||||
13
devices/E3106/flashloader/init_before_download_norflash.txt
Normal file
13
devices/E3106/flashloader/init_before_download_norflash.txt
Normal file
@@ -0,0 +1,13 @@
|
||||
h
|
||||
WCP15Ex 0 1 0 0 0x08E7087A
|
||||
WCP15Ex 0 1 0 1 0x00000020
|
||||
WCP15Ex 0 9 1 1 0x4E0001
|
||||
WCP15Ex 0 9 1 0 0x4F0001
|
||||
exec EnableEraseAllFlashBanks
|
||||
Erase 0x10007000 0x10008000 noreset
|
||||
Erase 0x10407000 0x10408000 noreset
|
||||
Erase 0x10807000 0x10808000 noreset
|
||||
w4 0x4E0000 0xBE00BE00
|
||||
setpc 0x4E0000
|
||||
wreg CPSR 0x3F
|
||||
q
|
||||
@@ -0,0 +1,22 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>sfs.flash</loader>
|
||||
<range>CODE 0x10000000 0x10000080</range>
|
||||
<abs_offset>0x10000000</abs_offset>
|
||||
<args>
|
||||
255
|
||||
0
|
||||
</args>
|
||||
</pass>
|
||||
<pass>
|
||||
<loader>sf.flash</loader>
|
||||
<range>CODE 0x504000 0x57ffff</range>
|
||||
<abs_offset>0x10008000</abs_offset>
|
||||
<args>
|
||||
0
|
||||
1
|
||||
0x504000
|
||||
</args>
|
||||
</pass>
|
||||
</flash_board>
|
||||
10
devices/E3106/flashloader/iram/norflash/sf.flash
Normal file
10
devices/E3106/flashloader/iram/norflash/sf.flash
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>../../flashloader_norflash.out</exe>
|
||||
<macro>../../iar_flashmacro.mac</macro>
|
||||
<page>512</page>
|
||||
<block>504 0x1000</block>
|
||||
<flash_base>0x10008000</flash_base>
|
||||
<aggregate>1</aggregate>
|
||||
</flash_device>
|
||||
10
devices/E3106/flashloader/iram/norflash/sfs.flash
Normal file
10
devices/E3106/flashloader/iram/norflash/sfs.flash
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>../../flashloader_norflash.out</exe>
|
||||
<macro>../../iar_flashmacro.mac</macro>
|
||||
<page>512</page>
|
||||
<block>1 0x1000</block>
|
||||
<flash_base>0x10000000</flash_base>
|
||||
<aggregate>1</aggregate>
|
||||
</flash_device>
|
||||
10
devices/E3106/flashloader/xip/norflash/bootloader.flash
Normal file
10
devices/E3106/flashloader/xip/norflash/bootloader.flash
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>../../flashloader_norflash.out</exe>
|
||||
<macro>../../iar_flashmacro.mac</macro>
|
||||
<page>512</page>
|
||||
<block>312 0x1000</block>
|
||||
<flash_base>0x10008000</flash_base>
|
||||
<aggregate>1</aggregate>
|
||||
</flash_device>
|
||||
@@ -0,0 +1,32 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>sfs.flash</loader>
|
||||
<range>CODE 0x10000000 0x10000080</range>
|
||||
<abs_offset>0x10000000</abs_offset>
|
||||
<args>
|
||||
255
|
||||
0
|
||||
</args>
|
||||
</pass>
|
||||
<pass>
|
||||
<loader>bootloader.flash</loader>
|
||||
<range>CODE 0x504000 0x7FFFFF</range>
|
||||
<abs_offset>0x10008000</abs_offset>
|
||||
<args>
|
||||
0
|
||||
1
|
||||
0x504000
|
||||
</args>
|
||||
</pass>
|
||||
<pass>
|
||||
<loader>sf.flash</loader>
|
||||
<range>CODE 0x10140000 0x101FFFFF</range>
|
||||
<abs_offset>0x10140000</abs_offset>
|
||||
<args>
|
||||
0
|
||||
0
|
||||
0x10140000
|
||||
</args>
|
||||
</pass>
|
||||
</flash_board>
|
||||
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>sf.flash</loader>
|
||||
<range>CODE 0x10140000 0x101FFFFF</range>
|
||||
<abs_offset>0x10140000</abs_offset>
|
||||
<args>
|
||||
0
|
||||
0
|
||||
0x10140000
|
||||
</args>
|
||||
</pass>
|
||||
</flash_board>
|
||||
@@ -0,0 +1,32 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<flash_board>
|
||||
<pass>
|
||||
<loader>sfs.flash</loader>
|
||||
<range>CODE 0x10000000 0x10000080</range>
|
||||
<abs_offset>0x10000000</abs_offset>
|
||||
<args>
|
||||
255
|
||||
0
|
||||
</args>
|
||||
</pass>
|
||||
<pass>
|
||||
<loader>bootloader.flash</loader>
|
||||
<range>CODE 0x10008000 0x1013FFFF</range>
|
||||
<abs_offset>0x10008000</abs_offset>
|
||||
<args>
|
||||
0
|
||||
1
|
||||
0x504000
|
||||
</args>
|
||||
</pass>
|
||||
<pass>
|
||||
<loader>sf.flash</loader>
|
||||
<range>CODE 0x10140000 0x101FFFFF</range>
|
||||
<abs_offset>0x10140000</abs_offset>
|
||||
<args>
|
||||
0
|
||||
0
|
||||
0x10140000
|
||||
</args>
|
||||
</pass>
|
||||
</flash_board>
|
||||
10
devices/E3106/flashloader/xip/norflash/sf.flash
Normal file
10
devices/E3106/flashloader/xip/norflash/sf.flash
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>../../flashloader_norflash.out</exe>
|
||||
<macro>../../iar_flashmacro.mac</macro>
|
||||
<page>512</page>
|
||||
<block>192 0x1000</block>
|
||||
<flash_base>0x10140000</flash_base>
|
||||
<aggregate>1</aggregate>
|
||||
</flash_device>
|
||||
10
devices/E3106/flashloader/xip/norflash/sfs.flash
Normal file
10
devices/E3106/flashloader/xip/norflash/sfs.flash
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<flash_device>
|
||||
<exe>../../flashloader_norflash.out</exe>
|
||||
<macro>../../iar_flashmacro.mac</macro>
|
||||
<page>512</page>
|
||||
<block>1 0x1000</block>
|
||||
<flash_base>0x10000000</flash_base>
|
||||
<aggregate>1</aggregate>
|
||||
</flash_device>
|
||||
363
devices/E3106/include/clock_ip.h
Normal file
363
devices/E3106/include/clock_ip.h
Normal file
@@ -0,0 +1,363 @@
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// WARNING: Automatically generated file, don't modify anymore!!!
|
||||
//
|
||||
// Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef CLOCK_IP_H
|
||||
#define CLOCK_IP_H
|
||||
|
||||
#include <sdrv_ckgen.h>
|
||||
|
||||
extern const sdrv_pll_node_t g_rc_32k;
|
||||
extern const sdrv_pll_node_t g_fs_32k;
|
||||
extern const sdrv_pll_node_t g_rc_24m;
|
||||
extern const sdrv_pll_node_t g_fs_24m;
|
||||
extern const sdrv_pll_node_t g_pll1_root;
|
||||
extern const sdrv_pll_node_t g_pll2_root;
|
||||
extern const sdrv_pll_node_t g_pll3_root;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_bus_cr5_sf;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_i2c_sf_1_to_3;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_i2c_sf_4_to_6;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_spi_sf_1_to_3;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_spi_sf_4_to_6;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_uart_sf_1_to_6;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_uart_sf_7_to_12;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_enet1_tx;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_enet1_rmii;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_enet1_phy_ref;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_enet1_timer_sec;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_i2s_mclk0;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_xspi1a;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_xspi1b;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_saci2_clk;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_saci2_pdm_clk;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_xtrg;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_etmr1;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_etmr2;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_epwm1;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_epwm2;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_sehc1;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_can;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_adc1;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_adc2;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_adc3;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_acmp;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_ioc;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_ip_pt_sns_sf;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_bus_sf_test;
|
||||
extern const sdrv_ckgen_slice_node_t g_ckgen_bus_ap_bus;
|
||||
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_cr5_sf_aclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_fab_sf_mainclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_fab_sf_hsmclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_fab_sf_perclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_fab_sf_xspi1aclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_fab_sf_xspi1bclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_fab_ap_apmainclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_fab_ap_perclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_cr5_sf_clkin;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_iramc1_aclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_iromc_aclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_dma_sf_clk0;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_dma_sf_clk1;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_dma_sf_aclk0;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_dma_sf_aclk1;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_dma_sf_hclk0;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_dma_sf_hclk1;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c1_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c2_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c3_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c4_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c5_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c6_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi1_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi2_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi3_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi4_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi5_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi6_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart1_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart2_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart3_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart4_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart5_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart6_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart7_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart8_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart9_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart10_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart11_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart12_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd16_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd21_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd3_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd4_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd5_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd6_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd7_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd23_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_etmr1_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_etmr2_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_pt_sns_sf_dig_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_epwm1_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_epwm2_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_iramc1_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_iromc_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_gpio_sf_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_wdt1_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_wdt2_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_wdt1_bus_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_wdt2_bus_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_wdt8_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_wdt8_bus_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sem1_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sem2_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_iomuxc_sf_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_iomuxc_sf_comp_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_efusec_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_mac_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_mpc_cr5_sf_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_scr_sf_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_u_ckgen_sf_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_rstgen_sf_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_dma_sf_pclk0;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_dma_sf_pclk1;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xb_sf_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_apbmux2_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_apbmux3_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_apbmux4_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_apbmux3_sf_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_ppc_apbmux1_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_ppc_apbmux2_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_ppc_apbmux3_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_ppc_apbmux4_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_smc_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_vd_sf_dig_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_por_sf_dig_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xtrg_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_fs_24m_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_acmp1_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_acmp2_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_acmp3_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_acmp4_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sadc1_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sadc2_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sadc3_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_ioc_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_btm1_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_btm2_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_btm3_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_btm4_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_eic_sf_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_istc_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_apb_seip_nvm_mst_dst_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xspi1a_dma_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xspi1b_dma_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_tx_dmaclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_rx_dmaclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_pdm_dmaclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_tx_perclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_rx_perclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_pdm_perclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xb_sf_hclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_bti_sf_ahb_hclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_vic1_hclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_vic_sf_irqsync;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c1_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c2_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c3_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c4_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c5_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_i2c6_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi1_spi_per_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi2_spi_per_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi3_spi_per_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi4_spi_per_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi5_spi_per_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_spi6_spi_per_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart1_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart2_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart3_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart4_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart5_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart6_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart7_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart8_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart9_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart10_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart11_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_uart12_i_sclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_enet1_ref_clk_tx_i;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xspi1_test_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_enet1_ptp_ref_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xspi1a_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xspi1b_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_pdm_per_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xtrg_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_etmr1_ahf_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_etmr2_ahf_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_epwm1_ahf_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_epwm2_ahf_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_etmr1_hf_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_etmr2_hf_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_epwm1_hf_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_epwm2_hf_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sehc1_main_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd16_ipg_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd21_ipg_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd3_ipg_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd4_ipg_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd5_ipg_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd6_ipg_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd7_ipg_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd23_ipg_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sadc1_ctrl_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sadc2_ctrl_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sadc3_ctrl_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_acmp1_ctrl_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_acmp2_ctrl_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_acmp3_ctrl_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_acmp4_ctrl_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_ioc_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_pt_sns_sf_clkin;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_istc_i_istc_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_smc_clk_24m;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd16_clk24m;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd21_clk24m;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd3_clk24m;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd4_clk24m;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd5_clk24m;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd6_clk24m;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd7_clk24m;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_canfd23_clk24m;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xtrg_wdt_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_dcdc1_clk_24m;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_vic1_wdt_ref_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_wdt1_main_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_wdt2_main_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_wdt8_main_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_btm1_i_xtal24mhz_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_btm2_i_xtal24mhz_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_btm3_i_xtal24mhz_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_btm4_i_xtal24mhz_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_pt_sns_sf_dig_clk_24m;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xspi_slv_aclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_enet1_aclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_xspi_slv_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_enet1_clk_csr_i;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_cslite_pclkdbg;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_cslite_pclksys;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sehc1_aclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_seip_sh_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_usb2_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sehc1_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_seip_i_pclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_seip_i_hclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_seip_i_fd_ref_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_i2s_mclk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_ext_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_i2s_tx_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_saci2_i2s_rx_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_usb_i_phy_ref_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sehc1_cqe_sqs_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_sehc1_tm_clk;
|
||||
extern const sdrv_ckgen_cg_node_t g_ckgen_gating_rtc_pclk;
|
||||
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_adc1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_adc2[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_adc3[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_acmp1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_acmp2[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_acmp3[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_acmp4[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_cr5_sf[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_iramc1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_iromc[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_dma_sf[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_i2c1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_i2c2[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_i2c3[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_i2c4[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_i2c5[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_i2c6[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_spi1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_spi2[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_spi3[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_spi4[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_spi5[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_spi6[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart2[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart3[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart4[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart5[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart6[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart7[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart8[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart9[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart10[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart11[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_uart12[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_canfd16[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_canfd21[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_canfd3[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_canfd4[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_canfd5[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_canfd6[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_canfd7[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_canfd23[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_etmr1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_etmr2[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_pt_sns_sf_dig[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_epwm1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_epwm2[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_gpio_sf[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_wdt1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_wdt2[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_wdt8[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_sem1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_sem2[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_iomuxc_sf[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_efusec[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_scr_sf[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_rstgen_sf[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_smc[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_vd_sf_dig[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_por_sf_dig[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_xtrg[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_ioc[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_btm1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_btm2[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_btm3[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_btm4[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_eic_sf[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_vic1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_enet1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_xspi1a[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_xspi1b[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_saci2[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_sehc1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_pt_sns_sf_ana[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_dcdc1[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_xspi_slv[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_cslite[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_seip[];
|
||||
extern const sdrv_ckgen_node_t *g_ckgen_usb[];
|
||||
|
||||
extern const sdrv_ckgen_bus_config_t g_pre_bus_config;
|
||||
extern const sdrv_ckgen_rate_config_t g_pll_config;
|
||||
extern const sdrv_ckgen_bus_config_t g_bus_config;
|
||||
extern const sdrv_ckgen_rate_config_t g_ip_config;
|
||||
extern const sdrv_ckgen_ip_clock_config_t g_enable_config;
|
||||
|
||||
#if CONFIG_CLK_DUMP
|
||||
extern sdrv_clk_config_t g_clk_config;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
45
devices/E3106/include/core_id.h
Normal file
45
devices/E3106/include/core_id.h
Normal file
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* core_id.h
|
||||
*
|
||||
* Copyright (c) 2020 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Description: E3 core id interface.
|
||||
*
|
||||
* Revision History:
|
||||
* -----------------
|
||||
*/
|
||||
|
||||
#ifndef _CORE_ID_H_
|
||||
#define _CORE_ID_H_
|
||||
|
||||
#ifndef ASSEMBLY
|
||||
#include "armv7-r/register.h"
|
||||
|
||||
/* core numbers */
|
||||
#define CORE_NUM 1
|
||||
|
||||
/* core id */
|
||||
#define CORE_SF 0
|
||||
|
||||
/* core numbers in SMP (Symmetrical Multi-Processing) system */
|
||||
#define CORE_NUM_SMP 1
|
||||
|
||||
/**
|
||||
* @brief Get the core id
|
||||
*
|
||||
* SF 0
|
||||
*
|
||||
* @return core id
|
||||
*/
|
||||
static inline int get_core_id(void)
|
||||
{
|
||||
return CORE_SF;
|
||||
}
|
||||
|
||||
/* Get the core id in SMP (Symmetrical Multi-Processing) system */
|
||||
#define get_core_id_smp() get_core_id()
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
38
devices/E3106/include/device_pin.h
Normal file
38
devices/E3106/include/device_pin.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/**
|
||||
* @file device_pin.h
|
||||
* @brief Sdrv device init pin header.
|
||||
*
|
||||
* @copyright Copyright (c) 2022 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef DEVICE_PIN_H_
|
||||
#define DEVICE_PIN_H_
|
||||
#include <types.h>
|
||||
|
||||
#define TAISHAN_PIN_NUM 125
|
||||
#define TAISHAN_SAFETY_PIN_START 0
|
||||
#define TAISHAN_SAFETY_PIN_NUM 125
|
||||
|
||||
#define TAISHAN_PINCTRL_GET_BASE(pin) (APB_IOMUXC_SF_BASE)
|
||||
|
||||
#define TAISHAN_PINCTRL_GET_INDEX(pin) ((pin) + 1)
|
||||
|
||||
#define PINCTRL_IS_IDX(pin, mux) (((pin) << 8) + (mux))
|
||||
|
||||
#define TAISHAN_GPIO_GET_BASE(pin) (APB_GPIO_SF_BASE)
|
||||
|
||||
#define TAISHAN_GPIO_GET_INDEX(pin) (pin)
|
||||
|
||||
#define RTC_DOMAIN_SYS_MODE0 0
|
||||
#define RTC_DOMAIN_SYS_MODE1 1
|
||||
#define RTC_DOMAIN_SYS_POR_B 2
|
||||
#define RTC_DOMAIN_SYS_BUTTON 3
|
||||
#define RTC_DOMAIN_SYS_WAKEUP0 4
|
||||
#define RTC_DOMAIN_SYS_WAKEUP1 5
|
||||
#define RTC_DOMAIN_SYS_CTRL0 6
|
||||
#define RTC_DOMAIN_SYS_CTRL1 7
|
||||
|
||||
#define RTC_DOMAIN_PIN_NUM 8
|
||||
|
||||
#endif /* DEVICE_PIN_H_ */
|
||||
192
devices/E3106/include/dma_mux.h
Normal file
192
devices/E3106/include/dma_mux.h
Normal file
@@ -0,0 +1,192 @@
|
||||
/**
|
||||
* @brief Unique ID of the peripheral for DMA in SF domain .
|
||||
*
|
||||
* For peripheral transactions,DMA channel should set corresponding
|
||||
* mux id to select peripheral.
|
||||
*/
|
||||
typedef enum {
|
||||
SDRV_DMA_MUX_ID_CANFD16,
|
||||
SDRV_DMA_MUX_ID_CANFD21,
|
||||
SDRV_DMA_MUX_ID_CANFD3,
|
||||
SDRV_DMA_MUX_ID_CANFD4,
|
||||
SDRV_DMA_MUX_ID_CANFD5,
|
||||
SDRV_DMA_MUX_ID_CANFD6,
|
||||
SDRV_DMA_MUX_ID_CANFD7,
|
||||
SDRV_DMA_MUX_ID_CANFD23,
|
||||
SDRV_DMA_MUX_ID_ENET1_REQ_0,
|
||||
SDRV_DMA_MUX_ID_ENET1_REQ_1,
|
||||
SDRV_DMA_MUX_ID_ENET1_REQ_2,
|
||||
SDRV_DMA_MUX_ID_ENET1_REQ_3,
|
||||
SDRV_DMA_MUX_ID_I2C1,
|
||||
SDRV_DMA_MUX_ID_I2C2,
|
||||
SDRV_DMA_MUX_ID_I2C3,
|
||||
SDRV_DMA_MUX_ID_I2C4,
|
||||
SDRV_DMA_MUX_ID_I2C5,
|
||||
SDRV_DMA_MUX_ID_I2C6,
|
||||
SDRV_DMA_MUX_ID_XSPI1_A_RD,
|
||||
SDRV_DMA_MUX_ID_XSPI1_A_WR,
|
||||
SDRV_DMA_MUX_ID_XSPI1_B_RD,
|
||||
SDRV_DMA_MUX_ID_XSPI1_B_WR,
|
||||
SDRV_DMA_MUX_ID_SPI1_RX,
|
||||
SDRV_DMA_MUX_ID_SPI1_TX,
|
||||
SDRV_DMA_MUX_ID_SPI2_RX,
|
||||
SDRV_DMA_MUX_ID_SPI2_TX,
|
||||
SDRV_DMA_MUX_ID_SPI3_RX,
|
||||
SDRV_DMA_MUX_ID_SPI3_TX,
|
||||
SDRV_DMA_MUX_ID_SPI4_RX,
|
||||
SDRV_DMA_MUX_ID_SPI4_TX,
|
||||
SDRV_DMA_MUX_ID_SPI5_RX,
|
||||
SDRV_DMA_MUX_ID_SPI5_TX,
|
||||
SDRV_DMA_MUX_ID_SPI6_RX,
|
||||
SDRV_DMA_MUX_ID_SPI6_TX,
|
||||
SDRV_DMA_MUX_ID_EPWM1_A,
|
||||
SDRV_DMA_MUX_ID_EPWM1_B,
|
||||
SDRV_DMA_MUX_ID_EPWM1_C,
|
||||
SDRV_DMA_MUX_ID_EPWM1_D,
|
||||
SDRV_DMA_MUX_ID_EPWM1_OVF,
|
||||
SDRV_DMA_MUX_ID_EPWM2_A,
|
||||
SDRV_DMA_MUX_ID_EPWM2_B,
|
||||
SDRV_DMA_MUX_ID_EPWM2_C,
|
||||
SDRV_DMA_MUX_ID_EPWM2_D,
|
||||
SDRV_DMA_MUX_ID_EPWM2_OVF,
|
||||
SDRV_DMA_MUX_ID_ETMR1_A,
|
||||
SDRV_DMA_MUX_ID_ETMR1_B,
|
||||
SDRV_DMA_MUX_ID_ETMR1_C,
|
||||
SDRV_DMA_MUX_ID_ETMR1_D,
|
||||
SDRV_DMA_MUX_ID_ETMR1_OVF,
|
||||
SDRV_DMA_MUX_ID_ETMR2_A,
|
||||
SDRV_DMA_MUX_ID_ETMR2_B,
|
||||
SDRV_DMA_MUX_ID_ETMR2_C,
|
||||
SDRV_DMA_MUX_ID_ETMR2_D,
|
||||
SDRV_DMA_MUX_ID_ETMR2_OVF,
|
||||
SDRV_DMA_MUX_ID_XTRG_0,
|
||||
SDRV_DMA_MUX_ID_XTRG_1,
|
||||
SDRV_DMA_MUX_ID_UART1_TX,
|
||||
SDRV_DMA_MUX_ID_UART1_RX,
|
||||
SDRV_DMA_MUX_ID_UART2_TX,
|
||||
SDRV_DMA_MUX_ID_UART2_RX,
|
||||
SDRV_DMA_MUX_ID_UART3_TX,
|
||||
SDRV_DMA_MUX_ID_UART3_RX,
|
||||
SDRV_DMA_MUX_ID_UART4_TX,
|
||||
SDRV_DMA_MUX_ID_UART4_RX,
|
||||
SDRV_DMA_MUX_ID_UART5_TX,
|
||||
SDRV_DMA_MUX_ID_UART5_RX,
|
||||
SDRV_DMA_MUX_ID_UART6_TX,
|
||||
SDRV_DMA_MUX_ID_UART6_RX,
|
||||
SDRV_DMA_MUX_ID_UART7_TX,
|
||||
SDRV_DMA_MUX_ID_UART7_RX,
|
||||
SDRV_DMA_MUX_ID_UART8_TX,
|
||||
SDRV_DMA_MUX_ID_UART8_RX,
|
||||
SDRV_DMA_MUX_ID_UART9_TX,
|
||||
SDRV_DMA_MUX_ID_UART9_RX,
|
||||
SDRV_DMA_MUX_ID_UART10_TX,
|
||||
SDRV_DMA_MUX_ID_UART10_RX,
|
||||
SDRV_DMA_MUX_ID_UART11_TX,
|
||||
SDRV_DMA_MUX_ID_UART11_RX,
|
||||
SDRV_DMA_MUX_ID_UART12_TX,
|
||||
SDRV_DMA_MUX_ID_UART12_RX,
|
||||
SDRV_DMA_MUX_ID_ADC1_0,
|
||||
SDRV_DMA_MUX_ID_ADC1_1,
|
||||
SDRV_DMA_MUX_ID_ADC2_0,
|
||||
SDRV_DMA_MUX_ID_ADC2_1,
|
||||
SDRV_DMA_MUX_ID_ADC3_0,
|
||||
SDRV_DMA_MUX_ID_ADC3_1,
|
||||
SDRV_DMA_MUX_ID_SACI2_TX,
|
||||
SDRV_DMA_MUX_ID_SACI2_RX,
|
||||
SDRV_DMA_MUX_ID_SACI2_PDM,
|
||||
SDRV_DMA_MUX_ID_ISTC,
|
||||
} sdrv_dma_sf_mux_id_e;
|
||||
|
||||
#define DMA_SF_PERIPHERALS_MUX_MAP \
|
||||
{SDRV_DMA_MUX_ID_CANFD16, APB_CANFD16_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_CANFD21, APB_CANFD21_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_CANFD3, APB_CANFD3_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_CANFD4, APB_CANFD4_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_CANFD5, APB_CANFD5_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_CANFD6, APB_CANFD6_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_CANFD7, APB_CANFD7_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_CANFD23, APB_CANFD23_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_I2C3, APB_I2C3_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_I2C4, APB_I2C4_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_I2C5, APB_I2C5_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_I2C6, APB_I2C6_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_I2C3, APB_I2C3_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_I2C4, APB_I2C4_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_I2C5, APB_I2C5_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_I2C6, APB_I2C6_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_XSPI1_A_RD, APB_XSPI1PORTA_BASE, 0x2000, \
|
||||
SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_XSPI1_A_WR, APB_XSPI1PORTA_BASE, 0x280, \
|
||||
SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_XSPI1_B_RD, APB_XSPI1PORTB_BASE, 0x2000, \
|
||||
SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_XSPI1_B_WR, APB_XSPI1PORTB_BASE, 0x280, \
|
||||
SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_SPI1_RX, APB_SPI1_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_SPI1_TX, APB_SPI1_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_SPI2_RX, APB_SPI2_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_SPI2_TX, APB_SPI2_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_SPI3_RX, APB_SPI3_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_SPI3_TX, APB_SPI3_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_SPI4_RX, APB_SPI4_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_SPI4_TX, APB_SPI4_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_SPI5_RX, APB_SPI5_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_SPI5_TX, APB_SPI5_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_SPI6_RX, APB_SPI6_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_SPI6_TX, APB_SPI6_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_EPWM1_A, APB_EPWM1_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_EPWM1_B, APB_EPWM1_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_EPWM1_C, APB_EPWM1_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_EPWM1_D, APB_EPWM1_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_EPWM1_OVF, APB_EPWM1_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_EPWM2_A, APB_EPWM2_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_EPWM2_B, APB_EPWM2_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_EPWM2_C, APB_EPWM2_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_EPWM2_D, APB_EPWM2_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_EPWM2_OVF, APB_EPWM2_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ETMR1_A, APB_ETMR1_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ETMR1_B, APB_ETMR1_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ETMR1_C, APB_ETMR1_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ETMR1_D, APB_ETMR1_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ETMR1_OVF, APB_ETMR1_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ETMR2_A, APB_ETMR2_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ETMR2_B, APB_ETMR2_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ETMR2_C, APB_ETMR2_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ETMR2_D, APB_ETMR2_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ETMR2_OVF, APB_ETMR2_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_UART1_TX, APB_UART1_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART1_RX, APB_UART1_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_UART2_TX, APB_UART2_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART2_RX, APB_UART2_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_UART3_TX, APB_UART3_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART3_RX, APB_UART3_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_UART4_TX, APB_UART4_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART4_RX, APB_UART4_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_UART5_TX, APB_UART5_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART5_RX, APB_UART5_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_UART6_TX, APB_UART6_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART6_RX, APB_UART6_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_UART7_TX, APB_UART7_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART7_RX, APB_UART7_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_UART8_TX, APB_UART8_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART8_RX, APB_UART8_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_UART9_TX, APB_UART9_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART9_RX, APB_UART9_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_UART10_TX, APB_UART10_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART10_RX, APB_UART10_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_UART11_TX, APB_UART11_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART11_RX, APB_UART11_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_UART12_TX, APB_UART12_BASE, 0x200, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_UART12_RX, APB_UART12_BASE, 0x300, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_ADC1_0, APB_ADC1_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ADC1_1, APB_ADC1_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ADC2_0, APB_ADC2_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ADC2_1, APB_ADC2_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ADC3_0, APB_ADC3_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_ADC3_1, APB_ADC3_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
|
||||
{SDRV_DMA_MUX_ID_SACI2_TX, APB_SACI2_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
|
||||
{SDRV_DMA_MUX_ID_SACI2_RX, APB_SACI2_BASE, 0x4000, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_SACI2_PDM, APB_SACI2_BASE, 0x6000, SDRV_DMA_MUX_RD}, \
|
||||
{SDRV_DMA_MUX_ID_ISTC, APB_ISTC_BASE, 0xffff, SDRV_DMA_MUX_BOTH},
|
||||
|
||||
#define SDRV_DMA_SF_MAX_CHANNEL (16) /* SF DMA channel number */
|
||||
217
devices/E3106/include/irq_num.h
Normal file
217
devices/E3106/include/irq_num.h
Normal file
@@ -0,0 +1,217 @@
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// WARNING: Automatically generated file, don't modify anymore!!!
|
||||
//
|
||||
// Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef IRQ_NUM_H
|
||||
#define IRQ_NUM_H
|
||||
|
||||
#define GPIO_SF_SYNC_DGPIO_INTR_NUM 4
|
||||
#define GPIO_SF_ASYNC_DGPIO_INTR_NUM 4
|
||||
#define GPIO_SF_SYNC_GRP_0_INTR_NUM 5
|
||||
#define GPIO_SF_ASYNC_GRP_0_INTR_NUM 5
|
||||
#define GPIO_SF_SYNC_GRP_1_INTR_NUM 6
|
||||
#define GPIO_SF_ASYNC_GRP_1_INTR_NUM 6
|
||||
#define GPIO_SF_SYNC_GRP_2_INTR_NUM 7
|
||||
#define GPIO_SF_ASYNC_GRP_2_INTR_NUM 7
|
||||
#define GPIO_SF_SYNC_GRP_3_INTR_NUM 8
|
||||
#define GPIO_SF_ASYNC_GRP_3_INTR_NUM 8
|
||||
|
||||
#define CR5_SF_NPMUIRQ0_INTR_NUM 10
|
||||
|
||||
#define SMC_SMC_WAKEUP_0_INTR_NUM 15
|
||||
#define WDT1_WDT_INTR_NUM 16
|
||||
#define WDT2_WDT_INTR_NUM 17
|
||||
|
||||
#define WDT8_WDT_INTR_NUM 20
|
||||
#define DMA_SF_DMA0_CH_0_INTR_NUM 21
|
||||
#define DMA_SF_DMA0_CH_1_INTR_NUM 22
|
||||
#define DMA_SF_DMA0_CH_2_INTR_NUM 23
|
||||
#define DMA_SF_DMA0_CH_3_INTR_NUM 24
|
||||
#define DMA_SF_DMA0_CH_4_INTR_NUM 25
|
||||
#define DMA_SF_DMA0_CH_5_INTR_NUM 26
|
||||
#define DMA_SF_DMA0_CH_6_INTR_NUM 27
|
||||
#define DMA_SF_DMA0_CH_7_INTR_NUM 28
|
||||
#define DMA_SF_DMA0_CH_8_INTR_NUM 29
|
||||
#define DMA_SF_DMA0_CH_9_INTR_NUM 30
|
||||
#define DMA_SF_DMA0_CH_10_INTR_NUM 31
|
||||
#define DMA_SF_DMA0_CH_11_INTR_NUM 32
|
||||
#define DMA_SF_DMA0_CH_12_INTR_NUM 33
|
||||
#define DMA_SF_DMA0_CH_13_INTR_NUM 34
|
||||
#define DMA_SF_DMA0_CH_14_INTR_NUM 35
|
||||
#define DMA_SF_DMA0_CH_15_INTR_NUM 36
|
||||
#define DMA_SF_DMA0_INTR_NUM 37
|
||||
#define DMA_SF_DMA1_CH_0_INTR_NUM 38
|
||||
#define DMA_SF_DMA1_CH_1_INTR_NUM 39
|
||||
#define DMA_SF_DMA1_CH_2_INTR_NUM 40
|
||||
#define DMA_SF_DMA1_CH_3_INTR_NUM 41
|
||||
#define DMA_SF_DMA1_CH_4_INTR_NUM 42
|
||||
#define DMA_SF_DMA1_CH_5_INTR_NUM 43
|
||||
#define DMA_SF_DMA1_CH_6_INTR_NUM 44
|
||||
#define DMA_SF_DMA1_CH_7_INTR_NUM 45
|
||||
#define DMA_SF_DMA1_CH_8_INTR_NUM 46
|
||||
#define DMA_SF_DMA1_CH_9_INTR_NUM 47
|
||||
#define DMA_SF_DMA1_CH_10_INTR_NUM 48
|
||||
#define DMA_SF_DMA1_CH_11_INTR_NUM 49
|
||||
#define DMA_SF_DMA1_CH_12_INTR_NUM 50
|
||||
#define DMA_SF_DMA1_CH_13_INTR_NUM 51
|
||||
#define DMA_SF_DMA1_CH_14_INTR_NUM 52
|
||||
#define DMA_SF_DMA1_CH_15_INTR_NUM 53
|
||||
#define DMA_SF_DMA1_INTR_NUM 54
|
||||
|
||||
#define SEM1_O_SEM_CPU_INTR_NUM 57
|
||||
#define SEM2_O_SEM_CPU_INTR_NUM 58
|
||||
#define UART1_INTR_NUM 59
|
||||
#define UART2_INTR_NUM 60
|
||||
#define UART3_INTR_NUM 61
|
||||
#define UART4_INTR_NUM 62
|
||||
#define UART5_INTR_NUM 63
|
||||
#define UART6_INTR_NUM 64
|
||||
#define UART7_INTR_NUM 65
|
||||
#define UART8_INTR_NUM 66
|
||||
#define UART9_INTR_NUM 67
|
||||
#define UART10_INTR_NUM 68
|
||||
#define UART11_INTR_NUM 69
|
||||
#define UART12_INTR_NUM 70
|
||||
|
||||
#define I2C1_INTR_NUM 75
|
||||
#define I2C2_INTR_NUM 76
|
||||
#define I2C3_INTR_NUM 77
|
||||
#define I2C4_INTR_NUM 78
|
||||
#define I2C5_INTR_NUM 79
|
||||
#define I2C6_INTR_NUM 80
|
||||
|
||||
#define SPI1_SPI_INTR_NUM 83
|
||||
#define SPI2_SPI_INTR_NUM 84
|
||||
#define SPI3_SPI_INTR_NUM 85
|
||||
#define SPI4_SPI_INTR_NUM 86
|
||||
#define SPI5_SPI_INTR_NUM 87
|
||||
#define SPI6_SPI_INTR_NUM 88
|
||||
|
||||
#define XSPI1_IRQ0_INTR_NUM 91
|
||||
#define XSPI1_IRQ1_INTR_NUM 92
|
||||
|
||||
#define XSPI_SLV_INTR_NUM 95
|
||||
#define SACI2_I2S_INTR_NUM 96
|
||||
#define SACI2_PDM_INTR_NUM 97
|
||||
|
||||
#define USB_INTR_NUM 100
|
||||
#define ENET1_SBD_INTR_NUM 101
|
||||
#define ENET1_SBD_PERCH_TX_O0_INTR_NUM 102
|
||||
#define ENET1_SBD_PERCH_TX_O1_INTR_NUM 102
|
||||
#define ENET1_SBD_PERCH_TX_O2_INTR_NUM 102
|
||||
#define ENET1_SBD_PERCH_TX_O3_INTR_NUM 102
|
||||
#define ENET1_SBD_PERCH_TX_O4_INTR_NUM 102
|
||||
#define ENET1_SBD_PERCH_RX_O0_INTR_NUM 102
|
||||
#define ENET1_SBD_PERCH_RX_O1_INTR_NUM 102
|
||||
#define ENET1_SBD_PERCH_RX_O2_INTR_NUM 102
|
||||
#define ENET1_SBD_PERCH_RX_O3_INTR_NUM 102
|
||||
#define ENET1_SBD_PERCH_RX_O4_INTR_NUM 102
|
||||
#define ENET1_LPI_INTR_NUM 103
|
||||
#define ENET1_PMT_INTR_NUM 103
|
||||
|
||||
#define SEHC1_SEHC_INTR_NUM 106
|
||||
#define SEHC1_SEHC_WAKEUP_INTR_NUM 107
|
||||
|
||||
#define CANFD16_CANFD_INTR_NUM 110
|
||||
#define CANFD21_CANFD_INTR_NUM 111
|
||||
#define CANFD3_CANFD_INTR_NUM 112
|
||||
#define CANFD4_CANFD_INTR_NUM 113
|
||||
#define CANFD5_CANFD_INTR_NUM 114
|
||||
#define CANFD6_CANFD_INTR_NUM 115
|
||||
#define CANFD7_CANFD_INTR_NUM 116
|
||||
#define CANFD23_CANFD_INTR_NUM 117
|
||||
|
||||
#define SEIP_PKE_INTR_NUM 120
|
||||
#define SEIP_SKE_INTR_NUM 121
|
||||
#define SEIP_HASH_INTR_NUM 122
|
||||
#define SEIP_TRNG_INTR_NUM 123
|
||||
#define SEIP_KEY_CHK_INTR_NUM 124
|
||||
#define SEIP_SOC_INTR_NUM 125
|
||||
#define SEIP_UART_INTR_NUM 126
|
||||
#define SEIP_SENSOR_INTR_NUM 127
|
||||
#define SEIP_O_INTR_SE2SOC_MBOX_INTR_NUM 128
|
||||
#define SEIP_SEIP_ERR_INTR_NUM 129
|
||||
|
||||
#define BTM1_O_BTM_INTR_NUM 131
|
||||
#define BTM2_O_BTM_INTR_NUM 132
|
||||
#define BTM3_O_BTM_INTR_NUM 133
|
||||
#define BTM4_O_BTM_INTR_NUM 134
|
||||
|
||||
#define ETMR1_CHN_A_INTR_NUM 135
|
||||
#define ETMR1_CHN_B_INTR_NUM 135
|
||||
#define ETMR1_CHN_C_INTR_NUM 135
|
||||
#define ETMR1_CHN_D_INTR_NUM 135
|
||||
#define ETMR1_CNT_OVF_INTR_NUM 136
|
||||
#define ETMR2_CHN_A_INTR_NUM 137
|
||||
#define ETMR2_CHN_B_INTR_NUM 137
|
||||
#define ETMR2_CHN_C_INTR_NUM 137
|
||||
#define ETMR2_CHN_D_INTR_NUM 137
|
||||
#define ETMR2_CNT_OVF_INTR_NUM 138
|
||||
|
||||
#define EPWM1_CHN_A_INTR_NUM 141
|
||||
#define EPWM1_CHN_B_INTR_NUM 141
|
||||
#define EPWM1_CHN_C_INTR_NUM 141
|
||||
#define EPWM1_CHN_D_INTR_NUM 141
|
||||
#define EPWM1_CNT_OVF_INTR_NUM 142
|
||||
#define EPWM2_CHN_A_INTR_NUM 143
|
||||
#define EPWM2_CHN_B_INTR_NUM 143
|
||||
#define EPWM2_CHN_C_INTR_NUM 143
|
||||
#define EPWM2_CHN_D_INTR_NUM 143
|
||||
#define EPWM2_CNT_OVF_INTR_NUM 144
|
||||
|
||||
#define XTRG_FUNC_INTR_NUM 147
|
||||
#define IOC_GPIO_SYNC_INTR_NUM 148
|
||||
#define IOC_GPIO_ASYNC_INTR_NUM 148
|
||||
#define RTC1_RTC_WAKEUP_INTR_NUM 149
|
||||
#define RTC1_RTC_PERIODICAL_INTR_NUM 150
|
||||
#define RTC1_VIOLATION_INTR_NUM 151
|
||||
#define RTC2_RTC_WAKEUP_INTR_NUM 152
|
||||
#define RTC2_RTC_PERIODICAL_INTR_NUM 153
|
||||
#define RTC2_VIOLATION_INTR_NUM 154
|
||||
#define TM_VIOLATION_INTR_NUM 155
|
||||
|
||||
#define VD_SF_DIG_O_VDC_FUNC_INTR_NUM 157
|
||||
#define PT_SNS_SF_DIG_PVT_0_INTR_NUM 158
|
||||
#define PT_SNS_SF_DIG_PVT_1_INTR_NUM 159
|
||||
#define SCR_SF_SCR_APB_PSLVERR_INTR_NUM 160
|
||||
|
||||
#define PMU_CORE_PMU_INTR_NUM 162
|
||||
#define RSTGEN_SF_RSTGEN_INTR_NUM 163
|
||||
#define U_CKGEN_SF_CKGEN_INTR_NUM 164
|
||||
|
||||
#define SMC_SMC_INTR_NUM 165
|
||||
#define SADC1_O_SADC_INTR_NUM 166
|
||||
#define SADC2_O_SADC_INTR_NUM 167
|
||||
#define SADC3_O_SADC_INTR_NUM 168
|
||||
#define ACMP1_O_ACMP_INTR_NUM 169
|
||||
#define ACMP2_O_ACMP_INTR_NUM 170
|
||||
#define ACMP3_O_ACMP_INTR_NUM 171
|
||||
#define ACMP4_O_ACMP_INTR_NUM 172
|
||||
#define DCDC1_O_DCDC_FUNC_INTR_NUM 173
|
||||
|
||||
#define FS_32K_FS_32K_INTR_NUM 175
|
||||
#define ISTC_INTR_NUM 176
|
||||
#define MPC_XSPI1A_FUNC_INTR_NUM 177
|
||||
#define MPC_XSPI1B_FUNC_INTR_NUM 177
|
||||
#define MPC_R5SF_S_FUNC_INTR_NUM 177
|
||||
#define MPC_ROMC_FUNC_INTR_NUM 177
|
||||
#define MPC_IRAMC1_FUNC_INTR_NUM 177
|
||||
#define MPC_IRAMC2_FUNC_INTR_NUM 177
|
||||
#define MPC_VIC1_FUNC_INTR_NUM 177
|
||||
#define MAC_FUNC_INTR_NUM 177
|
||||
#define PPC_APBMUX2_FUNC_INTR_NUM 177
|
||||
#define PPC_APBMUX3_FUNC_INTR_NUM 177
|
||||
#define PPC_APBMUX4_FUNC_INTR_NUM 177
|
||||
#define MPC_SEIP_FUNC_INTR_NUM 177
|
||||
#define PPC_APBMUX1_FUNC_INTR_NUM 177
|
||||
#define GPIO_SF_SGPIO_INTR_NUM 178
|
||||
#define IRQ_MAX_INTR_NUM 178
|
||||
|
||||
|
||||
#endif /* IRQ_NUM_H */
|
||||
26
devices/E3106/include/part.h
Normal file
26
devices/E3106/include/part.h
Normal file
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* part.h
|
||||
*
|
||||
* Copyright (c) 2020 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Description: E3 part device IP macro.
|
||||
*
|
||||
* Revision History:
|
||||
* -----------------
|
||||
*/
|
||||
|
||||
#ifndef SDRV_PART_H_
|
||||
#define SDRV_PART_H_
|
||||
|
||||
#define CONFIG_E3106 1
|
||||
|
||||
/*
|
||||
* Bit mask of XSPI ports that require dummy fix up, using spi_nor.id as shift. For example, to
|
||||
* use XSPI1 Port A and XSPI2 Port A, define the bitmask as (1 << 0 | 1 << 2).
|
||||
*/
|
||||
#define CONFIG_IS25LP064A_DUMMY_FIXUP (1 << 0)
|
||||
|
||||
#define CONFIG_E3L 1
|
||||
|
||||
#endif /* SDRV_PART_H_ */
|
||||
139
devices/E3106/include/pinctrl.h
Normal file
139
devices/E3106/include/pinctrl.h
Normal file
@@ -0,0 +1,139 @@
|
||||
/**
|
||||
* @file pinctrl.h
|
||||
* @brief Sdrv pinctrl device header.
|
||||
* pinctrl for E3110F4
|
||||
*
|
||||
* @copyright Copyright (c) 2022 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef PINCTRL_H_
|
||||
#define PINCTRL_H_
|
||||
|
||||
#define JTAG_TDI 0
|
||||
#define JTAG_TDO 1
|
||||
#define JTAG_TRST_N 2
|
||||
#define JTAG_TMS 3
|
||||
#define JTAG_TCK 4
|
||||
#define GPIO_X0 5
|
||||
#define GPIO_X1 6
|
||||
#define GPIO_X2 7
|
||||
#define GPIO_X3 8
|
||||
#define GPIO_X4 9
|
||||
#define GPIO_X5 10
|
||||
#define GPIO_X6 11
|
||||
#define GPIO_X7 12
|
||||
#define GPIO_X8 13
|
||||
#define GPIO_X9 14
|
||||
#define GPIO_X10 15
|
||||
#define GPIO_X11 16
|
||||
#define GPIO_Y0 17
|
||||
#define GPIO_Y1 18
|
||||
#define GPIO_Y2 19
|
||||
#define GPIO_Y3 20
|
||||
#define GPIO_Y4 21
|
||||
#define GPIO_Y5 22
|
||||
#define GPIO_Y6 23
|
||||
#define GPIO_Y7 24
|
||||
#define GPIO_Y8 25
|
||||
#define GPIO_Y9 26
|
||||
#define GPIO_Y10 27
|
||||
#define GPIO_Y11 28
|
||||
#define GPIO_A0 29
|
||||
#define GPIO_A1 30
|
||||
#define GPIO_A2 31
|
||||
#define GPIO_A3 32
|
||||
#define GPIO_A4 33
|
||||
#define GPIO_A5 34
|
||||
#define GPIO_A6 35
|
||||
#define GPIO_A7 36
|
||||
#define GPIO_A8 37
|
||||
#define GPIO_A9 38
|
||||
#define GPIO_A10 39
|
||||
#define GPIO_A11 40
|
||||
#define GPIO_A12 41
|
||||
#define GPIO_A13 42
|
||||
#define GPIO_A14 43
|
||||
#define GPIO_A15 44
|
||||
#define GPIO_B0 45
|
||||
#define GPIO_B1 46
|
||||
#define GPIO_B2 47
|
||||
#define GPIO_B3 48
|
||||
#define GPIO_B4 49
|
||||
#define GPIO_B5 50
|
||||
#define GPIO_B6 51
|
||||
#define GPIO_B7 52
|
||||
#define GPIO_B8 53
|
||||
#define GPIO_B9 54
|
||||
#define GPIO_B10 55
|
||||
#define GPIO_B11 56
|
||||
#define GPIO_B12 57
|
||||
#define GPIO_B13 58
|
||||
#define GPIO_B14 59
|
||||
#define GPIO_B15 60
|
||||
#define GPIO_C0 61
|
||||
#define GPIO_C1 62
|
||||
#define GPIO_C2 63
|
||||
#define GPIO_C3 64
|
||||
#define GPIO_C4 65
|
||||
#define GPIO_C5 66
|
||||
#define GPIO_C6 67
|
||||
#define GPIO_C7 68
|
||||
#define GPIO_G0 69
|
||||
#define GPIO_G1 70
|
||||
#define GPIO_G2 71
|
||||
#define GPIO_G3 72
|
||||
#define GPIO_G4 73
|
||||
#define GPIO_G5 74
|
||||
#define GPIO_G6 75
|
||||
#define GPIO_G7 76
|
||||
#define GPIO_G8 77
|
||||
#define GPIO_G9 78
|
||||
#define GPIO_G10 79
|
||||
#define GPIO_G11 80
|
||||
#define GPIO_S0 81
|
||||
#define GPIO_S1 82
|
||||
#define GPIO_S2 83
|
||||
#define GPIO_S3 84
|
||||
#define GPIO_S4 85
|
||||
#define GPIO_S5 86
|
||||
#define GPIO_S6 87
|
||||
#define GPIO_S7 88
|
||||
#define GPIO_H0 89
|
||||
#define GPIO_H1 90
|
||||
#define GPIO_H2 91
|
||||
#define GPIO_H3 92
|
||||
#define GPIO_H4 93
|
||||
#define GPIO_H5 94
|
||||
#define GPIO_H6 95
|
||||
#define GPIO_H7 96
|
||||
#define GPIO_H8 97
|
||||
#define GPIO_H9 98
|
||||
#define GPIO_H10 99
|
||||
#define GPIO_H11 100
|
||||
#define GPIO_H12 101
|
||||
#define GPIO_H13 102
|
||||
#define GPIO_F0 103
|
||||
#define GPIO_F1 104
|
||||
#define GPIO_F2 105
|
||||
#define GPIO_F3 106
|
||||
#define GPIO_F4 107
|
||||
#define GPIO_F5 108
|
||||
#define GPIO_L0 109
|
||||
#define GPIO_L1 110
|
||||
#define GPIO_L2 111
|
||||
#define GPIO_L3 112
|
||||
#define GPIO_L4 113
|
||||
#define GPIO_L5 114
|
||||
#define GPIO_L6 115
|
||||
#define GPIO_L7 116
|
||||
#define GPIO_L8 117
|
||||
#define GPIO_L9 118
|
||||
#define GPIO_E0 119
|
||||
#define GPIO_E1 120
|
||||
#define GPIO_E2 121
|
||||
#define GPIO_E3 122
|
||||
#define GPIO_E4 123
|
||||
#define GPIO_E5 124
|
||||
|
||||
#endif /* PINCTRL_H_ */
|
||||
477
devices/E3106/include/regs_base.h
Normal file
477
devices/E3106/include/regs_base.h
Normal file
@@ -0,0 +1,477 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// WARNING: Automatically generated file, don't modify anymore!!!
|
||||
//
|
||||
// Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef REGS_BASE_H
|
||||
#define REGS_BASE_H
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Interrupt
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* Vectored Interrupt Controller (VIC) 1 Base Address, for SF Core (cluster 0) */
|
||||
#define VIC1_BASE (0xF1C00000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Bus Inter-Connect
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* Configuration Register for FAB_AP Fabric */
|
||||
#define APB_GPV_AP_BASE (0xF0C60000ul)
|
||||
|
||||
/* Configuration Register for FAB_XB Fabric */
|
||||
#define APB_GPV_XB_BASE (0xF0B50000ul)
|
||||
|
||||
/* Configuration Register for FAB_SAFETY Fabric */
|
||||
#define APB_GPV_SF_BASE (0xF0B40000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Security
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* Secure Element Intellectual Property */
|
||||
#define APB_SEIP_BASE (0xF0C50000ul)
|
||||
|
||||
/* E-Fuse controller */
|
||||
#define APB_EFUSEC_BASE (0xF0820000ul)
|
||||
|
||||
/* Secure Storage */
|
||||
#define APB_SEC_STORAGE_BASE (0xF00A0000ul)
|
||||
|
||||
/* Tamper Monitor */
|
||||
#define APB_TM_BASE (0xF0080000ul)
|
||||
|
||||
/* SEIP Secured Key Buffer */
|
||||
#define SEIP_SEIPSECUREDKEYBUFFER_BASE (0x02200000ul)
|
||||
|
||||
/* SEIP Kbuf */
|
||||
#define APB_KBUF_BASE (0xF21DE000ul)
|
||||
|
||||
/* SEIP APB System Reg */
|
||||
#define APB_APBSYSTEMREG_BASE (0xF21DD800ul)
|
||||
|
||||
/* SEIP UART0 */
|
||||
#define APB_SEIP_UART0_BASE (0xF21DD000ul)
|
||||
|
||||
/* SEIP Mailbox */
|
||||
#define APB_SEIP_MAILBOX_BASE (0xF21D8000ul)
|
||||
|
||||
/* SEIP AHB System Reg */
|
||||
#define APB_AHBSYSTEMREG_BASE (0xF21D0000ul)
|
||||
|
||||
/* SEIP HFE */
|
||||
#define APB_SEIP_HFE_BASE (0xF21CC000ul)
|
||||
|
||||
/* SEIP HKE */
|
||||
#define APB_SEIP_SKE_BASE (0xF21C8000ul)
|
||||
|
||||
/* SEIP TRNG */
|
||||
#define APB_SEIP_TRNG_BASE (0xF21C4000ul)
|
||||
|
||||
/* SEIP PKE */
|
||||
#define APB_SEIP_PKE_BASE (0xF21C0000ul)
|
||||
|
||||
/* SDIP SRAM1 */
|
||||
#define APB_SEIP_SRAM1_BASE (0xF21A0000ul)
|
||||
|
||||
/* SEIP SRAM0 */
|
||||
#define APB_SEIP_SRAM0_BASE (0xF2180000ul)
|
||||
|
||||
/* SEIP CPU FIO */
|
||||
#define APB_SEIP_CPU_FIO_BASE (0xF2160000ul)
|
||||
|
||||
/* SEIP CPU PLIC */
|
||||
#define APB_SEIP_CPU_PLIC_BASE (0xF2150000ul)
|
||||
|
||||
/* SEIP CPU CLINT */
|
||||
#define APB_SEIP_CPU_CLINT_BASE (0xF2140000ul)
|
||||
|
||||
/* SEIP DTCM */
|
||||
#define APB_SEIP_DTCM_BASE (0xF2120000ul)
|
||||
|
||||
/* SEIP ITCM */
|
||||
#define APB_SEIP_ITCM_BASE (0xF2100000ul)
|
||||
|
||||
/* SEIP Controller */
|
||||
#define SEIP_SEIP_BASE (0x02100000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Peripherals
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* SF Domain General Porpose Intput Output (GPIO) */
|
||||
#define APB_GPIO_SF_BASE (0xF0C40000ul)
|
||||
|
||||
/* Inter-Integrated Circuit (I2C) 6 */
|
||||
#define APB_I2C6_BASE (0xF0A80000ul)
|
||||
|
||||
/* Inter-Integrated Circuit (I2C) 5 */
|
||||
#define APB_I2C5_BASE (0xF0A70000ul)
|
||||
|
||||
/* Inter-Integrated Circuit (I2C) 4 */
|
||||
#define APB_I2C4_BASE (0xF0A60000ul)
|
||||
|
||||
/* Inter-Integrated Circuit (I2C) 3 */
|
||||
#define APB_I2C3_BASE (0xF0A50000ul)
|
||||
|
||||
/* Ethernet (ENET) 1 */
|
||||
#define APB_ENET1_BASE (0xF0930000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 12 */
|
||||
#define APB_UART12_BASE (0xF06B0000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 11 */
|
||||
#define APB_UART11_BASE (0xF06A0000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 10 */
|
||||
#define APB_UART10_BASE (0xF0690000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 9 */
|
||||
#define APB_UART9_BASE (0xF0680000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 8 */
|
||||
#define APB_UART8_BASE (0xF0670000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 7 */
|
||||
#define APB_UART7_BASE (0xF0660000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 6 */
|
||||
#define APB_UART6_BASE (0xF0650000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 5 */
|
||||
#define APB_UART5_BASE (0xF0640000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 4 */
|
||||
#define APB_UART4_BASE (0xF0630000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 3 */
|
||||
#define APB_UART3_BASE (0xF0620000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 2 */
|
||||
#define APB_UART2_BASE (0xF0610000ul)
|
||||
|
||||
/* Universal Asynchronous Receiver/Transmitter (UART) 1 */
|
||||
#define APB_UART1_BASE (0xF0600000ul)
|
||||
|
||||
/* Serial Peripheral Interface (SPI) 6 */
|
||||
#define APB_SPI6_BASE (0xF05D0000ul)
|
||||
|
||||
/* Serial Peripheral Interface (SPI) 5 */
|
||||
#define APB_SPI5_BASE (0xF05C0000ul)
|
||||
|
||||
/* Serial Peripheral Interface (SPI) 4 */
|
||||
#define APB_SPI4_BASE (0xF05B0000ul)
|
||||
|
||||
/* Serial Peripheral Interface (SPI) 3 */
|
||||
#define APB_SPI3_BASE (0xF05A0000ul)
|
||||
|
||||
/* Serial Peripheral Interface (SPI) 2 */
|
||||
#define APB_SPI2_BASE (0xF0590000ul)
|
||||
|
||||
/* Serial Peripheral Interface (SPI) 1 */
|
||||
#define APB_SPI1_BASE (0xF0580000ul)
|
||||
|
||||
/* CAN with Flexible Data rate (CANFD) 8 */
|
||||
#define APB_CANFD23_BASE (0xF0570000ul)
|
||||
|
||||
/* CAN with Flexible Data rate (CANFD) 7 */
|
||||
#define APB_CANFD7_BASE (0xF0560000ul)
|
||||
|
||||
/* CAN with Flexible Data rate (CANFD) 6 */
|
||||
#define APB_CANFD6_BASE (0xF0550000ul)
|
||||
|
||||
/* CAN with Flexible Data rate (CANFD) 5 */
|
||||
#define APB_CANFD5_BASE (0xF0540000ul)
|
||||
|
||||
/* CAN with Flexible Data rate (CANFD) 4 */
|
||||
#define APB_CANFD4_BASE (0xF0530000ul)
|
||||
|
||||
/* CAN with Flexible Data rate (CANFD) 3 */
|
||||
#define APB_CANFD3_BASE (0xF0520000ul)
|
||||
|
||||
/* CAN with Flexible Data rate (CANFD) 2 */
|
||||
#define APB_CANFD21_BASE (0xF0510000ul)
|
||||
|
||||
/* CAN with Flexible Data rate (CANFD) 1 */
|
||||
#define APB_CANFD16_BASE (0xF0500000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* USB
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* USB Controller */
|
||||
#define APB_USB_BASE (0xF0C30000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Audio
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* Serial Audio Controller Interface 1 */
|
||||
#define APB_SACI2_BASE (0xF0C20000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* External Memory Interface
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* SD/EMMC Host Controller 1 */
|
||||
#define APB_SEHC1_BASE (0xF0C10000ul)
|
||||
|
||||
/* Extended SPI Slave */
|
||||
#define APB_XSPI_SLV_BASE (0xF0950000ul)
|
||||
|
||||
/* Extended SPI 1 Port B Control Registers */
|
||||
#define APB_XSPI1PORTB_BASE (0xF0780000ul)
|
||||
|
||||
/* Extended SPI 1 Port A Control Registers */
|
||||
#define APB_XSPI1PORTA_BASE (0xF0770000ul)
|
||||
|
||||
/* Extended SPI1 Port B */
|
||||
#define XSPI1_XSPI1PORTB_BASE (0x18000000ul)
|
||||
|
||||
/* Extended SPI1 */
|
||||
#define XSPI1_BASE (0x10000000ul)
|
||||
|
||||
/* Extended SPI1 Port A */
|
||||
#define XSPI1_XSPI1PORTA_BASE (0x10000000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Internal Memory Configuration
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* IRAM1 RAM Controller */
|
||||
#define APB_IRAMC1_BASE (0xF0BE0000ul)
|
||||
|
||||
/* Internal ROM Controller */
|
||||
#define APB_IROMC_BASE (0xF08A0000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* FuSa
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* System Error Management 2 */
|
||||
#define APB_SEM2_BASE (0xF0BA0000ul)
|
||||
|
||||
/* System Error Management 1 */
|
||||
#define APB_SEM1_BASE (0xF0B90000ul)
|
||||
|
||||
/* Error Injection Controller for SF Domain */
|
||||
#define APB_EIC_SF_BASE (0xF0840000ul)
|
||||
|
||||
/* Input/Output Consistency */
|
||||
#define APB_IOC_BASE (0xF0750000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* ADC & ACMP
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* Analog Digital Converter 3 */
|
||||
#define APB_ADC3_BASE (0xF0B80000ul)
|
||||
|
||||
/* Analog Digital Converter 2 */
|
||||
#define APB_ADC2_BASE (0xF0B70000ul)
|
||||
|
||||
/* Analog Digital Converter 1 */
|
||||
#define APB_ADC1_BASE (0xF0B60000ul)
|
||||
|
||||
/* Analog Compare (ACMP) 2 */
|
||||
#define APB_ACMP2_BASE (0xF0AA0000ul)
|
||||
|
||||
/* Analog Compare (ACMP) 1 */
|
||||
#define APB_ACMP1_BASE (0xF0A90000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Access Permission Control
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* Memory Access Controller */
|
||||
#define APB_MAC_BASE (0xF0B30000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Timers
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* Watch Dog(WDT) 8 */
|
||||
#define APB_WDT8_BASE (0xF0B10000ul)
|
||||
|
||||
/* Watch Dog(WDT) 1 */
|
||||
#define APB_WDT1_BASE (0xF0AD0000ul)
|
||||
|
||||
/* Targeting general purpose timer 2 */
|
||||
#define APB_ETMR2_BASE (0xF04D0000ul)
|
||||
|
||||
/* Targeting general purpose timer 1 */
|
||||
#define APB_ETMR1_BASE (0xF04C0000ul)
|
||||
|
||||
/* Energy Pulse-Width Modulator 2 */
|
||||
#define APB_EPWM2_BASE (0xF0490000ul)
|
||||
|
||||
/* Energy Pulse-Width Modulator 1 */
|
||||
#define APB_EPWM1_BASE (0xF0480000ul)
|
||||
|
||||
/* Basic Timer Module (BTM) 4 */
|
||||
#define APB_BTM4_BASE (0xF0450000ul)
|
||||
|
||||
/* Basic Timer Module (BTM) 3 */
|
||||
#define APB_BTM3_BASE (0xF0440000ul)
|
||||
|
||||
/* Basic Timer Module (BTM) 2 */
|
||||
#define APB_BTM2_BASE (0xF0430000ul)
|
||||
|
||||
/* Basic Timer Module (BTM) 1 */
|
||||
#define APB_BTM1_BASE (0xF0420000ul)
|
||||
|
||||
/* Cross Trigger */
|
||||
#define APB_XTRG_BASE (0xF0410000ul)
|
||||
|
||||
/* Real Time Clock 2 */
|
||||
#define APB_RTC2_BASE (0xF0020000ul)
|
||||
|
||||
/* Real Time Clock 1 */
|
||||
#define APB_RTC1_BASE (0xF0010000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Debug
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* CoreSight */
|
||||
#define APB_CSSYS_BASE (0xF0A00000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* DMA
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* SF Domain Direct Memory Access (DMA) 1 */
|
||||
#define APB_DMA_SF1_BASE (0xF09B0000ul)
|
||||
|
||||
/* SF Domain Direct Memory Access (DMA) 0 */
|
||||
#define APB_DMA_SF0_BASE (0xF0970000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Power Management
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* Temperature Sensor for SF Domain */
|
||||
#define APB_PT_SNS_SF_BASE (0xF0920000ul)
|
||||
|
||||
/* Voltage Detector for SF Domain */
|
||||
#define APB_VD_SF_BASE (0xF0910000ul)
|
||||
|
||||
/* Power on Reset for Safety Domain */
|
||||
#define APB_POR_SF_BASE (0xF0880000ul)
|
||||
|
||||
/* System Work Mode Controller(SMC) */
|
||||
#define APB_SMC_BASE (0xF0870000ul)
|
||||
|
||||
/* Digital controller of bulk mode DC-DC converter(DCDC) */
|
||||
#define APB_DCDC1_BASE (0xF0830000ul)
|
||||
|
||||
/* Power Management Unit */
|
||||
#define APB_PMU_CORE_BASE (0xF0060000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Clock & Reset
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* Phase Locked Loop (PLL) 3 */
|
||||
#define APB_PLL3_BASE (0xF0900000ul)
|
||||
|
||||
/* Phase Locked Loop (PLL) 2 */
|
||||
#define APB_PLL2_BASE (0xF08F0000ul)
|
||||
|
||||
/* Phase Locked Loop (PLL) 1 */
|
||||
#define APB_PLL1_BASE (0xF08E0000ul)
|
||||
|
||||
/* SF Domain Clock Generator (CKGEN) */
|
||||
#define APB_CKGEN_SF_BASE (0xF08D0000ul)
|
||||
|
||||
/* SF Domain Reset Generator (RSTGEN) */
|
||||
#define APB_RSTGEN_SF_BASE (0xF08C0000ul)
|
||||
|
||||
/* 24MHZ generation block with failsafe function(FS24M) */
|
||||
#define APB_FS_24M_BASE (0xF0890000ul)
|
||||
|
||||
/* 32KHZ generation block with failsafe function (FS32K) */
|
||||
#define APB_FS_32K_BASE (0xF0030000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* System Control
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* SF Domain Status and Controller Register (SCR) */
|
||||
#define APB_SCR_SF_BASE (0xF08B0000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* I/O Control
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* SF Domain IO Multiplexing Controller(IOMUXC) */
|
||||
#define APB_IOMUXC_SF_BASE (0xF0860000ul)
|
||||
|
||||
/* RTC Domain IO Multiplexing Controller (IOMUXC) */
|
||||
#define APB_IOMUXC_RTC_BASE (0xF0070000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* Misc
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* In System Test Controller */
|
||||
#define APB_ISTC_BASE (0xF0850000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* CPU
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* Cluster 0 D-Cache */
|
||||
#define R5_SF_CACHE_R5_SF_DCACHE_BASE (0x01978000ul)
|
||||
|
||||
/* Cluster 0 I-Cache */
|
||||
#define R5_SF_CACHE_R5_SF_ICACHE_BASE (0x01970000ul)
|
||||
|
||||
/* Cluster 0 TCM A */
|
||||
#define R5_SF_TCM_R5_SF_TCMA_BASE (0x01940000ul)
|
||||
|
||||
/* Cluster 0 TCM B */
|
||||
#define R5_SF_TCM_R5_SF_TCMB_BASE (0x01930000ul)
|
||||
|
||||
|
||||
/*------------------------------------------------------
|
||||
* IRAM
|
||||
*------------------------------------------------------*/
|
||||
|
||||
/* IRAM1 Aliased Address */
|
||||
#define IRAM1ALIASED_BASE (0x00C00000ul)
|
||||
|
||||
/* IRAM1_ECC Aliased Address */
|
||||
#define IRAM1_ECCALIASED_BASE (0x00BE0000ul)
|
||||
|
||||
/* Internal RAM 1 */
|
||||
#define IRAM1_BASE (0x00500000ul)
|
||||
|
||||
/* RAM for IRAM1 ECC. Used as internal RAM when ECC is disabled. */
|
||||
#define IRAM1_ECC_BASE (0x004E0000ul)
|
||||
|
||||
#endif /* REGS_BASE_H */
|
||||
217
devices/E3106/include/reset_ip.h
Normal file
217
devices/E3106/include/reset_ip.h
Normal file
@@ -0,0 +1,217 @@
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// WARNING: Automatically generated file, don't modify anymore!!!
|
||||
//
|
||||
// Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef RESET_IP_H
|
||||
#define RESET_IP_H
|
||||
|
||||
#include <sdrv_rstgen.h>
|
||||
|
||||
/* SAF rstgen controller */
|
||||
extern sdrv_rstgen_t g_rstgen_saf;
|
||||
|
||||
/* global reset */
|
||||
extern sdrv_rstgen_glb_t rstctl_glb;
|
||||
|
||||
/* SAF core */
|
||||
extern sdrv_rstgen_sig_t rstsig_cr5_saf;
|
||||
|
||||
/**
|
||||
* @brief reset latent
|
||||
*
|
||||
* latent signals will reset automatically after power on.
|
||||
*
|
||||
* signals in latent:
|
||||
* AHB2APB1
|
||||
* AHB2APB2
|
||||
* AHB2APB3
|
||||
* AHB2APB4
|
||||
* APBMUX2
|
||||
* APBMUX3
|
||||
* IROMC
|
||||
* IOMUXC_SF_COMP
|
||||
* MAC
|
||||
* SCR_SF
|
||||
* WDT1
|
||||
* SEM1
|
||||
* SEM2
|
||||
* VD_SF_DIG
|
||||
* IOC
|
||||
* EIC_SF
|
||||
* FUSE_LSP_CMP
|
||||
* FAB_SF
|
||||
* UART1
|
||||
* UART2
|
||||
* UART3
|
||||
* UART4
|
||||
* UART5
|
||||
* UART6
|
||||
* UART7
|
||||
* UART8
|
||||
* UART9
|
||||
* UART10
|
||||
* UART11
|
||||
* UART12
|
||||
* SPI1
|
||||
* SPI2
|
||||
* SPI3
|
||||
* SPI4
|
||||
* SPI5
|
||||
* SPI6
|
||||
* I2C1
|
||||
* I2C2
|
||||
* I2C3
|
||||
* I2C4
|
||||
* I2C5
|
||||
* I2C6
|
||||
* ETMR1
|
||||
* ETMR2
|
||||
* EPWM1
|
||||
* EPWM2
|
||||
* MPC_XSPI1A
|
||||
* MPC_XSPI1B
|
||||
* AAPB_MPC_XSPI1A
|
||||
* AAPB_MPC_XSPI1B
|
||||
* AAPB_MPC_SEIP
|
||||
* WDT8
|
||||
* PPC_APBMUX2
|
||||
* PPC_APBMUX3
|
||||
* PPC_APBMUX4
|
||||
* PPC_APBMUX1
|
||||
* MPC_ROMC
|
||||
* XB_SF
|
||||
* MPC_IRAMC1
|
||||
* MPC_CR5_SF
|
||||
* POR_SF_DIG
|
||||
* PT_SNS_SF_DIG
|
||||
* MPC_VIC1
|
||||
* BTM1
|
||||
* BTM2
|
||||
* BTM3
|
||||
* BTM4
|
||||
* AAPB_XSPI1A
|
||||
* AAPB_XSPI1B
|
||||
* MPC_SEIP
|
||||
* APB_APBMUX1_SLV
|
||||
* APB_PMUX2_DEC_SLV
|
||||
* AAPB_APBMUX3
|
||||
* APB_DCDC1_SLV
|
||||
* APB_APBMUX4_SLV
|
||||
* AAXI_APSF_MST
|
||||
*/
|
||||
extern sdrv_rstgen_sig_t rstsig_latent;
|
||||
|
||||
/*
|
||||
* @brief reset mission
|
||||
*
|
||||
* reset mission signals will reset automatically after power on.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief reset mission 0
|
||||
*
|
||||
* signals in mission 0:
|
||||
* GPIO_SF
|
||||
* IOMUXC_SF
|
||||
* SMC
|
||||
* PMU_CORE
|
||||
* APB_APBMUX1_MST
|
||||
* APB_PMUX2_DEC_MST
|
||||
* APB_SEIP_NVM_MST
|
||||
*/
|
||||
extern sdrv_rstgen_sig_t rstsig_mission0;
|
||||
|
||||
/**
|
||||
* @brief reset mission 1
|
||||
*
|
||||
* signals in mission 1:
|
||||
* PLL1
|
||||
* PLL2
|
||||
* Pll3
|
||||
*/
|
||||
extern sdrv_rstgen_sig_t rstsig_mission1;
|
||||
|
||||
/**
|
||||
* @brief reset mission 2
|
||||
*
|
||||
* signals in mission 2:
|
||||
* ANA_SF_SADC1
|
||||
* ANA_SF_SADC2
|
||||
* ANA_SF_SADC3
|
||||
* ANA_SF_SACMP1
|
||||
* ANA_SF_SACMP2
|
||||
*/
|
||||
extern sdrv_rstgen_sig_t rstsig_mission2;
|
||||
|
||||
/**
|
||||
* @brief reset mission 3
|
||||
*
|
||||
* signals in mission 3:
|
||||
* IRAM1
|
||||
*/
|
||||
extern sdrv_rstgen_sig_t rstsig_mission3;
|
||||
|
||||
/**
|
||||
* @brief reset mission 4
|
||||
*
|
||||
* signals in mission 4:
|
||||
* DCDC1
|
||||
* APB_DCDC1_MST
|
||||
*/
|
||||
extern sdrv_rstgen_sig_t rstsig_mission4;
|
||||
|
||||
/**
|
||||
* @brief reset mission 5
|
||||
*
|
||||
* signals in mission 5:
|
||||
* APBMUX4
|
||||
* PTB
|
||||
* AHBDEC_SEIP
|
||||
* APB_SEC_STORAGE1_SLV
|
||||
* APB_SEIP_NVM_SLV
|
||||
* APB_APBMUX4_MST
|
||||
* AAXI_APSF_SLV
|
||||
*/
|
||||
extern sdrv_rstgen_sig_t rstsig_mission5;
|
||||
|
||||
/* reset module */
|
||||
extern sdrv_rstgen_sig_t rstsig_canfd16;
|
||||
extern sdrv_rstgen_sig_t rstsig_canfd21;
|
||||
extern sdrv_rstgen_sig_t rstsig_canfd3;
|
||||
extern sdrv_rstgen_sig_t rstsig_canfd4;
|
||||
extern sdrv_rstgen_sig_t rstsig_canfd5;
|
||||
extern sdrv_rstgen_sig_t rstsig_canfd6;
|
||||
extern sdrv_rstgen_sig_t rstsig_canfd7;
|
||||
extern sdrv_rstgen_sig_t rstsig_canfd23;
|
||||
extern sdrv_rstgen_sig_t rstsig_xspi1a;
|
||||
extern sdrv_rstgen_sig_t rstsig_xspi1b;
|
||||
extern sdrv_rstgen_sig_t rstsig_dma_rst0;
|
||||
extern sdrv_rstgen_sig_t rstsig_dma_rst1;
|
||||
extern sdrv_rstgen_sig_t rstsig_enet1;
|
||||
extern sdrv_rstgen_sig_t rstsig_vic1;
|
||||
extern sdrv_rstgen_sig_t rstsig_xspi_slv;
|
||||
extern sdrv_rstgen_sig_t rstsig_xtrg;
|
||||
extern sdrv_rstgen_sig_t rstsig_saci2;
|
||||
extern sdrv_rstgen_sig_t rstsig_sehc1;
|
||||
extern sdrv_rstgen_sig_t rstsig_usb;
|
||||
extern sdrv_rstgen_sig_t rstsig_seip;
|
||||
extern sdrv_rstgen_sig_t rstsig_cslite;
|
||||
|
||||
/* general register */
|
||||
extern sdrv_rstgen_general_reg_t reset_general_reg_sf_remap;
|
||||
extern sdrv_rstgen_general_reg_t reset_general_reg_sf_boot;
|
||||
extern sdrv_rstgen_general_reg_t reset_general_reg_rom_ctrl;
|
||||
|
||||
/* recovery module */
|
||||
extern sdrv_recovery_btm_t recovery_btm_list;
|
||||
extern sdrv_recovery_etimer_t recovery_etimer_list;
|
||||
extern sdrv_recovery_epwm_t recovery_epwm_list;
|
||||
extern sdrv_recovery_module_t recovery_module_array;
|
||||
#endif
|
||||
384
devices/E3106/include/scr_hw.h
Normal file
384
devices/E3106/include/scr_hw.h
Normal file
@@ -0,0 +1,384 @@
|
||||
/**
|
||||
* @file scr_hw.h
|
||||
* @brief Status and Controller Register (SCR) signal header file.
|
||||
*
|
||||
* @copyright Copyright (c) 2022 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*/
|
||||
#ifndef _SCR_HW_H_
|
||||
#define _SCR_HW_H_
|
||||
|
||||
#define SCR_SF_EFUSEC_MANU_CFG_87_64 {TYPE_RO, 32, 24}
|
||||
#define SCR_SF_EFUSEC_MISC_CFG_7 {TYPE_RO, 56, 1}
|
||||
#define SCR_SF_EFUSEC_MANU_CFG_95 {TYPE_RO, 57, 1}
|
||||
#define SCR_SF_EFUSEC_FA_CFG_0 {TYPE_RO, 58, 1}
|
||||
#define SCR_SF_FAB_SF_M_F_0_I_MAINNOPENDINGTRANS {TYPE_RO, 64, 1}
|
||||
#define SCR_SF_FAB_SF_M_F_1_I_MAINNOPENDINGTRANS {TYPE_RO, 65, 1}
|
||||
#define SCR_SF_FAB_SF_M_F_2_I_MAINNOPENDINGTRANS {TYPE_RO, 66, 1}
|
||||
#define SCR_SF_FAB_SF_M_F_3_I_MAINNOPENDINGTRANS {TYPE_RO, 67, 1}
|
||||
#define SCR_SF_FAB_SF_M_F_4_I_MAINNOPENDINGTRANS {TYPE_RO, 68, 1}
|
||||
#define SCR_SF_FAB_SF_M_F_5_I_MAINNOPENDINGTRANS {TYPE_RO, 69, 1}
|
||||
#define SCR_SF_FAB_SF_M_F_6_I_MAINNOPENDINGTRANS {TYPE_RO, 70, 1}
|
||||
#define SCR_SF_FAB_SF_M_F_GPV_I_MAINNOPENDINGTRANS {TYPE_RO, 71, 1}
|
||||
#define SCR_SF_FAB_SF_S_F_0_T_MAINNOPENDINGTRANS {TYPE_RO, 72, 1}
|
||||
#define SCR_SF_FAB_SF_S_F_1_T_MAINNOPENDINGTRANS {TYPE_RO, 73, 1}
|
||||
#define SCR_SF_FAB_SF_S_F_3_I_MAINNOPENDINGTRANS {TYPE_RO, 75, 1}
|
||||
#define SCR_SF_FAB_SF_S_F_4_I_MAINNOPENDINGTRANS {TYPE_RO, 76, 1}
|
||||
#define SCR_SF_FAB_SF_S_F_5_I_MAINNOPENDINGTRANS {TYPE_RO, 77, 1}
|
||||
#define SCR_SF_FAB_SF_S_F_6_I_MAINNOPENDINGTRANS {TYPE_RO, 78, 1}
|
||||
#define SCR_SF_FAB_SF_S_F_7_I_MAINNOPENDINGTRANS {TYPE_RO, 79, 1}
|
||||
#define SCR_SF_FAB_SF_SVREG_T_MAINNOPENDINGTRANS {TYPE_RO, 80, 1}
|
||||
#define SCR_SF_FAB_SF_SVREG_MAINNOPENDINGTRANS {TYPE_RO, 81, 1}
|
||||
#define SCR_SF_FAB_AP_M_A_0_I_MAINNOPENDINGTRANS {TYPE_RO, 82, 1}
|
||||
#define SCR_SF_FAB_AP_M_A_1_I_MAINNOPENDINGTRANS {TYPE_RO, 83, 1}
|
||||
#define SCR_SF_FAB_AP_M_A_2_I_MAINNOPENDINGTRANS {TYPE_RO, 84, 1}
|
||||
#define SCR_SF_FAB_AP_M_A_3_I_MAINNOPENDINGTRANS {TYPE_RO, 85, 1}
|
||||
#define SCR_SF_FAB_AP_M_A_4_I_MAINNOPENDINGTRANS {TYPE_RO, 86, 1}
|
||||
#define SCR_SF_FAB_AP_M_A_5_I_MAINNOPENDINGTRANS {TYPE_RO, 87, 1}
|
||||
#define SCR_SF_FAB_AP_M_A_GPV_I_MAINNOPENDINGTRANS {TYPE_RO, 88, 1}
|
||||
#define SCR_SF_FAB_AP_S_A_0_T_MAINNOPENDINGTRANS {TYPE_RO, 89, 1}
|
||||
#define SCR_SF_FAB_AP_SVREG_T_MAINNOPENDINGTRANS {TYPE_RO, 90, 1}
|
||||
#define SCR_SF_FAB_AP_SVREG_MAINNOPENDINGTRANS {TYPE_RO, 91, 1}
|
||||
#define SCR_SF_EFUSEC_FUSE_READY {TYPE_RO, 96, 1}
|
||||
#define SCR_SF_EFUSEC_FUSE_LATCHED_PARTIAL {TYPE_RO, 97, 1}
|
||||
#define SCR_SF_ANA_SF_AMUX_REF_P_CSEL_OUT_3_0 {TYPE_RO, 128, 4}
|
||||
#define SCR_SF_ANA_SF_AMUX_REF_N_CSEL_OUT_3_0 {TYPE_RO, 132, 4}
|
||||
#define SCR_SF_CR5_SF_FPIXC0 {TYPE_RO, 160, 1}
|
||||
#define SCR_SF_CR5_SF_FPOFC0 {TYPE_RO, 161, 1}
|
||||
#define SCR_SF_CR5_SF_FPUFC0 {TYPE_RO, 162, 1}
|
||||
#define SCR_SF_CR5_SF_FPIOC0 {TYPE_RO, 163, 1}
|
||||
#define SCR_SF_CR5_SF_FPDZC0 {TYPE_RO, 164, 1}
|
||||
#define SCR_SF_CR5_SF_FPIDC0 {TYPE_RO, 165, 1}
|
||||
#define SCR_SF_HV_DCDC_TGO2SAF_O_BUF_0 {TYPE_RO, 192, 1}
|
||||
#define SCR_SF_HV_DCDC_TGO2SAF_O_BUF_1 {TYPE_RO, 193, 1}
|
||||
#define SCR_SF_DMA_SF_MEM_AR_CMD_FIFO0_MEM_EMA_6_0 {TYPE_RO, 224, 7}
|
||||
#define SCR_SF_DMA_SF_MEM_AW_CMD_FIFO0_MEM_EMA_6_0 {TYPE_RO, 231, 7}
|
||||
#define SCR_SF_DMA_SF_MEM_AR_CMD_FIFO1_MEM_EMA_6_0 {TYPE_RO, 238, 7}
|
||||
#define SCR_SF_DMA_SF_MEM_AW_CMD_FIFO1_MEM_EMA_6_0 {TYPE_RO, 245, 7}
|
||||
#define SCR_SF_SCR_IRAM1_ECC_DISABLE {TYPE_L16, 0, 1}
|
||||
#define SCR_SF_REMAP_CR5_SF_AW_ADDR_OFFSET_19_0 {TYPE_L31, 0, 20}
|
||||
#define SCR_SF_SCR_REMAP_CR5_SF_REMAP_EN {TYPE_L31, 20, 1}
|
||||
#define SCR_SF_REMAP_CR5_SF_AR_ADDR_OFFSET_19_0 {TYPE_L31, 0, 20}
|
||||
#define SCR_SF_REMAP_CR5_SF_AR_REMAP_EN {TYPE_L31, 20, 1}
|
||||
#define SCR_SF_SCR_CR5_SF_DBGEN0 {TYPE_L31, 21, 1}
|
||||
#define SCR_SF_SCR_CR5_SF_NIDEN0 {TYPE_L31, 22, 1}
|
||||
#define SCR_SF_XSPI1_SRC_CFG_SWAP {TYPE_L31, 32, 1}
|
||||
#define SCR_SF_XSPI1_SRC_CFG_PARALLEL_MODE {TYPE_L31, 33, 1}
|
||||
#define SCR_SF_XSPI1_LOCKSTEP_DISABLE {TYPE_L31, 34, 1}
|
||||
#define SCR_SF_DMA_SF_LOCKSTEP_DISABLE {TYPE_L31, 64, 1}
|
||||
#define SCR_SF_SEIP_KEY_SEC_STORAGE_SCR_1_0 {TYPE_L31, 96, 2}
|
||||
#define SCR_SF_REMAP_CR5_SF_AW_IRQ_EN {TYPE_RW, 0, 1}
|
||||
#define SCR_SF_REMAP_CR5_SF_AR_IRQ_EN {TYPE_RW, 1, 1}
|
||||
#define SCR_SF_REMAP_CR5_SF_AW_UNCOR_IRQ_CLR {TYPE_RW, 2, 1}
|
||||
#define SCR_SF_REMAP_CR5_SF_AR_UNCOR_IRQ_CLR {TYPE_RW, 3, 1}
|
||||
#define SCR_SF_ETMR1_LP_MODE {TYPE_RW, 32, 1}
|
||||
#define SCR_SF_ETMR2_LP_MODE {TYPE_RW, 64, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ADC1_CH5N_CSEL_3 {TYPE_RW, 96, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ADC1_CH5P_CSEL_3 {TYPE_RW, 97, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH4N_CSEL_3 {TYPE_RW, 98, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH4P_CSEL_3 {TYPE_RW, 99, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH5N_CSEL_3 {TYPE_RW, 100, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH5P_CSEL_3 {TYPE_RW, 101, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ADC2_CH6N_CSEL_3 {TYPE_RW, 102, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ADC3_CH5N_CSEL_3 {TYPE_RW, 103, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ADC3_CH5P_CSEL_3 {TYPE_RW, 104, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ACMP1_CH5N_CSEL_3 {TYPE_RW, 105, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ACMP1_CH5P_CSEL_3 {TYPE_RW, 106, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ACMP2_CH6N_CSEL_3 {TYPE_RW, 107, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ACMP2_CH6P_CSEL_3 {TYPE_RW, 108, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ACMP3_CH5N_CSEL_3 {TYPE_RW, 109, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ACMP3_CH5P_CSEL_3 {TYPE_RW, 110, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ACMP4_CH6N_CSEL_3 {TYPE_RW, 111, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_ACMP4_CH6P_CSEL_3 {TYPE_RW, 112, 1}
|
||||
#define SCR_SF_AHB2APB1_COR_IRQ_EN {TYPE_RW, 128, 1}
|
||||
#define SCR_SF_AHB2APB1_UNCOR_IRQ_EN {TYPE_RW, 129, 1}
|
||||
#define SCR_SF_AHB2APB1_COR_IRQ_CLR {TYPE_RW, 130, 1}
|
||||
#define SCR_SF_AHB2APB1_UNCOR_IRQ_CLR {TYPE_RW, 131, 1}
|
||||
#define SCR_SF_AHB2APB2_COR_IRQ_EN {TYPE_RW, 132, 1}
|
||||
#define SCR_SF_AHB2APB2_UNCOR_IRQ_EN {TYPE_RW, 133, 1}
|
||||
#define SCR_SF_AHB2APB2_COR_IRQ_CLR {TYPE_RW, 134, 1}
|
||||
#define SCR_SF_AHB2APB2_UNCOR_IRQ_CLR {TYPE_RW, 135, 1}
|
||||
#define SCR_SF_AHB2APB3_COR_IRQ_EN {TYPE_RW, 136, 1}
|
||||
#define SCR_SF_AHB2APB3_UNCOR_IRQ_EN {TYPE_RW, 137, 1}
|
||||
#define SCR_SF_AHB2APB3_COR_IRQ_CLR {TYPE_RW, 138, 1}
|
||||
#define SCR_SF_AHB2APB3_UNCOR_IRQ_CLR {TYPE_RW, 139, 1}
|
||||
#define SCR_SF_AHB2APB4_COR_IRQ_EN {TYPE_RW, 140, 1}
|
||||
#define SCR_SF_AHB2APB4_UNCOR_IRQ_EN {TYPE_RW, 141, 1}
|
||||
#define SCR_SF_AHB2APB4_COR_IRQ_CLR {TYPE_RW, 142, 1}
|
||||
#define SCR_SF_AHB2APB4_UNCOR_IRQ_CLR {TYPE_RW, 143, 1}
|
||||
#define SCR_SF_APB_APBMUX1_MST_DST_IRQ_ENB {TYPE_RW, 160, 1}
|
||||
#define SCR_SF_APB_APBMUX1_MST_DST_UNCERR_CLR {TYPE_RW, 161, 1}
|
||||
#define SCR_SF_APB_APBMUX1_SLV_SRC_IRQ_ENB {TYPE_RW, 162, 1}
|
||||
#define SCR_SF_APB_APBMUX1_SLV_SRC_UNCERR_CLR {TYPE_RW, 163, 1}
|
||||
#define SCR_SF_AAPB_MAC_SRC_IRQ_ENB {TYPE_RW, 164, 1}
|
||||
#define SCR_SF_AAPB_MAC_SRC_UNCERR_CLR {TYPE_RW, 165, 1}
|
||||
#define SCR_SF_AAPB_MAC_DST_IRQ_ENB {TYPE_RW, 166, 1}
|
||||
#define SCR_SF_AAPB_MAC_DST_UNCERR_CLR {TYPE_RW, 167, 1}
|
||||
#define SCR_SF_APB_DCDC1_MST_DST_IRQ_ENB {TYPE_RW, 172, 1}
|
||||
#define SCR_SF_APB_DCDC1_MST_DST_UNCERR_CLR {TYPE_RW, 173, 1}
|
||||
#define SCR_SF_APB_DCDC1_SLV_SRC_IRQ_ENB {TYPE_RW, 174, 1}
|
||||
#define SCR_SF_APB_DCDC1_SLV_SRC_UNCERR_CLR {TYPE_RW, 175, 1}
|
||||
#define SCR_SF_APB_SEC_STORAGE1_MST_DST_IRQ_ENB {TYPE_RW, 176, 1}
|
||||
#define SCR_SF_APB_SEC_STORAGE1_MST_DST_UNCERR_CLR {TYPE_RW, 177, 1}
|
||||
#define SCR_SF_APB_SEC_STORAGE1_SLV_SRC_IRQ_ENB {TYPE_RW, 178, 1}
|
||||
#define SCR_SF_APB_SEC_STORAGE1_SLV_SRC_UNCERR_CLR {TYPE_RW, 179, 1}
|
||||
#define SCR_SF_AAPB_XSPI1A_SRC_IRQ_ENB {TYPE_RW, 192, 1}
|
||||
#define SCR_SF_AAPB_XSPI1A_SRC_UNCERR_CLR {TYPE_RW, 193, 1}
|
||||
#define SCR_SF_AAPB_XSPI1A_DST_IRQ_ENB {TYPE_RW, 194, 1}
|
||||
#define SCR_SF_AAPB_XSPI1A_DST_UNCERR_CLR {TYPE_RW, 195, 1}
|
||||
#define SCR_SF_AAPB_XSPI1B_SRC_IRQ_ENB {TYPE_RW, 196, 1}
|
||||
#define SCR_SF_AAPB_XSPI1B_SRC_UNCERR_CLR {TYPE_RW, 197, 1}
|
||||
#define SCR_SF_AAPB_XSPI1B_DST_IRQ_ENB {TYPE_RW, 198, 1}
|
||||
#define SCR_SF_AAPB_XSPI1B_DST_UNCERR_CLR {TYPE_RW, 199, 1}
|
||||
#define SCR_SF_AAPB_MPC_SEIP_SRC_UNCERR_CLR {TYPE_RW, 209, 1}
|
||||
#define SCR_SF_AAPB_MPC_SEIP_DST_UNCERR_CLR {TYPE_RW, 211, 1}
|
||||
#define SCR_SF_APB_PMUX3_DEC_SLV_SRC_IRQ_ENB {TYPE_RW, 212, 1}
|
||||
#define SCR_SF_APB_PMUX3_DEC_SLV_SRC_UNCERR_CLR {TYPE_RW, 213, 1}
|
||||
#define SCR_SF_APB_PMUX3_DEC_MST_DST_IRQ_ENB {TYPE_RW, 214, 1}
|
||||
#define SCR_SF_APB_PMUX3_DEC_MST_DST_UNCERR_CLR {TYPE_RW, 215, 1}
|
||||
#define SCR_SF_AAPB_APBMUX3_SRC_IRQ_ENB {TYPE_RW, 216, 1}
|
||||
#define SCR_SF_AAPB_APBMUX3_SRC_UNCERR_CLR {TYPE_RW, 217, 1}
|
||||
#define SCR_SF_AAPB_APBMUX3_DST_IRQ_ENB {TYPE_RW, 218, 1}
|
||||
#define SCR_SF_AAPB_APBMUX3_DST_UNCERR_CLR {TYPE_RW, 219, 1}
|
||||
#define SCR_SF_APB_APBMUX4_SLV_SRC_IRQ_ENB {TYPE_RW, 220, 1}
|
||||
#define SCR_SF_APB_APBMUX4_SLV_SRC_UNCERR_CLR {TYPE_RW, 221, 1}
|
||||
#define SCR_SF_APB_APBMUX4_MST_DST_IRQ_ENB {TYPE_RW, 222, 1}
|
||||
#define SCR_SF_APB_APBMUX4_MST_DST_UNCERR_CLR {TYPE_RW, 223, 1}
|
||||
#define SCR_SF_MPC_XSPI1A_SRC_IRQ_ENB {TYPE_RW, 224, 1}
|
||||
#define SCR_SF_MPC_XSPI1A_SRC_UNCERR_CLR {TYPE_RW, 225, 1}
|
||||
#define SCR_SF_MPC_XSPI1A_DST_IRQ_ENB {TYPE_RW, 226, 1}
|
||||
#define SCR_SF_MPC_XSPI1A_DST_UNCERR_CLR {TYPE_RW, 227, 1}
|
||||
#define SCR_SF_MPC_XSPI1B_SRC_IRQ_ENB {TYPE_RW, 228, 1}
|
||||
#define SCR_SF_MPC_XSPI1B_SRC_UNCERR_CLR {TYPE_RW, 229, 1}
|
||||
#define SCR_SF_MPC_XSPI1B_DST_IRQ_ENB {TYPE_RW, 230, 1}
|
||||
#define SCR_SF_MPC_XSPI1B_DST_UNCERR_CLR {TYPE_RW, 231, 1}
|
||||
#define SCR_SF_MPC_CR5_SF_SRC_IRQ_ENB {TYPE_RW, 256, 1}
|
||||
#define SCR_SF_MPC_CR5_SF_SRC_UNCERR_CLR {TYPE_RW, 257, 1}
|
||||
#define SCR_SF_MPC_CR5_SF_DST_IRQ_ENB {TYPE_RW, 258, 1}
|
||||
#define SCR_SF_MPC_CR5_SF_DST_UNCERR_CLR {TYPE_RW, 259, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_VREF1_VTRIM_4_0 {TYPE_RW, 288, 5}
|
||||
#define SCR_SF_SCR_VREF1_PDREF {TYPE_RW, 293, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_VREF2_VTRIM_4_0 {TYPE_RW, 294, 5}
|
||||
#define SCR_SF_SCR_VREF2_PDREF {TYPE_RW, 299, 1}
|
||||
#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF1_D0_10_8 {TYPE_RW, 320, 3}
|
||||
#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF1_D0_7_0 {TYPE_RW, 323, 8}
|
||||
#define SCR_SF_SCR_BGR_ANA_SF1_TRIM_SEL {TYPE_RW, 331, 1}
|
||||
#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF2_D0_10_8 {TYPE_RW, 352, 3}
|
||||
#define SCR_SF_SCAN_SAFMUX_BGR_ANA_SF2_D0_7_0 {TYPE_RW, 355, 8}
|
||||
#define SCR_SF_SCR_BGR_ANA_SF2_TRIM_SEL {TYPE_RW, 363, 1}
|
||||
#define SCR_SF_SCAN_SAFMUX_BGR_SF_D0_10_8 {TYPE_RW, 384, 3}
|
||||
#define SCR_SF_SCAN_SAFMUX_BGR_SF_D0_7_0 {TYPE_RW, 387, 8}
|
||||
#define SCR_SF_BGR33_SF_SCR_BGR33_SF_TRIM_SEL {TYPE_RW, 395, 1}
|
||||
#define SCR_SF_SCR_XSPI1_PA_SS1_SCLKB_SEL {TYPE_RW, 416, 1}
|
||||
#define SCR_SF_SCR_XSPI1_PB_SS1_SCLKB_SEL {TYPE_RW, 417, 1}
|
||||
#define SCR_SF_SCR_CR5_SF_CPUHALT0 {TYPE_RW, 448, 1}
|
||||
#define SCR_SF_SCR_CR5_SF_CPUHALT1 {TYPE_RW, 449, 1}
|
||||
#define SCR_SF_CR5_SF_SCR_CR5_IRQ_CLR {TYPE_RW, 450, 1}
|
||||
#define SCR_SF_CR5_SF_SCR_CR5_VICADDR_DISABLE {TYPE_RW, 451, 1}
|
||||
#define SCR_SF_SCR_CR5_SF_DCCMINP_0 {TYPE_RW, 452, 1}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A0_CTRL_3_0 {TYPE_RW, 544, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A1_CTRL_3_0 {TYPE_RW, 548, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A2_CTRL_3_0 {TYPE_RW, 552, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A3_CTRL_3_0 {TYPE_RW, 556, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A4_CTRL_3_0 {TYPE_RW, 560, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A5_CTRL_3_0 {TYPE_RW, 564, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A6_CTRL_3_0 {TYPE_RW, 568, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A7_CTRL_3_0 {TYPE_RW, 572, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A8_CTRL_3_0 {TYPE_RW, 576, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A9_CTRL_3_0 {TYPE_RW, 580, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A10_CTRL_3_0 {TYPE_RW, 584, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A11_CTRL_3_0 {TYPE_RW, 588, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A12_CTRL_3_0 {TYPE_RW, 592, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A13_CTRL_3_0 {TYPE_RW, 596, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A14_CTRL_3_0 {TYPE_RW, 600, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_A15_CTRL_3_0 {TYPE_RW, 604, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B0_CTRL_3_0 {TYPE_RW, 608, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B1_CTRL_3_0 {TYPE_RW, 612, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B2_CTRL_3_0 {TYPE_RW, 616, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B3_CTRL_3_0 {TYPE_RW, 620, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B4_CTRL_3_0 {TYPE_RW, 624, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B5_CTRL_3_0 {TYPE_RW, 628, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B6_CTRL_3_0 {TYPE_RW, 632, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B7_CTRL_3_0 {TYPE_RW, 636, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B8_CTRL_3_0 {TYPE_RW, 640, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B9_CTRL_3_0 {TYPE_RW, 644, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B10_CTRL_3_0 {TYPE_RW, 648, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B11_CTRL_3_0 {TYPE_RW, 652, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B12_CTRL_3_0 {TYPE_RW, 656, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B13_CTRL_3_0 {TYPE_RW, 660, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B14_CTRL_3_0 {TYPE_RW, 664, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_B15_CTRL_3_0 {TYPE_RW, 668, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_C0_CTRL_3_0 {TYPE_RW, 672, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_C1_CTRL_3_0 {TYPE_RW, 676, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_C2_CTRL_3_0 {TYPE_RW, 680, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_C3_CTRL_3_0 {TYPE_RW, 684, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_C4_CTRL_3_0 {TYPE_RW, 688, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_C5_CTRL_3_0 {TYPE_RW, 692, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_C6_CTRL_3_0 {TYPE_RW, 696, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_APD_A_C7_CTRL_3_0 {TYPE_RW, 700, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_REF_P_CSEL_3_0 {TYPE_RW, 736, 4}
|
||||
#define SCR_SF_ANA_SF_CFG_AMUX_REF_N_CSEL_3_0 {TYPE_RW, 740, 4}
|
||||
#define SCR_SF_SCR_SF_DEBUG_MODE {TYPE_RW, 768, 1}
|
||||
#define SCR_SF_ENET1_SBD_FLOWCTRL_I_4_0 {TYPE_RW, 800, 5}
|
||||
#define SCR_SF_SCR_ENET1_CAP_COMP_0_OE {TYPE_RW, 805, 1}
|
||||
#define SCR_SF_SCR_ENET1_CAP_COMP_1_OE {TYPE_RW, 806, 1}
|
||||
#define SCR_SF_SCR_ENET1_CAP_COMP_2_OE {TYPE_RW, 807, 1}
|
||||
#define SCR_SF_SCR_ENET1_CAP_COMP_3_OE {TYPE_RW, 808, 1}
|
||||
#define SCR_SF_SCR_ENET1_CLK_RMII_OE {TYPE_RW, 809, 1}
|
||||
#define SCR_SF_ETMR1_CMP_A_ZO_EN {TYPE_RW, 832, 1}
|
||||
#define SCR_SF_ETMR1_CMP_B_ZO_EN {TYPE_RW, 833, 1}
|
||||
#define SCR_SF_ETMR1_CMP_C_ZO_EN {TYPE_RW, 834, 1}
|
||||
#define SCR_SF_ETMR1_CMP_D_ZO_EN {TYPE_RW, 835, 1}
|
||||
#define SCR_SF_ETMR1_CMP_A_CBC_EN {TYPE_RW, 836, 1}
|
||||
#define SCR_SF_ETMR1_CMP_B_CBC_EN {TYPE_RW, 837, 1}
|
||||
#define SCR_SF_ETMR1_CMP_C_CBC_EN {TYPE_RW, 838, 1}
|
||||
#define SCR_SF_ETMR1_CMP_D_CBC_EN {TYPE_RW, 839, 1}
|
||||
#define SCR_SF_ETMR1_CMP_A0_SW_FRC_DIS {TYPE_RW, 840, 1}
|
||||
#define SCR_SF_ETMR1_CMP_A1_SW_FRC_DIS {TYPE_RW, 841, 1}
|
||||
#define SCR_SF_ETMR1_CMP_B0_SW_FRC_DIS {TYPE_RW, 842, 1}
|
||||
#define SCR_SF_ETMR1_CMP_B1_SW_FRC_DIS {TYPE_RW, 843, 1}
|
||||
#define SCR_SF_ETMR1_CMP_C0_SW_FRC_DIS {TYPE_RW, 844, 1}
|
||||
#define SCR_SF_ETMR1_CMP_C1_SW_FRC_DIS {TYPE_RW, 845, 1}
|
||||
#define SCR_SF_ETMR1_CMP_D0_SW_FRC_DIS {TYPE_RW, 846, 1}
|
||||
#define SCR_SF_ETMR1_CMP_D1_SW_FRC_DIS {TYPE_RW, 847, 1}
|
||||
#define SCR_SF_ETMR2_CMP_A_ZO_EN {TYPE_RW, 848, 1}
|
||||
#define SCR_SF_ETMR2_CMP_B_ZO_EN {TYPE_RW, 849, 1}
|
||||
#define SCR_SF_ETMR2_CMP_C_ZO_EN {TYPE_RW, 850, 1}
|
||||
#define SCR_SF_ETMR2_CMP_D_ZO_EN {TYPE_RW, 851, 1}
|
||||
#define SCR_SF_ETMR2_CMP_A_CBC_EN {TYPE_RW, 852, 1}
|
||||
#define SCR_SF_ETMR2_CMP_B_CBC_EN {TYPE_RW, 853, 1}
|
||||
#define SCR_SF_ETMR2_CMP_C_CBC_EN {TYPE_RW, 854, 1}
|
||||
#define SCR_SF_ETMR2_CMP_D_CBC_EN {TYPE_RW, 855, 1}
|
||||
#define SCR_SF_ETMR2_CMP_A0_SW_FRC_DIS {TYPE_RW, 856, 1}
|
||||
#define SCR_SF_ETMR2_CMP_A1_SW_FRC_DIS {TYPE_RW, 857, 1}
|
||||
#define SCR_SF_ETMR2_CMP_B0_SW_FRC_DIS {TYPE_RW, 858, 1}
|
||||
#define SCR_SF_ETMR2_CMP_B1_SW_FRC_DIS {TYPE_RW, 859, 1}
|
||||
#define SCR_SF_ETMR2_CMP_C0_SW_FRC_DIS {TYPE_RW, 860, 1}
|
||||
#define SCR_SF_ETMR2_CMP_C1_SW_FRC_DIS {TYPE_RW, 861, 1}
|
||||
#define SCR_SF_ETMR2_CMP_D0_SW_FRC_DIS {TYPE_RW, 862, 1}
|
||||
#define SCR_SF_ETMR2_CMP_D1_SW_FRC_DIS {TYPE_RW, 863, 1}
|
||||
#define SCR_SF_EPWM1_CMP_A_ZO_EN {TYPE_RW, 864, 1}
|
||||
#define SCR_SF_EPWM1_CMP_B_ZO_EN {TYPE_RW, 865, 1}
|
||||
#define SCR_SF_EPWM1_CMP_C_ZO_EN {TYPE_RW, 866, 1}
|
||||
#define SCR_SF_EPWM1_CMP_D_ZO_EN {TYPE_RW, 867, 1}
|
||||
#define SCR_SF_EPWM1_CMP_A_CBC_EN {TYPE_RW, 868, 1}
|
||||
#define SCR_SF_EPWM1_CMP_B_CBC_EN {TYPE_RW, 869, 1}
|
||||
#define SCR_SF_EPWM1_CMP_C_CBC_EN {TYPE_RW, 870, 1}
|
||||
#define SCR_SF_EPWM1_CMP_D_CBC_EN {TYPE_RW, 871, 1}
|
||||
#define SCR_SF_EPWM1_CMP_A0_SW_FRC_DIS {TYPE_RW, 872, 1}
|
||||
#define SCR_SF_EPWM1_CMP_A1_SW_FRC_DIS {TYPE_RW, 873, 1}
|
||||
#define SCR_SF_EPWM1_CMP_B0_SW_FRC_DIS {TYPE_RW, 874, 1}
|
||||
#define SCR_SF_EPWM1_CMP_B1_SW_FRC_DIS {TYPE_RW, 875, 1}
|
||||
#define SCR_SF_EPWM1_CMP_C0_SW_FRC_DIS {TYPE_RW, 876, 1}
|
||||
#define SCR_SF_EPWM1_CMP_C1_SW_FRC_DIS {TYPE_RW, 877, 1}
|
||||
#define SCR_SF_EPWM1_CMP_D0_SW_FRC_DIS {TYPE_RW, 878, 1}
|
||||
#define SCR_SF_EPWM1_CMP_D1_SW_FRC_DIS {TYPE_RW, 879, 1}
|
||||
#define SCR_SF_EPWM2_CMP_A_ZO_EN {TYPE_RW, 880, 1}
|
||||
#define SCR_SF_EPWM2_CMP_B_ZO_EN {TYPE_RW, 881, 1}
|
||||
#define SCR_SF_EPWM2_CMP_C_ZO_EN {TYPE_RW, 882, 1}
|
||||
#define SCR_SF_EPWM2_CMP_D_ZO_EN {TYPE_RW, 883, 1}
|
||||
#define SCR_SF_EPWM2_CMP_A_CBC_EN {TYPE_RW, 884, 1}
|
||||
#define SCR_SF_EPWM2_CMP_B_CBC_EN {TYPE_RW, 885, 1}
|
||||
#define SCR_SF_EPWM2_CMP_C_CBC_EN {TYPE_RW, 886, 1}
|
||||
#define SCR_SF_EPWM2_CMP_D_CBC_EN {TYPE_RW, 887, 1}
|
||||
#define SCR_SF_EPWM2_CMP_A0_SW_FRC_DIS {TYPE_RW, 888, 1}
|
||||
#define SCR_SF_EPWM2_CMP_A1_SW_FRC_DIS {TYPE_RW, 889, 1}
|
||||
#define SCR_SF_EPWM2_CMP_B0_SW_FRC_DIS {TYPE_RW, 890, 1}
|
||||
#define SCR_SF_EPWM2_CMP_B1_SW_FRC_DIS {TYPE_RW, 891, 1}
|
||||
#define SCR_SF_EPWM2_CMP_C0_SW_FRC_DIS {TYPE_RW, 892, 1}
|
||||
#define SCR_SF_EPWM2_CMP_C1_SW_FRC_DIS {TYPE_RW, 893, 1}
|
||||
#define SCR_SF_EPWM2_CMP_D0_SW_FRC_DIS {TYPE_RW, 894, 1}
|
||||
#define SCR_SF_EPWM2_CMP_D1_SW_FRC_DIS {TYPE_RW, 895, 1}
|
||||
#define SCR_SF_ETMR1_MUX_CPT_EN {TYPE_RW, 896, 1}
|
||||
#define SCR_SF_ETMR2_MUX_CPT_EN {TYPE_RW, 897, 1}
|
||||
#define SCR_SF_SCR_SF_EMA_UPD {TYPE_RW, 1088, 1}
|
||||
#define SCR_SF_SCR_AP_EMA_UPD {TYPE_RW, 1120, 1}
|
||||
#define SCR_SF_AAPB_PLL1_SRC_IRQ_ENB {TYPE_RW, 1152, 1}
|
||||
#define SCR_SF_AAPB_PLL1_SRC_UNCERR_CLR {TYPE_RW, 1153, 1}
|
||||
#define SCR_SF_AAPB_PLL1_DST_IRQ_ENB {TYPE_RW, 1154, 1}
|
||||
#define SCR_SF_AAPB_PLL1_DST_UNCERR_CLR {TYPE_RW, 1155, 1}
|
||||
#define SCR_SF_AAPB_PLL2_SRC_IRQ_ENB {TYPE_RW, 1156, 1}
|
||||
#define SCR_SF_AAPB_PLL2_SRC_UNCERR_CLR {TYPE_RW, 1157, 1}
|
||||
#define SCR_SF_AAPB_PLL2_DST_IRQ_ENB {TYPE_RW, 1158, 1}
|
||||
#define SCR_SF_AAPB_PLL2_DST_UNCERR_CLR {TYPE_RW, 1159, 1}
|
||||
#define SCR_SF_AAPB_PLL3_SRC_IRQ_ENB {TYPE_RW, 1160, 1}
|
||||
#define SCR_SF_AAPB_PLL3_SRC_UNCERR_CLR {TYPE_RW, 1161, 1}
|
||||
#define SCR_SF_AAPB_PLL3_DST_IRQ_ENB {TYPE_RW, 1162, 1}
|
||||
#define SCR_SF_AAPB_PLL3_DST_UNCERR_CLR {TYPE_RW, 1163, 1}
|
||||
#define SCR_SF_USB_I_USB2_WAKE_USER {TYPE_RW, 1184, 1}
|
||||
#define SCR_SF_IROMC_LP_MEM_STICKY_STICKY_SET {TYPE_RW, 1216, 1}
|
||||
#define SCR_SF_MEMCTRL_OVRD_EN {TYPE_RW, 1280, 1}
|
||||
#define SCR_SF_URFSPHD_EMA_2_0 {TYPE_RW, 1312, 3}
|
||||
#define SCR_SF_URFSPHD_EMAW_1_0 {TYPE_RW, 1315, 2}
|
||||
#define SCR_SF_URFSPHD_EMAS {TYPE_RW, 1317, 1}
|
||||
#define SCR_SF_URFSPHD_WABL {TYPE_RW, 1318, 1}
|
||||
#define SCR_SF_URFSPHD_WABLM_1_0 {TYPE_RW, 1319, 2}
|
||||
#define SCR_SF_URFSPHD_RAWL {TYPE_RW, 1321, 1}
|
||||
#define SCR_SF_URFSPHD_RAWLM_1_0 {TYPE_RW, 1322, 2}
|
||||
#define SCR_SF_GSRSPUHD_EMA_2_0 {TYPE_RW, 1324, 3}
|
||||
#define SCR_SF_GSRSPUHD_EMAW_1_0 {TYPE_RW, 1327, 2}
|
||||
#define SCR_SF_GSRSPUHD_EMAS {TYPE_RW, 1329, 1}
|
||||
#define SCR_SF_GSRSPUHD_WABL {TYPE_RW, 1330, 1}
|
||||
#define SCR_SF_GSRSPUHD_WABLM_1_0 {TYPE_RW, 1331, 2}
|
||||
#define SCR_SF_GSRSPUHD_RAWL {TYPE_RW, 1333, 1}
|
||||
#define SCR_SF_GSRSPUHD_RAWLM_1_0 {TYPE_RW, 1334, 2}
|
||||
#define SCR_SF_GSRSPHD_EMA_2_0 {TYPE_RW, 1336, 3}
|
||||
#define SCR_SF_GSRSPHD_EMAW_1_0 {TYPE_RW, 1339, 2}
|
||||
#define SCR_SF_GSRSPHD_EMAS {TYPE_RW, 1341, 1}
|
||||
#define SCR_SF_GSRSPHD_WABL {TYPE_RW, 1342, 1}
|
||||
#define SCR_SF_GSRSPHD_WABLM_0 {TYPE_RW, 1343, 1}
|
||||
#define SCR_SF_GSRSPHD_WABLM_1 {TYPE_RW, 1344, 1}
|
||||
#define SCR_SF_GSRSPHD_RAWL {TYPE_RW, 1345, 1}
|
||||
#define SCR_SF_GSRSPHD_RAWLM_1_0 {TYPE_RW, 1346, 2}
|
||||
#define SCR_SF_USRSPHD_EMA_2_0 {TYPE_RW, 1348, 3}
|
||||
#define SCR_SF_USRSPHD_EMAW_1_0 {TYPE_RW, 1351, 2}
|
||||
#define SCR_SF_USRSPHD_EMAS {TYPE_RW, 1353, 1}
|
||||
#define SCR_SF_USRSPHD_WABL {TYPE_RW, 1354, 1}
|
||||
#define SCR_SF_USRSPHD_WABLM_2_0 {TYPE_RW, 1355, 3}
|
||||
#define SCR_SF_USRSPHD_RAWL {TYPE_RW, 1358, 1}
|
||||
#define SCR_SF_USRSPHD_RAWLM_1_0 {TYPE_RW, 1359, 2}
|
||||
#define SCR_SF_GRFSPHD_EMA_2_0 {TYPE_RW, 1361, 3}
|
||||
#define SCR_SF_GRFSPHD_EMAW_1_0 {TYPE_RW, 1364, 2}
|
||||
#define SCR_SF_GRFSPHD_EMAS {TYPE_RW, 1366, 1}
|
||||
#define SCR_SF_GRFSPHD_WABL {TYPE_RW, 1367, 1}
|
||||
#define SCR_SF_GRFSPHD_WABLM_1_0 {TYPE_RW, 1368, 2}
|
||||
#define SCR_SF_GRFSPHD_RAWL {TYPE_RW, 1370, 1}
|
||||
#define SCR_SF_GRFSPHD_RAWLM_1_0 {TYPE_RW, 1371, 2}
|
||||
#define SCR_SF_GRF2PHD_EMAA_2_0 {TYPE_RW, 1373, 3}
|
||||
#define SCR_SF_GRF2PHD_EMAB_2_0 {TYPE_RW, 1376, 3}
|
||||
#define SCR_SF_GRF2PHD_EMASA {TYPE_RW, 1379, 1}
|
||||
#define SCR_SF_ROM_EMA_2_0 {TYPE_RW, 1380, 3}
|
||||
#define SCR_SF_ROM_KEN {TYPE_RW, 1383, 1}
|
||||
#define SCR_SF_BTI_SF_M0_TIMEOUT_DIV_7_0 {TYPE_R16W16, 0, 8}
|
||||
#define SCR_SF_BTI_SF_M0_BTI_EN {TYPE_R16W16, 8, 1}
|
||||
#define SCR_SF_BTI_SF_M0_UNCOR_IRQ_EN {TYPE_R16W16, 9, 1}
|
||||
#define SCR_SF_BTI_SF_M0_UNCOR_IRQ_CLR {TYPE_R16W16, 10, 1}
|
||||
#define SCR_SF_BTI_SF_P0_TIMEOUT_DIV_7_0 {TYPE_R16W16, 32, 8}
|
||||
#define SCR_SF_BTI_SF_P0_BTI_EN {TYPE_R16W16, 40, 1}
|
||||
#define SCR_SF_BTI_SF_P0_UNCOR_IRQ_EN {TYPE_R16W16, 41, 1}
|
||||
#define SCR_SF_BTI_SF_P0_UNCOR_IRQ_CLR {TYPE_R16W16, 42, 1}
|
||||
#define SCR_SF_BTI_SF_AHB_TIMEOUT_DIV_7_0 {TYPE_R16W16, 64, 8}
|
||||
#define SCR_SF_BTI_SF_AHB_BTI_EN {TYPE_R16W16, 72, 1}
|
||||
#define SCR_SF_BTI_SF_AHB_UNCOR_IRQ_EN {TYPE_R16W16, 73, 1}
|
||||
#define SCR_SF_BTI_SF_AHB_UNCOR_IRQ_CLR {TYPE_R16W16, 74, 1}
|
||||
#define SCR_SF_CANFD16_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 480, 4}
|
||||
#define SCR_SF_CANFD16_STOP_DOZE_SEL {TYPE_R16W16, 484, 1}
|
||||
#define SCR_SF_CANFD21_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 512, 4}
|
||||
#define SCR_SF_CANFD21_STOP_DOZE_SEL {TYPE_R16W16, 516, 1}
|
||||
#define SCR_SF_CANFD3_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 544, 4}
|
||||
#define SCR_SF_CANFD3_STOP_DOZE_SEL {TYPE_R16W16, 548, 1}
|
||||
#define SCR_SF_CANFD4_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 549, 4}
|
||||
#define SCR_SF_CANFD4_STOP_DOZE_SEL {TYPE_R16W16, 553, 1}
|
||||
#define SCR_SF_CANFD5_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 576, 4}
|
||||
#define SCR_SF_CANFD5_STOP_DOZE_SEL {TYPE_R16W16, 580, 1}
|
||||
#define SCR_SF_CANFD6_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 581, 4}
|
||||
#define SCR_SF_CANFD6_STOP_DOZE_SEL {TYPE_R16W16, 585, 1}
|
||||
#define SCR_SF_CANFD7_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 608, 4}
|
||||
#define SCR_SF_CANFD7_STOP_DOZE_SEL {TYPE_R16W16, 612, 1}
|
||||
#define SCR_SF_CANFD23_CANFD_DEBOUNCE_TIME_3_0 {TYPE_R16W16, 613, 4}
|
||||
#define SCR_SF_CANFD23_STOP_DOZE_SEL {TYPE_R16W16, 617, 1}
|
||||
#define SCR_SF_BTI_SF_M0_CHN_IDLE {TYPE_R16W16, 16, 1}
|
||||
#define SCR_SF_BTI_SF_P0_CHN_IDLE {TYPE_R16W16, 48, 1}
|
||||
#define SCR_SF_BTI_SF_AHB_CHN_IDLE {TYPE_R16W16, 80, 1}
|
||||
|
||||
#endif /*_SCR_HW_H_*/
|
||||
161
devices/E3106/linker/gcc/bootloader.ld
Normal file
161
devices/E3106/linker/gcc/bootloader.ld
Normal file
@@ -0,0 +1,161 @@
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
|
||||
CSTACK_SIZE = 0x1000;
|
||||
SVC_STACK_SIZE = 0x1000;
|
||||
IRQ_STACK_SIZE = 0x80;
|
||||
FIQ_STACK_SIZE = 0x1000;
|
||||
UND_STACK_SIZE = 0x80;
|
||||
ABT_STACK_SIZE = 0x80;
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
TCM (RW) : ORIGIN = 0x01900000, LENGTH = 0x00020000
|
||||
RAM (RW) : ORIGIN = 0x00504000, LENGTH = 0x0007C000
|
||||
RAMECC (RW) : ORIGIN = 0x004E0000, LENGTH = 0x00020000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* text/read-only data */
|
||||
.text : {
|
||||
KEEP(*(.intvec))
|
||||
*(.text* .sram.text.glue_7* .gnu.linkonce.t.*)
|
||||
} > RAM
|
||||
|
||||
.dummy_post_text : {
|
||||
__code_end = .;
|
||||
} > RAM
|
||||
|
||||
.rodata : ALIGN(4) {
|
||||
__rodata_start = .;
|
||||
__fault_handler_table_start = .;
|
||||
KEEP(*(.rodata.fault_handler_table))
|
||||
__fault_handler_table_end = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
} > RAM
|
||||
|
||||
/*
|
||||
* extra linker scripts tend to insert sections just after .rodata,
|
||||
* so we want to make sure this symbol comes after anything inserted above,
|
||||
* but not aligned to the next section necessarily.
|
||||
*/
|
||||
.dummy_post_rodata : {
|
||||
__rodata_end = .;
|
||||
} > RAM
|
||||
|
||||
.data : ALIGN(4) {
|
||||
__data_start = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
__commands_start = .;
|
||||
KEEP (*(.commands))
|
||||
__commands_end = .;
|
||||
} > RAM
|
||||
|
||||
.ctors : ALIGN(4) {
|
||||
__ctor_list = .;
|
||||
KEEP(*(.ctors .init_array))
|
||||
__ctor_end = .;
|
||||
} > RAM
|
||||
.dtors : ALIGN(4) {
|
||||
__dtor_list = .;
|
||||
KEEP(*(.dtors .fini_array))
|
||||
__dtor_end = .;
|
||||
} > RAM
|
||||
.got : { *(.got.plt) *(.got) } > RAM
|
||||
.dynamic : { *(.dynamic) } > RAM
|
||||
|
||||
/* List sections that have differet load address and link address,
|
||||
* requiring early section copy on start up.
|
||||
*/
|
||||
.earlycopy : ALIGN(4) {
|
||||
__earlycopy_start = .;
|
||||
|
||||
/* TCM code and data section. */
|
||||
LONG(ADDR(.tcm))
|
||||
LONG(SIZEOF(.tcm))
|
||||
LONG(LOADADDR(.tcm))
|
||||
|
||||
/* Add other sections here. */
|
||||
|
||||
__earlycopy_end = .;
|
||||
} > RAM
|
||||
|
||||
.nocache : ALIGN(1024) {
|
||||
_nocacheable_start = .;
|
||||
KEEP(*(.nocache))
|
||||
. = ALIGN(1024);
|
||||
_nocacheable_end = .;
|
||||
} > RAM
|
||||
|
||||
.dummy_post_data : {
|
||||
/* End of initialized sections. */
|
||||
__data_end = ALIGN(4);
|
||||
} > RAM
|
||||
|
||||
/* uninitialized data (in same segment as writable data) */
|
||||
.bss (NOLOAD) : ALIGN(4) {
|
||||
KEEP(*(.bss.prebss.*))
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} > RAM
|
||||
|
||||
/* exception stack */
|
||||
.except.stack (NOLOAD) : ALIGN(8) {
|
||||
__except_stack_start = .;
|
||||
. += CSTACK_SIZE;
|
||||
__cstack_end = .;
|
||||
. += SVC_STACK_SIZE;
|
||||
__svc_stack_end = .;
|
||||
. += IRQ_STACK_SIZE;
|
||||
__irq_stack_end = .;
|
||||
. += FIQ_STACK_SIZE;
|
||||
__fiq_stack_end = .;
|
||||
. += UND_STACK_SIZE;
|
||||
__und_stack_end = .;
|
||||
. += ABT_STACK_SIZE;
|
||||
__abt_stack_end = .;
|
||||
__except_stack_end = .;
|
||||
} > RAM
|
||||
|
||||
_end = .;
|
||||
|
||||
.heap (NOLOAD) : ALIGN(8) {
|
||||
_heap_start = .;
|
||||
*(.heap)
|
||||
} > RAM
|
||||
|
||||
_end_of_ram = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
_heap_end = _end_of_ram;
|
||||
|
||||
/* IRAM none-ecc data sections. */
|
||||
.noneecc (NOLOAD) : ALIGN(4) {
|
||||
_noneecc_start = .;
|
||||
*(.noneeccdata)
|
||||
_noneecc_end = ORIGIN(RAMECC) + LENGTH(RAMECC);
|
||||
} > RAMECC
|
||||
|
||||
/* TCM code and data sections. */
|
||||
.tcm : AT (__data_end) {
|
||||
__tcm_start = .;
|
||||
*(.tcmcode)
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.tcmdata)
|
||||
|
||||
__tcm_end = ALIGN(4);
|
||||
ASSERT(__tcm_end - __tcm_start <= LENGTH(TCM), "TCM overflow!");
|
||||
} > TCM
|
||||
|
||||
/* Strip unnecessary stuff */
|
||||
/DISCARD/ : { *(.comment .note) }
|
||||
}
|
||||
|
||||
166
devices/E3106/linker/gcc/flashloader.ld
Normal file
166
devices/E3106/linker/gcc/flashloader.ld
Normal file
@@ -0,0 +1,166 @@
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
|
||||
CSTACK_SIZE = 0x1000;
|
||||
SVC_STACK_SIZE = 0x1000;
|
||||
IRQ_STACK_SIZE = 0x80;
|
||||
FIQ_STACK_SIZE = 0x1000;
|
||||
UND_STACK_SIZE = 0x80;
|
||||
ABT_STACK_SIZE = 0x80;
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
TCM (RW) : ORIGIN = 0x004E0000, LENGTH = 0x00020000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* PrgCode */
|
||||
PrgCode : {
|
||||
_PRGCODE_start = .;
|
||||
KEEP(*(.PRGCODE .PRGCODE.*))
|
||||
_PRGCODE_end = .;
|
||||
} > TCM
|
||||
|
||||
/* T32CodeBegin */
|
||||
T32CodeBegin : {
|
||||
_T32CODEBEGIN_start = .;
|
||||
KEEP(*(.T32CODEBEGIN .T32CODEBEGIN.*))
|
||||
_T32CODEBEGIN_end = .;
|
||||
} > TCM
|
||||
|
||||
/* FuseCode */
|
||||
FuseCode : {
|
||||
_FUSECODE_start = .;
|
||||
KEEP(*(.FUSECODE .FUSECODE.*))
|
||||
_FUSECODE_end = .;
|
||||
} > TCM
|
||||
|
||||
/* PrgData */
|
||||
PrgData : {
|
||||
_PRGDATA_start = .;
|
||||
KEEP(*(.PRGDATA .PRGDATA.*))
|
||||
_PRGDATA_end = .;
|
||||
} > TCM
|
||||
|
||||
/* DevDscr */
|
||||
DevDscr : {
|
||||
_DEVDSCR_start = .;
|
||||
KEEP(*(.DEVDSCR .DEVDSCR.*))
|
||||
_DEVDSCR_end = .;
|
||||
} > TCM
|
||||
|
||||
/* text/read-only data */
|
||||
.text : {
|
||||
*(.text* .sram.text.glue_7* .gnu.linkonce.t.*)
|
||||
} > TCM
|
||||
|
||||
.dummy_post_text : {
|
||||
__code_end = .;
|
||||
} > TCM
|
||||
|
||||
.rodata : ALIGN(4) {
|
||||
__rodata_start = .;
|
||||
__fault_handler_table_start = .;
|
||||
KEEP(*(.rodata.fault_handler_table))
|
||||
__fault_handler_table_end = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
} > TCM
|
||||
|
||||
/*
|
||||
* extra linker scripts tend to insert sections just after .rodata,
|
||||
* so we want to make sure this symbol comes after anything inserted above,
|
||||
* but not aligned to the next section necessarily.
|
||||
*/
|
||||
.dummy_post_rodata : {
|
||||
__rodata_end = .;
|
||||
} > TCM
|
||||
|
||||
.data : ALIGN(4) {
|
||||
__data_start = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
__commands_start = .;
|
||||
KEEP (*(.commands))
|
||||
__commands_end = .;
|
||||
} > TCM
|
||||
|
||||
.ctors : ALIGN(4) {
|
||||
__ctor_list = .;
|
||||
KEEP(*(.ctors .init_array))
|
||||
__ctor_end = .;
|
||||
} > TCM
|
||||
.dtors : ALIGN(4) {
|
||||
__dtor_list = .;
|
||||
KEEP(*(.dtors .fini_array))
|
||||
__dtor_end = .;
|
||||
} > TCM
|
||||
|
||||
.nocache : ALIGN(1024) {
|
||||
_nocacheable_start = .;
|
||||
KEEP(*(.nocache))
|
||||
. = ALIGN(1024);
|
||||
_nocacheable_end = .;
|
||||
} > TCM
|
||||
|
||||
.dummy_post_data : {
|
||||
/* End of initialized sections. */
|
||||
__data_end = ALIGN(4);
|
||||
} > TCM
|
||||
|
||||
/* uninitialized data (in same segment as writable data) */
|
||||
.bss (NOLOAD) : ALIGN(4) {
|
||||
KEEP(*(.bss.prebss.*))
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} > TCM
|
||||
|
||||
_end = .;
|
||||
|
||||
.heap (NOLOAD) : ALIGN(8) {
|
||||
_heap_start = .;
|
||||
. += 0x1000;
|
||||
_heap_end = .;
|
||||
} > TCM
|
||||
|
||||
.except.stack (NOLOAD) : ALIGN(8) {
|
||||
__except_stack_start = .;
|
||||
. += CSTACK_SIZE;
|
||||
__cstack_end = .;
|
||||
. += SVC_STACK_SIZE;
|
||||
__svc_stack_end = .;
|
||||
. += IRQ_STACK_SIZE;
|
||||
__irq_stack_end = .;
|
||||
. += FIQ_STACK_SIZE;
|
||||
__fiq_stack_end = .;
|
||||
. += UND_STACK_SIZE;
|
||||
__und_stack_end = .;
|
||||
. += ABT_STACK_SIZE;
|
||||
__abt_stack_end = .;
|
||||
__except_stack_end = .;
|
||||
} > TCM
|
||||
|
||||
/* flashbuf */
|
||||
.flashbuf (NOLOAD) : ALIGN(4) {
|
||||
_flashbuf_start = .;
|
||||
. += 0x1000;
|
||||
_flashbuf_end = .;
|
||||
} > TCM
|
||||
|
||||
/* T32CodeEnd */
|
||||
T32CodeEnd : {
|
||||
_T32CODEEND_start = .;
|
||||
KEEP(*(.T32CODEEND .T32CODEEND.*))
|
||||
_T32CODEEND_end = .;
|
||||
} > TCM
|
||||
|
||||
/* Strip unnecessary stuff */
|
||||
/DISCARD/ : { *(.comment .note) }
|
||||
}
|
||||
|
||||
161
devices/E3106/linker/gcc/ram.ld
Normal file
161
devices/E3106/linker/gcc/ram.ld
Normal file
@@ -0,0 +1,161 @@
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
|
||||
CSTACK_SIZE = 0x1000;
|
||||
SVC_STACK_SIZE = 0x1000;
|
||||
IRQ_STACK_SIZE = 0x80;
|
||||
FIQ_STACK_SIZE = 0x1000;
|
||||
UND_STACK_SIZE = 0x80;
|
||||
ABT_STACK_SIZE = 0x80;
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
TCM (RW) : ORIGIN = 0x00000040, LENGTH = 0x0001FFC0
|
||||
RAM (RW) : ORIGIN = 0x00504000, LENGTH = 0x0007C000
|
||||
RAMECC (RW) : ORIGIN = 0x004E0000, LENGTH = 0x00020000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* text/read-only data */
|
||||
.text : {
|
||||
KEEP(*(.intvec))
|
||||
*(.text* .sram.text.glue_7* .gnu.linkonce.t.*)
|
||||
} > RAM
|
||||
|
||||
.dummy_post_text : {
|
||||
__code_end = .;
|
||||
} > RAM
|
||||
|
||||
.rodata : ALIGN(4) {
|
||||
__rodata_start = .;
|
||||
__fault_handler_table_start = .;
|
||||
KEEP(*(.rodata.fault_handler_table))
|
||||
__fault_handler_table_end = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
} > RAM
|
||||
|
||||
/*
|
||||
* extra linker scripts tend to insert sections just after .rodata,
|
||||
* so we want to make sure this symbol comes after anything inserted above,
|
||||
* but not aligned to the next section necessarily.
|
||||
*/
|
||||
.dummy_post_rodata : {
|
||||
__rodata_end = .;
|
||||
} > RAM
|
||||
|
||||
.data : ALIGN(4) {
|
||||
__data_start = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
__commands_start = .;
|
||||
KEEP (*(.commands))
|
||||
__commands_end = .;
|
||||
} > RAM
|
||||
|
||||
.ctors : ALIGN(4) {
|
||||
__ctor_list = .;
|
||||
KEEP(*(.ctors .init_array))
|
||||
__ctor_end = .;
|
||||
} > RAM
|
||||
.dtors : ALIGN(4) {
|
||||
__dtor_list = .;
|
||||
KEEP(*(.dtors .fini_array))
|
||||
__dtor_end = .;
|
||||
} > RAM
|
||||
.got : { *(.got.plt) *(.got) } > RAM
|
||||
.dynamic : { *(.dynamic) } > RAM
|
||||
|
||||
/* List sections that have differet load address and link address,
|
||||
* requiring early section copy on start up.
|
||||
*/
|
||||
.earlycopy : ALIGN(4) {
|
||||
__earlycopy_start = .;
|
||||
|
||||
/* TCM code and data section. */
|
||||
LONG(ADDR(.tcm))
|
||||
LONG(SIZEOF(.tcm))
|
||||
LONG(LOADADDR(.tcm))
|
||||
|
||||
/* Add other sections here. */
|
||||
|
||||
__earlycopy_end = .;
|
||||
} > RAM
|
||||
|
||||
.nocache : ALIGN(1024) {
|
||||
_nocacheable_start = .;
|
||||
KEEP(*(.nocache))
|
||||
. = ALIGN(1024);
|
||||
_nocacheable_end = .;
|
||||
} > RAM
|
||||
|
||||
.dummy_post_data : {
|
||||
/* End of initialized sections. */
|
||||
__data_end = ALIGN(4);
|
||||
} > RAM
|
||||
|
||||
/* uninitialized data (in same segment as writable data) */
|
||||
.bss (NOLOAD) : ALIGN(4) {
|
||||
KEEP(*(.bss.prebss.*))
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} > RAM
|
||||
|
||||
_end = .;
|
||||
|
||||
.heap (NOLOAD) : ALIGN(8) {
|
||||
_heap_start = .;
|
||||
*(.heap)
|
||||
} > RAM
|
||||
|
||||
_end_of_ram = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
_heap_end = _end_of_ram;
|
||||
|
||||
/* IRAM none-ecc data sections. */
|
||||
.noneecc (NOLOAD) : ALIGN(4) {
|
||||
_noneecc_start = .;
|
||||
*(.noneeccdata)
|
||||
_noneecc_end = ORIGIN(RAMECC) + LENGTH(RAMECC);
|
||||
} > RAMECC
|
||||
|
||||
/* TCM code and data sections. */
|
||||
.tcm : AT (__data_end) {
|
||||
__tcm_start = .;
|
||||
*(.tcmcode)
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.tcmdata)
|
||||
|
||||
__tcm_end = ALIGN(4);
|
||||
ASSERT(__tcm_end - __tcm_start <= LENGTH(TCM), "TCM overflow!");
|
||||
} > TCM
|
||||
|
||||
/* exception stack */
|
||||
.except.stack (NOLOAD) : ALIGN(8) {
|
||||
__except_stack_start = .;
|
||||
. += CSTACK_SIZE;
|
||||
__cstack_end = .;
|
||||
. += SVC_STACK_SIZE;
|
||||
__svc_stack_end = .;
|
||||
. += IRQ_STACK_SIZE;
|
||||
__irq_stack_end = .;
|
||||
. += FIQ_STACK_SIZE;
|
||||
__fiq_stack_end = .;
|
||||
. += UND_STACK_SIZE;
|
||||
__und_stack_end = .;
|
||||
. += ABT_STACK_SIZE;
|
||||
__abt_stack_end = .;
|
||||
__except_stack_end = .;
|
||||
} > TCM
|
||||
|
||||
/* Strip unnecessary stuff */
|
||||
/DISCARD/ : { *(.comment .note) }
|
||||
}
|
||||
|
||||
183
devices/E3106/linker/gcc/xip.ld
Normal file
183
devices/E3106/linker/gcc/xip.ld
Normal file
@@ -0,0 +1,183 @@
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
|
||||
CSTACK_SIZE = 0x1000;
|
||||
SVC_STACK_SIZE = 0x1000;
|
||||
IRQ_STACK_SIZE = 0x80;
|
||||
FIQ_STACK_SIZE = 0x1000;
|
||||
UND_STACK_SIZE = 0x80;
|
||||
ABT_STACK_SIZE = 0x80;
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ROM (R) : ORIGIN = 0x10140000, LENGTH = 0x002C0000
|
||||
TCM (RW) : ORIGIN = 0x00000040, LENGTH = 0x0001FFC0
|
||||
RAM (RW) : ORIGIN = 0x00504000, LENGTH = 0x0007C000
|
||||
RAMECC (RW) : ORIGIN = 0x004E0000, LENGTH = 0x00020000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* text/read-only data */
|
||||
.text : {
|
||||
KEEP(*(.intvec))
|
||||
*(.text* .sram.text.glue_7* .gnu.linkonce.t.*)
|
||||
} > ROM
|
||||
|
||||
.dummy_post_text : {
|
||||
__code_end = .;
|
||||
} > ROM
|
||||
|
||||
.rodata : ALIGN(4) {
|
||||
__rodata_start = .;
|
||||
__fault_handler_table_start = .;
|
||||
KEEP(*(.rodata.fault_handler_table))
|
||||
__fault_handler_table_end = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
} > ROM
|
||||
|
||||
/*
|
||||
* extra linker scripts tend to insert sections just after .rodata,
|
||||
* so we want to make sure this symbol comes after anything inserted above,
|
||||
* but not aligned to the next section necessarily.
|
||||
*/
|
||||
.dummy_post_rodata : {
|
||||
__rodata_end = .;
|
||||
} > ROM
|
||||
|
||||
/* List sections that have differet load address and link address,
|
||||
* requiring early section copy on start up.
|
||||
*/
|
||||
.earlycopy : ALIGN(4) {
|
||||
__earlycopy_start = .;
|
||||
|
||||
/* TCM code and data section. */
|
||||
LONG(ADDR(.tcm))
|
||||
LONG(SIZEOF(.tcm))
|
||||
LONG(LOADADDR(.tcm))
|
||||
|
||||
/* RAM code section. */
|
||||
LONG(ADDR(.ram.text))
|
||||
LONG(SIZEOF(.ram.text))
|
||||
LONG(LOADADDR(.ram.text))
|
||||
|
||||
/* RAM data section. */
|
||||
LONG(ADDR(.data))
|
||||
LONG(SIZEOF(.data))
|
||||
LONG(LOADADDR(.data))
|
||||
|
||||
__earlycopy_end = .;
|
||||
} > ROM
|
||||
|
||||
.ctors : ALIGN(4) {
|
||||
__ctor_list = .;
|
||||
KEEP(*(.ctors .init_array))
|
||||
__ctor_end = .;
|
||||
} > ROM
|
||||
|
||||
.dtors : ALIGN(4) {
|
||||
__dtor_list = .;
|
||||
KEEP(*(.dtors .fini_array))
|
||||
__dtor_end = .;
|
||||
} > ROM
|
||||
.got : { *(.got.plt) *(.got) } > ROM
|
||||
.dynamic : { *(.dynamic) } > ROM
|
||||
|
||||
__rom_end = .;
|
||||
|
||||
/* TCM code and data sections. */
|
||||
.tcm : AT (__rom_end ) ALIGN(4) {
|
||||
__tcm_start = .;
|
||||
*(.tcmcode)
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.tcmdata)
|
||||
|
||||
__tcm_end = ALIGN(4);
|
||||
ASSERT(__tcm_end - __tcm_start <= LENGTH(TCM), "TCM overflow!");
|
||||
} > TCM
|
||||
|
||||
/* exception stack */
|
||||
.except.stack (NOLOAD) : ALIGN(8) {
|
||||
__except_stack_start = .;
|
||||
. += CSTACK_SIZE;
|
||||
__cstack_end = .;
|
||||
. += SVC_STACK_SIZE;
|
||||
__svc_stack_end = .;
|
||||
. += IRQ_STACK_SIZE;
|
||||
__irq_stack_end = .;
|
||||
. += FIQ_STACK_SIZE;
|
||||
__fiq_stack_end = .;
|
||||
. += UND_STACK_SIZE;
|
||||
__und_stack_end = .;
|
||||
. += ABT_STACK_SIZE;
|
||||
__abt_stack_end = .;
|
||||
__except_stack_end = .;
|
||||
} > TCM
|
||||
|
||||
/* place R/W data and some code which cann't xip in the RAM */
|
||||
. = ORIGIN(RAM);
|
||||
|
||||
__data_load_start = LOADADDR(.tcm) + SIZEOF (.tcm);
|
||||
.data : AT (__data_load_start) ALIGN(4) {
|
||||
__data_start = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
__commands_start = .;
|
||||
KEEP (*(.commands))
|
||||
__commands_end = .;
|
||||
} > RAM
|
||||
|
||||
__ram_text_load_start = __data_load_start + SIZEOF (.data);
|
||||
/* code that is located in ram */
|
||||
.ram.text : AT (__ram_text_load_start) ALIGN(4) {
|
||||
KEEP (*(.ram.text*))
|
||||
} > RAM
|
||||
|
||||
.nocache : ALIGN(1024) {
|
||||
_nocacheable_start = .;
|
||||
KEEP(*(.nocache))
|
||||
. = ALIGN(1024);
|
||||
_nocacheable_end = .;
|
||||
} > RAM
|
||||
|
||||
.dummy_post_data : {
|
||||
/* End of initialized sections. */
|
||||
__data_end = ALIGN(4);
|
||||
} > RAM
|
||||
|
||||
/* uninitialized data (in same segment as writable data) */
|
||||
.bss (NOLOAD) : ALIGN(4) {
|
||||
KEEP(*(.bss.prebss.*))
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} > RAM
|
||||
|
||||
_end = .;
|
||||
|
||||
.heap (NOLOAD) : ALIGN(8) {
|
||||
_heap_start = .;
|
||||
*(.heap)
|
||||
} > RAM
|
||||
|
||||
_end_of_ram = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
_heap_end = _end_of_ram;
|
||||
|
||||
/* IRAM none-ecc data sections. */
|
||||
.noneecc (NOLOAD) : ALIGN(4) {
|
||||
_noneecc_start = .;
|
||||
*(.noneeccdata)
|
||||
_noneecc_end = ORIGIN(RAMECC) + LENGTH(RAMECC);
|
||||
} > RAMECC
|
||||
|
||||
/* Strip unnecessary stuff */
|
||||
/DISCARD/ : { *(.comment .note) }
|
||||
}
|
||||
|
||||
50
devices/E3106/linker/iar/bootloader.icf
Normal file
50
devices/E3106/linker/iar/bootloader.icf
Normal file
@@ -0,0 +1,50 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00504000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x00504000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x0057FFFF;
|
||||
define symbol __ICFEDIT_region_TCM_start__ = 0x01900000;
|
||||
define symbol __ICFEDIT_region_TCM_end__ = 0x0191FFFF;
|
||||
define symbol __ICFEDIT_region_RAMECC_start__ = 0x004E0000;
|
||||
define symbol __ICFEDIT_region_RAMECC_end__ = 0x004FFFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_fiqstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_undstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_abtstack__ = 0x80;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
|
||||
define region RAMECC_region = mem:[from __ICFEDIT_region_RAMECC_start__ to __ICFEDIT_region_RAMECC_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
|
||||
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
|
||||
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
|
||||
define block HEAP with alignment = 8, expanding size { section .heap };
|
||||
|
||||
define block COMMANDS { section .commands };
|
||||
define block TCMCODE with alignment = 4 { section .tcmcode};
|
||||
define block TCMDATA with alignment = 4 { section .tcmdata};
|
||||
define block NONEECCDATA with alignment = 4 { section .noneeccdata};
|
||||
|
||||
initialize by copy { section .tcmcode, section .tcmdata};
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
|
||||
block UND_STACK, block ABT_STACK, block COMMANDS, block HEAP };
|
||||
place in TCM_region { block TCMCODE, block TCMDATA};
|
||||
place in RAMECC_region { block NONEECCDATA};
|
||||
54
devices/E3106/linker/iar/bootloader_flashdebug.icf
Normal file
54
devices/E3106/linker/iar/bootloader_flashdebug.icf
Normal file
@@ -0,0 +1,54 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00504000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x00504000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x0057FFFF;
|
||||
define symbol __ICFEDIT_region_TCM_start__ = 0x01900000;
|
||||
define symbol __ICFEDIT_region_TCM_end__ = 0x0191FFFF;
|
||||
define symbol __ICFEDIT_region_RAMECC_start__ = 0x004E0000;
|
||||
define symbol __ICFEDIT_region_RAMECC_end__ = 0x004FFFFF;
|
||||
define symbol __ICFEDIT_region_SFS_start__ = 0x10000000;
|
||||
define symbol __ICFEDIT_region_SF_start__ = 0x10140000;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_fiqstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_undstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_abtstack__ = 0x80;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
|
||||
define region RAMECC_region = mem:[from __ICFEDIT_region_RAMECC_start__ to __ICFEDIT_region_RAMECC_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
|
||||
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
|
||||
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
|
||||
define block HEAP with alignment = 8, expanding size { section .heap };
|
||||
|
||||
define block COMMANDS { section .commands };
|
||||
define block TCMCODE with alignment = 4 { section .tcmcode};
|
||||
define block TCMDATA with alignment = 4 { section .tcmdata};
|
||||
define block NONEECCDATA with alignment = 4 { section .noneeccdata};
|
||||
|
||||
initialize by copy { section .tcmcode, section .tcmdata};
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
|
||||
block UND_STACK, block ABT_STACK, block COMMANDS, block HEAP };
|
||||
place in TCM_region { block TCMCODE, block TCMDATA};
|
||||
place in RAMECC_region { block NONEECCDATA};
|
||||
place at address mem:__ICFEDIT_region_SFS_start__ { section SFS_BIN };
|
||||
place at address mem:__ICFEDIT_region_SF_start__ { section SF_BIN };
|
||||
38
devices/E3106/linker/iar/flashloader.icf
Normal file
38
devices/E3106/linker/iar/flashloader.icf
Normal file
@@ -0,0 +1,38 @@
|
||||
define symbol __ICFEDIT_region_TCM_start__ = 0x004E0000;
|
||||
define symbol __ICFEDIT_region_TCM_end__ = 0x004FFFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = 0x4000 { };
|
||||
define block HEAP with alignment = 4, size = 0x2000 { };
|
||||
define block PADDING with alignment = 4, size = 0x1000 { };
|
||||
define block flashbuf with fixed order{section LOWEND, block PADDING, section HIGHSTART};
|
||||
keep { block PADDING};
|
||||
|
||||
do not initialize {section .noinit, section .PRGDATA};
|
||||
|
||||
"PrgCode":
|
||||
place at start of TCM_region {section .PRGCODE};
|
||||
|
||||
"T32CodeBegin":
|
||||
place in TCM_region {readonly section .T32CODEBEGIN};
|
||||
|
||||
"FuseCode":
|
||||
place in TCM_region {section .FUSECODE};
|
||||
|
||||
"PrgData":
|
||||
place in TCM_region {section .PRGDATA};
|
||||
|
||||
"DevDscr":
|
||||
place in TCM_region {section .DEVDSCR};
|
||||
|
||||
place in TCM_region {readonly};
|
||||
|
||||
place in TCM_region {readwrite, block HEAP, block CSTACK};
|
||||
|
||||
"BUF":
|
||||
place in TCM_region {block flashbuf};
|
||||
|
||||
"T32CodeEnd":
|
||||
place in TCM_region {section .T32CODEEND};
|
||||
49
devices/E3106/linker/iar/ram.icf
Normal file
49
devices/E3106/linker/iar/ram.icf
Normal file
@@ -0,0 +1,49 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00504000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x00504000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x0057FFFF;
|
||||
define symbol __ICFEDIT_region_TCM_start__ = 0x00000040;
|
||||
define symbol __ICFEDIT_region_TCM_end__ = 0x0001FFFF;
|
||||
define symbol __ICFEDIT_region_RAMECC_start__ = 0x004E0000;
|
||||
define symbol __ICFEDIT_region_RAMECC_end__ = 0x004FFFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_fiqstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_undstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_abtstack__ = 0x80;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
|
||||
define region RAMECC_region = mem:[from __ICFEDIT_region_RAMECC_start__ to __ICFEDIT_region_RAMECC_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
|
||||
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
|
||||
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
|
||||
define block HEAP with alignment = 8, expanding size { section .heap };
|
||||
|
||||
define block COMMANDS { section .commands };
|
||||
define block TCMCODE with alignment = 4 { section .tcmcode};
|
||||
define block TCMDATA with alignment = 4 { section .tcmdata};
|
||||
define block NONEECCDATA with alignment = 4 { section .noneeccdata};
|
||||
|
||||
initialize by copy { section .tcmcode, section .tcmdata};
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block COMMANDS, block HEAP };
|
||||
place in TCM_region { block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
|
||||
block UND_STACK, block ABT_STACK, block TCMCODE, block TCMDATA};
|
||||
place in RAMECC_region { block NONEECCDATA};
|
||||
50
devices/E3106/linker/iar/ram_20240813.icf
Normal file
50
devices/E3106/linker/iar/ram_20240813.icf
Normal file
@@ -0,0 +1,50 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00504000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x00504000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x0057FFFF;
|
||||
define symbol __ICFEDIT_region_TCM_start__ = 0x00000040;
|
||||
define symbol __ICFEDIT_region_TCM_end__ = 0x0001FFFF;
|
||||
define symbol __ICFEDIT_region_RAMECC_start__ = 0x004E0000;
|
||||
define symbol __ICFEDIT_region_RAMECC_end__ = 0x004FFFFF;
|
||||
define symbol __ICFEDIT_region_SFS_start__ = 0x10000000;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_fiqstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_undstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_abtstack__ = 0x80;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
|
||||
define region RAMECC_region = mem:[from __ICFEDIT_region_RAMECC_start__ to __ICFEDIT_region_RAMECC_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
|
||||
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
|
||||
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
|
||||
define block HEAP with alignment = 8, expanding size { section .heap };
|
||||
|
||||
define block COMMANDS { section .commands };
|
||||
define block TCMCODE with alignment = 4 { section .tcmcode};
|
||||
define block TCMDATA with alignment = 4 { section .tcmdata};
|
||||
define block NONEECCDATA with alignment = 4 { section .noneeccdata};
|
||||
|
||||
initialize by copy { section .tcmcode, section .tcmdata};
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block COMMANDS, block HEAP };
|
||||
place in TCM_region { block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
|
||||
block UND_STACK, block ABT_STACK, block TCMCODE, block TCMDATA};
|
||||
place in RAMECC_region { block NONEECCDATA};
|
||||
51
devices/E3106/linker/iar/ram_flashdebug.icf
Normal file
51
devices/E3106/linker/iar/ram_flashdebug.icf
Normal file
@@ -0,0 +1,51 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00504000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x00504000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x0057FFFF;
|
||||
define symbol __ICFEDIT_region_TCM_start__ = 0x00000040;
|
||||
define symbol __ICFEDIT_region_TCM_end__ = 0x0001FFFF;
|
||||
define symbol __ICFEDIT_region_RAMECC_start__ = 0x004E0000;
|
||||
define symbol __ICFEDIT_region_RAMECC_end__ = 0x004FFFFF;
|
||||
define symbol __ICFEDIT_region_SFS_start__ = 0x10000000;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_fiqstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_undstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_abtstack__ = 0x80;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
|
||||
define region RAMECC_region = mem:[from __ICFEDIT_region_RAMECC_start__ to __ICFEDIT_region_RAMECC_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
|
||||
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
|
||||
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
|
||||
define block HEAP with alignment = 8, expanding size { section .heap };
|
||||
|
||||
define block COMMANDS { section .commands };
|
||||
define block TCMCODE with alignment = 4 { section .tcmcode};
|
||||
define block TCMDATA with alignment = 4 { section .tcmdata};
|
||||
define block NONEECCDATA with alignment = 4 { section .noneeccdata};
|
||||
|
||||
initialize by copy { section .tcmcode, section .tcmdata};
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in RAM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block COMMANDS, block HEAP };
|
||||
place in TCM_region { block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
|
||||
block UND_STACK, block ABT_STACK, block TCMCODE, block TCMDATA};
|
||||
place in RAMECC_region { block NONEECCDATA};
|
||||
place at address mem:__ICFEDIT_region_SFS_start__ { section SFS_BIN };
|
||||
79
devices/E3106/linker/iar/xip.icf
Normal file
79
devices/E3106/linker/iar/xip.icf
Normal file
@@ -0,0 +1,79 @@
|
||||
define memory mem with size = 4G;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x00504000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x0057FFFF;
|
||||
define symbol __ICFEDIT_region_TCM_start__ = 0x00000040;
|
||||
define symbol __ICFEDIT_region_TCM_end__ = 0x0001FFFF;
|
||||
define symbol __ICFEDIT_region_RAMECC_start__ = 0x004E0000;
|
||||
define symbol __ICFEDIT_region_RAMECC_end__ = 0x004FFFFF;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x10140000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x103FFFFF;
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = __ICFEDIT_region_ROM_start__;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_fiqstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_undstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_abtstack__ = 0x80;
|
||||
|
||||
/*-blocks-*/
|
||||
define block RAM_TEXT with alignment = 4 { section .ram.text, section .textrw};
|
||||
define block BSS with alignment = 4 { section .bss, section .tbss };
|
||||
define block EXCEPTION_STACK with alignment = 4 { section .except.stack };
|
||||
define block RODATA with alignment = 4 { section .rodata.fault_handler_table, section .rodata};
|
||||
define block COMMANDS { section .commands };
|
||||
define block TCMCODE with alignment = 4 { section .tcmcode};
|
||||
define block TCMDATA with alignment = 4 { section .tcmdata};
|
||||
define block NONEECCDATA with alignment = 4 { section .noneeccdata};
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
|
||||
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
|
||||
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
|
||||
define block HEAP with alignment = 8, expanding size { section .heap };
|
||||
define block RO { readonly };
|
||||
define block RW { readwrite };
|
||||
define block ZI { zi };
|
||||
define block Region_Table with alignment = 32 { section .iar.init_table };
|
||||
|
||||
/*-regions-*/
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
|
||||
define region RAMECC_region = mem:[from __ICFEDIT_region_RAMECC_start__ to __ICFEDIT_region_RAMECC_end__];
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
|
||||
/*-placement-*/
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { section .boot };
|
||||
place in ROM_region { section .text };
|
||||
place in ROM_region { block RODATA };
|
||||
place in RAM_region { block COMMANDS };
|
||||
place in ROM_region { block RO };
|
||||
place in ROM_region { block Region_Table };
|
||||
|
||||
place in RAM_region { block RAM_TEXT };
|
||||
place in RAM_region { block BSS };
|
||||
place in TCM_region { block EXCEPTION_STACK };
|
||||
place in RAM_region { block RW };
|
||||
place in RAM_region { block ZI };
|
||||
place in TCM_region { block CSTACK };
|
||||
place in TCM_region { block SVC_STACK };
|
||||
place in TCM_region { block IRQ_STACK };
|
||||
place in TCM_region { block FIQ_STACK };
|
||||
place in TCM_region { block UND_STACK };
|
||||
place in TCM_region { block ABT_STACK };
|
||||
place in RAM_region { block HEAP };
|
||||
place in TCM_region { block TCMCODE, block TCMDATA};
|
||||
place in RAMECC_region { block NONEECCDATA};
|
||||
|
||||
|
||||
initialize by copy { section .tcmcode, section .tcmdata, section .ram.text, section .textrw, section .commands };
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .except.stack, section .noneeccdata, section .noinit, section .heap};
|
||||
|
||||
82
devices/E3106/linker/iar/xip_flashdebug_norflash.icf
Normal file
82
devices/E3106/linker/iar/xip_flashdebug_norflash.icf
Normal file
@@ -0,0 +1,82 @@
|
||||
define memory mem with size = 4G;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x00504000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x0057FFFF;
|
||||
define symbol __ICFEDIT_region_TCM_start__ = 0x00000040;
|
||||
define symbol __ICFEDIT_region_TCM_end__ = 0x0001FFFF;
|
||||
define symbol __ICFEDIT_region_RAMECC_start__ = 0x004E0000;
|
||||
define symbol __ICFEDIT_region_RAMECC_end__ = 0x004FFFFF;
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x10140000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x103FFFFF;
|
||||
define symbol __ICFEDIT_region_SFS_start__ = 0x10000000;
|
||||
define symbol __ICFEDIT_region_BOOTLOADER_start__ = 0x10008000;
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = __ICFEDIT_region_ROM_start__;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_svcstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_irqstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_fiqstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_undstack__ = 0x80;
|
||||
define symbol __ICFEDIT_size_abtstack__ = 0x80;
|
||||
|
||||
/*-blocks-*/
|
||||
define block RAM_TEXT with alignment = 4 { section .ram.text, section .textrw};
|
||||
define block BSS with alignment = 4 { section .bss, section .tbss };
|
||||
define block EXCEPTION_STACK with alignment = 4 { section .except.stack };
|
||||
define block RODATA with alignment = 4 { section .rodata.fault_handler_table, section .rodata};
|
||||
define block COMMANDS { section .commands };
|
||||
define block TCMCODE with alignment = 4 { section .tcmcode};
|
||||
define block TCMDATA with alignment = 4 { section .tcmdata};
|
||||
define block NONEECCDATA with alignment = 4 { section .noneeccdata};
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
|
||||
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
|
||||
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
|
||||
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
|
||||
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
|
||||
define block HEAP with alignment = 8, expanding size { section .heap };
|
||||
define block RO { readonly };
|
||||
define block RW { readwrite };
|
||||
define block ZI { zi };
|
||||
define block Region_Table with alignment = 32 { section .iar.init_table };
|
||||
|
||||
/*-regions-*/
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
|
||||
define region RAMECC_region = mem:[from __ICFEDIT_region_RAMECC_start__ to __ICFEDIT_region_RAMECC_end__];
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
|
||||
/*-placement-*/
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { section .boot };
|
||||
place in ROM_region { section .text };
|
||||
place in ROM_region { block RODATA };
|
||||
place in RAM_region { block COMMANDS };
|
||||
place in ROM_region { block RO };
|
||||
place in ROM_region { block Region_Table };
|
||||
|
||||
place in RAM_region { block RAM_TEXT };
|
||||
place in RAM_region { block BSS };
|
||||
place in TCM_region { block EXCEPTION_STACK };
|
||||
place in RAM_region { block RW };
|
||||
place in RAM_region { block ZI };
|
||||
place in TCM_region { block CSTACK };
|
||||
place in TCM_region { block SVC_STACK };
|
||||
place in TCM_region { block IRQ_STACK };
|
||||
place in TCM_region { block FIQ_STACK };
|
||||
place in TCM_region { block UND_STACK };
|
||||
place in TCM_region { block ABT_STACK };
|
||||
place in RAM_region { block HEAP };
|
||||
place in TCM_region { block TCMCODE, block TCMDATA};
|
||||
place in RAMECC_region { block NONEECCDATA};
|
||||
place at address mem:__ICFEDIT_region_SFS_start__ { section SFS_BIN };
|
||||
place at address mem:__ICFEDIT_region_BOOTLOADER_start__ { section BOOTLOADER_BIN };
|
||||
|
||||
initialize by copy { section .tcmcode, section .tcmdata, section .ram.text, section .textrw, section .commands };
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .except.stack, section .noneeccdata, section .noinit, section .heap};
|
||||
|
||||
56
devices/E3106/pacconfig/pac_config_sf_norflash.json
Normal file
56
devices/E3106/pacconfig/pac_config_sf_norflash.json
Normal file
@@ -0,0 +1,56 @@
|
||||
{
|
||||
"description": "e3 pac information file",
|
||||
"pac": [
|
||||
{
|
||||
"flash_type": "norflash",
|
||||
"type": "ospi",
|
||||
"sec_ver": "0",
|
||||
"partition": "false",
|
||||
"partition_file": "ospi.bpt",
|
||||
"xip_mode": "false",
|
||||
"sf_only_mode": "false",
|
||||
"boot_package_num": "3",
|
||||
"key": "TestRSA2048_ossl.pem",
|
||||
"ctl": "none",
|
||||
"uuid": "none",
|
||||
"dloader_entry": "0x504000",
|
||||
"core": {
|
||||
"sf_mode": "lockstep",
|
||||
"sp_mode": "None",
|
||||
"sx_mode": "None",
|
||||
"sf_entry": "0x504000",
|
||||
"sp0_entry": "0x600000",
|
||||
"sp1_entry": "0x680000",
|
||||
"sx0_entry": "0x500000",
|
||||
"sx1_entry": "0x580000",
|
||||
"sf_pad_size": "0x1000",
|
||||
"sp0_pad_size": "0x1000",
|
||||
"sp1_pad_size": "0x1000",
|
||||
"sx0_pad_size": "0x1000",
|
||||
"sx1_pad_size": "0x1000",
|
||||
"bootloader_mode": "false",
|
||||
"bootloader_entry": "0x504000",
|
||||
"bootloader_pad_size": "0x40000"
|
||||
},
|
||||
"sfs": {
|
||||
"name": "is25-1-1-4-dummy-dqs-100MHz.json",
|
||||
"boot0_addr": "0x7000",
|
||||
"boot1_addr": "0x207000",
|
||||
"boot2_addr": "0x407000"
|
||||
},
|
||||
"encryption": {
|
||||
"encryption_on": "false",
|
||||
"rfd": [
|
||||
{
|
||||
"pvk3": "112233445566778899aabbccddeeff00",
|
||||
"iv": "0d090d09",
|
||||
"start": "0x7000",
|
||||
"end": "0x207000",
|
||||
"boot":"true"
|
||||
}
|
||||
]
|
||||
},
|
||||
"rfd": "xspi_wrap_rfd_blk_pvk1_ks.rfd"
|
||||
}
|
||||
]
|
||||
}
|
||||
482
devices/E3106/reset_ip.c
Normal file
482
devices/E3106/reset_ip.c
Normal file
@@ -0,0 +1,482 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// WARNING: Automatically generated file, don't modify anymore!!!
|
||||
//
|
||||
// Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
//*****************************************************************************
|
||||
#include <types.h>
|
||||
#include <regs_base.h>
|
||||
#include <reset_ip.h>
|
||||
#include <compiler.h>
|
||||
#include <reg.h>
|
||||
#include <sdrv_scr.h>
|
||||
#include <scr_hw.h>
|
||||
#include "udelay/udelay.h"
|
||||
|
||||
/**
|
||||
* @brief E3L SAF reset signal id.
|
||||
*/
|
||||
typedef enum e3l_reset_signal_safety {
|
||||
E3L_RSTSIG_SAF_CR5_SAF = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_CORE, 0),
|
||||
E3L_RSTSIG_SAF_LATENT = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_LATENT, 0),
|
||||
E3L_RSTSIG_SAF_MISSION0 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 0),
|
||||
E3L_RSTSIG_SAF_MISSION1 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 1),
|
||||
E3L_RSTSIG_SAF_MISSION2 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 2),
|
||||
E3L_RSTSIG_SAF_MISSION3 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 3),
|
||||
E3L_RSTSIG_SAF_MISSION4 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 4),
|
||||
E3L_RSTSIG_SAF_MISSION5 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MISSION, 5),
|
||||
E3L_RSTSIG_SAF_CANFD16 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 0),
|
||||
E3L_RSTSIG_SAF_CANFD21,
|
||||
E3L_RSTSIG_SAF_CANFD3,
|
||||
E3L_RSTSIG_SAF_CANFD4,
|
||||
E3L_RSTSIG_SAF_CANFD5,
|
||||
E3L_RSTSIG_SAF_CANFD6 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 5),
|
||||
E3L_RSTSIG_SAF_CANFD7,
|
||||
E3L_RSTSIG_SAF_CANFD23,
|
||||
E3L_RSTSIG_SAF_XSPI1A,
|
||||
E3L_RSTSIG_SAF_XSPI1B,
|
||||
E3L_RSTSIG_SAF_DMA_RST0 = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 10),
|
||||
E3L_RSTSIG_SAF_DMA_RST1,
|
||||
E3L_RSTSIG_SAF_ENET1,
|
||||
E3L_RSTSIG_SAF_VIC1,
|
||||
E3L_RSTSIG_SAF_XSPI_SLV,
|
||||
E3L_RSTSIG_SAF_XTRG = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 15),
|
||||
E3L_RSTSIG_SAF_SACI2,
|
||||
E3L_RSTSIG_SAF_SEHC1,
|
||||
E3L_RSTSIG_SAF_USB,
|
||||
E3L_RSTSIG_SAF_SEIP,
|
||||
E3L_RSTSIG_SAF_CSLITE = SDRV_RSTGEN_SIG_ID(SDRV_RSTGEN_MODULE, 20),
|
||||
} e3l_reset_signal_safety_e;
|
||||
|
||||
/* SAF rstgen controller */
|
||||
sdrv_rstgen_t g_rstgen_saf = {
|
||||
.base = APB_RSTGEN_SF_BASE,
|
||||
};
|
||||
|
||||
/* global reset */
|
||||
sdrv_rstgen_glb_t rstctl_glb = {
|
||||
.rst_sf_ctl = &g_rstgen_saf,
|
||||
};
|
||||
|
||||
/* SAF core */
|
||||
sdrv_rstgen_sig_t rstsig_cr5_saf = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_CR5_SAF,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief reset latent
|
||||
*
|
||||
* latent signals will reset automatically after power on.
|
||||
*
|
||||
* signals in latent:
|
||||
* AHB2APB1
|
||||
* AHB2APB2
|
||||
* AHB2APB3
|
||||
* AHB2APB4
|
||||
* APBMUX2
|
||||
* APBMUX3
|
||||
* IROMC
|
||||
* IOMUXC_SF_COMP
|
||||
* MAC
|
||||
* SCR_SF
|
||||
* WDT1
|
||||
* SEM1
|
||||
* SEM2
|
||||
* VD_SF_DIG
|
||||
* IOC
|
||||
* EIC_SF
|
||||
* FUSE_LSP_CMP
|
||||
* FAB_SF
|
||||
* UART1
|
||||
* UART2
|
||||
* UART3
|
||||
* UART4
|
||||
* UART5
|
||||
* UART6
|
||||
* UART7
|
||||
* UART8
|
||||
* UART9
|
||||
* UART10
|
||||
* UART11
|
||||
* UART12
|
||||
* SPI1
|
||||
* SPI2
|
||||
* SPI3
|
||||
* SPI4
|
||||
* SPI5
|
||||
* SPI6
|
||||
* I2C1
|
||||
* I2C2
|
||||
* I2C3
|
||||
* I2C4
|
||||
* I2C5
|
||||
* I2C6
|
||||
* ETMR1
|
||||
* ETMR2
|
||||
* EPWM1
|
||||
* EPWM2
|
||||
* MPC_XSPI1A
|
||||
* MPC_XSPI1B
|
||||
* AAPB_MPC_XSPI1A
|
||||
* AAPB_MPC_XSPI1B
|
||||
* AAPB_MPC_SEIP
|
||||
* WDT8
|
||||
* PPC_APBMUX2
|
||||
* PPC_APBMUX3
|
||||
* PPC_APBMUX4
|
||||
* PPC_APBMUX1
|
||||
* MPC_ROMC
|
||||
* XB_SF
|
||||
* MPC_IRAMC1
|
||||
* MPC_CR5_SF
|
||||
* POR_SF_DIG
|
||||
* PT_SNS_SF_DIG
|
||||
* MPC_VIC1
|
||||
* BTM1
|
||||
* BTM2
|
||||
* BTM3
|
||||
* BTM4
|
||||
* AAPB_XSPI1A
|
||||
* AAPB_XSPI1B
|
||||
* MPC_SEIP
|
||||
* APB_APBMUX1_SLV
|
||||
* APB_PMUX2_DEC_SLV
|
||||
* AAPB_APBMUX3
|
||||
* APB_DCDC1_SLV
|
||||
* APB_APBMUX4_SLV
|
||||
* AAXI_APSF_MST
|
||||
*/
|
||||
sdrv_rstgen_sig_t rstsig_latent = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_LATENT,
|
||||
};
|
||||
|
||||
/*
|
||||
* @brief reset mission
|
||||
*
|
||||
* reset mission signals will reset automatically after power on.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief reset mission 0
|
||||
*
|
||||
* signals in mission 0:
|
||||
* GPIO_SF
|
||||
* IOMUXC_SF
|
||||
* SMC
|
||||
* PMU_CORE
|
||||
* APB_APBMUX1_MST
|
||||
* APB_PMUX2_DEC_MST
|
||||
* APB_SEIP_NVM_MST
|
||||
*/
|
||||
sdrv_rstgen_sig_t rstsig_mission0 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_MISSION0,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief reset mission 1
|
||||
*
|
||||
* signals in mission 1:
|
||||
* PLL1
|
||||
* PLL2
|
||||
* Pll3
|
||||
*/
|
||||
sdrv_rstgen_sig_t rstsig_mission1 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_MISSION1,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief reset mission 2
|
||||
*
|
||||
* signals in mission 2:
|
||||
* ANA_SF_SADC1
|
||||
* ANA_SF_SADC2
|
||||
* ANA_SF_SADC3
|
||||
* ANA_SF_SACMP1
|
||||
* ANA_SF_SACMP2
|
||||
*/
|
||||
sdrv_rstgen_sig_t rstsig_mission2 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_MISSION2,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief reset mission 3
|
||||
*
|
||||
* signals in mission 3:
|
||||
* IRAM1
|
||||
*/
|
||||
sdrv_rstgen_sig_t rstsig_mission3 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_MISSION3,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief reset mission 4
|
||||
*
|
||||
* signals in mission 4:
|
||||
* DCDC1
|
||||
* APB_DCDC1_MST
|
||||
*/
|
||||
sdrv_rstgen_sig_t rstsig_mission4 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_MISSION4,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief reset mission 5
|
||||
*
|
||||
* signals in mission 5:
|
||||
* APBMUX4
|
||||
* PTB
|
||||
* AHBDEC_SEIP
|
||||
* APB_SEC_STORAGE1_SLV
|
||||
* APB_SEIP_NVM_SLV
|
||||
* APB_APBMUX4_MST
|
||||
* AAXI_APSF_SLV
|
||||
*/
|
||||
sdrv_rstgen_sig_t rstsig_mission5 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_MISSION5,
|
||||
};
|
||||
|
||||
/* reset module */
|
||||
sdrv_rstgen_sig_t rstsig_canfd16 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_CANFD16,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_canfd21 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_CANFD21,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_canfd3 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_CANFD3,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_canfd4 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_CANFD4,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_canfd5 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_CANFD5,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_canfd6 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_CANFD6,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_canfd7 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_CANFD7,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_canfd23 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_CANFD23,
|
||||
};
|
||||
|
||||
typedef enum reset_xspi_port_id {
|
||||
RST_XSPI_1A = 0U,
|
||||
RST_XSPI_1B = 1U,
|
||||
RST_XSPI_NUM = 2U,
|
||||
} reset_xspi_port_id_e;
|
||||
|
||||
static sdrv_scr_t scr_ctrl = {
|
||||
.base = APB_SCR_SF_BASE,
|
||||
};
|
||||
|
||||
static uint32_t xspi_base[RST_XSPI_NUM] = {
|
||||
APB_XSPI1PORTA_BASE,
|
||||
APB_XSPI1PORTB_BASE,
|
||||
};
|
||||
|
||||
static scr_signal_t sig_xspi_scr[RST_XSPI_NUM][4] = {
|
||||
{
|
||||
SCR_SF_AAPB_XSPI1A_SRC_IRQ_ENB,
|
||||
SCR_SF_AAPB_XSPI1A_SRC_UNCERR_CLR,
|
||||
SCR_SF_AAPB_XSPI1A_DST_IRQ_ENB,
|
||||
SCR_SF_AAPB_XSPI1A_DST_UNCERR_CLR,
|
||||
},
|
||||
|
||||
{
|
||||
SCR_SF_AAPB_XSPI1B_SRC_IRQ_ENB,
|
||||
SCR_SF_AAPB_XSPI1B_SRC_UNCERR_CLR,
|
||||
SCR_SF_AAPB_XSPI1B_DST_IRQ_ENB,
|
||||
SCR_SF_AAPB_XSPI1B_DST_UNCERR_CLR,
|
||||
},
|
||||
};
|
||||
|
||||
/* clear XSPI sem error */
|
||||
static void rstsig_xspi_pre_handler(uint32_t rstgen_sig_id)
|
||||
{
|
||||
uint32_t xspi_id = RST_XSPI_1A;
|
||||
|
||||
if (rstgen_sig_id == E3L_RSTSIG_SAF_XSPI1A) {
|
||||
xspi_id = RST_XSPI_1A;
|
||||
}
|
||||
else if (rstgen_sig_id == E3L_RSTSIG_SAF_XSPI1B) {
|
||||
xspi_id = RST_XSPI_1B;
|
||||
}
|
||||
else {
|
||||
return;
|
||||
}
|
||||
|
||||
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][0], 0U);
|
||||
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][2], 0U);
|
||||
(void)readl(xspi_base[xspi_id]);
|
||||
};
|
||||
|
||||
static void rstsig_xspi_post_handler(uint32_t rstgen_sig_id)
|
||||
{
|
||||
uint32_t xspi_id = RST_XSPI_1A;
|
||||
|
||||
if (rstgen_sig_id == E3L_RSTSIG_SAF_XSPI1A) {
|
||||
xspi_id = RST_XSPI_1A;
|
||||
}
|
||||
else if (rstgen_sig_id == E3L_RSTSIG_SAF_XSPI1B) {
|
||||
xspi_id = RST_XSPI_1B;
|
||||
}
|
||||
else {
|
||||
return;
|
||||
}
|
||||
|
||||
udelay(10);
|
||||
(void)readl(xspi_base[xspi_id]);
|
||||
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][1], 1U);
|
||||
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][1], 0U);
|
||||
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][3], 1U);
|
||||
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][3], 0U);
|
||||
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][0], 1U);
|
||||
scr_set(&scr_ctrl, &sig_xspi_scr[xspi_id][2], 1U);
|
||||
}
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_xspi1a = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_XSPI1A,
|
||||
.pre_handler = rstsig_xspi_pre_handler,
|
||||
.post_handler = rstsig_xspi_post_handler,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_xspi1b = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_XSPI1B,
|
||||
.pre_handler = rstsig_xspi_pre_handler,
|
||||
.post_handler = rstsig_xspi_post_handler,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_dma_rst0 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_DMA_RST0,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_dma_rst1 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_DMA_RST1,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_enet1 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_ENET1,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_vic1 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_VIC1,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_xspi_slv = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_XSPI_SLV,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_xtrg = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_XTRG,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_saci2 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_SACI2,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_sehc1 = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_SEHC1,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_usb = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_USB,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_seip = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_SEIP,
|
||||
.need_clr_rst = true,
|
||||
};
|
||||
|
||||
sdrv_rstgen_sig_t rstsig_cslite = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = E3L_RSTSIG_SAF_CSLITE,
|
||||
};
|
||||
|
||||
/* general register */
|
||||
sdrv_rstgen_general_reg_t reset_general_reg_sf_remap = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = 1,
|
||||
};
|
||||
|
||||
sdrv_rstgen_general_reg_t reset_general_reg_sf_boot = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = 7,
|
||||
};
|
||||
|
||||
sdrv_rstgen_general_reg_t reset_general_reg_rom_ctrl = {
|
||||
.rst_ctl = &g_rstgen_saf,
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
/* recovery module */
|
||||
__WEAK sdrv_recovery_btm_t recovery_btm_list = {
|
||||
.btm_num = 4,
|
||||
.btm_base = {
|
||||
APB_BTM1_BASE,
|
||||
APB_BTM2_BASE,
|
||||
APB_BTM3_BASE,
|
||||
APB_BTM4_BASE,
|
||||
},
|
||||
};
|
||||
|
||||
__WEAK sdrv_recovery_etimer_t recovery_etimer_list = {
|
||||
.etimer_num = 2,
|
||||
.etimer_base = {
|
||||
APB_ETMR1_BASE,
|
||||
APB_ETMR2_BASE,
|
||||
},
|
||||
};
|
||||
|
||||
__WEAK sdrv_recovery_epwm_t recovery_epwm_list = {
|
||||
.epwm_num = 2,
|
||||
.epwm_base = {
|
||||
APB_EPWM1_BASE,
|
||||
APB_EPWM2_BASE,
|
||||
},
|
||||
};
|
||||
|
||||
__WEAK sdrv_recovery_module_t recovery_module_array = {
|
||||
.btm_list = &recovery_btm_list,
|
||||
.etimer_list = &recovery_etimer_list,
|
||||
.epwm_list = &recovery_epwm_list,
|
||||
};
|
||||
30
devices/E3106/script/IAR/flashloader_debug.mac
Normal file
30
devices/E3106/script/IAR/flashloader_debug.mac
Normal file
@@ -0,0 +1,30 @@
|
||||
tcm_init(tcma_base, tcmb_base)
|
||||
{
|
||||
__var actlr;
|
||||
|
||||
actlr = __jtagCP15ReadReg(1, 0, 0, 1);
|
||||
actlr &= ~((1 << 25) | (1 << 26) | (1 << 27));
|
||||
__jtagCP15WriteReg(1, 0, 0, 1, actlr);
|
||||
__jtagCP15WriteReg(9, 1, 0, 1, tcma_base | 1);
|
||||
__jtagCP15WriteReg(9, 1, 0, 0, tcmb_base | 1);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserReset()
|
||||
*********************************************************************/
|
||||
execUserReset()
|
||||
{
|
||||
__message "------------------------------ execUserReset ---------------------------------";
|
||||
/* Disable MPU*/
|
||||
__jtagCP15WriteReg(1, 0, 0, 0, 0x08E7087A);
|
||||
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserPreload()
|
||||
*********************************************************************/
|
||||
execUserPreload()
|
||||
{
|
||||
__message "------------------------------ execUserPreload ---------------------------------";
|
||||
tcm_init(0x1900000, 0x1910000);
|
||||
}
|
||||
95
devices/E3106/script/IAR/iram_remap.mac
Normal file
95
devices/E3106/script/IAR/iram_remap.mac
Normal file
@@ -0,0 +1,95 @@
|
||||
__param __sf_addr__=0x504000;
|
||||
|
||||
|
||||
core_remap(addr, start_bit1, start_bit2)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
|
||||
start_bit_val = start_bit1;
|
||||
width = 0x14;
|
||||
val = addr>>12;
|
||||
reg_addr = 0xf08b0000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val&0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val&0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xf08b0000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = start_bit2;
|
||||
width = 0x1;
|
||||
val = 1;
|
||||
reg_addr = 0xf08b0000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xf0670004;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val |= 0x01;
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
sf_remap()
|
||||
{
|
||||
core_remap(__sf_addr__, 0x0, 0x14);
|
||||
}
|
||||
|
||||
|
||||
sf_reset()
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
reg = 0xf08c0000 + 0x1A04;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<6);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
core_start(addr_offset)
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
|
||||
reg = 0xf08c0000 + addr_offset;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<0);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserReset()
|
||||
execUserPreReset()
|
||||
*********************************************************************/
|
||||
execUserPreload()
|
||||
{
|
||||
__message "------------------------------ execUserPreload Remap ---------------------------------";
|
||||
sf_remap();
|
||||
__delay(1000);
|
||||
|
||||
//__message "------------------------------ Reset ---------------------------------";
|
||||
sf_reset();
|
||||
|
||||
__message "------------------------------ Halt CPU by Jlink ---------------------------------";
|
||||
__jlinkExecCommand("Halt");
|
||||
}
|
||||
94
devices/E3106/script/IAR/xip_remap.mac
Normal file
94
devices/E3106/script/IAR/xip_remap.mac
Normal file
@@ -0,0 +1,94 @@
|
||||
__param __sf_addr__=0x100c1000;
|
||||
|
||||
core_remap(addr, start_bit1, start_bit2)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
|
||||
start_bit_val = start_bit1;
|
||||
width = 0x14;
|
||||
val = addr>>12;
|
||||
reg_addr = 0xf08b0000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val&0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val&0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xf08b0000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = start_bit2;
|
||||
width = 0x1;
|
||||
val = 1;
|
||||
reg_addr = 0xf08b0000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xf0670004;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val |= 0x01;
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
sf_remap()
|
||||
{
|
||||
core_remap(__sf_addr__, 0x0, 0x14);
|
||||
}
|
||||
|
||||
|
||||
sf_reset()
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
reg = 0xf08c0000 + 0x1A04;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<6);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
core_start(addr_offset)
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
|
||||
reg = 0xf08c0000 + addr_offset;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<0);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserReset()
|
||||
execUserPreReset()
|
||||
*********************************************************************/
|
||||
execUserPreload()
|
||||
{
|
||||
__message "------------------------------ execUserPreload Remap ---------------------------------";
|
||||
sf_remap();
|
||||
__delay(1000);
|
||||
|
||||
//__message "------------------------------ Reset ---------------------------------";
|
||||
sf_reset();
|
||||
|
||||
__message "------------------------------ Halt CPU by Jlink ---------------------------------";
|
||||
__jlinkExecCommand("Halt");
|
||||
}
|
||||
94
devices/E3106/script/IAR/xip_remap_norflash.mac
Normal file
94
devices/E3106/script/IAR/xip_remap_norflash.mac
Normal file
@@ -0,0 +1,94 @@
|
||||
__param __sf_addr__=0x10008000;
|
||||
|
||||
core_remap(addr, start_bit1, start_bit2)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
|
||||
start_bit_val = start_bit1;
|
||||
width = 0x14;
|
||||
val = addr>>12;
|
||||
reg_addr = 0xf08b0000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val&0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val&0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xf08b0000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = start_bit2;
|
||||
width = 0x1;
|
||||
val = 1;
|
||||
reg_addr = 0xf08b0000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xf0670004;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val |= 0x01;
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
sf_remap()
|
||||
{
|
||||
core_remap(__sf_addr__, 0x0, 0x14);
|
||||
}
|
||||
|
||||
|
||||
sf_reset()
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
reg = 0xf08c0000 + 0x1A04;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<6);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
core_start(addr_offset)
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
|
||||
reg = 0xf08c0000 + addr_offset;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<0);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserReset()
|
||||
execUserPreReset()
|
||||
*********************************************************************/
|
||||
execUserPreload()
|
||||
{
|
||||
__message "------------------------------ execUserPreload Remap ---------------------------------";
|
||||
sf_remap();
|
||||
__delay(1000);
|
||||
|
||||
//__message "------------------------------ Reset ---------------------------------";
|
||||
sf_reset();
|
||||
|
||||
__message "------------------------------ Halt CPU by Jlink ---------------------------------";
|
||||
__jlinkExecCommand("Halt");
|
||||
}
|
||||
227
devices/E3106/startup/gcc/startup.S
Normal file
227
devices/E3106/startup/gcc/startup.S
Normal file
@@ -0,0 +1,227 @@
|
||||
/*
|
||||
* arm_start.S
|
||||
*
|
||||
* Copyright (c) 2020 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Description: ARM start function.
|
||||
*
|
||||
* Revision History:
|
||||
* -----------------
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <armv7-r/arm.h>
|
||||
#include <armv7-r/cache.h>
|
||||
#include <compiler.h>
|
||||
|
||||
.globl __vector
|
||||
.weak Undefined_Handler
|
||||
.weak SWI_Handler
|
||||
.weak Prefetch_Handler
|
||||
.weak Abort_Handler
|
||||
.weak IRQ_Handler
|
||||
.weak FIQ_Handler
|
||||
|
||||
.section .intvec, "ax", %progbits
|
||||
|
||||
.arm
|
||||
|
||||
__vector:
|
||||
LDR PC,Reset_Addr
|
||||
LDR PC,Undefined_Addr
|
||||
LDR PC,SWI_Addr
|
||||
LDR PC,Prefetch_Addr
|
||||
LDR PC,Abort_Addr
|
||||
.word 0
|
||||
LDR PC,IRQ_Addr
|
||||
LDR PC,FIQ_Addr
|
||||
|
||||
Reset_Addr: .word Reset_Handler
|
||||
Undefined_Addr: .word Undefined_Handler
|
||||
SWI_Addr: .word SWI_Handler
|
||||
Prefetch_Addr: .word Prefetch_Handler
|
||||
Abort_Addr: .word Abort_Handler
|
||||
IRQ_Addr: .word IRQ_Handler
|
||||
FIQ_Addr: .word FIQ_Handler
|
||||
|
||||
.section .boot, "ax", %progbits
|
||||
|
||||
FUNCTION(Reset_Handler)
|
||||
/* do some early cpu setup */
|
||||
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r0
|
||||
|
||||
mrc p15, 0, r12, c1, c0, 0
|
||||
bic r12, r12, #(SCTLR_M | SCTLR_A | SCTLR_C)
|
||||
bic r12, r12, #(SCTLR_SW | SCTLR_I | SCTLR_RR)
|
||||
bic r12, r12, #(SCTLR_EE | SCTLR_TE)
|
||||
orr r12, r12, #(SCTLR_Z)
|
||||
#if CONFIG_ARM_HIGHVECTORS
|
||||
orr r12, r12, #(SCTLR_V)
|
||||
#else
|
||||
bic r12, r12, #(SCTLR_V)
|
||||
#endif
|
||||
mcr p15, 0, r12, c1, c0, 0
|
||||
|
||||
/* Configure peripheral ports */
|
||||
mrc p15, 0, r0, c15, c0, 1
|
||||
tst r0, #(0x1F << 2)
|
||||
beq .Lno_normal_axi_pp
|
||||
/* Enable LLPP normal AXI interface */
|
||||
orr r0, r0, #1
|
||||
mcr p15, 0, r0, c15, c0, 1
|
||||
.Lno_normal_axi_pp:
|
||||
mrc p15, 0, r0, c15, c0, 2
|
||||
tst r0, #(0x1F << 2)
|
||||
beq .Lno_virtual_axi_pp
|
||||
/* Enable LLPP virtual AXI interface */
|
||||
orr r0, r0, #1
|
||||
mcr p15, 0, r0, c15, c0, 2
|
||||
.Lno_virtual_axi_pp:
|
||||
mrc p15, 0, r0, c15, c0, 3
|
||||
tst r0, #(0x1F << 2)
|
||||
beq .Lno_ahb_pp
|
||||
/* Enable AHB peripheral interface */
|
||||
orr r0, r0, #1
|
||||
mcr p15, 0, r0, c15, c0, 3
|
||||
.Lno_ahb_pp:
|
||||
|
||||
/* enable tcm before use stacks */
|
||||
#if CONFIG_ARMV7R_USE_TCMA
|
||||
ldr r0, =CONFIG_ARMV7R_TCMA_BASE
|
||||
mov r1, #0
|
||||
#if CONFIG_ARMV7R_TCMA_ECC
|
||||
add r1, #1
|
||||
#endif
|
||||
bl tcma_enable_early
|
||||
#endif
|
||||
|
||||
#if CONFIG_ARMV7R_USE_TCMB
|
||||
ldr r0, =CONFIG_ARMV7R_TCMB_BASE
|
||||
mov r1, #0
|
||||
#if CONFIG_ARMV7R_TCMB_ECC
|
||||
add r1, #1
|
||||
#endif
|
||||
bl tcmb_enable_early
|
||||
#endif
|
||||
|
||||
.Lstack_setup:
|
||||
/* set up the stack for irq, fiq, abort, undefined, system/user, and lastly supervisor mode */
|
||||
mov r12, #0
|
||||
|
||||
/* Setup normal interrupt stack */
|
||||
cpsid i, #MODE_IRQ
|
||||
ldr r12, =__irq_stack_end
|
||||
mov sp, r12
|
||||
|
||||
/* Setup fast interrupt stack */
|
||||
cpsid i, #MODE_FIQ
|
||||
ldr r12, =__fiq_stack_end
|
||||
mov sp, r12
|
||||
|
||||
/* Setup data abort stack */
|
||||
cpsid i, #MODE_ABT
|
||||
ldr r12, =__abt_stack_end
|
||||
mov sp, r12
|
||||
|
||||
/* Setup undefined instruction stack */
|
||||
cpsid i, #MODE_UND
|
||||
ldr r12, =__und_stack_end
|
||||
mov sp, r12
|
||||
|
||||
/* Setup system/user stack */
|
||||
cpsid i, #MODE_SYS
|
||||
ldr r12, =__cstack_end
|
||||
mov sp, r12
|
||||
|
||||
/* Setup supervisor stack */
|
||||
cpsid i, #MODE_SVC
|
||||
ldr r12, =__svc_stack_end
|
||||
mov sp, r12
|
||||
|
||||
#if CONFIG_PM
|
||||
ldr r0, arm_context_restore_const
|
||||
blx r0
|
||||
#endif
|
||||
|
||||
/* enable cache, use stack enable after stack init */
|
||||
#if CONFIG_ARCH_EARLY_ENABLE_ICACHE
|
||||
ldr r0, =ICACHE
|
||||
bl arch_enable_cache
|
||||
#endif
|
||||
|
||||
#if CONFIG_ARCH_EARLY_ENABLE_DCACHE
|
||||
ldr r0, =DCACHE
|
||||
bl arch_enable_cache
|
||||
#endif
|
||||
|
||||
#if CONFIG_EARLYCOPY
|
||||
/* Copy sections from their load address to link address. */
|
||||
ldr r4, =__earlycopy_start
|
||||
ldr r5, =__earlycopy_end
|
||||
.Lsection_loop:
|
||||
cmp r4, r5
|
||||
beq .Lbss_init
|
||||
ldmia r4!, {r0, r1, r2} /* vma, size, lma */
|
||||
mov r6, r0
|
||||
mov r7, r1
|
||||
add r7, r6
|
||||
|
||||
.Lcopy_loop:
|
||||
cmp r6, r7
|
||||
ldrlt r3, [r2], #4
|
||||
strlt r3, [r6], #4
|
||||
blt .Lcopy_loop
|
||||
|
||||
/* Flush cache. */
|
||||
bl arch_clean_cache_range
|
||||
|
||||
b .Lsection_loop
|
||||
#endif
|
||||
|
||||
.Lbss_init:
|
||||
/* clear out the bss */
|
||||
ldr r4, =__bss_start
|
||||
ldr r5, =__bss_end
|
||||
mov r6, #0
|
||||
.Lbss_loop:
|
||||
cmp r4, r5
|
||||
strlt r6, [r4], #4
|
||||
blt .Lbss_loop
|
||||
|
||||
/* change to system mode */
|
||||
cpsid i, #MODE_SYS
|
||||
|
||||
#if CONFIG_ARCH_WITH_FPU
|
||||
bl arm_fpu_enable
|
||||
#endif
|
||||
|
||||
bl copy_intvec
|
||||
|
||||
bl device_init
|
||||
|
||||
bl main
|
||||
b .
|
||||
|
||||
FUNCTION(Undefined_Handler)
|
||||
b Arm_Undefined_Handler
|
||||
|
||||
FUNCTION(SWI_Handler)
|
||||
b Arm_SWI_Handler
|
||||
|
||||
FUNCTION(Prefetch_Handler)
|
||||
b Arm_Prefetch_Handler
|
||||
|
||||
FUNCTION(Abort_Handler)
|
||||
b Arm_Abort_Handler
|
||||
|
||||
FUNCTION(IRQ_Handler)
|
||||
b Arm_IRQ_Handler
|
||||
|
||||
FUNCTION(FIQ_Handler)
|
||||
b Arm_FIQ_Handler
|
||||
|
||||
#if CONFIG_PM
|
||||
arm_context_restore_const: .word arm_context_restore
|
||||
#endif
|
||||
249
devices/E3106/startup/iar/startup.S
Normal file
249
devices/E3106/startup/iar/startup.S
Normal file
@@ -0,0 +1,249 @@
|
||||
/*
|
||||
* startup.S
|
||||
*
|
||||
* Copyright (c) 2020 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Description: ARM start function.
|
||||
*
|
||||
* Revision History:
|
||||
* -----------------
|
||||
*/
|
||||
|
||||
INCLUDE config.h
|
||||
INCLUDE armv7-r/arm.h
|
||||
INCLUDE armv7-r/cache.h
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION IRQ_STACK:DATA:NOROOT(3)
|
||||
SECTION FIQ_STACK:DATA:NOROOT(3)
|
||||
SECTION SVC_STACK:DATA:NOROOT(3)
|
||||
SECTION ABT_STACK:DATA:NOROOT(3)
|
||||
SECTION UND_STACK:DATA:NOROOT(3)
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
PUBLIC __vector
|
||||
PUBLIC __iar_program_start
|
||||
EXTERN tcma_enable_early
|
||||
EXTERN tcmb_enable_early
|
||||
EXTERN arch_enable_cache
|
||||
EXTERN arch_clean_invalidate_dcache_all
|
||||
EXTERN copy_intvec
|
||||
EXTERN call_constructors
|
||||
EXTERN device_init
|
||||
|
||||
EXTERN Arm_Undefined_Handler
|
||||
EXTERN Arm_SWI_Handler
|
||||
EXTERN Arm_Prefetch_Handler
|
||||
EXTERN Arm_Abort_Handler
|
||||
EXTERN Arm_IRQ_Handler
|
||||
EXTERN Arm_FIQ_Handler
|
||||
|
||||
PUBWEAK Undefined_Handler
|
||||
PUBWEAK SWI_Handler
|
||||
PUBWEAK Prefetch_Handler
|
||||
PUBWEAK Abort_Handler
|
||||
PUBWEAK IRQ_Handler
|
||||
PUBWEAK FIQ_Handler
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
__vector:
|
||||
; All default exception handlers (except reset) are
|
||||
; defined as weak symbol definitions.
|
||||
; If a handler is defined by the application it will take precedence.
|
||||
LDR PC,Reset_Addr ; Reset
|
||||
LDR PC,Undefined_Addr ; Undefined instructions
|
||||
LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
|
||||
LDR PC,Prefetch_Addr ; Prefetch abort
|
||||
LDR PC,Abort_Addr ; Data abort
|
||||
DCD 0 ; RESERVED
|
||||
LDR PC,IRQ_Addr ; IRQ
|
||||
LDR PC,FIQ_Addr ; FIQ
|
||||
|
||||
DATA
|
||||
|
||||
Reset_Addr DC32 __iar_program_start
|
||||
Undefined_Addr DC32 Undefined_Handler
|
||||
SWI_Addr DC32 SWI_Handler
|
||||
Prefetch_Addr DC32 Prefetch_Handler
|
||||
Abort_Addr DC32 Abort_Handler
|
||||
IRQ_Addr DC32 IRQ_Handler
|
||||
FIQ_Addr DC32 FIQ_Handler
|
||||
|
||||
SECTION .boot:CODE:NOROOT(2)
|
||||
|
||||
EXTERN main
|
||||
REQUIRE __vector
|
||||
EXTWEAK __iar_data_init3
|
||||
EXTWEAK __iar_init_core
|
||||
EXTWEAK __iar_init_vfp
|
||||
EXTWEAK __iar_argc_argv
|
||||
|
||||
#if CONFIG_PM
|
||||
EXTERN arm_context_restore
|
||||
#endif
|
||||
|
||||
ARM
|
||||
|
||||
__iar_program_start:
|
||||
?cstartup:
|
||||
/* do some early cpu setup */
|
||||
mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
|
||||
msr cpsr_c, r0
|
||||
|
||||
mrc p15, 0, r12, c1, c0, 0
|
||||
bic r12, r12, #(SCTLR_M | SCTLR_A | SCTLR_C)
|
||||
bic r12, r12, #(SCTLR_SW | SCTLR_I | SCTLR_RR)
|
||||
bic r12, r12, #(SCTLR_EE | SCTLR_TE)
|
||||
orr r12, r12, #(SCTLR_Z)
|
||||
#if CONFIG_ARM_HIGHVECTORS
|
||||
orr r12, r12, #(SCTLR_V)
|
||||
#else
|
||||
bic r12, r12, #(SCTLR_V)
|
||||
#endif
|
||||
mcr p15, 0, r12, c1, c0, 0
|
||||
|
||||
/* Configure peripheral ports */
|
||||
mrc p15, 0, r0, c15, c0, 1
|
||||
tst r0, #(0x1F << 2)
|
||||
beq .Lno_normal_axi_pp
|
||||
/* Enable LLPP normal AXI interface */
|
||||
orr r0, r0, #1
|
||||
mcr p15, 0, r0, c15, c0, 1
|
||||
.Lno_normal_axi_pp:
|
||||
mrc p15, 0, r0, c15, c0, 2
|
||||
tst r0, #(0x1F << 2)
|
||||
beq .Lno_virtual_axi_pp
|
||||
/* Enable LLPP virtual AXI interface */
|
||||
orr r0, r0, #1
|
||||
mcr p15, 0, r0, c15, c0, 2
|
||||
.Lno_virtual_axi_pp:
|
||||
mrc p15, 0, r0, c15, c0, 3
|
||||
tst r0, #(0x1F << 2)
|
||||
beq .Lno_ahb_pp
|
||||
/* Enable AHB peripheral interface */
|
||||
orr r0, r0, #1
|
||||
mcr p15, 0, r0, c15, c0, 3
|
||||
.Lno_ahb_pp:
|
||||
|
||||
/* enable tcm before use stacks */
|
||||
#if CONFIG_ARMV7R_USE_TCMA
|
||||
ldr r0, =CONFIG_ARMV7R_TCMA_BASE
|
||||
mov r1, #0
|
||||
#if CONFIG_ARMV7R_TCMA_ECC
|
||||
add r1, #1
|
||||
#endif
|
||||
bl tcma_enable_early
|
||||
#endif
|
||||
|
||||
#if CONFIG_ARMV7R_USE_TCMB
|
||||
ldr r0, =CONFIG_ARMV7R_TCMB_BASE
|
||||
mov r1, #0
|
||||
#if CONFIG_ARMV7R_TCMB_ECC
|
||||
add r1, #1
|
||||
#endif
|
||||
bl tcmb_enable_early
|
||||
#endif
|
||||
|
||||
; Initialize the stack pointers.
|
||||
; The pattern below can be used for any of the exception stacks:
|
||||
; FIQ, IRQ, SVC, ABT, UND, SYS.
|
||||
; The USR mode uses the same stack as SYS.
|
||||
; The stack segments must be defined in the linker command file,
|
||||
; and be declared above.
|
||||
cps #MODE_SVC ; Set Supervisor mode bits
|
||||
ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK
|
||||
|
||||
cps #MODE_ABT ; Change the mode
|
||||
ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK
|
||||
|
||||
cps #MODE_UND ; Change the mode
|
||||
ldr sp,=SFE(UND_STACK) ; End of UND_STACK
|
||||
|
||||
cps #MODE_FIQ ; Change the mode
|
||||
ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK
|
||||
|
||||
cps #MODE_IRQ ; Change the mode
|
||||
ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK
|
||||
|
||||
cps #MODE_SYS ; Change the mode
|
||||
ldr sp,=SFE(CSTACK) ; End of CSTACK
|
||||
|
||||
#if CONFIG_PM
|
||||
cps #MODE_SVC ; Set Supervisor mode bits
|
||||
|
||||
ldr r0, arm_context_restore_const
|
||||
blx r0
|
||||
#endif
|
||||
|
||||
/* enable cache, use stack enable after stack init */
|
||||
#if CONFIG_ARCH_EARLY_ENABLE_ICACHE
|
||||
ldr r0, =ICACHE
|
||||
bl arch_enable_cache
|
||||
#endif
|
||||
|
||||
#if CONFIG_ARCH_EARLY_ENABLE_DCACHE
|
||||
ldr r0, =DCACHE
|
||||
bl arch_enable_cache
|
||||
#endif
|
||||
|
||||
/* Turn on core features assumed to be enabled */
|
||||
FUNCALL __iar_program_start, __iar_init_core
|
||||
bl __iar_init_core
|
||||
|
||||
/* Initialize VFP (if needed) */
|
||||
FUNCALL __iar_program_start, __iar_init_vfp
|
||||
bl __iar_init_vfp
|
||||
|
||||
/* Execute relocations & zero BSS */
|
||||
FUNCALL __iar_program_start, __iar_data_init3
|
||||
bl __iar_data_init3
|
||||
|
||||
#if CONFIG_ARCH_EARLY_ENABLE_DCACHE
|
||||
bl arch_clean_invalidate_dcache_all
|
||||
#endif
|
||||
|
||||
/* Setup command line */
|
||||
mov r0, #0
|
||||
FUNCALL __iar_program_start, __iar_argc_argv
|
||||
bl __iar_argc_argv
|
||||
|
||||
/* change to system mode */
|
||||
cpsid i, #MODE_SYS
|
||||
|
||||
FUNCALL __iar_program_start, copy_intvec
|
||||
bl copy_intvec
|
||||
|
||||
FUNCALL __iar_program_start, device_init
|
||||
bl device_init
|
||||
|
||||
FUNCALL __iar_program_start, main
|
||||
bl main
|
||||
b .
|
||||
|
||||
Undefined_Handler:
|
||||
b Arm_Undefined_Handler
|
||||
|
||||
SWI_Handler:
|
||||
b Arm_SWI_Handler
|
||||
|
||||
Prefetch_Handler:
|
||||
b Arm_Prefetch_Handler
|
||||
|
||||
Abort_Handler:
|
||||
b Arm_Abort_Handler
|
||||
|
||||
IRQ_Handler:
|
||||
b Arm_IRQ_Handler
|
||||
|
||||
FIQ_Handler:
|
||||
b Arm_FIQ_Handler
|
||||
|
||||
#if CONFIG_PM
|
||||
arm_context_restore_const DC32 arm_context_restore
|
||||
#endif
|
||||
|
||||
END
|
||||
88
devices/include/bits.h
Normal file
88
devices/include/bits.h
Normal file
@@ -0,0 +1,88 @@
|
||||
/*
|
||||
* Copyright (c) 2008 Travis Geiselbrecht
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files
|
||||
* (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef DEV_BITS_H
|
||||
#define DEV_BITS_H
|
||||
|
||||
#include <types.h>
|
||||
#include <compiler.h>
|
||||
#include <armv7-r/atomic.h>
|
||||
|
||||
#define BIT(x, bit) ((x) & (1UL << (bit)))
|
||||
#define BIT_SHIFT(x, bit) (((x) >> (bit)) & 1)
|
||||
#define BITS(x, high, low) ((x) & (((1UL<<((high)+1))-1) & ~((1UL<<(low))-1)))
|
||||
#define BITS_SHIFT(x, high, low) (((x) >> (low)) & ((1UL<<((high)-(low)+1))-1))
|
||||
#define BIT_SET(x, bit) (((x) & (1UL << (bit))) ? 1 : 0)
|
||||
|
||||
#define BITMAP_BITS_PER_WORD (sizeof(unsigned long) * 8)
|
||||
#define BITMAP_NUM_WORDS(x) (((x) + BITMAP_BITS_PER_WORD - 1) / BITMAP_BITS_PER_WORD)
|
||||
#define BITMAP_WORD(x) ((x) / BITMAP_BITS_PER_WORD)
|
||||
#define BITMAP_BIT_IN_WORD(x) ((x) & (BITMAP_BITS_PER_WORD - 1))
|
||||
|
||||
#define BITMAP_BITS_PER_INT (sizeof(unsigned int) * 8)
|
||||
#define BITMAP_BIT_IN_INT(x) ((x) & (BITMAP_BITS_PER_INT - 1))
|
||||
#define BITMAP_INT(x) ((x) / BITMAP_BITS_PER_INT)
|
||||
|
||||
#define BIT_MASK(x) (((x) >= sizeof(unsigned long) * 8) ? (0UL-1) : ((1UL << (x)) - 1))
|
||||
|
||||
static inline int bitmap_set(unsigned long *bitmap, int bit)
|
||||
{
|
||||
unsigned long mask = 1UL << BITMAP_BIT_IN_INT(bit);
|
||||
return arch_atomic_or(&((int *)bitmap)[BITMAP_INT(bit)], mask) & mask ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline int bitmap_clear(unsigned long *bitmap, int bit)
|
||||
{
|
||||
unsigned long mask = 1UL << BITMAP_BIT_IN_INT(bit);
|
||||
|
||||
return arch_atomic_and(&((int *)bitmap)[BITMAP_INT(bit)], ~mask) & mask ? 1:0;
|
||||
}
|
||||
|
||||
static inline int bitmap_test(unsigned long *bitmap, int bit)
|
||||
{
|
||||
return BIT_SET(bitmap[BITMAP_WORD(bit)], BITMAP_BIT_IN_WORD(bit));
|
||||
}
|
||||
|
||||
/* find first zero bit starting from LSB */
|
||||
static inline unsigned long _ffz(unsigned long x)
|
||||
{
|
||||
/* only for gcc, TODO */
|
||||
return __builtin_ffsl(~x) - 1;
|
||||
}
|
||||
|
||||
static inline int bitmap_ffz(unsigned long *bitmap, int numbits)
|
||||
{
|
||||
uint32_t i;
|
||||
int bit;
|
||||
|
||||
for (i = 0; i < BITMAP_NUM_WORDS(numbits); i++) {
|
||||
if (bitmap[i] == ~0UL)
|
||||
continue;
|
||||
bit = i * BITMAP_BITS_PER_WORD + _ffz(bitmap[i]);
|
||||
if (bit < numbits)
|
||||
return bit;
|
||||
return -1;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
80
devices/include/common.h
Normal file
80
devices/include/common.h
Normal file
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* common.h
|
||||
*
|
||||
* Copyright (c) 2020 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Description: common interface.
|
||||
*
|
||||
* Revision History:
|
||||
* -----------------
|
||||
*/
|
||||
|
||||
#ifndef COMMON_H
|
||||
#define COMMON_H
|
||||
|
||||
#include "part.h"
|
||||
#include "reg.h"
|
||||
#include "regs_base.h"
|
||||
|
||||
#if (CONFIG_E3 || CONFIG_D3 || CONFIG_E3L)
|
||||
|
||||
#define FUSE0_OFFSET 0x1000
|
||||
|
||||
/* Product ID fuse index, starting from address 0x18.
|
||||
* 0x18: PRODUCT_MINOR_ID
|
||||
* 0x19: PRODUCT_MAJOR_ID
|
||||
* 0x1A: [3:0] MASK_MINOR_ID, [7:4] MASK_MAJOR_ID
|
||||
*/
|
||||
#define PART_FUSE_INDEX 0x6
|
||||
#define V_MAJOR_MASK 0x00f00000
|
||||
#define V_MAJOR_POS 20
|
||||
#define V_MINOR_MASK 0x000f0000
|
||||
#define V_MINOR_POS 16
|
||||
|
||||
#ifndef ASSEMBLY
|
||||
|
||||
#if (CONFIG_E3 || CONFIG_D3)
|
||||
#define IS_1P1 (sdrv_fuse_get_major_chipid() == 0 && \
|
||||
sdrv_fuse_get_minor_chipid() == 1)
|
||||
#define IS_1P0 (sdrv_fuse_get_major_chipid() == 0 && \
|
||||
sdrv_fuse_get_minor_chipid() == 0)
|
||||
#define IS_P1 (sdrv_fuse_get_minor_chipid() == 1)
|
||||
#define IS_P0 (sdrv_fuse_get_minor_chipid() == 0)
|
||||
|
||||
#elif (CONFIG_E3L)
|
||||
#define IS_1P1 (sdrv_fuse_get_major_chipid() == 0 && \
|
||||
sdrv_fuse_get_minor_chipid() == 2)
|
||||
#define IS_1P0 (sdrv_fuse_get_major_chipid() == 0 && \
|
||||
sdrv_fuse_get_minor_chipid() <= 1)
|
||||
#define IS_P1 (sdrv_fuse_get_minor_chipid() == 2)
|
||||
#define IS_P0 (sdrv_fuse_get_minor_chipid() <= 1)
|
||||
|
||||
#endif
|
||||
|
||||
static inline uint32_t fuse_get_version(void)
|
||||
{
|
||||
return readl(APB_EFUSEC_BASE + FUSE0_OFFSET + PART_FUSE_INDEX * 4);
|
||||
}
|
||||
|
||||
static inline uint8_t sdrv_fuse_get_minor_chipid(void)
|
||||
{
|
||||
uint32_t info = fuse_get_version();
|
||||
uint8_t minor_id = (info & V_MINOR_MASK) >> V_MINOR_POS;
|
||||
|
||||
return minor_id;
|
||||
}
|
||||
|
||||
static inline uint8_t sdrv_fuse_get_major_chipid(void)
|
||||
{
|
||||
uint32_t info = fuse_get_version();
|
||||
uint8_t major_id = (info & V_MAJOR_MASK) >> V_MAJOR_POS;
|
||||
|
||||
return major_id;
|
||||
}
|
||||
|
||||
#endif /* !ASSEMBLY */
|
||||
|
||||
#endif /* CONFIG_E3 || CONFIG_D3 || CONFIG_E3L */
|
||||
|
||||
#endif /* !COMMON_H */
|
||||
271
devices/include/compiler.h
Normal file
271
devices/include/compiler.h
Normal file
@@ -0,0 +1,271 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2013 Travis Geiselbrecht
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files
|
||||
* (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _INCLUDE_COMPILER_H
|
||||
#define _INCLUDE_COMPILER_H
|
||||
|
||||
#ifndef ASSEMBLY
|
||||
|
||||
#if __GNUC__
|
||||
|
||||
#define likely(x) __builtin_expect(!!(x), 1)
|
||||
#define unlikely(x) __builtin_expect(!!(x), 0)
|
||||
#define __ASM __asm__
|
||||
#define __INLINE inline
|
||||
#define __STATIC_INLINE static inline
|
||||
#define __USED __attribute__((__used__))
|
||||
#define __UNUSED __attribute__((__unused__))
|
||||
#define __PACKED __attribute__((packed))
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#define __PRINTFLIKE(__fmt,__varargs) __attribute__((__format__ (__printf__, __fmt, __varargs)))
|
||||
#define __SCANFLIKE(__fmt,__varargs) __attribute__((__format__ (__scanf__, __fmt, __varargs)))
|
||||
#define __SECTION(x) __attribute((section(x)))
|
||||
#define __PURE __attribute((pure))
|
||||
#define __CONST __attribute((const))
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#define __MALLOC __attribute__((malloc))
|
||||
#define __WEAK __attribute__((weak))
|
||||
#define __GNU_INLINE __attribute__((gnu_inline))
|
||||
#define __GET_CALLER(x) __builtin_return_address(0)
|
||||
#define __GET_FRAME(x) __builtin_frame_address(0)
|
||||
#define __NAKED __attribute__((naked))
|
||||
#define __ISCONSTANT(x) __builtin_constant_p(x)
|
||||
#define __NO_INLINE __attribute((noinline))
|
||||
#define __SRAM __NO_INLINE __SECTION(".sram.text")
|
||||
#define __CONSTRUCTOR __attribute__((constructor))
|
||||
#define __DESTRUCTOR __attribute__((destructor))
|
||||
#define __OPTIMIZE(x) __attribute__((optimize(x)))
|
||||
|
||||
#define INCBIN(symname, sizename, filename, section) \
|
||||
__asm__ (".section " section "; .align 4; .globl "#symname); \
|
||||
__asm__ (""#symname ":\n.incbin \"" filename "\""); \
|
||||
__asm__ (".section " section "; .align 1;"); \
|
||||
__asm__ (""#symname "_end:"); \
|
||||
__asm__ (".section " section "; .align 4; .globl "#sizename); \
|
||||
__asm__ (""#sizename ": .long "#symname "_end - "#symname " - 1"); \
|
||||
extern unsigned char symname[]; \
|
||||
extern unsigned int sizename
|
||||
|
||||
#define INCFILE(symname, sizename, filename) INCBIN(symname, sizename, filename, ".rodata")
|
||||
|
||||
/* look for gcc 3.0 and above */
|
||||
#if (__GNUC__ > 3) || (__GNUC__ == 3 && __GNUC_MINOR__ >= 0)
|
||||
#define __ALWAYS_INLINE __attribute__((always_inline))
|
||||
#else
|
||||
#define __ALWAYS_INLINE
|
||||
#endif
|
||||
|
||||
/* look for gcc 3.1 and above */
|
||||
#if !defined(__DEPRECATED) // seems to be built in in some versions of the compiler
|
||||
#if (__GNUC__ > 3) || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1)
|
||||
#define __DEPRECATED __attribute((deprecated))
|
||||
#else
|
||||
#define __DEPRECATED
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* look for gcc 3.3 and above */
|
||||
#if (__GNUC__ > 3) || (__GNUC__ == 3 && __GNUC_MINOR__ >= 3)
|
||||
/* the may_alias attribute was introduced in gcc 3.3; before that, there
|
||||
* was no way to specify aliasiang rules on a type-by-type basis */
|
||||
#define __MAY_ALIAS __attribute__((may_alias))
|
||||
|
||||
/* nonnull was added in gcc 3.3 as well */
|
||||
#define __NONNULL(x) __attribute((nonnull x))
|
||||
#else
|
||||
#define __MAY_ALIAS
|
||||
#define __NONNULL(x)
|
||||
#endif
|
||||
|
||||
/* look for gcc 3.4 and above */
|
||||
#if (__GNUC__ > 3) || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
|
||||
#define __WARN_UNUSED_RESULT __attribute((warn_unused_result))
|
||||
#else
|
||||
#define __WARN_UNUSED_RESULT
|
||||
#endif
|
||||
|
||||
#if ((__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) && !defined(__clang__))
|
||||
#define __EXTERNALLY_VISIBLE __attribute__((externally_visible))
|
||||
#else
|
||||
#define __EXTERNALLY_VISIBLE
|
||||
#endif
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) || defined(__clang__)
|
||||
#define __UNREACHABLE __builtin_unreachable()
|
||||
#else
|
||||
#define __UNREACHABLE
|
||||
#endif
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)
|
||||
#ifdef __cplusplus
|
||||
#define STATIC_ASSERT(e) static_assert(e, #e)
|
||||
#else
|
||||
#define STATIC_ASSERT(e) _Static_assert(e, #e)
|
||||
#endif
|
||||
#else
|
||||
#define STATIC_ASSERT(e) extern char (*ct_assert(void)) [sizeof(char[1 - 2*!(e)])]
|
||||
#endif
|
||||
|
||||
/* compiler fence */
|
||||
#define CF do { __asm__ volatile("" ::: "memory"); } while(0)
|
||||
|
||||
#define __WEAK_ALIAS(x) __attribute__((weak, alias(x)))
|
||||
#define __ALIAS(x) __attribute__((alias(x)))
|
||||
|
||||
#define __LOCAL __attribute__ ((visibility("hidden")))
|
||||
|
||||
#define __THREAD __thread
|
||||
|
||||
#define __NOP __asm__ volatile("nop")
|
||||
|
||||
#define __BKPT __asm ("BKPT #0\n\t")
|
||||
|
||||
#define __ARM __attribute__((target("arm")))
|
||||
|
||||
#elif __ICCARM__
|
||||
|
||||
#include <intrinsics.h>
|
||||
#include <lnk_sym.h>
|
||||
|
||||
#ifdef __aarch64__
|
||||
static inline int __RBIT(int x) {
|
||||
int ret;
|
||||
asm("rbit %w0, %w1" :"=r"(ret) :"r"(x));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline int __CLZ(int x) {
|
||||
int ret;
|
||||
asm("clz %w0, %w1" :"=r"(ret) :"r"(x));
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline int _bin_fls(int x) {
|
||||
int i = __CLZ(x);
|
||||
return 32 - i;
|
||||
}
|
||||
|
||||
static inline int _bin_ffs(int x) {
|
||||
unsigned long __t = (x);
|
||||
return _bin_fls(__t & -__t);
|
||||
}
|
||||
|
||||
static inline int _bin_ctz(int x) {
|
||||
x = __RBIT(x);
|
||||
return __CLZ(x);
|
||||
}
|
||||
|
||||
#define likely(x) (x)
|
||||
#define unlikely(x) (x)
|
||||
#define __ASM asm
|
||||
#define __INLINE inline
|
||||
#define __STATIC_INLINE static inline
|
||||
#define __USED __root
|
||||
#define __UNUSED __attribute__((__unused__))
|
||||
#define __PACKED __attribute__((packed))
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#define __SECTION(x) __attribute__((section(x)))
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#define __ALWAYS_INLINE __attribute__((always_inline))
|
||||
#define __NO_INLINE __attribute__((noinline))
|
||||
#define __SRAM __NO_INLINE __SECTION(".sram.text")
|
||||
#define __CONSTRUCTOR __attribute__((constructor))
|
||||
#define __DEPRECATED __attribute__((deprecated))
|
||||
#define __offsetof(type, field) offsetof(type, field)
|
||||
|
||||
#define __PRINTFLIKE(__fmt,__varargs)
|
||||
#define __SCANFLIKE(__fmt,__varargs)
|
||||
#define __GET_CALLER(x) ((void *)__FILE__)
|
||||
#define __CONST
|
||||
#define __PURE
|
||||
#define __MALLOC
|
||||
#define __NONNULL(x)
|
||||
#define __EXTERNALLY_VISIBLE
|
||||
#define __UNREACHABLE
|
||||
#define __builtin_clz __CLZ
|
||||
#define __builtin_ffs(x) _bin_ffs(x)
|
||||
#define __builtin_ffsl(x) _bin_ffs(x)
|
||||
#define __builtin_ctz(x) _bin_ctz(x)
|
||||
#define __builtin_clzll __CLZ
|
||||
|
||||
#define STATIC_ASSERT(e) _Static_assert(e, #e)
|
||||
|
||||
#define CF do { asm volatile("" ::: "memory"); } while(0)
|
||||
|
||||
#define __NOP asm("nop")
|
||||
|
||||
#define __BKPT __asm ("BKPT #0\n\t")
|
||||
|
||||
#define __ARM __arm
|
||||
|
||||
#else
|
||||
|
||||
#define likely(x) (x)
|
||||
#define unlikely(x) (x)
|
||||
#define __ASM
|
||||
#define __INLINE
|
||||
#define __STATIC_INLINE
|
||||
#define __USED
|
||||
#define __UNUSED
|
||||
#define __PACKED
|
||||
#define __ALIGNED(x)
|
||||
#define __PRINTFLIKE(__fmt,__varargs)
|
||||
#define __SCANFLIKE(__fmt,__varargs)
|
||||
#define __SECTION(x)
|
||||
#define __PURE
|
||||
#define __CONST
|
||||
#define __NONNULL(x)
|
||||
#define __DEPRECATED
|
||||
#define __WARN_UNUSED_RESULT
|
||||
#define __ALWAYS_INLINE
|
||||
#define __MAY_ALIAS
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#if __GNUC__
|
||||
|
||||
#define FUNCTION(x) .global x; .type x,STT_FUNC; x:
|
||||
#define DATA(x) .global x; .type x,STT_OBJECT; x:
|
||||
|
||||
#define LOCAL_FUNCTION(x) .type x,STT_FUNC; x:
|
||||
#define LOCAL_DATA(x) .type x,STT_OBJECT; x:
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* TODO: add type check */
|
||||
#define countof(a) (sizeof(a) / sizeof((a)[0]))
|
||||
|
||||
/* CPP header guards */
|
||||
#ifdef __cplusplus
|
||||
#define __BEGIN_CDECLS extern "C" {
|
||||
#define __END_CDECLS }
|
||||
#else
|
||||
#define __BEGIN_CDECLS
|
||||
#define __END_CDECLS
|
||||
#endif
|
||||
|
||||
#endif
|
||||
76
devices/include/debug.h
Normal file
76
devices/include/debug.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* debug.h
|
||||
*
|
||||
* Copyright (c) 2020 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Description: debug interface.
|
||||
*
|
||||
* Revision History:
|
||||
* -----------------
|
||||
*/
|
||||
|
||||
#ifndef _INCLUDE_DEBUG_H
|
||||
#define _INCLUDE_DEBUG_H
|
||||
|
||||
#include <types.h>
|
||||
#include <stdio.h>
|
||||
#include <compiler.h>
|
||||
#include <param.h>
|
||||
#include <ctype.h>
|
||||
|
||||
/* SSDK debug level */
|
||||
#define SSDK_EMERG 0 /* System is unusable */
|
||||
#define SSDK_ALERT 1 /* Action must be taken immediately */
|
||||
#define SSDK_CRIT 2 /* Critical conditions */
|
||||
#define SSDK_ERR 3 /* Error conditions */
|
||||
#define SSDK_WARNING 4 /* Warning conditions */
|
||||
#define SSDK_NOTICE 5 /* Normal, but significant, condition */
|
||||
#define SSDK_INFO 6 /* Informational message */
|
||||
#define SSDK_DEBUG 7 /* Debug-level message */
|
||||
|
||||
/* SSDK printf */
|
||||
#if CONFIG_DEBUG
|
||||
#if CONFIG_PRINTF_LIB
|
||||
#include <printf/printf.h>
|
||||
#else
|
||||
#define printf(x...)
|
||||
#endif
|
||||
#define ssdk_printf(level, x...) do { if ((level) <= CONFIG_DEBUG_LEVEL) {printf(x); } } while (0)
|
||||
#define PANIC() ssdk_panic((const uint8_t *)__FILE__, (int)__LINE__)
|
||||
#define ASSERT(x) do { if (!(x)) PANIC(); } while (0)
|
||||
|
||||
static void ssdk_panic(const uint8_t *filename, int linenum)
|
||||
{
|
||||
ssdk_printf(SSDK_EMERG, "Assertion failed at file:%s line: %d\r\n",
|
||||
filename, linenum);
|
||||
__BKPT;
|
||||
for(;;);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief hex dump function
|
||||
*
|
||||
* @param[in] ptr: dump data address
|
||||
* @param[in] len: dump data length
|
||||
*/
|
||||
void hexdump(const void *ptr, size_t len);
|
||||
|
||||
/**
|
||||
* @brief hex dump8 function with display address
|
||||
*
|
||||
* @param[in] ptr: ptr dump data address
|
||||
* @param[in] len: len dump data length
|
||||
* @param[in] addr: disp_addr display address
|
||||
*/
|
||||
void hexdump8_ex(const void *ptr, size_t len, uint64_t addr);
|
||||
|
||||
#else
|
||||
#define ssdk_printf(level, x...)
|
||||
#define PANIC()
|
||||
#define ASSERT(x)
|
||||
#define hexdump(ptr, len)
|
||||
#define hexdump8_ex(ptr, len, disp_addr)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
189
devices/include/errno.h
Normal file
189
devices/include/errno.h
Normal file
@@ -0,0 +1,189 @@
|
||||
/*
|
||||
* errno.h
|
||||
*
|
||||
* Copyright (c) 2021 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Description: errno defines.
|
||||
*
|
||||
* Revision History:
|
||||
* -----------------
|
||||
*/
|
||||
|
||||
#ifndef DEV_ERRNO_H
|
||||
#define DEV_ERRNO_H
|
||||
|
||||
#if defined(__GNUC__) && !defined(__SES_ARM)
|
||||
|
||||
#include <sys/errno.h>
|
||||
|
||||
#else
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#include <c/errno.h>
|
||||
#define ERR_BASE _NERR
|
||||
#else
|
||||
#define ERR_BASE 0
|
||||
#endif
|
||||
|
||||
#if defined(__SES_ARM)
|
||||
#include "__SEGGER_RTL.h"
|
||||
#define errno (*__SEGGER_RTL_X_errno_addr())
|
||||
#endif
|
||||
|
||||
#define EPERM (ERR_BASE + 1)
|
||||
#define ENOENT (ERR_BASE + 2)
|
||||
#define ESRCH (ERR_BASE + 3)
|
||||
#define EINTR (ERR_BASE + 4)
|
||||
#define EIO (ERR_BASE + 5)
|
||||
#define ENXIO (ERR_BASE + 6)
|
||||
#define E2BIG (ERR_BASE + 7)
|
||||
#define ENOEXEC (ERR_BASE + 8)
|
||||
#define EBADF (ERR_BASE + 9)
|
||||
#define ECHILD (ERR_BASE + 10)
|
||||
#define EAGAIN (ERR_BASE + 11)
|
||||
|
||||
#ifndef ENOMEM
|
||||
#define ENOMEM (ERR_BASE + 12)
|
||||
#endif
|
||||
|
||||
#define EACCES (ERR_BASE + 13)
|
||||
#define EFAULT (ERR_BASE + 14)
|
||||
#define ENOTBLK (ERR_BASE + 15)
|
||||
#define EBUSY (ERR_BASE + 16)
|
||||
#define EEXIST (ERR_BASE + 17)
|
||||
#define EXDEV (ERR_BASE + 18)
|
||||
#define ENODEV (ERR_BASE + 19)
|
||||
#define ENOTDIR (ERR_BASE + 20)
|
||||
#define EISDIR (ERR_BASE + 21)
|
||||
|
||||
#ifndef EINVAL
|
||||
#define EINVAL (ERR_BASE + 22)
|
||||
#endif
|
||||
|
||||
#define ENFILE (ERR_BASE + 23)
|
||||
#define EMFILE (ERR_BASE + 24)
|
||||
#define ENOTTY (ERR_BASE + 25)
|
||||
#define ETXTBSY (ERR_BASE + 26)
|
||||
#define EFBIG (ERR_BASE + 27)
|
||||
#define ENOSPC (ERR_BASE + 28)
|
||||
#define ESPIPE (ERR_BASE + 29)
|
||||
#define EROFS (ERR_BASE + 30)
|
||||
#define EMLINK (ERR_BASE + 31)
|
||||
#define EPIPE (ERR_BASE + 32)
|
||||
|
||||
#ifndef EDOM
|
||||
#define EDOM (ERR_BASE + 33)
|
||||
#endif
|
||||
|
||||
#ifndef ERANGE
|
||||
#define ERANGE (ERR_BASE + 34)
|
||||
#endif
|
||||
|
||||
#define EDEADLK (ERR_BASE + 35)
|
||||
#define ENAMETOOLONG (ERR_BASE + 36)
|
||||
#define ENOLCK (ERR_BASE + 37)
|
||||
#define ENOSYS (ERR_BASE + 38)
|
||||
#define ENOTEMPTY (ERR_BASE + 39)
|
||||
#define ELOOP (ERR_BASE + 40)
|
||||
#define EWOULDBLOCK EAGAIN
|
||||
#define ENOMSG (ERR_BASE + 42)
|
||||
#define EIDRM (ERR_BASE + 43)
|
||||
#define ECHRNG (ERR_BASE + 44)
|
||||
#define EL2NSYNC (ERR_BASE + 45)
|
||||
#define EL3HLT (ERR_BASE + 46)
|
||||
#define EL3RST (ERR_BASE + 47)
|
||||
#define ELNRNG (ERR_BASE + 48)
|
||||
#define EUNATCH (ERR_BASE + 49)
|
||||
#define ENOCSI (ERR_BASE + 50)
|
||||
#define EL2HLT (ERR_BASE + 51)
|
||||
#define EBADE (ERR_BASE + 52)
|
||||
#define EBADR (ERR_BASE + 53)
|
||||
#define EXFULL (ERR_BASE + 54)
|
||||
#define ENOANO (ERR_BASE + 55)
|
||||
#define EBADRQC (ERR_BASE + 56)
|
||||
#define EBADSLT (ERR_BASE + 57)
|
||||
#define EDEADLOCK EDEADLK
|
||||
#define EBFONT (ERR_BASE + 59)
|
||||
#define ENOSTR (ERR_BASE + 60)
|
||||
#define ENODATA (ERR_BASE + 61)
|
||||
#define ETIME (ERR_BASE + 62)
|
||||
#define ENOSR (ERR_BASE + 63)
|
||||
#define ENONET (ERR_BASE + 64)
|
||||
#define ENOPKG (ERR_BASE + 65)
|
||||
#define EREMOTE (ERR_BASE + 66)
|
||||
#define ENOLINK (ERR_BASE + 67)
|
||||
#define EADV (ERR_BASE + 68)
|
||||
#define ESRMNT (ERR_BASE + 69)
|
||||
#define ECOMM (ERR_BASE + 70)
|
||||
#define EPROTO (ERR_BASE + 71)
|
||||
#define EMULTIHOP (ERR_BASE + 72)
|
||||
#define EDOTDOT (ERR_BASE + 73)
|
||||
#define EBADMSG (ERR_BASE + 74)
|
||||
#define EOVERFLOW (ERR_BASE + 75)
|
||||
#define ENOTUNIQ (ERR_BASE + 76)
|
||||
#define EBADFD (ERR_BASE + 77)
|
||||
#define EREMCHG (ERR_BASE + 78)
|
||||
#define ELIBACC (ERR_BASE + 79)
|
||||
#define ELIBBAD (ERR_BASE + 80)
|
||||
#define ELIBSCN (ERR_BASE + 81)
|
||||
#define ELIBMAX (ERR_BASE + 82)
|
||||
#define ELIBEXEC (ERR_BASE + 83)
|
||||
|
||||
#ifndef EILSEQ
|
||||
#define EILSEQ (ERR_BASE + 84)
|
||||
#endif
|
||||
|
||||
#define ERESTART (ERR_BASE + 85)
|
||||
#define ESTRPIPE (ERR_BASE + 86)
|
||||
#define EUSERS (ERR_BASE + 87)
|
||||
#define ENOTSOCK (ERR_BASE + 88)
|
||||
#define EDESTADDRREQ (ERR_BASE + 89)
|
||||
#define EMSGSIZE (ERR_BASE + 90)
|
||||
#define EPROTOTYPE (ERR_BASE + 91)
|
||||
#define ENOPROTOOPT (ERR_BASE + 92)
|
||||
#define EPROTONOSUPPORT (ERR_BASE + 93)
|
||||
#define ESOCKTNOSUPPORT (ERR_BASE + 94)
|
||||
#define EOPNOTSUPP (ERR_BASE + 95)
|
||||
#define ENOTSUP EOPNOTSUPP
|
||||
#define EPFNOSUPPORT (ERR_BASE + 96)
|
||||
#define EAFNOSUPPORT (ERR_BASE + 97)
|
||||
#define EADDRINUSE (ERR_BASE + 98)
|
||||
#define EADDRNOTAVAIL (ERR_BASE + 99)
|
||||
#define ENETDOWN (ERR_BASE + 100)
|
||||
#define ENETUNREACH (ERR_BASE + 101)
|
||||
#define ENETRESET (ERR_BASE + 102)
|
||||
#define ECONNABORTED (ERR_BASE + 103)
|
||||
#define ECONNRESET (ERR_BASE + 104)
|
||||
#define ENOBUFS (ERR_BASE + 105)
|
||||
#define EISCONN (ERR_BASE + 106)
|
||||
#define ENOTCONN (ERR_BASE + 107)
|
||||
#define ESHUTDOWN (ERR_BASE + 108)
|
||||
#define ETOOMANYREFS (ERR_BASE + 109)
|
||||
#define ETIMEDOUT (ERR_BASE + 110)
|
||||
#define ECONNREFUSED (ERR_BASE + 111)
|
||||
#define EHOSTDOWN (ERR_BASE + 112)
|
||||
#define EHOSTUNREACH (ERR_BASE + 113)
|
||||
#define EALREADY (ERR_BASE + 114)
|
||||
#define EINPROGRESS (ERR_BASE + 115)
|
||||
#define ESTALE (ERR_BASE + 116)
|
||||
#define EUCLEAN (ERR_BASE + 117)
|
||||
#define ENOTNAM (ERR_BASE + 118)
|
||||
#define ENAVAIL (ERR_BASE + 119)
|
||||
#define EISNAM (ERR_BASE + 120)
|
||||
#define EREMOTEIO (ERR_BASE + 121)
|
||||
#define EDQUOT (ERR_BASE + 122)
|
||||
#define ENOMEDIUM (ERR_BASE + 123)
|
||||
#define EMEDIUMTYPE (ERR_BASE + 124)
|
||||
#define ECANCELED (ERR_BASE + 125)
|
||||
#define ENOKEY (ERR_BASE + 126)
|
||||
#define EKEYEXPIRED (ERR_BASE + 127)
|
||||
#define EKEYREVOKED (ERR_BASE + 128)
|
||||
#define EKEYREJECTED (ERR_BASE + 129)
|
||||
#define EOWNERDEAD (ERR_BASE + 130)
|
||||
#define ENOTRECOVERABLE (ERR_BASE + 131)
|
||||
#define ERFKILL (ERR_BASE + 132)
|
||||
#define EHWPOISON (ERR_BASE + 133)
|
||||
#endif
|
||||
|
||||
#endif /* DEV_ERRNO_H */
|
||||
288
devices/include/lib/list.h
Normal file
288
devices/include/lib/list.h
Normal file
@@ -0,0 +1,288 @@
|
||||
/*
|
||||
* Copyright (c) 2008 Travis Geiselbrecht
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files
|
||||
* (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef INCLUDE_LIST_H
|
||||
#define INCLUDE_LIST_H
|
||||
|
||||
#include <compiler.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
__BEGIN_CDECLS;
|
||||
|
||||
#define containerof(ptr, type, member) \
|
||||
((type *)((uintptr_t)(ptr) - offsetof(type, member)))
|
||||
|
||||
struct list_node {
|
||||
struct list_node *prev;
|
||||
struct list_node *next;
|
||||
};
|
||||
|
||||
#define LIST_INITIAL_VALUE(list) { &(list), &(list) }
|
||||
#define LIST_INITIAL_CLEARED_VALUE { NULL, NULL }
|
||||
|
||||
static inline void list_initialize(struct list_node *list)
|
||||
{
|
||||
list->prev = list->next = list;
|
||||
}
|
||||
|
||||
static inline void list_clear_node(struct list_node *item)
|
||||
{
|
||||
item->prev = item->next = 0;
|
||||
}
|
||||
|
||||
static inline bool list_in_list(struct list_node *item)
|
||||
{
|
||||
if (item->prev == 0 && item->next == 0)
|
||||
return false;
|
||||
else
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline void list_add_head(struct list_node *list, struct list_node *item)
|
||||
{
|
||||
item->next = list->next;
|
||||
item->prev = list;
|
||||
list->next->prev = item;
|
||||
list->next = item;
|
||||
}
|
||||
|
||||
#define list_add_after(entry, new_entry) list_add_head(entry, new_entry)
|
||||
|
||||
static inline void list_add_tail(struct list_node *list, struct list_node *item)
|
||||
{
|
||||
item->prev = list->prev;
|
||||
item->next = list;
|
||||
list->prev->next = item;
|
||||
list->prev = item;
|
||||
}
|
||||
|
||||
#define list_add_before(entry, new_entry) list_add_tail(entry, new_entry)
|
||||
|
||||
static inline void list_delete(struct list_node *item)
|
||||
{
|
||||
item->next->prev = item->prev;
|
||||
item->prev->next = item->next;
|
||||
item->prev = item->next = 0;
|
||||
}
|
||||
|
||||
static inline struct list_node *list_remove_head(struct list_node *list)
|
||||
{
|
||||
if (list->next != list) {
|
||||
struct list_node *item = list->next;
|
||||
list_delete(item);
|
||||
return item;
|
||||
} else {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
#define list_remove_head_type(list, type, element) ({\
|
||||
struct list_node *__nod = list_remove_head(list);\
|
||||
type *__t;\
|
||||
if(__nod)\
|
||||
__t = containerof(__nod, type, element);\
|
||||
else\
|
||||
__t = (type *)0;\
|
||||
__t;\
|
||||
})
|
||||
|
||||
static inline struct list_node *list_remove_tail(struct list_node *list)
|
||||
{
|
||||
if (list->prev != list) {
|
||||
struct list_node *item = list->prev;
|
||||
list_delete(item);
|
||||
return item;
|
||||
} else {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
#define list_remove_tail_type(list, type, element) ({\
|
||||
struct list_node *__nod = list_remove_tail(list);\
|
||||
type *__t;\
|
||||
if(__nod)\
|
||||
__t = containerof(__nod, type, element);\
|
||||
else\
|
||||
__t = (type *)0;\
|
||||
__t;\
|
||||
})
|
||||
|
||||
static inline struct list_node *list_peek_head(struct list_node *list)
|
||||
{
|
||||
if (list->next != list) {
|
||||
return list->next;
|
||||
} else {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
#define list_peek_head_type(list, type, element) ({\
|
||||
struct list_node *__nod = list_peek_head(list);\
|
||||
type *__t;\
|
||||
if(__nod)\
|
||||
__t = containerof(__nod, type, element);\
|
||||
else\
|
||||
__t = (type *)0;\
|
||||
__t;\
|
||||
})
|
||||
|
||||
static inline struct list_node *list_peek_tail(struct list_node *list)
|
||||
{
|
||||
if (list->prev != list) {
|
||||
return list->prev;
|
||||
} else {
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
#define list_peek_tail_type(list, type, element) ({\
|
||||
struct list_node *__nod = list_peek_tail(list);\
|
||||
type *__t;\
|
||||
if(__nod)\
|
||||
__t = containerof(__nod, type, element);\
|
||||
else\
|
||||
__t = (type *)0;\
|
||||
__t;\
|
||||
})
|
||||
|
||||
static inline struct list_node *list_prev(struct list_node *list, struct list_node *item)
|
||||
{
|
||||
if (item->prev != list)
|
||||
return item->prev;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#define list_prev_type(list, item, type, element) ({\
|
||||
struct list_node *__nod = list_prev(list, item);\
|
||||
type *__t;\
|
||||
if(__nod)\
|
||||
__t = containerof(__nod, type, element);\
|
||||
else\
|
||||
__t = (type *)0;\
|
||||
__t;\
|
||||
})
|
||||
|
||||
static inline struct list_node *list_prev_wrap(struct list_node *list, struct list_node *item)
|
||||
{
|
||||
if (item->prev != list)
|
||||
return item->prev;
|
||||
else if (item->prev->prev != list)
|
||||
return item->prev->prev;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#define list_prev_wrap_type(list, item, type, element) ({\
|
||||
struct list_node *__nod = list_prev_wrap(list, item);\
|
||||
type *__t;\
|
||||
if(__nod)\
|
||||
__t = containerof(__nod, type, element);\
|
||||
else\
|
||||
__t = (type *)0;\
|
||||
__t;\
|
||||
})
|
||||
|
||||
static inline struct list_node *list_next(struct list_node *list, struct list_node *item)
|
||||
{
|
||||
if (item->next != list)
|
||||
return item->next;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#define list_next_type(list, item, type, element) ({\
|
||||
struct list_node *__nod = list_next(list, item);\
|
||||
type *__t;\
|
||||
if(__nod)\
|
||||
__t = containerof(__nod, type, element);\
|
||||
else\
|
||||
__t = (type *)0;\
|
||||
__t;\
|
||||
})
|
||||
|
||||
static inline struct list_node *list_next_wrap(struct list_node *list, struct list_node *item)
|
||||
{
|
||||
if (item->next != list)
|
||||
return item->next;
|
||||
else if (item->next->next != list)
|
||||
return item->next->next;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#define list_next_wrap_type(list, item, type, element) ({\
|
||||
struct list_node *__nod = list_next_wrap(list, item);\
|
||||
type *__t;\
|
||||
if(__nod)\
|
||||
__t = containerof(__nod, type, element);\
|
||||
else\
|
||||
__t = (type *)0;\
|
||||
__t;\
|
||||
})
|
||||
|
||||
// iterates over the list, node should be struct list_node*
|
||||
#define list_for_every(list, node) \
|
||||
for(node = (list)->next; node != (list); node = node->next)
|
||||
|
||||
// iterates over the list in a safe way for deletion of current node
|
||||
// node and temp_node should be struct list_node*
|
||||
#define list_for_every_safe(list, node, temp_node) \
|
||||
for(node = (list)->next, temp_node = (node)->next;\
|
||||
node != (list);\
|
||||
node = temp_node, temp_node = (node)->next)
|
||||
|
||||
// iterates over the list, entry should be the container structure type *
|
||||
#define list_for_every_entry(list, entry, type, member) \
|
||||
for((entry) = containerof((list)->next, type, member);\
|
||||
&(entry)->member != (list);\
|
||||
(entry) = containerof((entry)->member.next, type, member))
|
||||
|
||||
// iterates over the list in a safe way for deletion of current node
|
||||
// entry and temp_entry should be the container structure type *
|
||||
#define list_for_every_entry_safe(list, entry, temp_entry, type, member) \
|
||||
for(entry = containerof((list)->next, type, member),\
|
||||
temp_entry = containerof((entry)->member.next, type, member);\
|
||||
&(entry)->member != (list);\
|
||||
entry = temp_entry, temp_entry = containerof((temp_entry)->member.next, type, member))
|
||||
|
||||
static inline bool list_is_empty(struct list_node *list)
|
||||
{
|
||||
return (list->next == list) ? true : false;
|
||||
}
|
||||
|
||||
static inline size_t list_length(struct list_node *list)
|
||||
{
|
||||
size_t cnt = 0;
|
||||
struct list_node *node = list;
|
||||
list_for_every(list, node) {
|
||||
cnt++;
|
||||
}
|
||||
|
||||
return cnt;
|
||||
}
|
||||
|
||||
__END_CDECLS;
|
||||
|
||||
#endif
|
||||
39
devices/include/lnk_sym.h
Normal file
39
devices/include/lnk_sym.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/**
|
||||
* @file lnk_sym.h
|
||||
* @brief IAR link symbols.
|
||||
*
|
||||
* @copyright Copyright (c) 2021 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef DEV_LNK_SYM_H__
|
||||
#define DEV_LNK_SYM_H__
|
||||
|
||||
#include <types.h>
|
||||
|
||||
#ifdef __ICCARM__
|
||||
|
||||
#define __commands_start COMMANDS$$Base
|
||||
#define __commands_end COMMANDS$$Limit
|
||||
#define _heap_start HEAP$$Base
|
||||
#define _heap_end HEAP$$Limit
|
||||
#define __except_stack_start CSTACK$$Base
|
||||
#define __cstack_end CSTACK$$Limit
|
||||
#define __load_data_start DATA_init$$Base
|
||||
#define __data_start DATA$$Base
|
||||
#define __data_end DATA$$Limit
|
||||
#define __data_start_rom DATA$$Base
|
||||
#define __data_end DATA$$Limit
|
||||
#define __bss_start BSS$$Base
|
||||
#define __bss_end BSS$$Limit
|
||||
|
||||
#endif /* __ICCARM__ */
|
||||
|
||||
|
||||
#if !defined(ASSEMBLY)
|
||||
extern uint32_t *__except_stack_start;
|
||||
extern uint32_t *__cstack_end;
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* DEV_LNK_SYM_H__ */
|
||||
58
devices/include/param.h
Normal file
58
devices/include/param.h
Normal file
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2014 Travis Geiselbrecht
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files
|
||||
* (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef DEV_PARAM_H_
|
||||
#define DEV_PARAM_H_
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#ifndef ROUNDUP
|
||||
#define ROUNDUP(a, b) (((a) + ((b)-1)) & ~((b)-1))
|
||||
#endif
|
||||
|
||||
#ifndef ROUNDDOWN
|
||||
#define ROUNDDOWN(a, b) ((a) & ~((b)-1))
|
||||
#endif
|
||||
|
||||
#ifndef DIV_ROUND_UP
|
||||
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
|
||||
#endif
|
||||
|
||||
#ifndef ALIGN
|
||||
#define ALIGN(a, b) ROUNDUP(a, b)
|
||||
#endif
|
||||
|
||||
#ifndef IS_ALIGNED
|
||||
#define IS_ALIGNED(a, b) (!(((uintptr_t)(a)) & (((uintptr_t)(b))-1)))
|
||||
#endif
|
||||
|
||||
#ifndef ARRAY_SIZE
|
||||
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
|
||||
#endif
|
||||
|
||||
#endif
|
||||
76
devices/include/reg.h
Normal file
76
devices/include/reg.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2008 Travis Geiselbrecht
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files
|
||||
* (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge,
|
||||
* publish, distribute, sublicense, and/or sell copies of the Software,
|
||||
* and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef DEV_REG_H_
|
||||
#define DEV_REG_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define REG64(addr) ((volatile uint64_t *)(uintptr_t)(addr))
|
||||
#define REG32(addr) ((volatile uint32_t *)(uintptr_t)(addr))
|
||||
#define REG16(addr) ((volatile uint16_t *)(uintptr_t)(addr))
|
||||
#define REG8(addr) ((volatile uint8_t *)(uintptr_t)(addr))
|
||||
|
||||
#define RMWREG64(addr, startbit, width, val) *REG64(addr) = (*REG64(addr) & ~((((uint64_t)1u<<(width)) - 1u) << (startbit))) | ((uint64_t)(val) << (startbit))
|
||||
#define RMWREG32(addr, startbit, width, val) *REG32(addr) = (*REG32(addr) & ~((((uint32_t)1u<<(width)) - 1u) << (startbit))) | ((uint32_t)(val) << (startbit))
|
||||
#define RMWREG16(addr, startbit, width, val) *REG16(addr) = (*REG16(addr) & ~((((uint16_t)1u<<(width)) - 1u) << (startbit))) | ((uint16_t)(val) << (startbit))
|
||||
#define RMWREG8(addr, startbit, width, val) *REG8(addr) = (*REG8(addr) & ~((((uint8_t)1u<<(width)) - 1u) << (startbit))) | ((uint8_t)(val) << (startbit))
|
||||
|
||||
#define writeq(v, a) (*REG64(a) = (v))
|
||||
#define readq(a) (*REG64(a))
|
||||
#define writel(v, a) (*REG32(a) = (v))
|
||||
#define readl(a) (*REG32(a))
|
||||
#define writew(v, a) (*REG16(a) = (v))
|
||||
#define readw(a) (*REG16(a))
|
||||
#define writeb(v, a) (*REG8(a) = (v))
|
||||
#define readb(a) (*REG8(a))
|
||||
|
||||
static inline
|
||||
void clrbits_32(volatile uint32_t *addr, uint32_t clear)
|
||||
{
|
||||
*addr &= ~clear;
|
||||
}
|
||||
|
||||
static inline
|
||||
void setbits_32(volatile uint32_t *addr, uint32_t set)
|
||||
{
|
||||
*addr |= set;
|
||||
}
|
||||
|
||||
static inline
|
||||
void clrsetbits_32(volatile uint32_t *addr, uint32_t clear, uint32_t set)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
temp = *addr;
|
||||
temp &= ~clear;
|
||||
temp |= set;
|
||||
*addr = temp;
|
||||
}
|
||||
|
||||
#define CLRBITS_32(addr, clear) clrbits_32(REG32(addr), clear)
|
||||
#define SETBITS_32(addr, set) setbits_32(REG32(addr), set)
|
||||
#define CLRSETBITS_32(addr, clear, set) clrsetbits_32(REG32(addr), clear, set)
|
||||
|
||||
|
||||
#endif
|
||||
93
devices/include/spinlock.h
Normal file
93
devices/include/spinlock.h
Normal file
@@ -0,0 +1,93 @@
|
||||
/**
|
||||
* @brief spinlock.h
|
||||
*
|
||||
* Copyright (c) 2020 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Description: spinlock interface.
|
||||
*
|
||||
* Revision History:
|
||||
* -----------------
|
||||
*/
|
||||
|
||||
#ifndef _INCLUDE_SPINLOCK_H_
|
||||
#define _INCLUDE_SPINLOCK_H_
|
||||
|
||||
#ifndef ASSEMBLY
|
||||
|
||||
#include <armv7-r/spinlock.h>
|
||||
#include <armv7-r/irq.h>
|
||||
|
||||
__BEGIN_CDECLS
|
||||
|
||||
/**
|
||||
* @brief spinlock init.
|
||||
*
|
||||
* @param[in] spinlock spinlock address.
|
||||
*/
|
||||
static inline void spin_lock_init(spin_lock_t *spinlock)
|
||||
{
|
||||
arch_spin_lock_init(spinlock);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief spin lock.
|
||||
*
|
||||
* @param[in] spinlock spinlock address.
|
||||
*/
|
||||
static inline void spin_lock(spin_lock_t *spinlock)
|
||||
{
|
||||
arch_spin_lock(spinlock);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief spin trylock.
|
||||
*
|
||||
* @param[in] spinlock spinlock address.
|
||||
* @return try lock result.
|
||||
*/
|
||||
static inline int spin_trylock(spin_lock_t *spinlock)
|
||||
{
|
||||
return arch_spin_trylock(spinlock);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief spin unlock.
|
||||
*
|
||||
* @param[in] spinlock spinlock address.
|
||||
*/
|
||||
static inline void spin_unlock(spin_lock_t *spinlock)
|
||||
{
|
||||
arch_spin_unlock(spinlock);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief spin lock with irq save
|
||||
*
|
||||
* @param[in] spinlock spinlock address.
|
||||
* @return old irq state.
|
||||
*/
|
||||
static inline irq_state_t spin_lock_irqsave(spin_lock_t *spinlock)
|
||||
{
|
||||
irq_state_t state = arch_irq_save();
|
||||
spin_lock(spinlock);
|
||||
return state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief spin unlock with irq restore
|
||||
*
|
||||
* @param[in] spinlock spinlock address.
|
||||
* @param[in] state old irq state.
|
||||
*/
|
||||
static inline void spin_unlock_irqrestore(spin_lock_t *spinlock, irq_state_t state)
|
||||
{
|
||||
spin_unlock(spinlock);
|
||||
arch_irq_restore(state);
|
||||
}
|
||||
|
||||
__END_CDECLS
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
29
devices/include/types.h
Normal file
29
devices/include/types.h
Normal file
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* types.h
|
||||
*
|
||||
* Copyright (c) 2020 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Description: types interface.
|
||||
*
|
||||
* Revision History:
|
||||
* -----------------
|
||||
*/
|
||||
|
||||
#ifndef DEV_TYPES_H
|
||||
#define DEV_TYPES_H
|
||||
|
||||
#ifndef ASSEMBLY
|
||||
|
||||
#include <limits.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
typedef uintptr_t addr_t;
|
||||
typedef uintptr_t vaddr_t;
|
||||
typedef uintptr_t paddr_t;
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
34
devices/lib/segger/segger_rtl.c
Normal file
34
devices/lib/segger/segger_rtl.c
Normal file
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* segger_rtl.c
|
||||
*
|
||||
* Copyright (c) 2022 Semidrive Semiconductor.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Description: SEGGER RunTime Library port
|
||||
*
|
||||
* Revision History:
|
||||
* -----------------
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <param.h>
|
||||
#include <debug.h>
|
||||
#include <compiler.h>
|
||||
|
||||
#if __SES_ARM
|
||||
void __aeabi_assert(const char *expr, const char *file, int line)
|
||||
{
|
||||
ssdk_printf(SSDK_ERR, "assert in file:%s expr:%s line:%d\n", file, expr, line);
|
||||
PANIC();
|
||||
}
|
||||
|
||||
int __SEGGER_RTL_X_set_time_of_day(const struct timeval *__tp)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int __SEGGER_RTL_X_get_time_of_day (struct timeval *__tp)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
30
devices/script/IAR/flashloader_debug.mac
Normal file
30
devices/script/IAR/flashloader_debug.mac
Normal file
@@ -0,0 +1,30 @@
|
||||
tcm_init(tcma_base, tcmb_base)
|
||||
{
|
||||
__var actlr;
|
||||
|
||||
actlr = __jtagCP15ReadReg(1, 0, 0, 1);
|
||||
actlr &= ~((1 << 25) | (1 << 26) | (1 << 27));
|
||||
__jtagCP15WriteReg(1, 0, 0, 1, actlr);
|
||||
__jtagCP15WriteReg(9, 1, 0, 1, tcma_base | 1);
|
||||
__jtagCP15WriteReg(9, 1, 0, 0, tcmb_base | 1);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserReset()
|
||||
*********************************************************************/
|
||||
execUserReset()
|
||||
{
|
||||
__message "------------------------------ execUserReset ---------------------------------";
|
||||
/* Disable MPU*/
|
||||
__jtagCP15WriteReg(1, 0, 0, 0, 0x08E7087A);
|
||||
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserPreload()
|
||||
*********************************************************************/
|
||||
execUserPreload()
|
||||
{
|
||||
__message "------------------------------ execUserPreload ---------------------------------";
|
||||
tcm_init(0x3E0000, 0x3F0000);
|
||||
}
|
||||
231
devices/script/IAR/iram_remap.mac
Normal file
231
devices/script/IAR/iram_remap.mac
Normal file
@@ -0,0 +1,231 @@
|
||||
__param __sf_addr__=0x404000;
|
||||
__param __sp0_addr__=0x700000;
|
||||
__param __sp1_addr__=0x780000;
|
||||
__param __sx0_addr__=0x600000;
|
||||
__param __sx1_addr__=0x680000;
|
||||
|
||||
|
||||
core_remap(addr, start_bit1, start_bit2)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
|
||||
start_bit_val = start_bit1;
|
||||
width = 0x14;
|
||||
val = addr>>12;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val&0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val&0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = start_bit2;
|
||||
width = 0x1;
|
||||
val = 1;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xf0670004;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val |= 0x01;
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
sf_remap()
|
||||
{
|
||||
core_remap(__sf_addr__, 0x0, 0x14);
|
||||
}
|
||||
|
||||
sx0_remap()
|
||||
{
|
||||
core_remap(__sx0_addr__, 0x20, 0x34);
|
||||
}
|
||||
|
||||
sx1_remap()
|
||||
{
|
||||
core_remap(__sx1_addr__, 0x40, 0x54);
|
||||
}
|
||||
|
||||
sp0_remap()
|
||||
{
|
||||
core_remap(__sp0_addr__, 0x60, 0x74);
|
||||
}
|
||||
|
||||
sp1_remap()
|
||||
{
|
||||
core_remap(__sp1_addr__, 0x80, 0x94);
|
||||
}
|
||||
|
||||
sf_reset()
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
reg = 0xf0690000 + 0x1A0C;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<6);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
core_start(addr_offset)
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
|
||||
reg = 0xf0690000 + addr_offset;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<0);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
|
||||
sp0_start()
|
||||
{
|
||||
core_start(0x1A14);
|
||||
}
|
||||
|
||||
sp1_start()
|
||||
{
|
||||
core_start(0x1A1C);
|
||||
}
|
||||
|
||||
sx0_start()
|
||||
{
|
||||
core_start(0x1A24);
|
||||
}
|
||||
|
||||
sx1_start()
|
||||
{
|
||||
core_start(0x1A2C);
|
||||
}
|
||||
|
||||
sp_split_mode()
|
||||
{
|
||||
sp_split(0x1);
|
||||
}
|
||||
|
||||
sp_locksetp_mode()
|
||||
{
|
||||
sp_split(0);
|
||||
}
|
||||
|
||||
sp_split(val_set)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
start_bit_val = 0x160;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1A0;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1A1;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
sx_split_mode()
|
||||
{
|
||||
sx_split(0x1);
|
||||
}
|
||||
|
||||
sx_locksetp_mode()
|
||||
{
|
||||
sx_split(0);
|
||||
}
|
||||
|
||||
sx_split(val_set)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
start_bit_val = 0x180;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1C0;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1C1;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserReset()
|
||||
execUserPreReset()
|
||||
*********************************************************************/
|
||||
execUserPreload()
|
||||
{
|
||||
__message "------------------------------ execUserPreload Remap ---------------------------------";
|
||||
sf_remap();
|
||||
__delay(1000);
|
||||
|
||||
//__message "------------------------------ Reset ---------------------------------";
|
||||
sf_reset();
|
||||
|
||||
__message "------------------------------ Halt CPU by Jlink ---------------------------------";
|
||||
__jlinkExecCommand("Halt");
|
||||
}
|
||||
231
devices/script/IAR/xip_remap.mac
Normal file
231
devices/script/IAR/xip_remap.mac
Normal file
@@ -0,0 +1,231 @@
|
||||
__param __sf_addr__=0x100c1000;
|
||||
__param __sp0_addr__=0x10340000;
|
||||
__param __sp1_addr__=0x103C0000;
|
||||
__param __sx0_addr__=0x10440000;
|
||||
__param __sx1_addr__=0x104C0000;
|
||||
|
||||
|
||||
core_remap(addr, start_bit1, start_bit2)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
|
||||
start_bit_val = start_bit1;
|
||||
width = 0x14;
|
||||
val = addr>>12;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val&0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val&0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = start_bit2;
|
||||
width = 0x1;
|
||||
val = 1;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xf0670004;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val |= 0x01;
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
sf_remap()
|
||||
{
|
||||
core_remap(__sf_addr__, 0x0, 0x14);
|
||||
}
|
||||
|
||||
sx0_remap()
|
||||
{
|
||||
core_remap(__sx0_addr__, 0x20, 0x34);
|
||||
}
|
||||
|
||||
sx1_remap()
|
||||
{
|
||||
core_remap(__sx1_addr__, 0x40, 0x54);
|
||||
}
|
||||
|
||||
sp0_remap()
|
||||
{
|
||||
core_remap(__sp0_addr__, 0x60, 0x74);
|
||||
}
|
||||
|
||||
sp1_remap()
|
||||
{
|
||||
core_remap(__sp1_addr__, 0x80, 0x94);
|
||||
}
|
||||
|
||||
sf_reset()
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
reg = 0xf0690000 + 0x1A0C;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<6);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
core_start(addr_offset)
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
|
||||
reg = 0xf0690000 + addr_offset;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<0);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
|
||||
sp0_start()
|
||||
{
|
||||
core_start(0x1A14);
|
||||
}
|
||||
|
||||
sp1_start()
|
||||
{
|
||||
core_start(0x1A1C);
|
||||
}
|
||||
|
||||
sx0_start()
|
||||
{
|
||||
core_start(0x1A24);
|
||||
}
|
||||
|
||||
sx1_start()
|
||||
{
|
||||
core_start(0x1A2C);
|
||||
}
|
||||
|
||||
sp_split_mode()
|
||||
{
|
||||
sp_split(0x1);
|
||||
}
|
||||
|
||||
sp_locksetp_mode()
|
||||
{
|
||||
sp_split(0);
|
||||
}
|
||||
|
||||
sp_split(val_set)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
start_bit_val = 0x160;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1A0;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1A1;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
sx_split_mode()
|
||||
{
|
||||
sx_split(0x1);
|
||||
}
|
||||
|
||||
sx_locksetp_mode()
|
||||
{
|
||||
sx_split(0);
|
||||
}
|
||||
|
||||
sx_split(val_set)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
start_bit_val = 0x180;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1C0;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1C1;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserReset()
|
||||
execUserPreReset()
|
||||
*********************************************************************/
|
||||
execUserPreload()
|
||||
{
|
||||
__message "------------------------------ execUserPreload Remap ---------------------------------";
|
||||
sf_remap();
|
||||
__delay(1000);
|
||||
|
||||
//__message "------------------------------ Reset ---------------------------------";
|
||||
sf_reset();
|
||||
|
||||
__message "------------------------------ Halt CPU by Jlink ---------------------------------";
|
||||
__jlinkExecCommand("Halt");
|
||||
}
|
||||
231
devices/script/IAR/xip_remap_norflash.mac
Normal file
231
devices/script/IAR/xip_remap_norflash.mac
Normal file
@@ -0,0 +1,231 @@
|
||||
__param __sf_addr__=0x10008000;
|
||||
__param __sp0_addr__=0x10288000;
|
||||
__param __sp1_addr__=0x10308000;
|
||||
__param __sx0_addr__=0x10388000;
|
||||
__param __sx1_addr__=0x10408000;
|
||||
|
||||
|
||||
core_remap(addr, start_bit1, start_bit2)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
|
||||
start_bit_val = start_bit1;
|
||||
width = 0x14;
|
||||
val = addr>>12;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val&0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val&0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = start_bit2;
|
||||
width = 0x1;
|
||||
val = 1;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
__message reg_addr:%x;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
__message "original ", reg_val :%x;
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
__message "new ", reg_val :%x;
|
||||
|
||||
reg_addr = 0xf0670004;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val |= 0x01;
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
sf_remap()
|
||||
{
|
||||
core_remap(__sf_addr__, 0x0, 0x14);
|
||||
}
|
||||
|
||||
sx0_remap()
|
||||
{
|
||||
core_remap(__sx0_addr__, 0x20, 0x34);
|
||||
}
|
||||
|
||||
sx1_remap()
|
||||
{
|
||||
core_remap(__sx1_addr__, 0x40, 0x54);
|
||||
}
|
||||
|
||||
sp0_remap()
|
||||
{
|
||||
core_remap(__sp0_addr__, 0x60, 0x74);
|
||||
}
|
||||
|
||||
sp1_remap()
|
||||
{
|
||||
core_remap(__sp1_addr__, 0x80, 0x94);
|
||||
}
|
||||
|
||||
sf_reset()
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
reg = 0xf0690000 + 0x1A0C;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<6);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
core_start(addr_offset)
|
||||
{
|
||||
__var reg;
|
||||
__var val;
|
||||
|
||||
reg = 0xf0690000 + addr_offset;
|
||||
val = __readMemory32(reg, "Memory");
|
||||
val |= (1<<0);
|
||||
__message val:%x;
|
||||
__writeMemory32(val, reg, "Memory");
|
||||
__delay(1000);
|
||||
}
|
||||
|
||||
|
||||
sp0_start()
|
||||
{
|
||||
core_start(0x1A14);
|
||||
}
|
||||
|
||||
sp1_start()
|
||||
{
|
||||
core_start(0x1A1C);
|
||||
}
|
||||
|
||||
sx0_start()
|
||||
{
|
||||
core_start(0x1A24);
|
||||
}
|
||||
|
||||
sx1_start()
|
||||
{
|
||||
core_start(0x1A2C);
|
||||
}
|
||||
|
||||
sp_split_mode()
|
||||
{
|
||||
sp_split(0x1);
|
||||
}
|
||||
|
||||
sp_locksetp_mode()
|
||||
{
|
||||
sp_split(0);
|
||||
}
|
||||
|
||||
sp_split(val_set)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
start_bit_val = 0x160;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1A0;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1A1;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
sx_split_mode()
|
||||
{
|
||||
sx_split(0x1);
|
||||
}
|
||||
|
||||
sx_locksetp_mode()
|
||||
{
|
||||
sx_split(0);
|
||||
}
|
||||
|
||||
sx_split(val_set)
|
||||
{
|
||||
__var reg_addr;
|
||||
__var reg_val;
|
||||
__var start_bit_val;
|
||||
__var width;
|
||||
__var val;
|
||||
|
||||
start_bit_val = 0x180;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1C0;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
|
||||
start_bit_val = 0x1C1;
|
||||
width = 0x1;
|
||||
val = val_set;
|
||||
reg_addr = 0xF0680000 + 0x1400 + (start_bit_val>>5)*4;
|
||||
reg_val = __readMemory32(reg_addr, "Memory");
|
||||
reg_val = reg_val&(~(((1<<width)-1)<<(start_bit_val & 0x1f)));
|
||||
reg_val = reg_val|(val<<(start_bit_val & 0x1f));
|
||||
__writeMemory32(reg_val, reg_addr, "Memory");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* execUserReset()
|
||||
execUserPreReset()
|
||||
*********************************************************************/
|
||||
execUserPreload()
|
||||
{
|
||||
__message "------------------------------ execUserPreload Remap ---------------------------------";
|
||||
sf_remap();
|
||||
__delay(1000);
|
||||
|
||||
//__message "------------------------------ Reset ---------------------------------";
|
||||
sf_reset();
|
||||
|
||||
__message "------------------------------ Halt CPU by Jlink ---------------------------------";
|
||||
__jlinkExecCommand("Halt");
|
||||
}
|
||||
BIN
devices/script/JFLASH/E3106_NORFLASH/FDA.bin
Normal file
BIN
devices/script/JFLASH/E3106_NORFLASH/FDA.bin
Normal file
Binary file not shown.
BIN
devices/script/JFLASH/E3106_NORFLASH/boot0.bin
Normal file
BIN
devices/script/JFLASH/E3106_NORFLASH/boot0.bin
Normal file
Binary file not shown.
BIN
devices/script/JFLASH/E3106_NORFLASH/boot1.bin
Normal file
BIN
devices/script/JFLASH/E3106_NORFLASH/boot1.bin
Normal file
Binary file not shown.
BIN
devices/script/JFLASH/E3106_NORFLASH/boot2.bin
Normal file
BIN
devices/script/JFLASH/E3106_NORFLASH/boot2.bin
Normal file
Binary file not shown.
BIN
devices/script/JFLASH/E3106_NORFLASH/rfd.bin
Normal file
BIN
devices/script/JFLASH/E3106_NORFLASH/rfd.bin
Normal file
Binary file not shown.
BIN
devices/script/JFLASH/E3106_NORFLASH/sfs.bin
Normal file
BIN
devices/script/JFLASH/E3106_NORFLASH/sfs.bin
Normal file
Binary file not shown.
159
devices/script/JFLASH/JFlash.log
Normal file
159
devices/script/JFLASH/JFlash.log
Normal file
@@ -0,0 +1,159 @@
|
||||
SEGGER J-Link Commander V7.98a (Compiled Jul 19 2024 15:01:50)
|
||||
DLL version V7.98a, compiled Jul 19 2024 15:01:03
|
||||
|
||||
|
||||
J-Link Command File read successfully.
|
||||
Processing script file...
|
||||
J-Link>r
|
||||
J-Link connection not established yet but required for command.
|
||||
Connecting to J-Link via USB...
|
||||
****** Error: Error while evaluating J-Link script file: Error while compiling. Line 34, column 1:
|
||||
}
|
||||
^
|
||||
Missing return statement at the end of non-void function
|
||||
Failed prepare script file
|
||||
O.K.
|
||||
Firmware: J-Link V9 compiled May 7 2021 16:26:12
|
||||
Hardware version: V9.40
|
||||
J-Link uptime (since boot): N/A (Not supported by this model)
|
||||
S/N: 59406426
|
||||
License(s): RDI, GDB, FlashDL, FlashBP, JFlash
|
||||
VTref=3.333V
|
||||
Target connection not established yet but required for command.
|
||||
Device "E3106_NORFLASH" selected.
|
||||
|
||||
|
||||
Connecting to target via SWD
|
||||
Found SW-DP with ID 0x2BA01477
|
||||
DPIDR: 0x2BA01477
|
||||
CoreSight SoC-400 or earlier
|
||||
Scanning AP map to find all available APs
|
||||
AP[1]: Stopped AP scan as end of AP map has been reached
|
||||
AP[0]: APB-AP (IDR: 0x24770002)
|
||||
Iterating through AP map to find APB-AP to use
|
||||
AP[0]: APB-AP found
|
||||
ROMTbl[0][0]: CompAddr: F0A01000 CID: B105900D, PID: 004BBC15 Cortex-R5
|
||||
Found Cortex-R5 r1p3
|
||||
4 code breakpoints, 3 data breakpoints
|
||||
Debug architecture ARMv7.0
|
||||
Data endian: little
|
||||
Main ID register: 0x411FC153
|
||||
I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
|
||||
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
|
||||
TCM Type register: 0x00010001
|
||||
MPU Type register: 0x00001000
|
||||
System control register:
|
||||
Instruction endian: little
|
||||
Level-1 instruction cache disabled
|
||||
Level-1 data cache disabled
|
||||
MPU disabled
|
||||
Branch prediction enabled
|
||||
|
||||
****** Error: Error while evaluating J-Link script file: Error while compiling. Line 34, column 1:
|
||||
}
|
||||
^
|
||||
Missing return statement at the end of non-void function
|
||||
Failed prepare script file
|
||||
Memory zones:
|
||||
Zone: "Default" Description: Default access mode
|
||||
Zone: "APB-AP (AP0)" Description: DMA like acc. in AP0 addr. space
|
||||
Cortex-R5 identified.
|
||||
Reset delay: 0 ms
|
||||
Reset type NORMAL: Reset CPU + peripherals via reset pin. CPU halted immediately after reset.
|
||||
CPU not halted after Reset, halting using Halt request
|
||||
J-Link>h
|
||||
PC: (R15) = 0003D080, CPSR = 00000197 (ABORT mode, ARM IRQ dis.)
|
||||
Current:
|
||||
R0 =10000000, R1 =1143540C, R2 =00000003, R3 =0000036D
|
||||
R4 =5AA5F00F, R5 =A55A0FF0, R6 =5AA5F00F, R7 =0190FF70
|
||||
R8 =5AA5F00F, R9 =007C003C, R10=00000000, R11=0190FF6C, R12=00000000
|
||||
R13=01910000, R14=00040104, SPSR=00000000
|
||||
USR: R8 =5AA5F00F, R9 =007C003C, R10=00000000, R11=0190FF6C, R12=00000000
|
||||
R13=003FB8E8, R14=003FB8E9
|
||||
FIQ: R8 =00000000, R9 =00000000, R10=00000000, R11=00000000, R12=00000000
|
||||
R13=01910000, R14=00000000, SPSR=000001D3
|
||||
IRQ: R13=01910000, R14=00000000, SPSR=000001D3
|
||||
SVC: R13=0190FF58, R14=0190703C, SPSR=000001D3
|
||||
ABT: R13=01910000, R14=00040104, SPSR=00000197
|
||||
UND: R13=01910000, R14=00000000, SPSR=000001D3
|
||||
J-Link>WCP15Ex 0 1 0 0 0x08E7087A
|
||||
CP15[0, 1, 0, 0] = 0x08E7087A
|
||||
J-Link>WCP15Ex 0 1 0 1 0x00000020
|
||||
CP15[0, 1, 0, 1] = 0x00000020
|
||||
J-Link>WCP15Ex 0 9 1 1 0x3E0001
|
||||
CP15[0, 9, 1, 1] = 0x003E0001
|
||||
J-Link>WCP15Ex 0 9 1 0 0x3F0001
|
||||
CP15[0, 9, 1, 0] = 0x003F0001
|
||||
J-Link>q
|
||||
|
||||
Script processing completed.
|
||||
|
||||
Application log started
|
||||
- J-Flash V7.98a (J-Flash compiled Jul 19 2024 15:01:26)
|
||||
- JLinkARM.dll V7.98a (DLL compiled Jul 19 2024 15:01:03)
|
||||
Optional command line parameters found
|
||||
- [1]: -openprjD:\e3_176_ref_E3106_mcu_demo_E3_SSDK_PTG3.0_2024.07.20 21.35.43\e3_176_ref\devices\script\JFLASH\SemiDrive.jflash
|
||||
- [2]: -openD:\e3_176_ref_E3106_mcu_demo_E3_SSDK_PTG3.0_2024.07.20 21.35.43\e3_176_ref\devices\script\JFLASH\E3106_NORFLASH\sfs.bin,0x10000000
|
||||
- [3]: -jflashlogjflashlog_tmp.txt
|
||||
- [4]: -jlinklogjlinklog_tmp.txt
|
||||
- [5]: -mergeD:\e3_176_ref_E3106_mcu_demo_E3_SSDK_PTG3.0_2024.07.20 21.35.43\e3_176_ref\devices\script\JFLASH\E3106_NORFLASH\rfd.bin,0x100000F0
|
||||
- [6]: -auto
|
||||
- [7]: -exit
|
||||
Reading flash device list [C:\Program Files\SEGGER\JLink_V798a\ETC/JFlash/Flash.csv] ...
|
||||
- List of flash devices read successfully (451 Devices)
|
||||
Reading MCU device list ...
|
||||
- List of MCU devices read successfully (11299 Devices)
|
||||
Opening project file [D:\e3_176_ref_E3106_mcu_demo_E3_SSDK_PTG3.0_2024.07.20 21.35.43\e3_176_ref\devices\script\JFLASH\SemiDrive.jflash] ...
|
||||
- Project opened successfully
|
||||
Opening data file [D:\e3_176_ref_E3106_mcu_demo_E3_SSDK_PTG3.0_2024.07.20 21.35.43\e3_176_ref\devices\script\JFLASH\E3106_NORFLASH\sfs.bin] ...
|
||||
- Data file opened successfully (128 bytes, 1 range, CRC of data = 0x061E246F, CRC of file = 0x061E246F)
|
||||
Merging data file [D:\e3_176_ref_E3106_mcu_demo_E3_SSDK_PTG3.0_2024.07.20 21.35.43\e3_176_ref\devices\script\JFLASH\E3106_NORFLASH\rfd.bin] ...
|
||||
- Data files merged successfully (400 bytes, 2 ranges, CRC = 0xC5069972)
|
||||
Auto programming target (400 bytes, 2 ranges) ...
|
||||
- Connecting ...
|
||||
- ERROR: Timeout while reading DCC data
|
||||
|
||||
- ERROR: Failed to connect.
|
||||
Could not determine CPU clock frequency.
|
||||
- ERROR: Connect failed
|
||||
- ERROR: Could not auto program target, not connected
|
||||
J-Flash V7.98a Error: Timeout while reading DCC data
|
||||
Failed to connect.
|
||||
Could not determine CPU clock frequency.
|
||||
Connect failed
|
||||
Could not auto program target, not connected
|
||||
Close project
|
||||
- Project closed
|
||||
Application log started
|
||||
- J-Flash V7.98a (J-Flash compiled Jul 19 2024 15:01:26)
|
||||
- JLinkARM.dll V7.98a (DLL compiled Jul 19 2024 15:01:03)
|
||||
Optional command line parameters found
|
||||
- [1]: -openprjD:\e3_176_ref_E3106_mcu_demo_E3_SSDK_PTG3.0_2024.07.20 21.35.43\e3_176_ref\devices\script\JFLASH\SemiDrive.jflash
|
||||
- [2]: -openD:\e3_176_ref_E3106_mcu_demo_E3_SSDK_PTG3.0_2024.07.20 21.35.43\e3_176_ref\devices\script\JFLASH\E3106_NORFLASH\boot0.bin,0x10010000
|
||||
- [3]: -jflashlogjflashlog_tmp.txt
|
||||
- [4]: -jlinklogjlinklog_tmp.txt
|
||||
- [5]: -auto
|
||||
- [6]: -exit
|
||||
Reading flash device list [C:\Program Files\SEGGER\JLink_V798a\ETC/JFlash/Flash.csv] ...
|
||||
- List of flash devices read successfully (451 Devices)
|
||||
Reading MCU device list ...
|
||||
- List of MCU devices read successfully (11299 Devices)
|
||||
Opening project file [D:\e3_176_ref_E3106_mcu_demo_E3_SSDK_PTG3.0_2024.07.20 21.35.43\e3_176_ref\devices\script\JFLASH\SemiDrive.jflash] ...
|
||||
- Project opened successfully
|
||||
Opening data file [D:\e3_176_ref_E3106_mcu_demo_E3_SSDK_PTG3.0_2024.07.20 21.35.43\e3_176_ref\devices\script\JFLASH\E3106_NORFLASH\boot0.bin] ...
|
||||
- Data file opened successfully (148800 bytes, 1 range, CRC of data = 0x8E3EAC0F, CRC of file = 0x8E3EAC0F)
|
||||
Auto programming target (148800 bytes, 1 range) ...
|
||||
- Connecting ...
|
||||
- ERROR: Timeout while reading DCC data
|
||||
|
||||
- ERROR: Failed to connect.
|
||||
Could not determine CPU clock frequency.
|
||||
- ERROR: Connect failed
|
||||
- ERROR: Could not auto program target, not connected
|
||||
J-Flash V7.98a Error: Timeout while reading DCC data
|
||||
Failed to connect.
|
||||
Could not determine CPU clock frequency.
|
||||
Connect failed
|
||||
Could not auto program target, not connected
|
||||
Close project
|
||||
- Project closed
|
||||
740
devices/script/JFLASH/JLinkARM.log
Normal file
740
devices/script/JFLASH/JLinkARM.log
Normal file
@@ -0,0 +1,740 @@
|
||||
T0584 000:001.020 SEGGER J-Link V7.98a Log File
|
||||
T0584 000:001.251 DLL Compiled: Jul 19 2024 15:01:03
|
||||
T0584 000:001.337 Logging started @ 2024-07-28 11:37
|
||||
T0584 000:001.420 Process: C:\Program Files\SEGGER\JLink_V798a\JLink.exe
|
||||
T0584 000:001.508 - 1.506ms
|
||||
T0584 000:001.708 JLINK_SetWarnOutHandler(...)
|
||||
T0584 000:001.794 - 0.087ms
|
||||
T0584 000:001.891 JLINK_ExecCommand("scriptfile = D:\e3_176_ref_E3106_mcu_demo_E3_SSDK_PTG3.0_2024.07.20 21.35.43\e3_176_ref\devices\script\JFLASH\SemiDrive.JLinkScript", ...).
|
||||
T0584 000:002.026 - 0.131ms returns 0x00
|
||||
T0584 000:002.127 JLINK_OpenEx(...)
|
||||
T0584 000:005.016
|
||||
***** Error:
|
||||
T0584 000:005.167 Error while evaluating J-Link script file: Error while compiling. Line 34, column 1:
|
||||
}
|
||||
^
|
||||
Missing return statement at the end of non-void function
|
||||
T0584 000:005.735
|
||||
***** Error:
|
||||
T0584 000:005.816 Failed prepare script file
|
||||
T0584 000:026.143 Firmware: J-Link V9 compiled May 7 2021 16:26:12
|
||||
T0584 000:027.014 Firmware: J-Link V9 compiled May 7 2021 16:26:12
|
||||
T0584 000:027.307 Decompressing FW timestamp took 171 us
|
||||
T0584 000:033.112 Hardware: V9.40
|
||||
T0584 000:033.188 S/N: 59406426
|
||||
T0584 000:033.242 OEM: SEGGER
|
||||
T0584 000:033.295 Feature(s): RDI, GDB, FlashDL, FlashBP, JFlash
|
||||
T0584 000:033.895 Bootloader: (Could not read)
|
||||
T0584 000:034.602 TELNET listener socket opened on port 19021
|
||||
T0584 000:034.709 WEBSRV WEBSRV_Init(): Starting webserver thread(s)
|
||||
T0584 000:034.967 WEBSRV Webserver running on local port 19080
|
||||
T0584 000:035.380 Looking for J-Link GUI Server exe at: C:\Program Files\SEGGER\JLink_V798a\JLinkGUIServer.exe
|
||||
T0584 000:035.520 Forking J-Link GUI Server: C:\Program Files\SEGGER\JLink_V798a\JLinkGUIServer.exe
|
||||
T0584 000:092.174 J-Link GUI Server info: "J-Link GUI server V7.98a "
|
||||
T0584 000:100.588 - 98.451ms returns "O.K."
|
||||
T0584 000:100.753 JLINK_GetFirmwareString(...)
|
||||
T0584 000:100.795 - 0.046ms
|
||||
T0584 000:100.835 JLINK_GetHardwareVersion()
|
||||
T0584 000:100.873 - 0.036ms returns 94000
|
||||
T0584 000:100.932 JLINK_GetHWInfo(...)
|
||||
T0584 000:101.123 - 0.193ms returns 0
|
||||
T0584 000:101.170 JLINK_GetSN()
|
||||
T0584 000:101.208 - 0.040ms returns 59406426
|
||||
T0584 000:101.248 JLINK_GetOEMString(...)
|
||||
T0584 000:101.293 JLINK_EMU_GetCurrConnectionInfo()
|
||||
T0584 000:101.495 - 0.202ms returns 0
|
||||
T0584 000:101.542 JLINK_EMU_HasCapEx(0x00000026)
|
||||
T0584 000:101.579 - 0.037ms returns 0
|
||||
T0584 000:101.616 JLINK_GetEmuCaps()
|
||||
T0584 000:101.665 - 0.048ms returns 0xB9FF7BBF
|
||||
T0584 000:101.707 JLINK_GetEmuCaps()
|
||||
T0584 000:101.743 - 0.035ms returns 0xB9FF7BBF
|
||||
T0584 000:101.781 JLINK_GetHWStatus(...)
|
||||
T0584 000:101.960 - 0.178ms returns 0
|
||||
T0584 000:102.005 JLINK_EMU_HasCapEx(0x00000044)
|
||||
T0584 000:102.041 - 0.036ms returns 0
|
||||
T0584 000:102.085 JLINK_DEVICE_GetIndex(sDeviceName = E3106_NORFLASH)
|
||||
T0584 000:129.404 XML file found at: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\JLinkDevices.xml
|
||||
T0584 000:130.295 C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\JLinkDevices.xml evaluated successfully.
|
||||
T0584 000:130.349 Device entry created: E3110_HYPERFLASH
|
||||
T0584 000:130.387 ChipInfo:
|
||||
T0584 000:130.455 Vendor: SemiDrive
|
||||
T0584 000:130.514 Name: E3110_HYPERFLASH
|
||||
T0584 000:130.591 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:130.647 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:130.702 WorkRAMSize: 0x00060000
|
||||
T0584 000:130.757 FlashBankInfo:
|
||||
T0584 000:130.811 Name: OSPI Flash
|
||||
T0584 000:130.866 BaseAddr: 0x10000000
|
||||
T0584 000:131.118 LoaderInfo:
|
||||
T0584 000:131.194 Name: OSPI_Flash
|
||||
T0584 000:131.267 MaxSize: 0x08000000
|
||||
T0584 000:131.340 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3110\hyperflash.out
|
||||
T0584 000:131.414 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:131.585 Device entry created: E3206_HYPERFLASH
|
||||
T0584 000:131.637 ChipInfo:
|
||||
T0584 000:131.710 Vendor: SemiDrive
|
||||
T0584 000:131.784 Name: E3206_HYPERFLASH
|
||||
T0584 000:131.967 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:132.045 WorkRAMAddr: 0x004E0000
|
||||
T0584 000:132.119 WorkRAMSize: 0x00060000
|
||||
T0584 000:132.184 FlashBankInfo:
|
||||
T0584 000:132.239 Name: OSPI Flash
|
||||
T0584 000:132.294 BaseAddr: 0x10000000
|
||||
T0584 000:132.489 LoaderInfo:
|
||||
T0584 000:132.546 Name: OSPI_Flash
|
||||
T0584 000:132.610 MaxSize: 0x08000000
|
||||
T0584 000:132.665 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3206\hyperflash.out
|
||||
T0584 000:132.719 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:132.780 Device entry created: E3210_HYPERFLASH
|
||||
T0584 000:132.816 ChipInfo:
|
||||
T0584 000:132.871 Vendor: SemiDrive
|
||||
T0584 000:132.937 Name: E3210_HYPERFLASH
|
||||
T0584 000:133.007 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:133.064 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:133.119 WorkRAMSize: 0x00060000
|
||||
T0584 000:133.173 FlashBankInfo:
|
||||
T0584 000:133.227 Name: OSPI Flash
|
||||
T0584 000:133.282 BaseAddr: 0x10000000
|
||||
T0584 000:133.469 LoaderInfo:
|
||||
T0584 000:133.525 Name: OSPI_Flash
|
||||
T0584 000:133.580 MaxSize: 0x08000000
|
||||
T0584 000:133.634 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3210\hyperflash.out
|
||||
T0584 000:133.688 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:133.749 Device entry created: E3420_HYPERFLASH
|
||||
T0584 000:133.785 ChipInfo:
|
||||
T0584 000:133.840 Vendor: SemiDrive
|
||||
T0584 000:133.896 Name: E3420_HYPERFLASH
|
||||
T0584 000:133.996 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:134.075 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:134.149 WorkRAMSize: 0x00060000
|
||||
T0584 000:134.224 FlashBankInfo:
|
||||
T0584 000:134.299 Name: OSPI Flash
|
||||
T0584 000:134.377 BaseAddr: 0x10000000
|
||||
T0584 000:134.637 LoaderInfo:
|
||||
T0584 000:134.715 Name: OSPI_Flash
|
||||
T0584 000:134.788 MaxSize: 0x08000000
|
||||
T0584 000:134.863 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3420\hyperflash.out
|
||||
T0584 000:134.946 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:135.027 Device entry created: E3430_HYPERFLASH
|
||||
T0584 000:135.075 ChipInfo:
|
||||
T0584 000:135.146 Vendor: SemiDrive
|
||||
T0584 000:135.221 Name: E3430_HYPERFLASH
|
||||
T0584 000:135.299 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:135.374 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:135.452 WorkRAMSize: 0x00060000
|
||||
T0584 000:135.525 FlashBankInfo:
|
||||
T0584 000:135.597 Name: OSPI Flash
|
||||
T0584 000:135.671 BaseAddr: 0x10000000
|
||||
T0584 000:135.918 LoaderInfo:
|
||||
T0584 000:135.990 Name: OSPI_Flash
|
||||
T0584 000:136.046 MaxSize: 0x08000000
|
||||
T0584 000:136.100 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3430\hyperflash.out
|
||||
T0584 000:136.155 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:136.215 Device entry created: E3640_HYPERFLASH
|
||||
T0584 000:136.252 ChipInfo:
|
||||
T0584 000:136.306 Vendor: SemiDrive
|
||||
T0584 000:136.364 Name: E3640_HYPERFLASH
|
||||
T0584 000:136.435 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:136.490 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:136.545 WorkRAMSize: 0x00060000
|
||||
T0584 000:136.599 FlashBankInfo:
|
||||
T0584 000:136.666 Name: OSPI Flash
|
||||
T0584 000:136.748 BaseAddr: 0x10000000
|
||||
T0584 000:137.007 LoaderInfo:
|
||||
T0584 000:137.077 Name: OSPI_Flash
|
||||
T0584 000:137.153 MaxSize: 0x08000000
|
||||
T0584 000:137.229 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3640\hyperflash.out
|
||||
T0584 000:137.429 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:137.518 Device entry created: E3648_HYPERFLASH
|
||||
T0584 000:137.573 ChipInfo:
|
||||
T0584 000:137.655 Vendor: SemiDrive
|
||||
T0584 000:137.751 Name: E3648_HYPERFLASH
|
||||
T0584 000:137.827 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:137.902 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:137.981 WorkRAMSize: 0x00060000
|
||||
T0584 000:138.063 FlashBankInfo:
|
||||
T0584 000:138.147 Name: OSPI Flash
|
||||
T0584 000:138.221 BaseAddr: 0x10000000
|
||||
T0584 000:138.439 LoaderInfo:
|
||||
T0584 000:138.514 Name: OSPI_Flash
|
||||
T0584 000:138.581 MaxSize: 0x08000000
|
||||
T0584 000:138.636 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3648\hyperflash.out
|
||||
T0584 000:138.705 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:138.776 Device entry created: D3248_NORFLASH
|
||||
T0584 000:138.851 ChipInfo:
|
||||
T0584 000:138.985 Vendor: SemiDrive
|
||||
T0584 000:139.065 Name: D3248_NORFLASH
|
||||
T0584 000:139.123 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:139.196 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:139.309 WorkRAMSize: 0x00060000
|
||||
T0584 000:139.398 FlashBankInfo:
|
||||
T0584 000:139.508 Name: OSPI Flash
|
||||
T0584 000:139.685 BaseAddr: 0x10000000
|
||||
T0584 000:140.016 LoaderInfo:
|
||||
T0584 000:140.093 Name: OSPI_Flash
|
||||
T0584 000:140.168 MaxSize: 0x08000000
|
||||
T0584 000:140.299 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\D3248\norflash.out
|
||||
T0584 000:140.365 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:140.553 Device entry created: E3104_NORFLASH
|
||||
T0584 000:140.594 ChipInfo:
|
||||
T0584 000:140.649 Vendor: SemiDrive
|
||||
T0584 000:140.705 Name: E3104_NORFLASH
|
||||
T0584 000:140.760 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:140.815 WorkRAMAddr: 0x004E0000
|
||||
T0584 000:140.870 WorkRAMSize: 0x00060000
|
||||
T0584 000:140.935 FlashBankInfo:
|
||||
T0584 000:140.990 Name: OSPI Flash
|
||||
T0584 000:141.045 BaseAddr: 0x10000000
|
||||
T0584 000:141.246 LoaderInfo:
|
||||
T0584 000:141.302 Name: OSPI_Flash
|
||||
T0584 000:141.357 MaxSize: 0x08000000
|
||||
T0584 000:141.411 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3104\norflash.out
|
||||
T0584 000:141.466 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:141.527 Device entry created: E3106_NORFLASH
|
||||
T0584 000:141.563 ChipInfo:
|
||||
T0584 000:141.617 Vendor: SemiDrive
|
||||
T0584 000:141.672 Name: E3106_NORFLASH
|
||||
T0584 000:141.727 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:141.782 WorkRAMAddr: 0x004E0000
|
||||
T0584 000:141.837 WorkRAMSize: 0x00060000
|
||||
T0584 000:141.899 FlashBankInfo:
|
||||
T0584 000:141.965 Name: OSPI Flash
|
||||
T0584 000:142.021 BaseAddr: 0x10000000
|
||||
T0584 000:142.194 LoaderInfo:
|
||||
T0584 000:142.250 Name: OSPI_Flash
|
||||
T0584 000:142.305 MaxSize: 0x08000000
|
||||
T0584 000:142.359 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3106\norflash.out
|
||||
T0584 000:142.413 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:142.473 Device entry created: E3110_NORFLASH
|
||||
T0584 000:142.510 ChipInfo:
|
||||
T0584 000:142.564 Vendor: SemiDrive
|
||||
T0584 000:142.618 Name: E3110_NORFLASH
|
||||
T0584 000:142.675 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:142.729 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:142.784 WorkRAMSize: 0x00060000
|
||||
T0584 000:142.846 FlashBankInfo:
|
||||
T0584 000:142.913 Name: OSPI Flash
|
||||
T0584 000:142.970 BaseAddr: 0x10000000
|
||||
T0584 000:143.139 LoaderInfo:
|
||||
T0584 000:143.195 Name: OSPI_Flash
|
||||
T0584 000:143.249 MaxSize: 0x08000000
|
||||
T0584 000:143.304 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3110\norflash.out
|
||||
T0584 000:143.358 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:143.418 Device entry created: E3205_NORFLASH
|
||||
T0584 000:143.456 ChipInfo:
|
||||
T0584 000:143.510 Vendor: SemiDrive
|
||||
T0584 000:143.565 Name: E3205_NORFLASH
|
||||
T0584 000:143.620 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:143.675 WorkRAMAddr: 0x004E0000
|
||||
T0584 000:143.729 WorkRAMSize: 0x00060000
|
||||
T0584 000:143.783 FlashBankInfo:
|
||||
T0584 000:143.837 Name: OSPI Flash
|
||||
T0584 000:143.898 BaseAddr: 0x10000000
|
||||
T0584 000:144.075 LoaderInfo:
|
||||
T0584 000:144.132 Name: OSPI_Flash
|
||||
T0584 000:144.187 MaxSize: 0x08000000
|
||||
T0584 000:144.242 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3205\norflash.out
|
||||
T0584 000:144.297 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:144.356 Device entry created: E3210_NORFLASH
|
||||
T0584 000:144.392 ChipInfo:
|
||||
T0584 000:144.446 Vendor: SemiDrive
|
||||
T0584 000:144.501 Name: E3210_NORFLASH
|
||||
T0584 000:144.556 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:144.611 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:144.665 WorkRAMSize: 0x00060000
|
||||
T0584 000:144.719 FlashBankInfo:
|
||||
T0584 000:144.774 Name: OSPI Flash
|
||||
T0584 000:144.828 BaseAddr: 0x10000000
|
||||
T0584 000:145.024 LoaderInfo:
|
||||
T0584 000:145.081 Name: OSPI_Flash
|
||||
T0584 000:145.136 MaxSize: 0x08000000
|
||||
T0584 000:145.190 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3210\norflash.out
|
||||
T0584 000:145.244 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:145.304 Device entry created: E3340_NORFLASH
|
||||
T0584 000:145.340 ChipInfo:
|
||||
T0584 000:145.394 Vendor: SemiDrive
|
||||
T0584 000:145.449 Name: E3340_NORFLASH
|
||||
T0584 000:145.504 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:145.559 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:145.614 WorkRAMSize: 0x00060000
|
||||
T0584 000:145.668 FlashBankInfo:
|
||||
T0584 000:145.723 Name: OSPI Flash
|
||||
T0584 000:145.778 BaseAddr: 0x10000000
|
||||
T0584 000:145.958 LoaderInfo:
|
||||
T0584 000:146.015 Name: OSPI_Flash
|
||||
T0584 000:146.070 MaxSize: 0x08000000
|
||||
T0584 000:146.124 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3340\norflash.out
|
||||
T0584 000:146.178 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:146.238 Device entry created: E3420_NORFLASH
|
||||
T0584 000:146.274 ChipInfo:
|
||||
T0584 000:146.328 Vendor: SemiDrive
|
||||
T0584 000:146.382 Name: E3420_NORFLASH
|
||||
T0584 000:146.438 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:146.492 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:146.548 WorkRAMSize: 0x00060000
|
||||
T0584 000:146.602 FlashBankInfo:
|
||||
T0584 000:146.657 Name: OSPI Flash
|
||||
T0584 000:146.711 BaseAddr: 0x10000000
|
||||
T0584 000:146.877 LoaderInfo:
|
||||
T0584 000:146.942 Name: OSPI_Flash
|
||||
T0584 000:146.997 MaxSize: 0x08000000
|
||||
T0584 000:147.052 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3420\norflash.out
|
||||
T0584 000:147.106 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:147.249 Device entry created: E3430_NORFLASH
|
||||
T0584 000:147.286 ChipInfo:
|
||||
T0584 000:147.347 Vendor: SemiDrive
|
||||
T0584 000:147.415 Name: E3430_NORFLASH
|
||||
T0584 000:147.471 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:147.526 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:147.580 WorkRAMSize: 0x00060000
|
||||
T0584 000:147.634 FlashBankInfo:
|
||||
T0584 000:147.688 Name: OSPI Flash
|
||||
T0584 000:147.743 BaseAddr: 0x10000000
|
||||
T0584 000:147.934 LoaderInfo:
|
||||
T0584 000:148.002 Name: OSPI_Flash
|
||||
T0584 000:148.057 MaxSize: 0x08000000
|
||||
T0584 000:148.112 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3430\norflash.out
|
||||
T0584 000:148.167 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:148.228 Device entry created: E3640_NORFLASH
|
||||
T0584 000:148.264 ChipInfo:
|
||||
T0584 000:148.318 Vendor: SemiDrive
|
||||
T0584 000:148.373 Name: E3640_NORFLASH
|
||||
T0584 000:148.428 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:148.483 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:148.538 WorkRAMSize: 0x00060000
|
||||
T0584 000:148.592 FlashBankInfo:
|
||||
T0584 000:148.646 Name: OSPI Flash
|
||||
T0584 000:148.700 BaseAddr: 0x10000000
|
||||
T0584 000:148.871 LoaderInfo:
|
||||
T0584 000:148.949 Name: OSPI_Flash
|
||||
T0584 000:149.015 MaxSize: 0x08000000
|
||||
T0584 000:149.086 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3640\norflash.out
|
||||
T0584 000:149.152 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:149.225 Device entry created: E3648_NORFLASH
|
||||
T0584 000:149.269 ChipInfo:
|
||||
T0584 000:149.335 Vendor: SemiDrive
|
||||
T0584 000:149.413 Name: E3648_NORFLASH
|
||||
T0584 000:149.476 Core: JLINK_CORE_CORTEX_R5
|
||||
T0584 000:149.532 WorkRAMAddr: 0x003E0000
|
||||
T0584 000:149.586 WorkRAMSize: 0x00060000
|
||||
T0584 000:149.656 FlashBankInfo:
|
||||
T0584 000:149.740 Name: OSPI Flash
|
||||
T0584 000:149.818 BaseAddr: 0x10000000
|
||||
T0584 000:150.082 LoaderInfo:
|
||||
T0584 000:150.166 Name: OSPI_Flash
|
||||
T0584 000:150.244 MaxSize: 0x08000000
|
||||
T0584 000:150.337 Loader: C:\Users\liumin\AppData\Roaming\SEGGER\JLinkDevices\Devices\SemiDrive\E3648\norflash.out
|
||||
T0584 000:150.424 LoaderType: FLASH_ALGO_TYPE_OPEN
|
||||
T0584 000:151.316 - 49.230ms returns 6578
|
||||
T0584 000:151.367 JLINK_ExecCommand("device=E3106_NORFLASH", ...).
|
||||
T0584 000:152.771 Flash bank @ 0x00000000: SFL: Parsing sectorization info from ELF file
|
||||
T0584 000:152.834 FlashDevice.SectorInfo[0]: .SectorSize = 0x00001000, .SectorStartAddr = 0x00000000
|
||||
T0584 000:152.952 OFL: Init() present @ offset 0x0000C455
|
||||
T0584 000:153.019 OFL: UnInit() present @ offset 0x0000C4B5
|
||||
T0584 000:153.084 OFL: EraseSector() present @ offset 0x0000C4C3
|
||||
T0584 000:153.148 OFL: ProgramPage() present @ offset 0x0000C4FF
|
||||
T0584 000:153.212 OFL: EraseChip() present @ offset 0x0000C6E7
|
||||
T0584 000:153.276 OFL: BlankCheck() present @ offset 0x0000C53F
|
||||
T0584 000:153.340 OFL: Verify() N/A
|
||||
T0584 000:153.407 OFL: SEGGER_FL_Erase() N/A
|
||||
T0584 000:153.471 OFL: SEGGER_OPEN_Erase() present @ offset 0x0000C771
|
||||
T0584 000:153.536 OFL: SEGGER_FL_Program() N/A
|
||||
T0584 000:153.600 OFL: SEGGER_OPEN_Program() present @ offset 0x0000C66F
|
||||
T0584 000:153.665 OFL: SEGGER_FL_Read() N/A
|
||||
T0584 000:153.729 OFL: SEGGER_OPEN_Read() present @ offset 0x0000C717
|
||||
T0584 000:153.794 OFL: SEGGER_FL_CalcCRC() N/A
|
||||
T0584 000:153.858 OFL: SEGGER_OPEN_CalcCRC() present @ offset 0x0000C5ED
|
||||
T0584 000:153.929 OFL: SEGGER_FL_Start() N/A
|
||||
T0584 000:153.994 OFL: SEGGER_OPEN_Start() N/A
|
||||
T0584 000:154.058 OFL: SEGGER_FL_GetFlashInfo() N/A
|
||||
T0584 000:154.123 OFL: SEGGER_OPEN_GetFlashInfo() N/A
|
||||
T0584 000:154.194 OFL: SEGGER_FL_Verify() N/A
|
||||
T0584 000:154.260 OFL: SEGGER_FL_CheckBlank() N/A
|
||||
T0584 000:154.324 OFL: SEGGER_FL_Prepare() N/A
|
||||
T0584 000:154.389 OFL: SEGGER_FL_Restore() N/A
|
||||
T0584 000:154.453 OFL: SEGGER_FL_EraseChip() N/A
|
||||
T0584 000:154.518 OFL var <SEGGER_FL_GoIntEn>: N/A
|
||||
T0584 000:157.759 Device "E3106_NORFLASH" selected.
|
||||
T0584 000:160.004 - 8.595ms returns 0x00
|
||||
T0584 000:160.098 JLINK_EnableLog(...)
|
||||
T0584 000:160.138 - 0.040ms
|
||||
T0584 000:160.180 JLINK_GetEmuCaps()
|
||||
T0584 000:160.217 - 0.036ms returns 0xB9FF7BBF
|
||||
T0584 000:160.256 JLINK_TIF_GetAvailable(...)
|
||||
T0584 000:160.432 - 0.175ms
|
||||
T0584 000:160.479 JLINK_TIF_Select(JLINKARM_TIF_SWD)
|
||||
T0584 000:160.970 - 0.490ms returns 0x00
|
||||
T0584 000:161.017 JLINK_IsConnected()
|
||||
T0584 000:161.056 - 0.038ms returns FALSE
|
||||
T0584 000:161.095 JLINK_SetSpeed(4000)
|
||||
T0584 000:161.190 - 0.095ms
|
||||
T0584 000:161.233 JLINK_Connect()
|
||||
T0584 000:163.924
|
||||
***** Error:
|
||||
T0584 000:164.025 Error while evaluating J-Link script file: Error while compiling. Line 34, column 1:
|
||||
}
|
||||
^
|
||||
Missing return statement at the end of non-void function
|
||||
T0584 000:164.303
|
||||
***** Error:
|
||||
T0584 000:164.400 Failed prepare script file
|
||||
T0584 000:164.950 Found SW-DP with ID 0x2BA01477
|
||||
T0584 000:168.174 DPIDR: 0x2BA01477
|
||||
T0584 000:168.233 CoreSight SoC-400 or earlier
|
||||
T0584 000:168.287 Scanning AP map to find all available APs
|
||||
T0584 000:168.799 AP[1]: Stopped AP scan as end of AP map has been reached
|
||||
T0584 000:168.857 AP[0]: APB-AP (IDR: 0x24770002)
|
||||
T0584 000:168.921 Iterating through AP map to find APB-AP to use
|
||||
T0584 000:168.975 AP[0]: APB-AP found
|
||||
T0584 000:183.077 ROMTbl[0][0]: CompAddr: F0A01000 CID: B105900D, PID: 004BBC15 Cortex-R5
|
||||
T0584 000:184.808 Found Cortex-R5 r1p3
|
||||
T0584 000:184.877 4 code breakpoints, 3 data breakpoints
|
||||
T0584 000:184.940 Debug architecture ARMv7.0
|
||||
T0584 000:207.441 Data endian: little
|
||||
T0584 000:211.236 Main ID register: 0x411FC153
|
||||
T0584 000:231.743 I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
|
||||
T0584 000:231.815 D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
|
||||
T0584 000:238.432 TCM Type register: 0x00010001
|
||||
T0584 000:242.362 MPU Type register: 0x00001000
|
||||
T0584 000:246.372 System control register:
|
||||
T0584 000:246.448 Instruction endian: little
|
||||
T0584 000:246.503 Level-1 instruction cache disabled
|
||||
T0584 000:246.558 Level-1 data cache disabled
|
||||
T0584 000:246.614 MPU disabled
|
||||
T0584 000:246.668 Branch prediction enabled
|
||||
T0584 000:261.113 -- Max. mem block: 0x00010C40
|
||||
T0584 000:261.298 - 100.064ms returns 0x00
|
||||
T0584 000:261.394 JLINK_GetIdData(pIdData)
|
||||
T0584 000:261.733 pIdData->ScanLen=4
|
||||
T0584 000:261.790 pIdData->NumDevices=1
|
||||
T0584 000:261.852 pIdData->aId[0]=0x2BA01477
|
||||
T0584 000:261.905 pIdData->aIrRead[0]=0
|
||||
T0584 000:261.958 pIdData->aScanLen[0]=4
|
||||
T0584 000:262.012 pIdData->aScanRead[0]=0
|
||||
T0584 000:262.065 - 0.671ms
|
||||
T0584 000:262.111 JLINK_GetMemZones(...)
|
||||
T0584 000:262.148 - 0.037ms returns 2
|
||||
T0584 000:262.189 JLINK_HasError()
|
||||
T0584 000:262.228 JLINK_CORE_GetFound()
|
||||
T0584 000:262.266 - 0.037ms returns 0xC0100FF
|
||||
T0584 000:262.313 JLINK_GetResetTypeDesc
|
||||
T0584 000:262.350 - 0.036ms
|
||||
T0584 000:262.392 JLINK_SetResetDelay(0)
|
||||
T0584 000:262.428 - 0.036ms
|
||||
T0584 000:262.468 JLINK_Reset()
|
||||
T0584 000:392.723
|
||||
***** Warning:
|
||||
T0584 000:392.881 CPU not halted after Reset, halting using Halt request
|
||||
T0584 000:399.763 - 137.287ms
|
||||
T0584 000:400.115 JLINK_Halt()
|
||||
T0584 000:400.239 - 0.122ms returns 0x00
|
||||
T0584 000:400.378 JLINK_GetDeviceFamily
|
||||
T0584 000:400.458 - 0.080ms returns 12
|
||||
T0584 000:400.535 JLINK_CORE_GetFound()
|
||||
T0584 000:400.633 - 0.095ms returns 0xC0100FF
|
||||
T0584 000:400.778 JLINK_ReadRegs(NumRegs = 17, Indexes: 9, 8, 0, 1, 2, 3, 4, 5, 6, 7, 74, 75, 76, 77, 78, 79, 80)
|
||||
T0584 000:403.363 -- R15 (PC)=0x3D080, CPSR=0x197, R0=0x10000000, R1=0x1143540C, R2=0x03, R3=0x36D, R4=0x5AA5F00F, R5=0xA55A0FF0, R6=0x5AA5F00F, R7=0x190FF70, R8=0x5AA5F00F, R9=0x7C003C, R10=0x00, R11=0x190FF6C, R12=0x00, R13=0x1910000, R14=0x40104
|
||||
T0584 000:403.539 - 2.761ms returns 0x00
|
||||
T0584 000:403.669 JLINK_ReadRegs(NumRegs = 7, Indexes: 10, 11, 12, 13, 14, 15, 16)
|
||||
T0584 000:403.812 -- R8_USR=0x5AA5F00F, R9_USR=0x7C003C, R10_USR=0x00, R11_USR=0x190FF6C, R12_USR=0x00, R13_USR=0x3FB8E8, R14_USR=0x3FB8E9
|
||||
T0584 000:403.974 - 0.304ms returns 0x00
|
||||
T0584 000:404.059 JLINK_ReadRegs(NumRegs = 8, Indexes: 18, 19, 20, 21, 22, 23, 24, 17)
|
||||
T0584 000:405.940 -- R8_FIQ=0x00, R9_FIQ=0x00, R10_FIQ=0x00, R11_FIQ=0x00, R12_FIQ=0x00, R13_FIQ=0x1910000, R14_FIQ=0x00, SPSR_FIQ=0x1D3
|
||||
T0584 000:406.384 - 2.320ms returns 0x00
|
||||
T0584 000:406.485 JLINK_ReadRegs(NumRegs = 3, Indexes: 32, 33, 31)
|
||||
T0584 000:407.579 -- R13_IRQ=0x1910000, R14_IRQ=0x00, SPSR_IRQ=0x1D3
|
||||
T0584 000:407.700 - 1.214ms returns 0x00
|
||||
T0584 000:407.802 JLINK_ReadRegs(NumRegs = 3, Indexes: 26, 27, 25)
|
||||
T0584 000:408.723 -- R13_SVC=0x190FF58, R14_SVC=0x190703C, SPSR_SVC=0x1D3
|
||||
T0584 000:408.888 - 1.085ms returns 0x00
|
||||
T0584 000:408.994 JLINK_ReadRegs(NumRegs = 3, Indexes: 29, 30, 28)
|
||||
T0584 000:409.073 -- R13_ABT=0x1910000, R14_ABT=0x40104, SPSR_ABT=0x197
|
||||
T0584 000:409.185 - 0.190ms returns 0x00
|
||||
T0584 000:409.262 JLINK_ReadRegs(NumRegs = 3, Indexes: 35, 36, 34)
|
||||
T0584 000:410.534 -- R13_UND=0x1910000, R14_UND=0x00, SPSR_UND=0x1D3
|
||||
T0584 000:410.676 - 1.413ms returns 0x00
|
||||
T0584 000:410.809 JLINK_CP15_WriteEx(CRn = 1, CRm = 0, op1 = 0, op2 = 0, Data = 0x08E7087A)
|
||||
T0584 000:418.158 - 7.349ms returns 0
|
||||
T0584 000:418.278 JLINK_CP15_WriteEx(CRn = 1, CRm = 0, op1 = 0, op2 = 1, Data = 0x00000020)
|
||||
T0584 000:423.940 - 5.661ms returns 0
|
||||
T0584 000:424.053 JLINK_CP15_WriteEx(CRn = 9, CRm = 1, op1 = 0, op2 = 1, Data = 0x003E0001)
|
||||
T0584 000:429.725 - 5.671ms returns 0
|
||||
T0584 000:429.921 JLINK_CP15_WriteEx(CRn = 9, CRm = 1, op1 = 0, op2 = 0, Data = 0x003F0001)
|
||||
T0584 000:435.892 - 5.970ms returns 0
|
||||
T0584 000:436.025 JLINK_IsOpen()
|
||||
T0584 000:436.102 - 0.076ms returns 0x01
|
||||
T0584 000:446.409 JLINK_Close()
|
||||
T0584 000:463.521 - 17.110ms
|
||||
T0584 000:463.653
|
||||
T0584 000:463.785 Closed
|
||||
T4594 000:193.475 SEGGER J-Link V7.98a Log File
|
||||
T4594 000:193.866 DLL Compiled: Jul 19 2024 15:01:03
|
||||
T4594 000:193.965 Logging started @ 2024-07-28 11:37
|
||||
T4594 000:194.062 Process: C:\Program Files\SEGGER\JLink_V798a\JFlash.exe
|
||||
T4594 000:194.192 - 194.185ms
|
||||
T4594 000:194.346 JLINK_SelectUSB(Port = 0)
|
||||
T4594 000:200.677 - 6.329ms returns 0
|
||||
T4594 000:200.837 JLINK_OpenEx(...)
|
||||
T4594 000:207.719 Firmware: J-Link V9 compiled May 7 2021 16:26:12
|
||||
T4594 000:208.948 Firmware: J-Link V9 compiled May 7 2021 16:26:12
|
||||
T4594 000:209.283 Decompressing FW timestamp took 135 us
|
||||
T4594 000:214.933 Hardware: V9.40
|
||||
T4594 000:215.251 S/N: 59406426
|
||||
T4594 000:215.305 OEM: SEGGER
|
||||
T4594 000:215.359 Feature(s): RDI, GDB, FlashDL, FlashBP, JFlash
|
||||
T4594 000:215.963 Bootloader: (Could not read)
|
||||
T4594 000:216.687 TELNET listener socket opened on port 19021
|
||||
T4594 000:217.004 WEBSRV WEBSRV_Init(): Starting webserver thread(s)
|
||||
T4594 000:217.166 WEBSRV Webserver running on local port 19080
|
||||
T4594 000:217.461 Looking for J-Link GUI Server exe at: C:\Program Files\SEGGER\JLink_V798a\JLinkGUIServer.exe
|
||||
T4594 000:217.562 Forking J-Link GUI Server: C:\Program Files\SEGGER\JLink_V798a\JLinkGUIServer.exe
|
||||
T4594 000:229.506 J-Link GUI Server info: "J-Link GUI server V7.98a "
|
||||
T4594 000:229.918 - 29.073ms returns "O.K."
|
||||
T4594 000:229.999 JLINK_GetFirmwareString(...)
|
||||
T4594 000:230.057 - 0.060ms
|
||||
T4594 000:230.115 JLINK_GetSN()
|
||||
T4594 000:230.165 - 0.052ms returns 59406426
|
||||
T4594 000:230.324 JLINK_TIF_Select(JLINKARM_TIF_SWD)
|
||||
T4594 000:230.912 - 0.583ms returns 0x00
|
||||
T4594 000:230.982 JLINK_EMU_GetProductId()
|
||||
T4594 000:231.039 - 0.057ms
|
||||
T4594 000:233.799 JLINK_CORE_Select(0xC0100FF == Cortex-R5)
|
||||
T4594 000:233.890 - 0.092ms
|
||||
T4594 000:233.953 JLINK_ExecCommand("Device = E3640_HYPERFLASH", ...).
|
||||
T4594 000:236.162 Flash bank @ 0x00000000: SFL: Parsing sectorization info from ELF file
|
||||
T4594 000:236.259 FlashDevice.SectorInfo[0]: .SectorSize = 0x00040000, .SectorStartAddr = 0x00000000
|
||||
T4594 000:236.376 OFL: Init() present @ offset 0x0000D691
|
||||
T4594 000:236.466 OFL: UnInit() present @ offset 0x0000D6F3
|
||||
T4594 000:236.554 OFL: EraseSector() present @ offset 0x0000D703
|
||||
T4594 000:236.801 OFL: ProgramPage() present @ offset 0x0000D741
|
||||
T4594 000:236.976 OFL: EraseChip() present @ offset 0x0000D967
|
||||
T4594 000:237.110 OFL: BlankCheck() present @ offset 0x0000D7A5
|
||||
T4594 000:237.244 OFL: Verify() N/A
|
||||
T4594 000:237.451 OFL: SEGGER_FL_Erase() N/A
|
||||
T4594 000:237.603 OFL: SEGGER_OPEN_Erase() present @ offset 0x0000D9F1
|
||||
T4594 000:237.914 OFL: SEGGER_FL_Program() N/A
|
||||
T4594 000:238.487 OFL: SEGGER_OPEN_Program() present @ offset 0x0000D8D1
|
||||
T4594 000:238.701 OFL: SEGGER_FL_Read() N/A
|
||||
T4594 000:238.798 OFL: SEGGER_OPEN_Read() present @ offset 0x0000D997
|
||||
T4594 000:238.889 OFL: SEGGER_FL_CalcCRC() N/A
|
||||
T4594 000:238.979 OFL: SEGGER_OPEN_CalcCRC() present @ offset 0x0000D84F
|
||||
T4594 000:239.083 OFL: SEGGER_FL_Start() N/A
|
||||
T4594 000:239.764 OFL: SEGGER_OPEN_Start() N/A
|
||||
T4594 000:239.860 OFL: SEGGER_FL_GetFlashInfo() N/A
|
||||
T4594 000:239.957 OFL: SEGGER_OPEN_GetFlashInfo() N/A
|
||||
T4594 000:240.044 OFL: SEGGER_FL_Verify() N/A
|
||||
T4594 000:240.132 OFL: SEGGER_FL_CheckBlank() N/A
|
||||
T4594 000:240.353 OFL: SEGGER_FL_Prepare() N/A
|
||||
T4594 000:240.465 OFL: SEGGER_FL_Restore() N/A
|
||||
T4594 000:240.553 OFL: SEGGER_FL_EraseChip() N/A
|
||||
T4594 000:240.755 OFL var <SEGGER_FL_GoIntEn>: N/A
|
||||
T4594 000:246.886 Device "E3640_HYPERFLASH" selected.
|
||||
T4594 000:250.115 - 16.103ms returns 0x00
|
||||
T4594 000:250.189 JLINK_ExecCommand("ExcludeFlashCacheRange 0x0-0xFFFFFFFF", ...).
|
||||
T4594 000:250.252 - 0.010ms returns 0x00
|
||||
T4594 000:250.304 JLINK_ExecCommand("SetEnableMemCache 0", ...).
|
||||
T4594 000:250.356 - 0.001ms returns 0x01
|
||||
T4594 000:250.407 JLINK_ExecCommand("SetAllowFlashCache 0", ...).
|
||||
T4594 000:250.459 - 0.001ms returns 0x01
|
||||
T4594 000:250.519 JLINK_GetAvailableLicense()
|
||||
T4594 000:260.149 - 9.628ms returns 0x05
|
||||
T4594 000:260.314 JLINK_SetEndian(ARM_ENDIAN_LITTLE)
|
||||
T4594 000:260.371 - 0.057ms returns 0
|
||||
T4594 000:260.539 JLINK_SetSpeed(4000)
|
||||
T4594 000:260.800 - 0.260ms
|
||||
T4594 000:260.868 JLINK_GetSpeed()
|
||||
T4594 000:260.919 - 0.050ms returns 4000
|
||||
T4594 000:260.987 JLINK_GetHWStatus(...)
|
||||
T4594 000:261.227 - 0.244ms returns 0
|
||||
T4594 000:261.291 JLINK_Connect()
|
||||
T4594 000:262.117 Found SW-DP with ID 0x2BA01477
|
||||
T4594 000:265.830 DPIDR: 0x2BA01477
|
||||
T4594 000:265.922 CoreSight SoC-400 or earlier
|
||||
T4594 000:265.998 Scanning AP map to find all available APs
|
||||
T4594 000:266.623 AP[1]: Stopped AP scan as end of AP map has been reached
|
||||
T4594 000:266.708 AP[0]: APB-AP (IDR: 0x24770002)
|
||||
T4594 000:266.789 Iterating through AP map to find APB-AP to use
|
||||
T4594 000:266.868 AP[0]: APB-AP found
|
||||
T4594 000:286.083 ROMTbl[0][0]: CompAddr: F0A01000 CID: B105900D, PID: 004BBC15 Cortex-R5
|
||||
T4594 000:287.791 Found Cortex-R5 r1p3
|
||||
T4594 000:287.865 4 code breakpoints, 3 data breakpoints
|
||||
T4594 000:287.919 Debug architecture ARMv7.0
|
||||
T4594 000:310.445 Data endian: little
|
||||
T4594 000:314.354 Main ID register: 0x411FC153
|
||||
T4594 000:418.507
|
||||
***** Error:
|
||||
T4594 000:418.584 Timeout while reading DCC data
|
||||
T4594 000:519.481
|
||||
***** Error:
|
||||
T4594 000:519.562 Timeout while reading DCC data
|
||||
T4594 000:519.627 I-Cache L1: 0 KB, 1 Sets, 16 Bytes/Line, 1-Way
|
||||
T4594 000:519.682 D-Cache L1: 0 KB, 1 Sets, 16 Bytes/Line, 1-Way
|
||||
T4594 000:620.432
|
||||
***** Error:
|
||||
T4594 000:620.513 Timeout while reading DCC data
|
||||
T4594 000:620.571 D-Cache L2: 0 KB, 1 Sets, 16 Bytes/Line, 1-Way
|
||||
T4594 000:721.352
|
||||
***** Error:
|
||||
T4594 000:721.433 Timeout while reading DCC data
|
||||
T4594 000:822.369
|
||||
***** Error:
|
||||
T4594 000:822.456 Timeout while reading DCC data
|
||||
T4594 000:822.523 L3 (unknown cache type)
|
||||
T4594 000:923.212
|
||||
***** Error:
|
||||
T4594 000:923.293 Timeout while reading DCC data
|
||||
T4594 000:923.350 TCM Type register: 0x00208FE0
|
||||
T4594 001:023.283
|
||||
***** Error:
|
||||
T4594 001:023.364 Timeout while reading DCC data
|
||||
T4594 001:023.421 MPU Type register: 0x00208FE0
|
||||
T4594 001:124.248
|
||||
***** Error:
|
||||
T4594 001:124.635 Timeout while reading DCC data
|
||||
T4594 001:124.713 System control register:
|
||||
T4594 001:124.786 Instruction endian: little
|
||||
T4594 001:124.858 Level-1 instruction cache disabled
|
||||
T4594 001:124.928 Level-1 data cache disabled
|
||||
T4594 001:125.002 MPU disabled
|
||||
T4594 001:125.056 Branch prediction enabled
|
||||
T4594 001:130.458 -- Max. mem block: 0x00010C40
|
||||
T4594 001:130.624 - 869.332ms returns 0x00
|
||||
T4594 001:130.841 JLINK_Halt()
|
||||
T4594 001:133.246 - 2.405ms returns 0x00
|
||||
T4594 001:133.305 JLINK_SetSpeed(4000)
|
||||
T4594 001:133.393 - 0.088ms
|
||||
T4594 001:133.435 JLINK_GetSpeed()
|
||||
T4594 001:133.472 - 0.036ms returns 4000
|
||||
T4594 001:139.476 JLINK_Close()
|
||||
T4594 001:154.682 - 15.204ms
|
||||
T4594 001:154.764
|
||||
T4594 001:154.816 Closed
|
||||
T2988 000:187.790 SEGGER J-Link V7.98a Log File
|
||||
T2988 000:188.080 DLL Compiled: Jul 19 2024 15:01:03
|
||||
T2988 000:188.170 Logging started @ 2024-07-28 11:37
|
||||
T2988 000:188.289 Process: C:\Program Files\SEGGER\JLink_V798a\JFlash.exe
|
||||
T2988 000:188.427 - 188.421ms
|
||||
T2988 000:188.610 JLINK_SelectUSB(Port = 0)
|
||||
T2988 000:195.304 - 6.701ms returns 0
|
||||
T2988 000:195.463 JLINK_OpenEx(...)
|
||||
T2988 000:202.342 Firmware: J-Link V9 compiled May 7 2021 16:26:12
|
||||
T2988 000:203.130 Firmware: J-Link V9 compiled May 7 2021 16:26:12
|
||||
T2988 000:203.438 Decompressing FW timestamp took 131 us
|
||||
T2988 000:209.162 Hardware: V9.40
|
||||
T2988 000:209.506 S/N: 59406426
|
||||
T2988 000:209.561 OEM: SEGGER
|
||||
T2988 000:209.615 Feature(s): RDI, GDB, FlashDL, FlashBP, JFlash
|
||||
T2988 000:210.210 Bootloader: (Could not read)
|
||||
T2988 000:210.910 TELNET listener socket opened on port 19021
|
||||
T2988 000:211.212 WEBSRV WEBSRV_Init(): Starting webserver thread(s)
|
||||
T2988 000:211.393 WEBSRV Webserver running on local port 19080
|
||||
T2988 000:211.684 Looking for J-Link GUI Server exe at: C:\Program Files\SEGGER\JLink_V798a\JLinkGUIServer.exe
|
||||
T2988 000:211.785 Forking J-Link GUI Server: C:\Program Files\SEGGER\JLink_V798a\JLinkGUIServer.exe
|
||||
T2988 000:224.603 J-Link GUI Server info: "J-Link GUI server V7.98a "
|
||||
T2988 000:225.008 - 29.539ms returns "O.K."
|
||||
T2988 000:225.096 JLINK_GetFirmwareString(...)
|
||||
T2988 000:225.158 - 0.065ms
|
||||
T2988 000:225.216 JLINK_GetSN()
|
||||
T2988 000:225.267 - 0.054ms returns 59406426
|
||||
T2988 000:225.426 JLINK_TIF_Select(JLINKARM_TIF_SWD)
|
||||
T2988 000:225.996 - 0.568ms returns 0x00
|
||||
T2988 000:226.053 JLINK_EMU_GetProductId()
|
||||
T2988 000:226.101 - 0.047ms
|
||||
T2988 000:228.956 JLINK_CORE_Select(0xC0100FF == Cortex-R5)
|
||||
T2988 000:229.040 - 0.085ms
|
||||
T2988 000:229.099 JLINK_ExecCommand("Device = E3640_HYPERFLASH", ...).
|
||||
T2988 000:230.981 Flash bank @ 0x00000000: SFL: Parsing sectorization info from ELF file
|
||||
T2988 000:231.076 FlashDevice.SectorInfo[0]: .SectorSize = 0x00040000, .SectorStartAddr = 0x00000000
|
||||
T2988 000:231.199 OFL: Init() present @ offset 0x0000D691
|
||||
T2988 000:231.295 OFL: UnInit() present @ offset 0x0000D6F3
|
||||
T2988 000:231.389 OFL: EraseSector() present @ offset 0x0000D703
|
||||
T2988 000:231.475 OFL: ProgramPage() present @ offset 0x0000D741
|
||||
T2988 000:231.588 OFL: EraseChip() present @ offset 0x0000D967
|
||||
T2988 000:231.691 OFL: BlankCheck() present @ offset 0x0000D7A5
|
||||
T2988 000:231.789 OFL: Verify() N/A
|
||||
T2988 000:231.907 OFL: SEGGER_FL_Erase() N/A
|
||||
T2988 000:231.997 OFL: SEGGER_OPEN_Erase() present @ offset 0x0000D9F1
|
||||
T2988 000:232.099 OFL: SEGGER_FL_Program() N/A
|
||||
T2988 000:232.218 OFL: SEGGER_OPEN_Program() present @ offset 0x0000D8D1
|
||||
T2988 000:232.308 OFL: SEGGER_FL_Read() N/A
|
||||
T2988 000:232.394 OFL: SEGGER_OPEN_Read() present @ offset 0x0000D997
|
||||
T2988 000:232.545 OFL: SEGGER_FL_CalcCRC() N/A
|
||||
T2988 000:232.678 OFL: SEGGER_OPEN_CalcCRC() present @ offset 0x0000D84F
|
||||
T2988 000:232.764 OFL: SEGGER_FL_Start() N/A
|
||||
T2988 000:232.851 OFL: SEGGER_OPEN_Start() N/A
|
||||
T2988 000:232.939 OFL: SEGGER_FL_GetFlashInfo() N/A
|
||||
T2988 000:233.031 OFL: SEGGER_OPEN_GetFlashInfo() N/A
|
||||
T2988 000:233.136 OFL: SEGGER_FL_Verify() N/A
|
||||
T2988 000:233.233 OFL: SEGGER_FL_CheckBlank() N/A
|
||||
T2988 000:233.356 OFL: SEGGER_FL_Prepare() N/A
|
||||
T2988 000:233.540 OFL: SEGGER_FL_Restore() N/A
|
||||
T2988 000:233.650 OFL: SEGGER_FL_EraseChip() N/A
|
||||
T2988 000:233.749 OFL var <SEGGER_FL_GoIntEn>: N/A
|
||||
T2988 000:238.922 Device "E3640_HYPERFLASH" selected.
|
||||
T2988 000:242.335 - 13.179ms returns 0x00
|
||||
T2988 000:242.402 JLINK_ExecCommand("ExcludeFlashCacheRange 0x0-0xFFFFFFFF", ...).
|
||||
T2988 000:242.464 - 0.009ms returns 0x00
|
||||
T2988 000:242.516 JLINK_ExecCommand("SetEnableMemCache 0", ...).
|
||||
T2988 000:242.574 - 0.002ms returns 0x01
|
||||
T2988 000:242.629 JLINK_ExecCommand("SetAllowFlashCache 0", ...).
|
||||
T2988 000:242.679 - 0.001ms returns 0x01
|
||||
T2988 000:242.742 JLINK_GetAvailableLicense()
|
||||
T2988 000:250.927 - 8.184ms returns 0x05
|
||||
T2988 000:251.026 JLINK_SetEndian(ARM_ENDIAN_LITTLE)
|
||||
T2988 000:251.069 - 0.043ms returns 0
|
||||
T2988 000:251.196 JLINK_SetSpeed(4000)
|
||||
T2988 000:251.381 - 0.184ms
|
||||
T2988 000:251.448 JLINK_GetSpeed()
|
||||
T2988 000:251.498 - 0.049ms returns 4000
|
||||
T2988 000:251.563 JLINK_GetHWStatus(...)
|
||||
T2988 000:251.775 - 0.214ms returns 0
|
||||
T2988 000:251.832 JLINK_Connect()
|
||||
T2988 000:252.624 Found SW-DP with ID 0x2BA01477
|
||||
T2988 000:255.901 DPIDR: 0x2BA01477
|
||||
T2988 000:255.971 CoreSight SoC-400 or earlier
|
||||
T2988 000:256.025 Scanning AP map to find all available APs
|
||||
T2988 000:256.552 AP[1]: Stopped AP scan as end of AP map has been reached
|
||||
T2988 000:256.614 AP[0]: APB-AP (IDR: 0x24770002)
|
||||
T2988 000:256.668 Iterating through AP map to find APB-AP to use
|
||||
T2988 000:256.721 AP[0]: APB-AP found
|
||||
T2988 000:270.422 ROMTbl[0][0]: CompAddr: F0A01000 CID: B105900D, PID: 004BBC15 Cortex-R5
|
||||
T2988 000:272.116 Found Cortex-R5 r1p3
|
||||
T2988 000:272.178 4 code breakpoints, 3 data breakpoints
|
||||
T2988 000:272.233 Debug architecture ARMv7.0
|
||||
T2988 000:293.329 Data endian: little
|
||||
T2988 000:297.449 Main ID register: 0x411FC153
|
||||
T2988 000:414.311
|
||||
***** Error:
|
||||
T2988 000:414.443 Timeout while reading DCC data
|
||||
T2988 000:414.535 I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
|
||||
T2988 000:414.611 D-Cache L1: 0 KB, 1 Sets, 16 Bytes/Line, 1-Way
|
||||
T2988 000:516.116
|
||||
***** Error:
|
||||
T2988 000:516.198 Timeout while reading DCC data
|
||||
T2988 000:516.255 TCM Type register: 0x01240000
|
||||
T2988 000:617.469
|
||||
***** Error:
|
||||
T2988 000:617.692 Timeout while reading DCC data
|
||||
T2988 000:617.764 MPU Type register: 0x01240000
|
||||
T2988 000:717.987
|
||||
***** Error:
|
||||
T2988 000:718.067 Timeout while reading DCC data
|
||||
T2988 000:718.123 System control register:
|
||||
T2988 000:718.177 Instruction endian: little
|
||||
T2988 000:718.230 Level-1 instruction cache disabled
|
||||
T2988 000:718.283 Level-1 data cache disabled
|
||||
T2988 000:718.336 MPU disabled
|
||||
T2988 000:718.390 Branch prediction disabled
|
||||
T2988 000:723.415 -- Max. mem block: 0x00010C40
|
||||
T2988 000:723.587 - 471.754ms returns 0x00
|
||||
T2988 000:723.823 JLINK_Halt()
|
||||
T2988 000:726.348 - 2.524ms returns 0x00
|
||||
T2988 000:726.413 JLINK_SetSpeed(4000)
|
||||
T2988 000:726.503 - 0.090ms
|
||||
T2988 000:726.546 JLINK_GetSpeed()
|
||||
T2988 000:726.582 - 0.035ms returns 4000
|
||||
T2988 000:736.298 JLINK_Close()
|
||||
T2988 000:743.166 - 6.867ms
|
||||
T2988 000:743.251
|
||||
T2988 000:743.304 Closed
|
||||
53
devices/script/JFLASH/SemiDrive.JLinkScript
Normal file
53
devices/script/JFLASH/SemiDrive.JLinkScript
Normal file
@@ -0,0 +1,53 @@
|
||||
/*********************************************************************
|
||||
* SEGGER Microcontroller GmbH *
|
||||
* Solutions for real time microcontroller applications *
|
||||
**********************************************************************
|
||||
* *
|
||||
* (c) 1995 - 2018 SEGGER Microcontroller GmbH *
|
||||
* *
|
||||
* Internet: www.segger.com Support: support@segger.com *
|
||||
* *
|
||||
**********************************************************************
|
||||
----------------------------------------------------------------------
|
||||
Purpose :
|
||||
---------------------------END-OF-HEADER------------------------------
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ResetTarget
|
||||
*/
|
||||
//void ResetTarget(void) {
|
||||
// In case cores 1-3 are reset, we do nothing,
|
||||
// as we would lose connection to these cores, when resetting the device
|
||||
// as a reset disables the clock to them.
|
||||
//}
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* InitTarget
|
||||
*/
|
||||
int ConfigTargetSettings(void) {
|
||||
JLINK_SYS_Report("----------JLinkScript ConfigTargetSettings----------");
|
||||
JLINK_CPU = CORTEX_R5;
|
||||
JLINK_CORESIGHT_CoreBaseAddr = 0xF2081000;
|
||||
}
|
||||
|
||||
//static void disable_watchdog(U32 Addr) {
|
||||
// int ret;
|
||||
// ret = JLINK_MEM_ReadU32(Addr);
|
||||
// ret = ret & (~2);
|
||||
// JLINK_MEM_WriteU32(Addr, ret);
|
||||
//}
|
||||
//
|
||||
//int AfterResetTarget(void){
|
||||
// JLINK_SYS_Report("----------JLinkScript AfterResetTarget----------");
|
||||
// disable_watchdog(0xF07E0000);
|
||||
// disable_watchdog(0xF07F0000);
|
||||
// disable_watchdog(0xF2100000);
|
||||
// disable_watchdog(0xF2110000);
|
||||
// disable_watchdog(0xF0BE0000);
|
||||
// disable_watchdog(0xF0BF0000);
|
||||
// disable_watchdog(0xF31F0000);
|
||||
// return 0;
|
||||
//}
|
||||
78
devices/script/JFLASH/SemiDrive.jflash
Normal file
78
devices/script/JFLASH/SemiDrive.jflash
Normal file
@@ -0,0 +1,78 @@
|
||||
AppVersion = 75604
|
||||
FileVersion = 2
|
||||
[GENERAL]
|
||||
aATEModuleSel[24] = 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
|
||||
ConnectMode = 0
|
||||
CurrentFile = ""
|
||||
DataFileSAddr = 0x00000000
|
||||
GUIMode = 0
|
||||
HostName = ""
|
||||
TargetIF = 1
|
||||
USBPort = 0
|
||||
USBSerialNo = 0x00000000
|
||||
UseATEModuleSelection = 0
|
||||
[JTAG]
|
||||
IRLen = 0
|
||||
MultipleTargets = 0
|
||||
NumDevices = 0
|
||||
Speed0 = 4000
|
||||
Speed1 = 4000
|
||||
TAP_Number = 0
|
||||
UseAdaptive0 = 0
|
||||
UseAdaptive1 = 0
|
||||
UseMaxSpeed0 = 0
|
||||
UseMaxSpeed1 = 0
|
||||
[CPU]
|
||||
NumInitSteps = 0
|
||||
NumExitSteps = 0
|
||||
UseScriptFile = 0
|
||||
ScriptFile = ""
|
||||
UseRAM = 1
|
||||
RAMAddr = 0x003E0000
|
||||
RAMSize = 0x00060000
|
||||
CheckCoreID = 0
|
||||
CoreID = 0x00000000
|
||||
CoreIDMask = 0x0F000FFF
|
||||
UseAutoSpeed = 0x00000001
|
||||
ClockSpeed = 0x00000000
|
||||
EndianMode = 0
|
||||
ChipName = "E3640_HYPERFLASH"
|
||||
[FLASH]
|
||||
aRangeSel[1] = 0-8191
|
||||
BankName = "OSPI Flash"
|
||||
BankSelMode = 1
|
||||
BaseAddr = 0x10000000
|
||||
NumBanks = 1
|
||||
[PRODUCTION]
|
||||
AutoPerformsDisconnect = 0
|
||||
AutoPerformsErase = 1
|
||||
AutoPerformsProgram = 1
|
||||
AutoPerformsSecure = 0
|
||||
AutoPerformsStartApp = 0
|
||||
AutoPerformsUnsecure = 0
|
||||
AutoPerformsVerify = 1
|
||||
EnableFixedVTref = 0
|
||||
EnableTargetPower = 0
|
||||
EraseType = 1
|
||||
FixedVTref = 0x00000CE4
|
||||
MonitorVTref = 1
|
||||
MonitorVTrefMax = 0x0000157C
|
||||
MonitorVTrefMin = 0x000003E8
|
||||
OverrideTimeouts = 0
|
||||
ProgramSN = 0
|
||||
SerialFile = ""
|
||||
SNAddr = 0x00000000
|
||||
SNInc = 0x00000001
|
||||
SNLen = 0x00000004
|
||||
SNListFile = ""
|
||||
SNValue = 0x00000001
|
||||
StartAppType = 0
|
||||
TargetPowerDelay = 0x00000014
|
||||
TimeoutErase = 0x00003A98
|
||||
TimeoutProgram = 0x00002710
|
||||
TimeoutVerify = 0x00002710
|
||||
VerifyType = 1
|
||||
[PERFORMANCE]
|
||||
DisableSkipBlankDataOnProgram = 0x00000000
|
||||
PerfromBlankCheckPriorEraseChip = 0x00000001
|
||||
PerfromBlankCheckPriorEraseSelectedSectors = 0x00000000
|
||||
282
devices/script/JFLASH/jflash.bat
Normal file
282
devices/script/JFLASH/jflash.bat
Normal file
@@ -0,0 +1,282 @@
|
||||
@echo off
|
||||
@REM chcp 65001
|
||||
setlocal EnableDelayedExpansion
|
||||
|
||||
|
||||
|
||||
@REM 配置路径
|
||||
set JLinkPathName="C:\Program Files\SEGGER\JLink_V798a\JLink.exe"
|
||||
set JFlashPathName="C:\Program Files\SEGGER\JLink_V798a\JFlash.exe"
|
||||
set device="E3106_NORFLASH"
|
||||
|
||||
@REM E3:=0x3E0001/0x3F0001 E3L:0x4E0001/0x4F0001
|
||||
set TCMBConfig=0x3E0001
|
||||
set TCMAConfig=0x3F0001
|
||||
|
||||
@REM 可不修改
|
||||
set JFlashLogPathName="%cd%\JFlash.log"
|
||||
set JLinkARMLogPathName="%cd%\JLinkARM.log"
|
||||
set JFlashProjPathName="%cd%\SemiDrive.jflash"
|
||||
set JLinkScriptPathName="%cd%\SemiDrive.JLinkScript"
|
||||
|
||||
|
||||
|
||||
call :PREPROCESS_BEFORE_DOWNLOAD
|
||||
|
||||
|
||||
|
||||
@REM ================================================================================================================================================
|
||||
@REM norflash 下载
|
||||
@REM ================================================================================================================================================
|
||||
|
||||
set flash_folder=E3106_NORFLASH
|
||||
|
||||
@REM @REM sfs和rfd在一个扇区，需merge再download
|
||||
set DownloadFilePathName="%cd%\%flash_folder%\sfs.bin"
|
||||
set DownloadFileAddr=0x10000000
|
||||
set MergeFilePathName="%cd%\%flash_folder%\rfd.bin"
|
||||
set MergeFileAddr=0x100000F0
|
||||
call :JFlash_EXE %DownloadFilePathName% %DownloadFileAddr% %MergeFilePathName% %MergeFileAddr%
|
||||
|
||||
set DownloadFilePathName="%cd%\%flash_folder%\boot0.bin"
|
||||
set DownloadFileAddr=0x10010000
|
||||
call :JFlash_EXE %DownloadFilePathName% %DownloadFileAddr%
|
||||
|
||||
@REM set DownloadFilePathName="%cd%\%flash_folder%\boot1.bin"
|
||||
@REM set DownloadFileAddr=0x10407000
|
||||
@REM call :JFlash_EXE %DownloadFilePathName% %DownloadFileAddr%
|
||||
|
||||
@REM set DownloadFilePathName="%cd%\%flash_folder%\boot2.bin"
|
||||
@REM set DownloadFileAddr=0x10807000
|
||||
@REM call :JFlash_EXE %DownloadFilePathName% %DownloadFileAddr%
|
||||
|
||||
@REM set DownloadFilePathName="%cd%\%flash_folder%\0x140000.bin"
|
||||
@REM set DownloadFileAddr=0x10140000
|
||||
@REM call :JFlash_EXE %DownloadFilePathName% %DownloadFileAddr%
|
||||
|
||||
echo Download Done
|
||||
pause
|
||||
|
||||
|
||||
|
||||
@REM ================================================================================================================================================
|
||||
@REM hyperflash 下载
|
||||
@REM ================================================================================================================================================
|
||||
|
||||
REM set flash_folder=E3106_NORFLASH
|
||||
|
||||
@REM @REM sfs和rfd在一个扇区，需merge再download
|
||||
@REM set DownloadFilePathName="%cd%\%flash_folder%\sfs.bin"
|
||||
@REM set DownloadFileAddr=0x10000000
|
||||
@REM set MergeFilePathName="%cd%\%flash_folder%\rfd.bin"
|
||||
@REM set MergeFileAddr=0x100000F0
|
||||
@REM call :JFlash_EXE %DownloadFilePathName% %DownloadFileAddr% %MergeFilePathName% %MergeFileAddr%
|
||||
|
||||
@REM set DownloadFilePathName="%cd%\%flash_folder%\boot0.bin"
|
||||
@REM set DownloadFileAddr=0x100C0000
|
||||
@REM call :JFlash_EXE %DownloadFilePathName% %DownloadFileAddr%
|
||||
|
||||
@REM set DownloadFilePathName="%cd%\%flash_folder%\boot1.bin"
|
||||
@REM set DownloadFileAddr=0x104C0000
|
||||
@REM call :JFlash_EXE %DownloadFilePathName% %DownloadFileAddr%
|
||||
|
||||
@REM set DownloadFilePathName="%cd%\%flash_folder%\boot2.bin"
|
||||
@REM set DownloadFileAddr=0x108C0000
|
||||
@REM call :JFlash_EXE %DownloadFilePathName% %DownloadFileAddr%
|
||||
|
||||
@REM set DownloadFilePathName="%cd%\%flash_folder%\0x140000.bin"
|
||||
@REM set DownloadFileAddr=0x10140000
|
||||
@REM call :JFlash_EXE %DownloadFilePathName% %DownloadFileAddr%
|
||||
|
||||
@REM echo Download Done
|
||||
@REM pause
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@REM ================================================================================================================================================
|
||||
@REM 自定义函数
|
||||
@REM ================================================================================================================================================
|
||||
|
||||
@REM JFlash_EXE <DownloadFilePathName> <Address> [<MergeFilePathName> <Address>]
|
||||
@REM 执行jflash
|
||||
:JFlash_EXE
|
||||
SETLOCAL
|
||||
call :DEL_FILE_IF_EXIST jflashlog_tmp.txt
|
||||
call :DEL_FILE_IF_EXIST jlinklog_tmp.txt
|
||||
if exist "%~1" (
|
||||
set DownloadFile=%~1,%~2
|
||||
if "%~3" equ "" (
|
||||
start /min /wait "J-Flash" %JFlashPathName% ^
|
||||
-openprj%JFlashProjPathName% ^
|
||||
-open"!DownloadFile!" ^
|
||||
-jflashlog"jflashlog_tmp.txt" ^
|
||||
-jlinklog"jlinklog_tmp.txt" ^
|
||||
-auto ^
|
||||
-exit
|
||||
if ERRORLEVEL 1 goto ERROR
|
||||
) else (
|
||||
if exist "%~3" (
|
||||
set MergeFile=%~3,%~4
|
||||
start /min /wait "J-Flash" %JFlashPathName% ^
|
||||
-openprj%JFlashProjPathName% ^
|
||||
-open"!DownloadFile!" ^
|
||||
-jflashlog"jflashlog_tmp.txt" ^
|
||||
-jlinklog"jlinklog_tmp.txt" ^
|
||||
-merge"!MergeFile!" ^
|
||||
-auto ^
|
||||
-exit
|
||||
if ERRORLEVEL 1 goto ERROR
|
||||
) else (
|
||||
echo %~3 Not Exist
|
||||
goto END
|
||||
)
|
||||
)
|
||||
|
||||
echo !DownloadFile! Download Succeed
|
||||
if "!MergeFile!" neq "" echo !MergeFile! Download Succeed
|
||||
|
||||
goto DONE
|
||||
|
||||
) else (
|
||||
echo %~1 Not Exist
|
||||
goto END
|
||||
)
|
||||
:ERROR
|
||||
echo !DownloadFile! Download Failed
|
||||
if "!MergeFile!" neq "" echo !MergeFile! Download Failed
|
||||
type jflashlog_tmp.txt >> %JFlashLogPathName%
|
||||
type jlinklog_tmp.txt >> %JLinkARMLogPathName%
|
||||
del jflashlog_tmp.txt
|
||||
del jlinklog_tmp.txt
|
||||
exit /b 1
|
||||
:DONE
|
||||
type jflashlog_tmp.txt >> %JFlashLogPathName%
|
||||
type jlinklog_tmp.txt >> %JLinkARMLogPathName%
|
||||
del jflashlog_tmp.txt
|
||||
del jlinklog_tmp.txt
|
||||
:END
|
||||
ENDLOCAL
|
||||
goto:eof
|
||||
|
||||
|
||||
:DEL_FILE_IF_EXIST
|
||||
if exist %1 (
|
||||
del %1
|
||||
)
|
||||
goto:eof
|
||||
|
||||
|
||||
:PREPROCESS_BEFORE_DOWNLOAD
|
||||
call :DEL_FILE_IF_EXIST %JFlashLogPathName%
|
||||
call :DEL_FILE_IF_EXIST %JLinkARMLogPathName%
|
||||
call :DEL_FILE_IF_EXIST cmd.txt
|
||||
|
||||
echo r >> cmd.txt
|
||||
echo h >> cmd.txt
|
||||
echo WCP15Ex 0 1 0 0 0x08E7087A >> cmd.txt
|
||||
echo WCP15Ex 0 1 0 1 0x00000020 >> cmd.txt
|
||||
echo WCP15Ex 0 9 1 1 %TCMBConfig% >> cmd.txt
|
||||
echo WCP15Ex 0 9 1 0 %TCMAConfig% >> cmd.txt
|
||||
echo q >> cmd.txt
|
||||
%JLinkPathName% -device %device% -if SWD -speed 4000 -autoconnect 1 -CommandFile cmd.txt -JLinkScriptFile %JLinkScriptPathName% -log %JLinkARMLogPathName% > %JFlashLogPathName%
|
||||
if ERRORLEVEL 1 goto ERROR
|
||||
:ERROR
|
||||
del cmd.txt
|
||||
goto:eof
|
||||
3
devices/script/JFLASH/readme.txt
Normal file
3
devices/script/JFLASH/readme.txt
Normal file
@@ -0,0 +1,3 @@
|
||||
1. 修改SemiDrive.jflash工程文件中的device，例：E3640_HYPERFLASH
|
||||
2. 修改jflash.bat中的路径和device等变量，待下载文件的路径和地址等
|
||||
3. 执行jflash.bat
|
||||
46
devices/script/JLINK/d3/sf.JLinkScript
Normal file
46
devices/script/JLINK/d3/sf.JLinkScript
Normal file
@@ -0,0 +1,46 @@
|
||||
/*********************************************************************
|
||||
* (c) 1995 - 2019 SEGGER Microcontroller GmbH *
|
||||
* The Embedded Experts *
|
||||
* www.segger.com *
|
||||
**********************************************************************
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global functions
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ConfigTargetSettings()
|
||||
*
|
||||
* Function description
|
||||
* Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
|
||||
* For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
|
||||
* that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
|
||||
* May also be used to specify the device name in case debugger does not pass it to the DLL.
|
||||
*
|
||||
* Return value
|
||||
* >= 0 O.K.
|
||||
* < 0 Error
|
||||
*
|
||||
* Notes
|
||||
* (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
|
||||
* (2) Should only set some global DLL variables
|
||||
*/
|
||||
int ConfigTargetSettings(void) {
|
||||
//
|
||||
// Access Port map specfication
|
||||
// Core type
|
||||
// Access Port to use
|
||||
// Specify core base address
|
||||
// Specify CTI base address
|
||||
JLINK_SYS_Report("----------------J-Link script: ConfigTargetSettings() For Semdrive D3 SF Cortex-R5---------------");
|
||||
JLINK_CPU = CORTEX_R5;
|
||||
//JLINK_CORESIGHT_IndexAPBAPToUse = 0;
|
||||
JLINK_CORESIGHT_CoreBaseAddr = 0xF2081000;
|
||||
return 0;
|
||||
}
|
||||
/*************************** end of file ****************************/
|
||||
|
||||
46
devices/script/JLINK/d3/sp0.JLinkScript
Normal file
46
devices/script/JLINK/d3/sp0.JLinkScript
Normal file
@@ -0,0 +1,46 @@
|
||||
/*********************************************************************
|
||||
* (c) 1995 - 2019 SEGGER Microcontroller GmbH *
|
||||
* The Embedded Experts *
|
||||
* www.segger.com *
|
||||
**********************************************************************
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global functions
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ConfigTargetSettings()
|
||||
*
|
||||
* Function description
|
||||
* Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
|
||||
* For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
|
||||
* that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
|
||||
* May also be used to specify the device name in case debugger does not pass it to the DLL.
|
||||
*
|
||||
* Return value
|
||||
* >= 0 O.K.
|
||||
* < 0 Error
|
||||
*
|
||||
* Notes
|
||||
* (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
|
||||
* (2) Should only set some global DLL variables
|
||||
*/
|
||||
int ConfigTargetSettings(void) {
|
||||
//
|
||||
// Access Port map specfication
|
||||
// Core type
|
||||
// Access Port to use
|
||||
// Specify core base address
|
||||
// Specify CTI base address
|
||||
JLINK_SYS_Report("----------------J-Link script: ConfigTargetSettings() For Semdrive D3 SP0 Cortex-R5---------------");
|
||||
JLINK_CPU = CORTEX_R5;
|
||||
//JLINK_CORESIGHT_IndexAPBAPToUse = 0;
|
||||
JLINK_CORESIGHT_CoreBaseAddr = 0xF2082000;
|
||||
return 0;
|
||||
}
|
||||
/*************************** end of file ****************************/
|
||||
|
||||
46
devices/script/JLINK/d3/sp1.JLinkScript
Normal file
46
devices/script/JLINK/d3/sp1.JLinkScript
Normal file
@@ -0,0 +1,46 @@
|
||||
/*********************************************************************
|
||||
* (c) 1995 - 2019 SEGGER Microcontroller GmbH *
|
||||
* The Embedded Experts *
|
||||
* www.segger.com *
|
||||
**********************************************************************
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global functions
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ConfigTargetSettings()
|
||||
*
|
||||
* Function description
|
||||
* Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
|
||||
* For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
|
||||
* that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
|
||||
* May also be used to specify the device name in case debugger does not pass it to the DLL.
|
||||
*
|
||||
* Return value
|
||||
* >= 0 O.K.
|
||||
* < 0 Error
|
||||
*
|
||||
* Notes
|
||||
* (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
|
||||
* (2) Should only set some global DLL variables
|
||||
*/
|
||||
int ConfigTargetSettings(void) {
|
||||
//
|
||||
// Access Port map specfication
|
||||
// Core type
|
||||
// Access Port to use
|
||||
// Specify core base address
|
||||
// Specify CTI base address
|
||||
JLINK_SYS_Report("----------------J-Link script: ConfigTargetSettings() For Semdrive D3 SP1 Cortex-R5---------------");
|
||||
JLINK_CPU = CORTEX_R5;
|
||||
//JLINK_CORESIGHT_IndexAPBAPToUse = 0;
|
||||
JLINK_CORESIGHT_CoreBaseAddr = 0xF2083000;
|
||||
return 0;
|
||||
}
|
||||
/*************************** end of file ****************************/
|
||||
|
||||
46
devices/script/JLINK/d3/sx0.JLinkScript
Normal file
46
devices/script/JLINK/d3/sx0.JLinkScript
Normal file
@@ -0,0 +1,46 @@
|
||||
/*********************************************************************
|
||||
* (c) 1995 - 2019 SEGGER Microcontroller GmbH *
|
||||
* The Embedded Experts *
|
||||
* www.segger.com *
|
||||
**********************************************************************
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global functions
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ConfigTargetSettings()
|
||||
*
|
||||
* Function description
|
||||
* Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
|
||||
* For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
|
||||
* that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
|
||||
* May also be used to specify the device name in case debugger does not pass it to the DLL.
|
||||
*
|
||||
* Return value
|
||||
* >= 0 O.K.
|
||||
* < 0 Error
|
||||
*
|
||||
* Notes
|
||||
* (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
|
||||
* (2) Should only set some global DLL variables
|
||||
*/
|
||||
int ConfigTargetSettings(void) {
|
||||
//
|
||||
// Access Port map specfication
|
||||
// Core type
|
||||
// Access Port to use
|
||||
// Specify core base address
|
||||
// Specify CTI base address
|
||||
JLINK_SYS_Report("----------------J-Link script: ConfigTargetSettings() For Semdrive D3 SX0 Cortex-R5---------------");
|
||||
JLINK_CPU = CORTEX_R5;
|
||||
//JLINK_CORESIGHT_IndexAPBAPToUse = 0;
|
||||
JLINK_CORESIGHT_CoreBaseAddr = 0xF2084000;
|
||||
return 0;
|
||||
}
|
||||
/*************************** end of file ****************************/
|
||||
|
||||
46
devices/script/JLINK/d3/sx1.JLinkScript
Normal file
46
devices/script/JLINK/d3/sx1.JLinkScript
Normal file
@@ -0,0 +1,46 @@
|
||||
/*********************************************************************
|
||||
* (c) 1995 - 2019 SEGGER Microcontroller GmbH *
|
||||
* The Embedded Experts *
|
||||
* www.segger.com *
|
||||
**********************************************************************
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global functions
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ConfigTargetSettings()
|
||||
*
|
||||
* Function description
|
||||
* Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
|
||||
* For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
|
||||
* that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
|
||||
* May also be used to specify the device name in case debugger does not pass it to the DLL.
|
||||
*
|
||||
* Return value
|
||||
* >= 0 O.K.
|
||||
* < 0 Error
|
||||
*
|
||||
* Notes
|
||||
* (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
|
||||
* (2) Should only set some global DLL variables
|
||||
*/
|
||||
int ConfigTargetSettings(void) {
|
||||
//
|
||||
// Access Port map specfication
|
||||
// Core type
|
||||
// Access Port to use
|
||||
// Specify core base address
|
||||
// Specify CTI base address
|
||||
JLINK_SYS_Report("----------------J-Link script: ConfigTargetSettings() For Semdrive D3 SX1 Cortex-R5---------------");
|
||||
JLINK_CPU = CORTEX_R5;
|
||||
//JLINK_CORESIGHT_IndexAPBAPToUse = 0;
|
||||
JLINK_CORESIGHT_CoreBaseAddr = 0xF2085000;
|
||||
return 0;
|
||||
}
|
||||
/*************************** end of file ****************************/
|
||||
|
||||
94
devices/script/JLINK/e3/readme
Normal file
94
devices/script/JLINK/e3/readme
Normal file
@@ -0,0 +1,94 @@
|
||||
## 简介
|
||||
|
||||
介绍通过j-link使用secure debug功能
|
||||
该功能支持JTAG模式，不支持SWD模式
|
||||
芯片匹配debug key成功后开启debug接口
|
||||
|
||||
##硬件连接
|
||||
|
||||
- e3_gateway参考板
|
||||
- Jlink debugger
|
||||
|
||||
##注意事项
|
||||
- 确认板子JTAG功能正常，对于e3 gateway参考板需要去掉TDO/TDI上的两个电阻。
|
||||
- 需要通过fuse工具烧UID,debug key和使能secure debug。
|
||||
- 确认sf.JLinkScript中SetupSecureDebug的操作被打开，默认是关闭的。
|
||||
- IAR工程下 接口如果是SWD,修改为JTAG。
|
||||
- IAR工程下 如果 options->Debugger->Extra Options下没有指定sf.JLinkScript
|
||||
增加command：--jlink_script_file=$PROJ_DIR$\..\..\..\..\..\..\devices\script\JLINK\e3\sf.JLinkScript
|
||||
|
||||
- SES工程下 接口如果是SWD,修改为JTAG。
|
||||
- SES工程下 如果 options->Debug->J-Link->Script File下没有选择sf.JLinkScript
|
||||
则手动指定路径：ssdk\devices\script\JLINK\e3\sf.JLinkScript
|
||||
|
||||
##测试方法
|
||||
当板子以以下方式烧UID,debug key和使能secure debug.
|
||||
Debug Key:
|
||||
+-----------------------+------------+------------------+
|
||||
| name | fuse addr | fuse value |
|
||||
+-----------------------+------------+------------------+
|
||||
| UID[0, 31] | 0x1010 | 0x12345678 |
|
||||
| UID[32, 63] | 0x1014 | 0xABCDEF88 |
|
||||
| SEC_DBG_CFG[31, 0] | 0x1280 | 0x74657374(key0) |
|
||||
| SEC_DBG_CFG[63, 32] | 0x1284 | 0x6b657930(key1) |
|
||||
| MSIC_CFG3/SDBG_MODE | 0x12b0 | 0x00800000 |
|
||||
+-----------------------+------------+------------------+
|
||||
|
||||
IAR下执行attach通过，脚本同时会返回UID，
|
||||
SES下可以通过执行connect确认；
|
||||
提供错误的debug key则无法执行通过。
|
||||
|
||||
##expected log
|
||||
--------------SetupSecureDebug-----------------
|
||||
UID: 0x12345678
|
||||
UID: 0xABCDEF88
|
||||
ID: 0x4BA00477
|
||||
|
||||
##流程说明
|
||||
- 该流程涉及JTAG状态机的转化，instruction和data的传入。
|
||||
- key0, key1对应传入的debug key。v保存读出来的id。
|
||||
- Note: key0 --> SEC_DBG_CFG[31, 0], key1 --> SEC_DBG_CFG[63, 32]!!
|
||||
|
||||
void SetupSecureDebug(void) {
|
||||
int v;
|
||||
int key0;
|
||||
int key1;
|
||||
int cmd;
|
||||
|
||||
cmd = 0xf;
|
||||
key0 = 0x74657374;
|
||||
key1 = 0x6b657930;
|
||||
|
||||
JLINK_SYS_Report("--------------SetupSecureDebug-----------------");
|
||||
JLINK_SelectTIF(JLINK_TIF_JTAG);
|
||||
CPU = CORTEX_R5;
|
||||
|
||||
//prototype:int JLINK_JTAG_Write(U32 tms, U32 tdi, U32 NumBits);
|
||||
JLINK_JTAG_Write(0x1f, 0, 5); // goto Test-Logic Reset state
|
||||
JLINK_JTAG_Write(0x6, 0, 5); //goto shift-ir state
|
||||
JLINK_JTAG_Write(0x8, 0xf, 4); // shift in UID instruction, goto exit1-ir
|
||||
|
||||
JLINK_JTAG_Write(0x3, cmd, 4); //goto shift-dr state
|
||||
|
||||
JLINK_JTAG_Write(0x00000000, 0x0, 32); //shift in 64bit dummy code. shift out our uid
|
||||
v = JLINK_JTAG_GetU32(0);
|
||||
JLINK_SYS_Report1("UID: ", v);
|
||||
JLINK_JTAG_Write(0x80000000, 0x0, 32); //shift in 64bit dummy code. shift out our uid, goto exit1-dr
|
||||
v = JLINK_JTAG_GetU32(0);
|
||||
JLINK_SYS_Report1("UID: ", v);
|
||||
|
||||
JLINK_JTAG_Write(0x1f, 0, 5); // goto Test-Logic Reset state
|
||||
JLINK_JTAG_Write(0x2, 0x0, 4); // goto shift-dr state
|
||||
|
||||
JLINK_JTAG_Write(0x00000000, key0, 32); //shift in the corresponding key
|
||||
JLINK_JTAG_Write(0x80000000, key1, 32); //shift in the corresponding key
|
||||
|
||||
JLINK_JTAG_Write(0x1f, 0, 5); // goto Test-Logic Reset state
|
||||
JLINK_JTAG_Write(0x2, 0x0, 4); // goto shift-dr state
|
||||
|
||||
JLINK_JTAG_Write(0x80000000, 0x0, 32); // shift our IDCODE
|
||||
v = JLINK_JTAG_GetU32(0);
|
||||
JLINK_SYS_Report1("ID: ", v);
|
||||
|
||||
JLINK_JTAG_Write(0x1, 0, 2); // goto idle state
|
||||
}
|
||||
95
devices/script/JLINK/e3/sf.JLinkScript
Normal file
95
devices/script/JLINK/e3/sf.JLinkScript
Normal file
@@ -0,0 +1,95 @@
|
||||
/*********************************************************************
|
||||
* (c) 1995 - 2019 SEGGER Microcontroller GmbH *
|
||||
* The Embedded Experts *
|
||||
* www.segger.com *
|
||||
**********************************************************************
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global functions
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ConfigTargetSettings()
|
||||
*
|
||||
* Function description
|
||||
* Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
|
||||
* For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
|
||||
* that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
|
||||
* May also be used to specify the device name in case debugger does not pass it to the DLL.
|
||||
*
|
||||
* Return value
|
||||
* >= 0 O.K.
|
||||
* < 0 Error
|
||||
*
|
||||
* Notes
|
||||
* (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
|
||||
* (2) Should only set some global DLL variables
|
||||
*/
|
||||
int ConfigTargetSettings(void) {
|
||||
//
|
||||
// Access Port map specfication
|
||||
// Core type
|
||||
// Access Port to use
|
||||
// Specify core base address
|
||||
// Specify CTI base address
|
||||
JLINK_SYS_Report("----------------J-Link script: ConfigTargetSettings() For Semdrive E3 SF Cortex-R5---------------");
|
||||
JLINK_CPU = CORTEX_R5;
|
||||
//JLINK_CORESIGHT_IndexAPBAPToUse = 0;
|
||||
JLINK_CORESIGHT_CoreBaseAddr = 0xF2081000;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void SetupSecureDebug(void) {
|
||||
int v;
|
||||
int key0;
|
||||
int key1;
|
||||
int cmd;
|
||||
|
||||
cmd = 0xf;
|
||||
key0 = 0x74657374; // key0 --> SEC_DBG_CFG[31, 0]!!
|
||||
key1 = 0x6b657930; // key1 --> SEC_DBG_CFG[63, 32]!!
|
||||
|
||||
JLINK_SYS_Report("--------------SetupSecureDebug-----------------");
|
||||
JLINK_SelectTIF(JLINK_TIF_JTAG);
|
||||
CPU = CORTEX_R5;
|
||||
|
||||
//prototype:int JLINK_JTAG_Write(U32 tms, U32 tdi, U32 NumBits);
|
||||
JLINK_JTAG_Write(0x1f, 0, 5); // goto Test-Logic Reset state
|
||||
JLINK_JTAG_Write(0x6, 0, 5); //goto shift-ir state
|
||||
JLINK_JTAG_Write(0x8, cmd, 4); // shift in UID instruction, goto exit1-ir
|
||||
|
||||
JLINK_JTAG_Write(0x3, 0x0, 4); //goto shift-dr state
|
||||
|
||||
JLINK_JTAG_Write(0x00000000, 0x0, 32); //shift in 64bit dummy code. shift out our uid
|
||||
v = JLINK_JTAG_GetU32(0);
|
||||
JLINK_SYS_Report1("UID: ", v);
|
||||
JLINK_JTAG_Write(0x80000000, 0x0, 32); //shift in 64bit dummy code. shift out our uid, goto exit1-dr
|
||||
v = JLINK_JTAG_GetU32(0);
|
||||
JLINK_SYS_Report1("UID: ", v);
|
||||
|
||||
JLINK_JTAG_Write(0x1f, 0, 5); // goto Test-Logic Reset state
|
||||
JLINK_JTAG_Write(0x2, 0x0, 4); // goto shift-dr state
|
||||
|
||||
JLINK_JTAG_Write(0x00000000, key0, 32); //shift in the corresponding key
|
||||
JLINK_JTAG_Write(0x80000000, key1, 32); //shift in the corresponding key, goto exit1-ir
|
||||
|
||||
JLINK_JTAG_Write(0x1f, 0, 5); // goto Test-Logic Reset state
|
||||
JLINK_JTAG_Write(0x2, 0x0, 4); // goto shift-dr state
|
||||
|
||||
JLINK_JTAG_Write(0x80000000, 0x0, 32); // shift our IDCODE
|
||||
v = JLINK_JTAG_GetU32(0);
|
||||
JLINK_SYS_Report1(" ID: ", v);
|
||||
|
||||
JLINK_JTAG_Write(0x1, 0, 2); // goto idle state
|
||||
}
|
||||
|
||||
void InitTarget(void) {
|
||||
// SetupSecureDebug();
|
||||
}
|
||||
|
||||
/*************************** end of file ****************************/
|
||||
|
||||
46
devices/script/JLINK/e3/sp0.JLinkScript
Normal file
46
devices/script/JLINK/e3/sp0.JLinkScript
Normal file
@@ -0,0 +1,46 @@
|
||||
/*********************************************************************
|
||||
* (c) 1995 - 2019 SEGGER Microcontroller GmbH *
|
||||
* The Embedded Experts *
|
||||
* www.segger.com *
|
||||
**********************************************************************
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global functions
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ConfigTargetSettings()
|
||||
*
|
||||
* Function description
|
||||
* Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
|
||||
* For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
|
||||
* that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
|
||||
* May also be used to specify the device name in case debugger does not pass it to the DLL.
|
||||
*
|
||||
* Return value
|
||||
* >= 0 O.K.
|
||||
* < 0 Error
|
||||
*
|
||||
* Notes
|
||||
* (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
|
||||
* (2) Should only set some global DLL variables
|
||||
*/
|
||||
int ConfigTargetSettings(void) {
|
||||
//
|
||||
// Access Port map specfication
|
||||
// Core type
|
||||
// Access Port to use
|
||||
// Specify core base address
|
||||
// Specify CTI base address
|
||||
JLINK_SYS_Report("----------------J-Link script: ConfigTargetSettings() For Semdrive E3 SP0 Cortex-R5---------------");
|
||||
JLINK_CPU = CORTEX_R5;
|
||||
//JLINK_CORESIGHT_IndexAPBAPToUse = 0;
|
||||
JLINK_CORESIGHT_CoreBaseAddr = 0xF2082000;
|
||||
return 0;
|
||||
}
|
||||
/*************************** end of file ****************************/
|
||||
|
||||
46
devices/script/JLINK/e3/sp1.JLinkScript
Normal file
46
devices/script/JLINK/e3/sp1.JLinkScript
Normal file
@@ -0,0 +1,46 @@
|
||||
/*********************************************************************
|
||||
* (c) 1995 - 2019 SEGGER Microcontroller GmbH *
|
||||
* The Embedded Experts *
|
||||
* www.segger.com *
|
||||
**********************************************************************
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global functions
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ConfigTargetSettings()
|
||||
*
|
||||
* Function description
|
||||
* Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
|
||||
* For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
|
||||
* that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
|
||||
* May also be used to specify the device name in case debugger does not pass it to the DLL.
|
||||
*
|
||||
* Return value
|
||||
* >= 0 O.K.
|
||||
* < 0 Error
|
||||
*
|
||||
* Notes
|
||||
* (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
|
||||
* (2) Should only set some global DLL variables
|
||||
*/
|
||||
int ConfigTargetSettings(void) {
|
||||
//
|
||||
// Access Port map specfication
|
||||
// Core type
|
||||
// Access Port to use
|
||||
// Specify core base address
|
||||
// Specify CTI base address
|
||||
JLINK_SYS_Report("----------------J-Link script: ConfigTargetSettings() For Semdrive E3 SP1 Cortex-R5---------------");
|
||||
JLINK_CPU = CORTEX_R5;
|
||||
//JLINK_CORESIGHT_IndexAPBAPToUse = 0;
|
||||
JLINK_CORESIGHT_CoreBaseAddr = 0xF2083000;
|
||||
return 0;
|
||||
}
|
||||
/*************************** end of file ****************************/
|
||||
|
||||
46
devices/script/JLINK/e3/sx0.JLinkScript
Normal file
46
devices/script/JLINK/e3/sx0.JLinkScript
Normal file
@@ -0,0 +1,46 @@
|
||||
/*********************************************************************
|
||||
* (c) 1995 - 2019 SEGGER Microcontroller GmbH *
|
||||
* The Embedded Experts *
|
||||
* www.segger.com *
|
||||
**********************************************************************
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global functions
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ConfigTargetSettings()
|
||||
*
|
||||
* Function description
|
||||
* Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
|
||||
* For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
|
||||
* that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
|
||||
* May also be used to specify the device name in case debugger does not pass it to the DLL.
|
||||
*
|
||||
* Return value
|
||||
* >= 0 O.K.
|
||||
* < 0 Error
|
||||
*
|
||||
* Notes
|
||||
* (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
|
||||
* (2) Should only set some global DLL variables
|
||||
*/
|
||||
int ConfigTargetSettings(void) {
|
||||
//
|
||||
// Access Port map specfication
|
||||
// Core type
|
||||
// Access Port to use
|
||||
// Specify core base address
|
||||
// Specify CTI base address
|
||||
JLINK_SYS_Report("----------------J-Link script: ConfigTargetSettings() For Semdrive E3 SX0 Cortex-R5---------------");
|
||||
JLINK_CPU = CORTEX_R5;
|
||||
//JLINK_CORESIGHT_IndexAPBAPToUse = 0;
|
||||
JLINK_CORESIGHT_CoreBaseAddr = 0xF2084000;
|
||||
return 0;
|
||||
}
|
||||
/*************************** end of file ****************************/
|
||||
|
||||
46
devices/script/JLINK/e3/sx1.JLinkScript
Normal file
46
devices/script/JLINK/e3/sx1.JLinkScript
Normal file
@@ -0,0 +1,46 @@
|
||||
/*********************************************************************
|
||||
* (c) 1995 - 2019 SEGGER Microcontroller GmbH *
|
||||
* The Embedded Experts *
|
||||
* www.segger.com *
|
||||
**********************************************************************
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global functions
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ConfigTargetSettings()
|
||||
*
|
||||
* Function description
|
||||
* Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
|
||||
* For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
|
||||
* that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
|
||||
* May also be used to specify the device name in case debugger does not pass it to the DLL.
|
||||
*
|
||||
* Return value
|
||||
* >= 0 O.K.
|
||||
* < 0 Error
|
||||
*
|
||||
* Notes
|
||||
* (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
|
||||
* (2) Should only set some global DLL variables
|
||||
*/
|
||||
int ConfigTargetSettings(void) {
|
||||
//
|
||||
// Access Port map specfication
|
||||
// Core type
|
||||
// Access Port to use
|
||||
// Specify core base address
|
||||
// Specify CTI base address
|
||||
JLINK_SYS_Report("----------------J-Link script: ConfigTargetSettings() For Semdrive E3 SX1 Cortex-R5---------------");
|
||||
JLINK_CPU = CORTEX_R5;
|
||||
//JLINK_CORESIGHT_IndexAPBAPToUse = 0;
|
||||
JLINK_CORESIGHT_CoreBaseAddr = 0xF2085000;
|
||||
return 0;
|
||||
}
|
||||
/*************************** end of file ****************************/
|
||||
|
||||
286
devices/script/SES/cmd_download.py
Normal file
286
devices/script/SES/cmd_download.py
Normal file
@@ -0,0 +1,286 @@
|
||||
import sys
|
||||
import os
|
||||
import re
|
||||
import subprocess, shlex
|
||||
|
||||
|
||||
|
||||
################################################## download ##################################################
|
||||
def get_sdk_root_path_by_project_path(ProjectPath):
|
||||
Pattern = r'(.*)/boards/'
|
||||
SearchResult = re.search(Pattern, ProjectPath, re.S)
|
||||
if SearchResult != None:
|
||||
return SearchResult.group(1)
|
||||
else:
|
||||
print("Error: correct ssdk root path was not found")
|
||||
sys.exit(1)
|
||||
|
||||
def add_double_quotes(Strings):
|
||||
return '"' + Strings + '"'
|
||||
|
||||
def jlink_exe_file(FilePathName):
|
||||
JlinkCmd = JlinkExe + add_double_quotes(FilePathName)
|
||||
args = shlex.split(JlinkCmd)
|
||||
# subprocess.run(args, check=True, stdout=subprocess.DEVNULL)
|
||||
subprocess.run(args, check=True)
|
||||
|
||||
def download_file(File, Addr):
|
||||
print("loadfile: %s %s" %(File, Addr))
|
||||
CmdFilePathName = ProjectPath + "/cmd.txt"
|
||||
LoadFileString = "LoadFile " + add_double_quotes(File) + " " + Addr + " noreset"
|
||||
ExitString = "q"
|
||||
with open(CmdFilePathName, "w") as f:
|
||||
f.write("h" + "\n")
|
||||
f.write(LoadFileString + "\n")
|
||||
f.write(ExitString)
|
||||
try:
|
||||
jlink_exe_file(CmdFilePathName)
|
||||
os.remove(CmdFilePathName)
|
||||
except Exception as e:
|
||||
os.remove(CmdFilePathName)
|
||||
raise Exception("download error:\n %s" %e)
|
||||
|
||||
def get_download_info_by_project_file(ProjectPathName, FlashType):
|
||||
with open(ProjectPathName, "r", encoding="utf-8") as f:
|
||||
Content = f.read()
|
||||
Pattern = r'(<configuration\s*Name="Download_{0}"(?:(?!<|hidden).)*/>)'.format(FlashType)
|
||||
SearchResult = re.search(Pattern, Content, re.S)
|
||||
if SearchResult != None:
|
||||
return SearchResult.group(1)
|
||||
else:
|
||||
print("Error: no download info find")
|
||||
sys.exit(1)
|
||||
|
||||
def get_multicore_download_info_by_project_file(ProjectPathName, FlashType, Part):
|
||||
with open(ProjectPathName, "r", encoding="utf-8") as f:
|
||||
Content = f.read()
|
||||
Pattern = r'(<configuration\s*Name="(?:Download|Sign)_{0}_Multicore_{1}"(?:(?!<|hidden).)*/>)'.format(FlashType, Part)
|
||||
SearchResultMulticore = re.search(Pattern, Content, re.S)
|
||||
if SearchResultMulticore != None:
|
||||
return SearchResultMulticore.group(1)
|
||||
else:
|
||||
return None
|
||||
|
||||
def get_str_from_download_info(DownloadInfo, FindString):
|
||||
Pattern = FindString + r'="(.*?)"'
|
||||
SearchResult = re.search(Pattern, DownloadInfo, re.S)
|
||||
if SearchResult != None:
|
||||
return SearchResult.group(1)
|
||||
else:
|
||||
return None
|
||||
|
||||
def is_sfs_file(FileName):
|
||||
Pattern = r'sfs_.*'
|
||||
SearchResult = re.search(Pattern, FileName, re.S)
|
||||
if SearchResult != None:
|
||||
return True
|
||||
else:
|
||||
return False
|
||||
|
||||
def is_need_sign(FileName):
|
||||
if is_sfs_file(FileName) == True:
|
||||
return False
|
||||
elif FileName == "sf_signed.bin" or FileName == "sp0_signed.bin" or FileName == "sp1_signed.bin" or FileName == "sx0_signed.bin" or FileName == "sx1_signed.bin":
|
||||
return True
|
||||
elif FileName == "sf.bin" or FileName == "sp0.bin" or FileName == "sp1.bin" or FileName == "sx0.bin" or FileName == "sx1.bin":
|
||||
return False
|
||||
else:
|
||||
print("Error: %s is error file name" %FileName)
|
||||
sys.exit(1)
|
||||
|
||||
def is_need_download(FileName):
|
||||
if is_sfs_file(FileName) == True:
|
||||
return True
|
||||
elif FileName == "sf_signed.bin" or FileName == "sf.bin" or FileName == "sp0.bin" or FileName == "sp1.bin" or FileName == "sx0.bin" or FileName == "sx1.bin":
|
||||
return True
|
||||
elif FileName == "sp0_signed.bin" or FileName == "sp1_signed.bin" or FileName == "sx0_signed.bin" or FileName == "sx1_signed.bin":
|
||||
return False
|
||||
else:
|
||||
print("Error: %s is error file name" %FileName)
|
||||
sys.exit(1)
|
||||
|
||||
def get_unsigned_bin_name(FileName):
|
||||
DictTmp = {'sf_signed.bin':'sf.bin', 'sp0_signed.bin':'sp0.bin', 'sp1_signed.bin':'sp1.bin', 'sx0_signed.bin':'sx0.bin', 'sx1_signed.bin':'sx1.bin'}
|
||||
return DictTmp.get(FileName)
|
||||
|
||||
def gen_info_from_download_info(DownloadInfo, FileString, AddrString):
|
||||
if DownloadInfo == None:
|
||||
return
|
||||
FilePathName = get_str_from_download_info(DownloadInfo, FileString)
|
||||
if FilePathName != None and FilePathName != "":
|
||||
FilePathName = os.path.abspath(FilePathName.replace("$(ProjectDir)", ProjectPath)).replace('\\', '/')
|
||||
FilePath = os.path.dirname(FilePathName)
|
||||
FileName = os.path.basename(FilePathName)
|
||||
if is_need_sign(FileName):
|
||||
# 签名
|
||||
UnsignedBinPathName = FilePath + "/" + get_unsigned_bin_name(FileName)
|
||||
Addr = get_str_from_download_info(DownloadInfo, AddrString)
|
||||
if Addr != None and Addr != "":
|
||||
UnsignedBinAddr = Addr
|
||||
SignInfoDict.update({UnsignedBinPathName:UnsignedBinAddr})
|
||||
if is_need_download(FileName):
|
||||
Addr = get_str_from_download_info(DownloadInfo, AddrString)
|
||||
if Addr != None and Addr != "":
|
||||
DownloadInfoDict.update({FilePathName:Addr})
|
||||
|
||||
def get_sign_and_download_info_by_project_file(ProjectPathName, FlashType, Part):
|
||||
DownloadInfo = get_download_info_by_project_file(ProjectPathName, FlashType)
|
||||
MulticoreDownloadInfo = get_multicore_download_info_by_project_file(ProjectPathName, FlashType, Part)
|
||||
FileString = "debug_additional_load_file"
|
||||
AddrStr = "debug_additional_load_file_address"
|
||||
gen_info_from_download_info(DownloadInfo, FileString, AddrStr)
|
||||
gen_info_from_download_info(MulticoreDownloadInfo, FileString, AddrStr)
|
||||
FileString = "debug_additional_load_file1"
|
||||
AddrStr = "debug_additional_load_file_address1"
|
||||
gen_info_from_download_info(DownloadInfo, FileString, AddrStr)
|
||||
gen_info_from_download_info(MulticoreDownloadInfo, FileString, AddrStr)
|
||||
FileString = "debug_additional_load_file2"
|
||||
AddrStr = "debug_additional_load_file_address2"
|
||||
gen_info_from_download_info(DownloadInfo, FileString, AddrStr)
|
||||
gen_info_from_download_info(MulticoreDownloadInfo, FileString, AddrStr)
|
||||
FileString = "debug_additional_load_file3"
|
||||
AddrStr = "debug_additional_load_file_address3"
|
||||
gen_info_from_download_info(DownloadInfo, FileString, AddrStr)
|
||||
gen_info_from_download_info(MulticoreDownloadInfo, FileString, AddrStr)
|
||||
FileString = "external_build_file_name"
|
||||
AddrStr = "external_load_address"
|
||||
gen_info_from_download_info(DownloadInfo, FileString, AddrStr)
|
||||
gen_info_from_download_info(MulticoreDownloadInfo, FileString, AddrStr)
|
||||
|
||||
def download_file_by_download_info(**DownloadInfoDict):
|
||||
for key, value in DownloadInfoDict.items():
|
||||
if not os.path.exists(key):
|
||||
print("Error: %s does not exist" %key)
|
||||
sys.exit(1)
|
||||
download_file(key, value)
|
||||
|
||||
|
||||
|
||||
################################################## sign ##################################################
|
||||
def get_core_by_pathname(FilePathName):
|
||||
FileName = os.path.basename(FilePathName)
|
||||
DictTmp = {'sf.bin':'0', 'sp0.bin':'2', 'sp1.bin':'3', 'sx0.bin':'4', 'sx1.bin':'5'}
|
||||
return DictTmp.get(FileName)
|
||||
|
||||
def get_entry_by_pathname(FilePathName, PartId):
|
||||
FileName = os.path.basename(FilePathName)
|
||||
if PartId == "E3104" or PartId == "E3106" or PartId == "E3205" or PartId == "E3206":
|
||||
DictTmp = {'sf.bin':'0x504000'}
|
||||
elif PartId == "E3110" or PartId == "E3210" or PartId == "E3340" or PartId == "D3246" or PartId == "D3248":
|
||||
DictTmp = {'sf.bin':'0x404000'}
|
||||
elif PartId == "E3420":
|
||||
DictTmp = {'sf.bin':'0x404000', 'sx0.bin':'0x500000', 'sx1.bin':'0x580000'}
|
||||
elif PartId == "E3430":
|
||||
DictTmp = {'sf.bin':'0x404000', 'sx0.bin':'0x600000', 'sx1.bin':'0x680000'}
|
||||
elif PartId == "E3640" or PartId == "E3648":
|
||||
DictTmp = {'sf.bin':'0x404000', 'sp0.bin':'0x700000', 'sp1.bin':'0x780000', 'sx0.bin':'0x600000', 'sx1.bin':'0x680000'}
|
||||
else:
|
||||
print("Error: %s does not exist" %PartId)
|
||||
sys.exit(1)
|
||||
if DictTmp.get(FileName) == None:
|
||||
print("Error: %s does not exist" %FileName)
|
||||
sys.exit(1)
|
||||
return DictTmp.get(FileName)
|
||||
|
||||
def get_bpt_base_by_part(FlashType):
|
||||
if FlashType == "HYPERFLASH":
|
||||
return 0x100C0000
|
||||
elif FlashType == "NORFLASH":
|
||||
return 0x10007000
|
||||
else:
|
||||
print("Error: FlashType error")
|
||||
sys.exit(1)
|
||||
|
||||
def get_dlp_by_addr(Addr, FlashType):
|
||||
return int((int(Addr, 16) - get_bpt_base_by_part(FlashType)) / 512)
|
||||
|
||||
def get_iib_info_by_sign_info(**SignInfoDict):
|
||||
global SignedBinPathName
|
||||
IIBInfo = ""
|
||||
for key, value in SignInfoDict.items():
|
||||
if not os.path.exists(key):
|
||||
print("Error: %s does not exist" %key)
|
||||
sys.exit(1)
|
||||
if os.path.basename(key) == "sf.bin":
|
||||
SignedBinPathName = add_double_quotes(os.path.dirname(key) + "/sf_signed.bin")
|
||||
IIBInfo += "--iib core=%s type=0x0 image=%s dlp=0x%x to=%s entry=%s\n" % (get_core_by_pathname(key), add_double_quotes(key), get_dlp_by_addr(value, FlashType), get_entry_by_pathname(key, Part), get_entry_by_pathname(key, Part))
|
||||
return IIBInfo
|
||||
|
||||
def sign_file_by_sign_info(**SignInfoDict):
|
||||
SecVer = 0
|
||||
KeyName = "TestRSA2048_ossl.pem"
|
||||
PSN = "0x100"
|
||||
IIBInfo = get_iib_info_by_sign_info(**SignInfoDict)
|
||||
ATB_SIGNER = "./sign_tool/windows/atb_signer.exe"
|
||||
os.chdir(os.path.join(SdkRootPath, "tools", "sdtools"))
|
||||
SignCmd = ATB_SIGNER + " sign --v 2 --sec_ver %s --dgst sha256 --rcp key=sign_tool/keys/%s\n%s--psn %s --of %s" %(SecVer, KeyName, IIBInfo, PSN, SignedBinPathName)
|
||||
print("SignCmd: %s" %SignCmd)
|
||||
print("sign file: %s" %SignedBinPathName)
|
||||
try:
|
||||
args = shlex.split(SignCmd)
|
||||
# subprocess.run(args, check=True, stdout=subprocess.DEVNULL)
|
||||
subprocess.run(args, check=True)
|
||||
except Exception as e:
|
||||
raise Exception("sign error:\n %s" %e)
|
||||
|
||||
|
||||
|
||||
################################################## main ##################################################
|
||||
if __name__ == "__main__":
|
||||
# 处理入参
|
||||
JlinkPath = os.path.abspath(sys.argv[1]).replace('\\', '/')
|
||||
ProjectPathName = os.path.abspath(sys.argv[2]).replace('\\', '/')
|
||||
Part = sys.argv[3]
|
||||
FlashType = sys.argv[4]
|
||||
OperationType = sys.argv[5]
|
||||
|
||||
# 生成需要的变量
|
||||
ProjectPath = os.path.dirname(ProjectPathName)
|
||||
SdkRootPath = get_sdk_root_path_by_project_path(ProjectPath)
|
||||
|
||||
# 如果是ide，进行签名后退出；如果是cmd，签名后继续下载
|
||||
if OperationType == "$(OPS)":
|
||||
OnlySignBin = True
|
||||
elif OperationType == "download":
|
||||
OnlySignBin = False
|
||||
else:
|
||||
print("Error: %s is unsupport operation type" %OperationType)
|
||||
sys.exit(1)
|
||||
|
||||
|
||||
|
||||
SignInfoDict = {}
|
||||
DownloadInfoDict = {}
|
||||
get_sign_and_download_info_by_project_file(ProjectPathName, FlashType, Part)
|
||||
print(SignInfoDict)
|
||||
print(DownloadInfoDict)
|
||||
|
||||
if not SignInfoDict:
|
||||
print("Error: no signed files info found")
|
||||
sys.exit(1)
|
||||
sign_file_by_sign_info(**SignInfoDict)
|
||||
|
||||
# 初始化TCM，擦除Flash
|
||||
if OnlySignBin == False:
|
||||
if not DownloadInfoDict:
|
||||
print("Error: no download files info found")
|
||||
sys.exit(1)
|
||||
DeviceName = Part + "_" + FlashType
|
||||
JlinkPathName = add_double_quotes(JlinkPath + '/JLink.exe')
|
||||
JlinkExe = JlinkPathName + " -device " + DeviceName + " -if SWD -speed 4000 -autoconnect 1 -CommandFile "
|
||||
|
||||
if FlashType == "HYPERFLASH":
|
||||
InitFilePathName = os.path.join(SdkRootPath, "devices", Part, "flashloader", "init_before_download_hyperflash.txt").replace('\\', '/')
|
||||
elif FlashType == "NORFLASH":
|
||||
InitFilePathName = os.path.join(SdkRootPath, "devices", Part, "flashloader", "init_before_download_norflash.txt").replace('\\', '/')
|
||||
else:
|
||||
print("Error: %s is not right type" %FlashType)
|
||||
sys.exit(1)
|
||||
|
||||
print("init tcm and erase flash: %s" %InitFilePathName)
|
||||
try:
|
||||
jlink_exe_file(InitFilePathName)
|
||||
except Exception as e:
|
||||
raise Exception("download error:\n %s" %e)
|
||||
|
||||
download_file_by_download_info(**DownloadInfoDict)
|
||||
12
devices/script/SES/init_before_download.js
Normal file
12
devices/script/SES/init_before_download.js
Normal file
@@ -0,0 +1,12 @@
|
||||
function init_before_download(cmd_file_path_name)
|
||||
{
|
||||
// TargetInterface.message(cmd_file_path_name)
|
||||
var JLinkDir = TargetInterface.expandMacro("$(JLinkDir)");
|
||||
var DeviceName = TargetInterface.expandMacro("$(DeviceName)");
|
||||
var JLinkDir2 = JLinkDir.replace('\\', '/');
|
||||
// TargetInterface.message(JLinkDir2);
|
||||
var cmd = '"' + JLinkDir2 + "/JLink.exe" + '"' + " -device " + DeviceName + " -if SWD -speed 4000 -autoconnect 1 -CommandFile " + '"' + cmd_file_path_name + '"';
|
||||
// TargetInterface.resetAndStop()
|
||||
// TargetInterface.delay(1000)
|
||||
CWSys.run(cmd, true);
|
||||
}
|
||||
104
devices/script/SES/readme.txt
Normal file
104
devices/script/SES/readme.txt
Normal file
@@ -0,0 +1,104 @@
|
||||
一、SES FlashDebug模式使用方法：
|
||||
1. 添加SemiDrive devices。
|
||||
在JLink AppData目录下（常见为C:\Users\Administrator\AppData\Roaming\SEGGER）添加SemiDrive devices。
|
||||
具体方法为：将ssdk\prebuilts\JLinkDevices目录拷贝到Link AppData目录下的SEGGER文件夹内。
|
||||
其中，包含JLinkDevices.xml文件和Devices\SemiDrive文件夹所有芯片Part的Flashloader。
|
||||
|
||||
2. 将Devices信息拷贝到Jlink安装目录（Jlink版本大于V7.62不需要这一步）。
|
||||
如果Jlink版本低于V7.62（可以在Windows开始菜单栏搜索Jlink查看），还需要额外再将Devices信息拷贝到Jlink安装目录。
|
||||
先将ssdk_dev\prebuilts\JLinkDevices\Devices\SemiDrive目录拷贝到Jlink安装目录下的Devices文件夹内（如C:\Program Files\SEGGER\JLink\Devices）。
|
||||
再将ssdk_dev\prebuilts\JLinkDevices\JLinkDevices.xml文件替换Jlink安装目录原有的JLinkDevices.xml文件（建议先将原文件备份再替换）。
|
||||
|
||||
3. 重新打开SES工程（如在完成第1步之前先打开了SES工程，需要关闭后重新打开工程）。
|
||||
|
||||
4. 编译FlashDebug模式工程（xip需要先编译bootloader工程，再编译app工程的Debug或FlashDebug模式）。
|
||||
编译完成后会在SES\Output\FlashDebug\Exe目录中自动生成签名bin文件，如sf_signed.bin。
|
||||
|
||||
5. 在SES IDE中点击Target——Download xxx。
|
||||
IDE调用Flashloader完成flash文件下载。
|
||||
|
||||
二、FlashDebug模式的配置包含如下内容（已默认添加到工程中）：
|
||||
1.post-build
|
||||
"$(ProjectDir)/../../../../../prebuilts/windows/python-3.7.0/python.exe" "$(ProjectDir)/../../../../../devices/script/SES/cmd_download.py" "$(JLinkDir)" "$(SolutionPath)" "$(PART_ID)" "HYPERFLASH" "$(OPS)"
|
||||
或者
|
||||
"$(ProjectDir)/../../../../../prebuilts/windows/python-3.7.0/python.exe" "$(ProjectDir)/../../../../../devices/script/SES/cmd_download.py" "$(JLinkDir)" "$(SolutionPath)" "$(PART_ID)" "NORFLASH" "$(OPS)"
|
||||
|
||||
2.Target Script
|
||||
Reset Script:
|
||||
init_before_download("$(ProjectDir)/../../../../../devices/$(PART_ID)/flashloader/init_before_download_hyperflash.txt")
|
||||
或者
|
||||
init_before_download("$(ProjectDir)/../../../../../devices/$(PART_ID)/flashloader/init_before_download_norflash.txt")
|
||||
Target Script File:
|
||||
$(ProjectDir)/../../../../../devices/script/SES/init_before_download.js
|
||||
|
||||
3.loader
|
||||
driver类:
|
||||
所有工程
|
||||
debug：
|
||||
无需配置
|
||||
FlashDebug:
|
||||
Download_HYPERFLASH(Download_NORFLASH):
|
||||
$(ProjectDir)/Output/FlashDebug/Exe/sf_signed.bin - 0x100C0000(0x10007000)
|
||||
$(ProjectDir)/../../../../../tools/sdtools/sfs/sfs_s26h-hyperflash.bin - 0x10000000
|
||||
xip类:（签名bootloader，所有核的app不签名）
|
||||
bootloader工程：
|
||||
debug
|
||||
无需配置
|
||||
FlashDebug:
|
||||
不支持
|
||||
sf工程中
|
||||
debug：
|
||||
配置device name
|
||||
配置init_before_download
|
||||
init_before_download("$(ProjectDir)/../../../../../../devices/$(PART_ID)/flashloader/init_before_download.txt")
|
||||
$(ProjectDir)/../../../../../../devices/script/SES/init_before_download.js
|
||||
FlashDebug:
|
||||
Download_HYPERFLASH(Download_NORFLASH):
|
||||
$(ProjectDir)/../../bootloader/SES/Output/Debug/Exe/sf_signed.bin - 0x100C0000(0x10007000)
|
||||
$(ProjectDir)/../../../../../../tools/sdtools/sfs/sfs_s26h-hyperflash.bin - 0x10000000
|
||||
$(ProjectDir)/Output/FlashDebug/Exe/sf.bin - 0x10140000
|
||||
Download_HYPERFLASH_Multicore(Download_NORFLASH_Multicore):
|
||||
$(ProjectDir)/../../sp0/SES/Output/FlashDebug/Exe/sp0.bin - 0x10340000(0x10288000)
|
||||
$(ProjectDir)/../../sp1/SES/Output/FlashDebug/Exe/sp1.bin - 0x103C0000(0x10308000)
|
||||
$(ProjectDir)/../../sx0/SES/Output/FlashDebug/Exe/sx0.bin - 0x10440000(0x10388000)
|
||||
$(ProjectDir)/../../sx1/SES/Output/FlashDebug/Exe/sx1.bin - 0x104C0000(0x10408000)
|
||||
sp/sx工程中
|
||||
debug:
|
||||
配置device name
|
||||
FlashDebug:
|
||||
Download_HYPERFLASH(Download_NORFLASH):
|
||||
$(ProjectDir)Output/FlashDebug/Exe/sp0.bin - 0x10340000(0x10288000)
|
||||
$(ProjectDir)Output/FlashDebug/Exe/sp1.bin - 0x103C0000(0x10308000)
|
||||
$(ProjectDir)Output/FlashDebug/Exe/sx0.bin - 0x10440000(0x10388000)
|
||||
$(ProjectDir)Output/FlashDebug/Exe/sx1.bin - 0x104C0000(0x10408000)
|
||||
多核类：（所有核都签名）
|
||||
sf工程中
|
||||
debug：
|
||||
无需配置
|
||||
FlashDebug:
|
||||
Download_HYPERFLASH(Download_NORFLASH):
|
||||
$(ProjectDir)/Output/FlashDebug/Exe/sf_signed.bin - 0x100C0000(0x10007000)
|
||||
$(ProjectDir)/../../../../../../tools/sdtools/sfs/sfs_s26h-hyperflash.bin - 0x10000000
|
||||
Download_HYPERFLASH_Multicore(Download_NORFLASH_Multicore):
|
||||
$(ProjectDir)/../../sp0/SES/Output/FlashDebug/Exe/sp0_signed.bin - 0x10340000(0x10288000)
|
||||
$(ProjectDir)/../../sp1/SES/Output/FlashDebug/Exe/sp1_signed.bin - 0x103C0000(0x10308000)
|
||||
$(ProjectDir)/../../sx0/SES/Output/FlashDebug/Exe/sx0_signed.bin - 0x10440000(0x10388000)
|
||||
$(ProjectDir)/../../sx1/SES/Output/FlashDebug/Exe/sx1_signed.bin - 0x104C0000(0x10408000)
|
||||
sp/sx工程中
|
||||
debug：
|
||||
无需配置
|
||||
FlashDebug:
|
||||
不支持
|
||||
|
||||
4.target device
|
||||
$(PART_ID)_HYPERFLASH/$(PART_ID)_NORFLASH
|
||||
|
||||
注意： norflash和hyperflash下载地址和sfs类型不同
|
||||
|
||||
三、命令行下载：
|
||||
1. 条件：
|
||||
安装SEGEER Embeded Studio时请在安装对话框Additional Component中确认勾选Install Little Endian Library Files（默认已勾选）。
|
||||
2. 下载命令：
|
||||
例：
|
||||
"D:\Program Files\SEGGER\SEGGER Embedded Studio for ARM 7.10a\bin\emBuild" -config "FlashDebug" -D OPS=download -project "sf" "E:\WSL\git_repo\E3_DEV\boards\e3_gateway\driver_demo\acmp\SES\acmp.emProject"
|
||||
"D:\Program Files\SEGGER\SEGGER Embedded Studio for ARM 7.10a\bin\emBuild" -config "FlashDebug" -D OPS=download -project "sf" "E:\WSL\git_repo\E3_DEV\boards\e3_gateway\app_demo\xip\sf\SES\sf.emProject"
|
||||
261
devices/script/Trace32/download.cmm
Normal file
261
devices/script/Trace32/download.cmm
Normal file
@@ -0,0 +1,261 @@
|
||||
|
||||
ON ERROR JUMPTO EXIT
|
||||
|
||||
LOCAL &flashloader_pathname §or_size
|
||||
Var.NEWLOCAL char[10][128] \download_file_pathname
|
||||
Var.NEWLOCAL char[10][128] \download_file_address
|
||||
|
||||
; User Config Download Options
|
||||
|
||||
;&flashloader_pathname="~~~~/../../E3104/flashloader/flashloader_norflash.out"
|
||||
;Var.set \download_file_pathname[0]="semi drive/e3/test/sfs.bin"
|
||||
;Var.set \download_file_address[0]="0x10000000"
|
||||
;Var.set \download_file_pathname[1]="semi drive/e3/test/rfd.bin"
|
||||
;Var.set \download_file_address[1]="0x100000F0"
|
||||
;Var.set \download_file_pathname[2]="semi drive/e3/test/boot0.bin"
|
||||
;Var.set \download_file_address[2]="0x100C0000"
|
||||
;Var.set \download_file_pathname[3]="semi drive/e3/test/boot1.bin"
|
||||
;Var.set \download_file_address[3]="0x104C0000"
|
||||
;Var.set \download_file_pathname[4]="semi drive/e3/test/boot2.bin"
|
||||
;Var.set \download_file_address[4]="0x108C0000"
|
||||
|
||||
&flashloader_pathname="~~~~/../../E3640/flashloader/flashloader_hyperflash.out"
|
||||
Var.set \download_file_pathname[0]="~~/semi drive/e3/test pathhavespace/sfs.bin"
|
||||
Var.set \download_file_address[0]="0x10000000"
|
||||
Var.set \download_file_pathname[1]="~~/semi drive/e3/test pathhavespace/rfd.bin"
|
||||
Var.set \download_file_address[1]="0x100000F0"
|
||||
Var.set \download_file_pathname[2]="~~/semi drive/e3/test pathhavespace/boot0.bin"
|
||||
Var.set \download_file_address[2]="0x100C0000"
|
||||
Var.set \download_file_pathname[3]="~~/semi drive/e3/test pathhavespace/boot1.bin"
|
||||
Var.set \download_file_address[3]="0x104C0000"
|
||||
Var.set \download_file_pathname[4]="~~/semi drive/e3/test pathhavespace/boot2.bin"
|
||||
Var.set \download_file_address[4]="0x108C0000"
|
||||
|
||||
;&flashloader_pathname="~~~~/../../E3104/flashloader/flashloader_norflash.out"
|
||||
;Var.set \download_file_pathname[0]="~~/semi drive/e3/test pathhavespace/sfs.bin"
|
||||
;Var.set \download_file_address[0]="0x10000000"
|
||||
;Var.set \download_file_pathname[1]="~~/semi drive/e3/test pathhavespace/rfd.bin"
|
||||
;Var.set \download_file_address[1]="0x100000F0"
|
||||
;Var.set \download_file_pathname[2]="~~/semi drive/e3/test pathhavespace/boot0.bin"
|
||||
;Var.set \download_file_address[2]="0x10007000"
|
||||
;Var.set \download_file_pathname[3]="~~/semi drive/e3/test pathhavespace/boot1.bin"
|
||||
;Var.set \download_file_address[3]="0x10407000"
|
||||
;Var.set \download_file_pathname[4]="~~/semi drive/e3/test pathhavespace/boot2.bin"
|
||||
;Var.set \download_file_address[4]="0x10807000"
|
||||
|
||||
;&flashloader_pathname="~~~~/../../E3104/flashloader/flashloader_norflash.out"
|
||||
;Var.set \download_file_pathname[0]="test_noflashloader/sfs.bin"
|
||||
;Var.set \download_file_address[0]="0x10000000"
|
||||
;Var.set \download_file_pathname[1]="test_noflashloader/rfd.bin"
|
||||
;Var.set \download_file_address[1]="0x100000F0"
|
||||
;Var.set \download_file_pathname[2]="test_noflashloader/boot0.bin"
|
||||
;Var.set \download_file_address[2]="0x100C0000"
|
||||
;Var.set \download_file_pathname[3]="test_noflashloader/boot1.bin"
|
||||
;Var.set \download_file_address[3]="0x104C0000"
|
||||
;Var.set \download_file_pathname[4]="test_noflashloader/boot2.bin"
|
||||
;Var.set \download_file_address[4]="0x108C0000"
|
||||
|
||||
;&flashloader_pathname="test_nobin/flashloader.out"
|
||||
;Var.set \download_file_pathname[0]="test_nobin/sfs.bin"
|
||||
;Var.set \download_file_address[0]="0x10000000"
|
||||
;Var.set \download_file_pathname[1]="test_nobin/rfd.bin"
|
||||
;Var.set \download_file_address[1]="0x100000F0"
|
||||
;Var.set \download_file_pathname[2]="test_nobin/boot0.bin"
|
||||
;Var.set \download_file_address[2]="0x100C0000"
|
||||
;Var.set \download_file_pathname[3]="test_nobin/boot1.bin"
|
||||
;Var.set \download_file_address[3]="0x104C0000"
|
||||
;Var.set \download_file_pathname[4]="test_nobin/boot2.bin"
|
||||
;Var.set \download_file_address[4]="0x108C0000"
|
||||
|
||||
GOSUB CHECK_FILE_IS_EXIST "&flashloader_pathname"
|
||||
GOSUB CHECK_FILES_IS_EXIST \download_file_pathname
|
||||
GOSUB INIT
|
||||
GOSUB DOWNLOAD_FILES \download_file_pathname \download_file_address §or_size
|
||||
|
||||
EXIT:
|
||||
IF OS.FILE(flashloader.bin)==TRUE()
|
||||
RM flashloader.bin
|
||||
ON ERROR inherit
|
||||
ENDDO
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
INIT:
|
||||
; jtag clock config
|
||||
SYStem.JtagClock 20MHz
|
||||
|
||||
; cpu config
|
||||
SYStem.CPU CortexR5F
|
||||
|
||||
; mem access port
|
||||
SYStem.CONFIG.apbaccessport 0
|
||||
SYStem.CONFIG.apbap1.base 0x2000
|
||||
SYStem.CONFIG.debugaccessport 0
|
||||
SYStem.CONFIG.debugap1.base 0x2000
|
||||
|
||||
; DBG
|
||||
SYStem.CONFIG.COREDEBUG.Base 0xF2081000
|
||||
|
||||
SYStem.attach
|
||||
|
||||
Break
|
||||
|
||||
PRIVATE &tcm_base &program_begin &program_end &arg_base
|
||||
|
||||
; disable mpu and cache
|
||||
Data.SET C15:0x0001 0x08E7087A
|
||||
Data.SET C15:0x0101 0x00000020
|
||||
|
||||
; init tcm
|
||||
Data.LOAD.Elf "&flashloader_pathname" /NoCode
|
||||
&tcm_base=ADDRESS.OFFSET(sYmbol.SECADDRESS(PrgCode))
|
||||
&program_begin=ADDRESS.OFFSET(sYmbol.SECADDRESS(T32CodeBegin))
|
||||
&program_end=ADDRESS.OFFSET(sYmbol.SECEND(T32CodeEnd))
|
||||
Data.SET C15:0x0019 (&tcm_base+0x10000)|0x1
|
||||
Data.SET C15:0x0119 &tcm_base|0x1
|
||||
|
||||
; generate flashloader.bin
|
||||
Data.LOAD.Elf "&flashloader_pathname"
|
||||
Data.SAVE.Binary flashloader.bin D:&program_begin--&program_end
|
||||
|
||||
; calc config para
|
||||
&info_base=ADDRESS.OFFSET(sYmbol.SECADDRESS(DevDscr))
|
||||
§or_size=DATA.Long(D:(&info_base+0xA0))
|
||||
&arg_base=&tcm_base+0x20000-0x2020
|
||||
|
||||
FLASH.RESet
|
||||
|
||||
FLASH.Create 1. 0x10000000--0x11FFFFFF §or_size TARGET LONG
|
||||
FLASH.TARGET &program_begin &arg_base 0x1000 flashloader.bin /STACKSIZE 0x1000
|
||||
; test error handle
|
||||
;FLASH.TARGET &program_begin &arg_base 0x1000++ flashloader.bin /STACKSIZE 0x1000
|
||||
|
||||
RETURN
|
||||
|
||||
|
||||
|
||||
CHECK_FILES_IS_EXIST:
|
||||
PRIVATE &i &file_pathname &file_pathname_len
|
||||
ENTRY &file_pathname_array
|
||||
&i=0.
|
||||
WHILE &i<10
|
||||
(
|
||||
&file_pathname_len=STRing.LENgth(Var.STRing(&file_pathname_array[&i]))
|
||||
IF &file_pathname_len!=0
|
||||
(
|
||||
&file_pathname = Var.STRing(&file_pathname_array[&i])
|
||||
GOSUB CHECK_FILE_IS_EXIST "&file_pathname"
|
||||
&i=&i+1
|
||||
)
|
||||
ELSE
|
||||
(
|
||||
IF &i!=0
|
||||
RETURN
|
||||
ELSE
|
||||
ENDDO
|
||||
)
|
||||
)
|
||||
|
||||
|
||||
|
||||
CHECK_FILE_IS_EXIST:
|
||||
ENTRY &file_pathname
|
||||
IF OS.FILE(&file_pathname)==FALSE()
|
||||
(
|
||||
PRINT &file_pathname " is not exist"
|
||||
ENDDO
|
||||
)
|
||||
ELSE
|
||||
RETURN
|
||||
|
||||
|
||||
|
||||
DOWNLOAD_FILES:
|
||||
PRIVATE &i &file_pathname &file_pathname_len &file_address
|
||||
ENTRY &file_pathname_array &file_address_array §or_size
|
||||
&i=0.
|
||||
WHILE &i<10
|
||||
(
|
||||
&file_pathname_len=STRing.LENgth(Var.STRing(&file_pathname_array[&i]))
|
||||
IF &file_pathname_len!=0
|
||||
(
|
||||
&file_pathname = Var.STRing(&file_pathname_array[&i])
|
||||
&file_address = Var.STRing(&file_address_array[&i])
|
||||
GOSUB DOWNLOAD_FILE "&file_pathname" &file_address §or_size
|
||||
&i=&i+1
|
||||
)
|
||||
ELSE
|
||||
(
|
||||
RETURN
|
||||
)
|
||||
)
|
||||
|
||||
|
||||
|
||||
DOWNLOAD_FILE:
|
||||
PRIVATE &file_size §or_num &erase_address_end
|
||||
ENTRY &download_file_pathname &download_file_address &download_sector_size
|
||||
|
||||
IF &download_file_address%&download_sector_size==0
|
||||
(
|
||||
&file_size=OS.FILE.SIZE(&download_file_pathname)
|
||||
IF &file_size%&download_sector_size==0
|
||||
§or_num=&file_size/&download_sector_size
|
||||
ELSE
|
||||
§or_num=&file_size/&download_sector_size+1
|
||||
&erase_address_end=CONVert.INTTOHEX(&download_file_address+§or_num*§or_size-1)
|
||||
FLASH.Erase &download_file_address--&erase_address_end
|
||||
)
|
||||
FLASH.Program ALL
|
||||
Data.LOAD.Binary &download_file_pathname &download_file_address
|
||||
FLASH.Program OFF
|
||||
|
||||
RETURN
|
||||
|
||||
60
devices/script/Trace32/e3_attach_sf.cmm
Normal file
60
devices/script/Trace32/e3_attach_sf.cmm
Normal file
@@ -0,0 +1,60 @@
|
||||
; --------------------------------------------------------------------------------
|
||||
; @Title: Example for manual JTAG access, Debugger in DOWN Mode
|
||||
; @Description:
|
||||
;This script reads out the IDCODE of an ARM7 core when the debugger is in
|
||||
;DOWN mode.
|
||||
;Detailed knowledge about JTAG is required to use manual JTAG control signals!
|
||||
;Tested on an ARM7 target board.
|
||||
; @Keywords: idcode
|
||||
; @Author: PEG
|
||||
; @Props: Template
|
||||
; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
||||
; --------------------------------------------------------------------------------
|
||||
; $Id: example1.cmm 6982 2023-02-22 11:10:17Z kjmal $
|
||||
; @Copyright: Semidrive semiconductor
|
||||
; @Title: Semidrive Secure Debug logic.
|
||||
; The debugger is in DOWN mode, the JTAG driver is tristated.
|
||||
|
||||
area
|
||||
SYStem.CPU CortexR5
|
||||
SYStem.CONFIG.apbaccessport 0
|
||||
SYStem.CONFIG.apbap1.base 0x2000
|
||||
SYStem.CONFIG.debugaccessport 0
|
||||
SYStem.CONFIG.debugap1.base 0x2000
|
||||
SYStem.CONFIG.COREDEBUG.Base 0xF2081000
|
||||
;e3
|
||||
;SYStem.CONFIG.COREDEBUG.Base 0xF0a01000
|
||||
SYStem.Option.TRST OFF
|
||||
SYStem.JtagClock 1MHz
|
||||
JTAG.PIN ENable
|
||||
; enable JTAG output driver
|
||||
JTAG.SHIFTTMS 1 1 1 1 1
|
||||
; soft reset of the JTAG interface, goto Test-Logic Reset state
|
||||
JTAG.SHIFTTMS 0 1 1 0 0
|
||||
; goto Shift-IR state
|
||||
JTAG.SHIFTREG 1 1 1 1
|
||||
; shift in UID instruction, goto exit1-ir
|
||||
JTAG.SHIFTTMS 1 1 0 0
|
||||
; goto Shift-DR state
|
||||
JTAG.SHIFTREG %long 0x0 0x0
|
||||
; shift in 64bit dummy code. shift out our uid, goto exit1-dr
|
||||
PRINT JTAG.SHIFT()
|
||||
; print the UID
|
||||
JTAG.SHIFTTMS 1 1 0 0
|
||||
; goto Shift-DR state
|
||||
JTAG.SHIFTREG %long 0x74657374 0x6b657930
|
||||
; Note: 0x74657374 --> SEC_DBG_CFG[31, 0]!!, 0x6b657930 --> SEC_DBG_CFG[63, 32]!!
|
||||
; shift in the corresponding key .shift out our uid, goto exit1-dr
|
||||
PRINT JTAG.SHIFT()
|
||||
JTAG.SHIFTTMS 1 1 1 1 1
|
||||
; goto Test-Logic Reset state
|
||||
JTAG.SHIFTTMS 0 1 0 0
|
||||
; goto Shift-DR state
|
||||
JTAG.SHIFTREG %long 0x0
|
||||
; shift our IDCODE, goto exit1-dr
|
||||
PRINT JTAG.SHIFT()
|
||||
JTAG.PIN Disable
|
||||
; Disable JTAG output driver
|
||||
SYStem.Mode Attach
|
||||
;attach
|
||||
ENDDO
|
||||
38
devices/script/Trace32/readme
Normal file
38
devices/script/Trace32/readme
Normal file
@@ -0,0 +1,38 @@
|
||||
## 简介
|
||||
|
||||
介绍通过Trac32使用secure debug功能
|
||||
该功能支持JTAG模式，不支持SWD模式
|
||||
芯片匹配debug key成功后开启debug接口
|
||||
|
||||
##硬件连接
|
||||
|
||||
- e3_gateway参考板
|
||||
- Trace32
|
||||
|
||||
##注意事项
|
||||
- 确认板子JTAG功能正常，对于e3 gateway参考板需要去掉TDO/TDI上的两个电阻。
|
||||
- 需要通过fuse工具烧UID,debug key和使能secure debug。
|
||||
- 接口如果是SWD,需要修改为JTAG。
|
||||
|
||||
##测试方法
|
||||
当板子以以下方式烧UID,debug key和使能secure debug.
|
||||
Debug Key:
|
||||
+-----------------------+------------+------------------+
|
||||
| name | fuse addr | fuse value |
|
||||
+-----------------------+------------+------------------+
|
||||
| UID[0, 31] | 0x1010 | 0x12345678 |
|
||||
| UID[32, 63] | 0x1014 | 0xABCDEF88 |
|
||||
| SEC_DBG_CFG[31, 0] | 0x1280 | 0x74657374(key0) |
|
||||
| SEC_DBG_CFG[63, 32] | 0x1284 | 0x6b657930(key1) |
|
||||
| MSIC_CFG3/SDBG_MODE | 0x12b0 | 0x00800000 |
|
||||
+-----------------------+------------+------------------+
|
||||
|
||||
脚本拖入trace32.exe并执行
|
||||
CD.DO 本地路径\e3_attach_sf.cmm
|
||||
|
||||
提供错误的debug key则无法执行通过。
|
||||
|
||||
##expected log
|
||||
0ABCDEF8812345678
|
||||
0ABCDEF8812345678
|
||||
4BA00477
|
||||
Reference in New Issue
Block a user