193 lines
10 KiB
C
193 lines
10 KiB
C
/**
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* @brief Unique ID of the peripheral for DMA in SF domain .
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*
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* For peripheral transactions,DMA channel should set corresponding
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* mux id to select peripheral.
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*/
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typedef enum {
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SDRV_DMA_MUX_ID_CANFD16,
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SDRV_DMA_MUX_ID_CANFD21,
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SDRV_DMA_MUX_ID_CANFD3,
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SDRV_DMA_MUX_ID_CANFD4,
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SDRV_DMA_MUX_ID_CANFD5,
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SDRV_DMA_MUX_ID_CANFD6,
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SDRV_DMA_MUX_ID_CANFD7,
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SDRV_DMA_MUX_ID_CANFD23,
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SDRV_DMA_MUX_ID_ENET1_REQ_0,
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SDRV_DMA_MUX_ID_ENET1_REQ_1,
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SDRV_DMA_MUX_ID_ENET1_REQ_2,
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SDRV_DMA_MUX_ID_ENET1_REQ_3,
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SDRV_DMA_MUX_ID_I2C1,
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SDRV_DMA_MUX_ID_I2C2,
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SDRV_DMA_MUX_ID_I2C3,
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SDRV_DMA_MUX_ID_I2C4,
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SDRV_DMA_MUX_ID_I2C5,
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SDRV_DMA_MUX_ID_I2C6,
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SDRV_DMA_MUX_ID_XSPI1_A_RD,
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SDRV_DMA_MUX_ID_XSPI1_A_WR,
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SDRV_DMA_MUX_ID_XSPI1_B_RD,
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SDRV_DMA_MUX_ID_XSPI1_B_WR,
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SDRV_DMA_MUX_ID_SPI1_RX,
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SDRV_DMA_MUX_ID_SPI1_TX,
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SDRV_DMA_MUX_ID_SPI2_RX,
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SDRV_DMA_MUX_ID_SPI2_TX,
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SDRV_DMA_MUX_ID_SPI3_RX,
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SDRV_DMA_MUX_ID_SPI3_TX,
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SDRV_DMA_MUX_ID_SPI4_RX,
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SDRV_DMA_MUX_ID_SPI4_TX,
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SDRV_DMA_MUX_ID_SPI5_RX,
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SDRV_DMA_MUX_ID_SPI5_TX,
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SDRV_DMA_MUX_ID_SPI6_RX,
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SDRV_DMA_MUX_ID_SPI6_TX,
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SDRV_DMA_MUX_ID_EPWM1_A,
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SDRV_DMA_MUX_ID_EPWM1_B,
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SDRV_DMA_MUX_ID_EPWM1_C,
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SDRV_DMA_MUX_ID_EPWM1_D,
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SDRV_DMA_MUX_ID_EPWM1_OVF,
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SDRV_DMA_MUX_ID_EPWM2_A,
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SDRV_DMA_MUX_ID_EPWM2_B,
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SDRV_DMA_MUX_ID_EPWM2_C,
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SDRV_DMA_MUX_ID_EPWM2_D,
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SDRV_DMA_MUX_ID_EPWM2_OVF,
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SDRV_DMA_MUX_ID_ETMR1_A,
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SDRV_DMA_MUX_ID_ETMR1_B,
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SDRV_DMA_MUX_ID_ETMR1_C,
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SDRV_DMA_MUX_ID_ETMR1_D,
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SDRV_DMA_MUX_ID_ETMR1_OVF,
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SDRV_DMA_MUX_ID_ETMR2_A,
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SDRV_DMA_MUX_ID_ETMR2_B,
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SDRV_DMA_MUX_ID_ETMR2_C,
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SDRV_DMA_MUX_ID_ETMR2_D,
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SDRV_DMA_MUX_ID_ETMR2_OVF,
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SDRV_DMA_MUX_ID_XTRG_0,
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SDRV_DMA_MUX_ID_XTRG_1,
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SDRV_DMA_MUX_ID_UART1_TX,
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SDRV_DMA_MUX_ID_UART1_RX,
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SDRV_DMA_MUX_ID_UART2_TX,
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SDRV_DMA_MUX_ID_UART2_RX,
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SDRV_DMA_MUX_ID_UART3_TX,
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SDRV_DMA_MUX_ID_UART3_RX,
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SDRV_DMA_MUX_ID_UART4_TX,
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SDRV_DMA_MUX_ID_UART4_RX,
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SDRV_DMA_MUX_ID_UART5_TX,
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SDRV_DMA_MUX_ID_UART5_RX,
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SDRV_DMA_MUX_ID_UART6_TX,
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SDRV_DMA_MUX_ID_UART6_RX,
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SDRV_DMA_MUX_ID_UART7_TX,
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SDRV_DMA_MUX_ID_UART7_RX,
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SDRV_DMA_MUX_ID_UART8_TX,
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SDRV_DMA_MUX_ID_UART8_RX,
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SDRV_DMA_MUX_ID_UART9_TX,
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SDRV_DMA_MUX_ID_UART9_RX,
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SDRV_DMA_MUX_ID_UART10_TX,
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SDRV_DMA_MUX_ID_UART10_RX,
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SDRV_DMA_MUX_ID_UART11_TX,
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SDRV_DMA_MUX_ID_UART11_RX,
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SDRV_DMA_MUX_ID_UART12_TX,
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SDRV_DMA_MUX_ID_UART12_RX,
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SDRV_DMA_MUX_ID_ADC1_0,
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SDRV_DMA_MUX_ID_ADC1_1,
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SDRV_DMA_MUX_ID_ADC2_0,
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SDRV_DMA_MUX_ID_ADC2_1,
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SDRV_DMA_MUX_ID_ADC3_0,
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SDRV_DMA_MUX_ID_ADC3_1,
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SDRV_DMA_MUX_ID_SACI2_TX,
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SDRV_DMA_MUX_ID_SACI2_RX,
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SDRV_DMA_MUX_ID_SACI2_PDM,
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SDRV_DMA_MUX_ID_ISTC,
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} sdrv_dma_sf_mux_id_e;
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#define DMA_SF_PERIPHERALS_MUX_MAP \
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{SDRV_DMA_MUX_ID_CANFD16, APB_CANFD16_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_CANFD21, APB_CANFD21_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_CANFD3, APB_CANFD3_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_CANFD4, APB_CANFD4_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_CANFD5, APB_CANFD5_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_CANFD6, APB_CANFD6_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_CANFD7, APB_CANFD7_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_CANFD23, APB_CANFD23_BASE, 0x80, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_I2C3, APB_I2C3_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_I2C4, APB_I2C4_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_I2C5, APB_I2C5_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_I2C6, APB_I2C6_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_I2C3, APB_I2C3_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_I2C4, APB_I2C4_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_I2C5, APB_I2C5_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_I2C6, APB_I2C6_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_XSPI1_A_RD, APB_XSPI1PORTA_BASE, 0x2000, \
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SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_XSPI1_A_WR, APB_XSPI1PORTA_BASE, 0x280, \
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SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_XSPI1_B_RD, APB_XSPI1PORTB_BASE, 0x2000, \
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SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_XSPI1_B_WR, APB_XSPI1PORTB_BASE, 0x280, \
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SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_SPI1_RX, APB_SPI1_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_SPI1_TX, APB_SPI1_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_SPI2_RX, APB_SPI2_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_SPI2_TX, APB_SPI2_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_SPI3_RX, APB_SPI3_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_SPI3_TX, APB_SPI3_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_SPI4_RX, APB_SPI4_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_SPI4_TX, APB_SPI4_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_SPI5_RX, APB_SPI5_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_SPI5_TX, APB_SPI5_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_SPI6_RX, APB_SPI6_BASE, 0x3000, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_SPI6_TX, APB_SPI6_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_EPWM1_A, APB_EPWM1_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_EPWM1_B, APB_EPWM1_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_EPWM1_C, APB_EPWM1_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_EPWM1_D, APB_EPWM1_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_EPWM1_OVF, APB_EPWM1_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_EPWM2_A, APB_EPWM2_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_EPWM2_B, APB_EPWM2_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_EPWM2_C, APB_EPWM2_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_EPWM2_D, APB_EPWM2_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_EPWM2_OVF, APB_EPWM2_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ETMR1_A, APB_ETMR1_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ETMR1_B, APB_ETMR1_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ETMR1_C, APB_ETMR1_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ETMR1_D, APB_ETMR1_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ETMR1_OVF, APB_ETMR1_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ETMR2_A, APB_ETMR2_BASE, 0xc0, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ETMR2_B, APB_ETMR2_BASE, 0xc4, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ETMR2_C, APB_ETMR2_BASE, 0xc8, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ETMR2_D, APB_ETMR2_BASE, 0xcc, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ETMR2_OVF, APB_ETMR2_BASE, 0x104, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_UART1_TX, APB_UART1_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART1_RX, APB_UART1_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_UART2_TX, APB_UART2_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART2_RX, APB_UART2_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_UART3_TX, APB_UART3_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART3_RX, APB_UART3_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_UART4_TX, APB_UART4_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART4_RX, APB_UART4_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_UART5_TX, APB_UART5_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART5_RX, APB_UART5_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_UART6_TX, APB_UART6_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART6_RX, APB_UART6_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_UART7_TX, APB_UART7_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART7_RX, APB_UART7_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_UART8_TX, APB_UART8_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART8_RX, APB_UART8_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_UART9_TX, APB_UART9_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART9_RX, APB_UART9_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_UART10_TX, APB_UART10_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART10_RX, APB_UART10_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_UART11_TX, APB_UART11_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART11_RX, APB_UART11_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_UART12_TX, APB_UART12_BASE, 0x200, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_UART12_RX, APB_UART12_BASE, 0x300, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_ADC1_0, APB_ADC1_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ADC1_1, APB_ADC1_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ADC2_0, APB_ADC2_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ADC2_1, APB_ADC2_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ADC3_0, APB_ADC3_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_ADC3_1, APB_ADC3_BASE, 0x3C0, SDRV_DMA_MUX_BOTH}, \
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{SDRV_DMA_MUX_ID_SACI2_TX, APB_SACI2_BASE, 0x2000, SDRV_DMA_MUX_WR}, \
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{SDRV_DMA_MUX_ID_SACI2_RX, APB_SACI2_BASE, 0x4000, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_SACI2_PDM, APB_SACI2_BASE, 0x6000, SDRV_DMA_MUX_RD}, \
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{SDRV_DMA_MUX_ID_ISTC, APB_ISTC_BASE, 0xffff, SDRV_DMA_MUX_BOTH},
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#define SDRV_DMA_SF_MAX_CHANNEL (16) /* SF DMA channel number */
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