250K-T8S
This commit is contained in:
505
START_XC.a51
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505
START_XC.a51
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$NOMOD51
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;------------------------------------------------------------------------------
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; This file is part of the C51 Compiler package
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; Startup Code for the Infineon XC8xx devices
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; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc.
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; Version 20100601
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; -------- Revision ---------
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; - Previous version 20100405
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; - Added XC864 with option for LIN_BSL parameters
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; - Renamed NDIV_XC866 to NDIV_XC86x
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;
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; *** <<< Use Configuration Wizard in Context Menu >>> ***
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;------------------------------------------------------------------------------
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; STARTUP.A51: This code is executed after processor reset.
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;
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; To translate this file use A51 with the following invocation:
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;
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; A51 STARTUP.A51
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;
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; To link the modified STARTUP.OBJ file to your application use the following
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; Lx51 invocation:
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;
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; Lx51 your object file list, STARTUP.OBJ controls
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;
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;------------------------------------------------------------------------------
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;
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;<e> Use off-chip XTAL
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;<i> XC8xx series runs by default from on-chip osciallator.
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;<i> optionally you may use a off-chip XTAL
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;
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XTAL EQU 1 ; set to 0 On-chip oscillator/ not used for XC82x devices
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;
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;<e> Device = " XC82x "
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XC82x_CHIP EQU 0 ;applicable to XC83x
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;---------------------------------------------------------------------
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;resulting in fsys = 80MHz for XC866/XC864 and fsys = 96MHz for XC88x unless otherwise mentioned
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;
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;<e> Device = " XC866 "
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XC866_CHIP EQU 0
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;<e> Device = " XC864 "
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XC864_CHIP EQU 0
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;
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; <o> PLL N-Divider
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; <i> PLL N-Divider must result in fsys = 80MHz
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; <0=> N=14
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; <1=> N=15
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; <2=> N=16 (10 MHz XTAL)
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; <3=> N=17
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; <4=> N=18
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; <5=> N=19
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; <6=> N=20 (8 MHz XTAL)
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; <7=> N=21
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; <8=> N=24
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; <9=> N=28
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; <10=> N=30
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; <11=> N=32 (5 MHz XTAL)
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; <12=> N=40
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; <13=> N=42
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; <14=> N=45
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; <15=> N=50
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;
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NDIV_XC86x EQU 2 ; default 2
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;</e>
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;---------------------------------------------------------------------
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;<e> Device = " XC88x "
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XC88x_CHIP EQU 1
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;
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; <o> PLL N-Divider for *NON-SAL* device fsys = 96 MHz
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; <0=> N=10
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; <1=> N=12
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; <2=> N=13
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; <3=> N=14
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; <4=> N=15
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; <5=> N=16 (12 MHz XTAL)
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; <6=> N=17
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; <7=> N=18
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; <8=> N=19
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; <9=> N=20 (9.6 MHz On-Chip XTAL)
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; <10=> N=24 (8 MHz XTAL)
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; <11=> N=30
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; <12=> N=32 (6 MHz XTAL)
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; <13=> N=36
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; <14=> N=40
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; <15=> N=48 (4 MHz XTAL)
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;
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; <o> PLL N-Divider for *SAL* device -> fsys = 80 MHz
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; <0=> N=10
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; <1=> N=12
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; <2=> N=13
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; <3=> N=14
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; <4=> N=15
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; <5=> N=16 (10 MHz On-Chip XTAL)
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; <6=> N=17
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; <7=> N=18
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; <8=> N=19
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; <9=> N=20 (8 MHz XTAL)
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; <10=> N=24
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; <11=> N=30
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; <12=> N=32 (5 MHz XTAL)
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; <13=> N=36
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; <14=> N=40 (4 MHz XTAL)
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; <15=> N=48
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;
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NDIV_XC88x EQU 10 ; default 10
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;</e>
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;---------------------------------------------------------------------
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;<e> Device = " XC87x "
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XC878_CHIP_16FF EQU 0
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XC878_CHIP_13FF EQU 0
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XC874_CHIP_16FF EQU 0
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XC874_CHIP_13FF EQU 0
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;4 MHz
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NDIV_XC87x_PLL_CON EQU 0x18
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NDIV_XC87x_PLL_CON1 EQU 0x20
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NR_XC87x EQU 0x00
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OD_XC87x EQU 0x00
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;6 MHz
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;NDIV_XC87x_PLL_CON EQU 0x18
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;NDIV_XC87x_PLL_CON1 EQU 0x20
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;NR_XC87x EQU 0x01
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;OD_XC87x EQU 0x00
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;8 MHz default
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;NDIV_XC87x_PLL_CON EQU 0x18
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;NDIV_XC87x_PLL_CON1 EQU 0x20
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;NR_XC87x EQU 0x02
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;OD_XC87x EQU 0x00
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;</e>
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;</e>
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;------------------------------------------------------------------------------
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;
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; User-defined <h> Power-On Initialization of Memory
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;
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; With the following EQU statements the initialization of memory
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; at processor reset can be defined:
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;
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;<o> IDATA memory length <0x0-0x100>
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;<i> Note: The absolute start-address of IDATA memory is always 0
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;<i> The IDATA space overlaps physically the DATA and BIT areas.
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IDATALEN EQU 0x100
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;
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; <o> XDATA memory start address <0x0-0xFFFF>
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; <i> absolute start-address of XDATA memory
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XDATASTART EQU 0xF000
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;
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; <o> XDATA memory length <0x0-0xFFFF>
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; <i> length of XDATA memory in bytes.
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IF (XC82x_CHIP)
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XDATALEN EQU 0x100
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ELSEIF (XC866_CHIP || XC864_CHIP)
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XDATALEN EQU 0x200
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ELSEIF (XC88x_CHIP)
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XDATALEN EQU 0x600
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ELSEIF (XC878_CHIP_16FF || XC878_CHIP_13FF)
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XDATALEN EQU 0xC00
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ELSEIF (XC874_CHIP_16FF || XC874_CHIP_13FF)
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XDATALEN EQU 0xC00
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ENDIF
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;
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; <o> PDATA memory start address <0x0-0xFFFF>
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; <i> absolute start-address of PDATA memory
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PDATASTART EQU 0xF000
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;
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; <o> PDATA memory length <0x0-0xFF>
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; <i> length of PDATA memory in bytes.
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PDATALEN EQU 0
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;
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; </h>
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;------------------------------------------------------------------------------
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;
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; <h> Reentrant Stack Initilization
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;
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; The following EQU statements define the stack pointer for reentrant
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; functions and initialized it:
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;
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; Stack Space for reentrant functions in the SMALL model.
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; <e> Activate reentrant Stack (SMALL model)
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IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
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; <o> top of stack <0x0-0xFF>
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; <i> set top of stack to highest location+1
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IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
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; </e>
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;
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; Stack Space for reentrant functions in the LARGE model.
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; <e> Activate reentrant Stack (LARGE model)
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XBPSTACK EQU 0 ; set to 1 if large reentrant is used.
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; <o> top of stack <0x0-0xFFFF>
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; <i> set top of stack to highest location+1.
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XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1
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; </e>
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;
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; Stack Space for reentrant functions in the COMPACT model.
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; <e> Activate reentrant Stack (COMPACT model)
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PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
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;
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; <o> top of stack <0x0-0xFF>
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; <i> set top of stack to highest location+1.
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PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
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; </e>
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; </h>
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;------------------------------------------------------------------------------
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;
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; <e>Set Memory Page for Using the Compact Model with 64 KByte xdata RAM
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;
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; <i>Define the xdata page used for pdata variables.
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; <i>PPAGE must conform with the PPAGE set in the linker invocation.
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;
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; Enable pdata memory page initalization
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PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.
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;
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; <o> PPAGE number <0x0-0xFF>
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; <i> uppermost 256-byte address of the page used for pdata variables.
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PPAGE EQU 0xF0
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;
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; </e>
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;------------------------------------------------------------------------------
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;
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; <e>Parameters for LIN Boostrap Loader (XC864 only)
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; <i>When these values are not defined, an XC864 device stays in
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; <i>LIN-BSL mode and does not start the user application
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;
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; Enable LIN BSL parameter initialization
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LIN_BSL EQU 1 ; set to 1 if LIN BSL parameters should be generated in flash table
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;
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; <o> NAC: No. Activity Count <0x00-0xFF>
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; <i> specifies the delay (n * 5ms) before jumping to user mode.
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; <i> 0x01: 0 ms delay. Jump to User Mode immediately
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; <i> 0x02: 5 ms delay before jumping to User Mode
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; <i> 0x03: 10 ms delay before jumping to User Mode
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; <i> 0x04 - 0x0C: 15 - 55 ms delay before jumping to User Mode
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; <i> 0x0D - 0xFF, 0x00: Enter LIN BSL Mode (Invalid NAC)
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LIN_NAC EQU 0x01
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;
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; <o> NAD: Node Address for Diagnostic <0x00-0xFF>
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; <i> specifies the address of the active slave node.
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LIN_NAD EQU 0x01
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;
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; </e>
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;------------------------------------------------------------------------------
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;Check the chip selection
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IF ((XC82x_CHIP + XC866_CHIP + XC864_CHIP + XC88x_CHIP + XC878_CHIP_16FF + XC878_CHIP_13FF + XC874_CHIP_16FF + XC874_CHIP_13FF) > 1)
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__ERROR__ "Please select only one chip!"
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ELSEIF ((XC82x_CHIP + XC866_CHIP + XC864_CHIP + XC88x_CHIP + XC878_CHIP_16FF + XC878_CHIP_13FF + XC874_CHIP_16FF + XC874_CHIP_13FF) == 0)
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__ERROR__ "Please select a chip!"
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ENDIF
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IF (XTAL <> 0)
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IF (XC866_CHIP <> 0 || XC864_CHIP <> 0)
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NDIV EQU NDIV_XC86x
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ELSEIF (XC88x_CHIP <> 0)
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NDIV EQU NDIV_XC88x
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ELSEIF (XC878_CHIP_16FF <> 0 || XC878_CHIP_13FF <> 0)
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;nothing
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ELSEIF (XC874_CHIP_16FF <> 0 || XC874_CHIP_13FF <> 0)
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;nothing
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ELSEIF (XC82x_CHIP <> 0)
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;nothing
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ELSE
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__WARNING__ "Default NDIV selection is XC866"
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NDIV EQU NDIV_XC86x ;Default
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ENDIF
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ENDIF ;End of XTAL selection
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; Standard SFR Symbols
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ACC DATA 0E0H
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B DATA 0F0H
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SP DATA 81H
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DPL DATA 82H
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DPH DATA 83H
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; XC8xx specific SFR Symbols used in STARTUP code
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IF (XC82x_CHIP == 0)
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; Take note of different SFR addresses for XC82x. Currently not used.
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sfr SCU_PAGE = 0xBF
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sfr PLL_CON = 0xB7
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sfr PLL_CON1 = 0xEA;//SCU,RMAP=0,Page=1
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sfr CMCON = 0xBA
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sfr OSC_CON = 0xB6
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sfr PASSWD = 0xBB
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sfr XADDRH = 0xB3
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sfr MEX3 = 0x96
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ENDIF
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IF(XC874_CHIP_13FF == 1 || XC874_CHIP_16FF == 1)
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sfr PORT_PAGE = 0xB2
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sfr P3_PUDEN = 0xB1
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sfr P4_PUDEN = 0xC9
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ENDIF
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NAME ?C_STARTUP
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?C_C51STARTUP SEGMENT CODE
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?STACK SEGMENT IDATA
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RSEG ?STACK
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DS 1
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EXTRN CODE (?C_START)
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PUBLIC ?C_STARTUP
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CSEG AT 0x2000
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?C_STARTUP: LJMP STARTUP1
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RSEG ?C_C51STARTUP
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STARTUP1:
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IF (XTAL <> 0)
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; switch to external XTAL
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IF(XC878_CHIP_16FF <> 0 || XC878_CHIP_13FF <> 0 || XC874_CHIP_16FF <> 0 || XC874_CHIP_13FF <> 0)
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MOV SCU_PAGE,#1;
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MOV PASSWD, #11000000B ;Disable Bit-Protection
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ANL OSC_CON, #~(0x01 << 2) ;OSCSS = 0
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ORL OSC_CON, #(0x01 << 6) ;Bypass PLL Output ( PLLBYP = 1 )
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ORL OSC_CON, #(0x01 << 5) ;Set PLL Power Down Mode ( PLLPD = 1)
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ANL OSC_CON, #~(0x01 << 3) ;XPD = 0, XTAL not powered down
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WAIT_XTAL_STABLE: ; delay necssary for external clock to stablise
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MOV R2,#0x1E ; wait about 1.5 ms ( varies with oscillator freq )
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LOOP:
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MOV R3,#0x64
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DJNZ R3, $
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DJNZ R2, LOOP
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OSC_WDT:
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ORL OSC_CON, #(0x01 << 1) ;Restart external oscillator watchdog
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MOV R0,#0x41 ;Wait for 65 cycles
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DJNZ R0, $
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;user may want to add an error counter for oscillator detection
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CHECK_EXTOSCR:
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MOV A, OSC_CON
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JNB ACC.0, OSC_WDT
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ORL OSC_CON, #(0x01 << 2) ;Select external oscillator
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MOV PLL_CON, #NDIV_XC87x_PLL_CON ; NDIV value
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MOV PLL_CON1, #NDIV_XC87x_PLL_CON1 ; NDIV Value
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MOV A, #NR_XC87x ; PDIV Value
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ORL PLL_CON1, A
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MOV A, #OD_XC87x ; KDIV Value
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ORL CMCON, A
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ANL OSC_CON, #~(0x01 << 5) ;Change to PLL Normal Mode ( PLLPD = 0)
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ORL OSC_CON, #(0x01 << 7) ;Restart the PLL watchdog ( PLLRDRES = 1)
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;user may want to add an error counter for PLL lock detection
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PLLNOTRUN:
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MOV A, PLL_CON
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JNB ACC.1, PLLNOTRUN ;PLL_Run Status
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PLLNOTLOCKED:
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MOV A, PLL_CON
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JNB ACC.0, PLLNOTLOCKED ;PLL_Lock Status
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ANL OSC_CON, #~(0x01 << 6) ;Disable bypass PLL output
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MOV PASSWD, #11000011B ;Enable Bit-Protection
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MOV SCU_PAGE,#0
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ELSEIF(XC866_CHIP <> 0 || XC864_CHIP <> 0 || XC88x_CHIP <> 0)
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MOV SCU_PAGE,#1
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ORL PLL_CON, #0x08 ; VCOBYP = 1
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ORL PLL_CON, #0x04 ; OSCDISC = 1 _ _ _ NDIV, VCOBYP, OSCDISC, RESLD, LOCK
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ANL OSC_CON, #0xF7 ; XPD = 0 power xtal
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||||
ORL OSC_CON, #0x04 ; OSCSS = 1 0, 0, 0, OSCPD, XPD, OSCSS, ORDRES, OSCR
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;all calculations are based on no wait state
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MOV R1,#0
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DelayXTAL0:
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MOV R0,#10 ; delay necssary for external clock to stablise (amplitude >= 0.4 * VDDC - refer to product data sheet)
|
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DelayXTAL: ; delay time should be adjusted according to different external osciallators
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DJNZ R1,$
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DJNZ R0,DelayXTAL
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; redetection of osc
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OSCR_NOTSET:
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MOV R0, #86
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ORL OSC_CON, #0x02 ; ORDRES = 1 ;restart oscillator run detection
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;assume no wait state, K = 2,
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;Apollo requires to wait for 256 clock cycles -> 2048 vco cycles
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;Elektra requires to wait for 342 clock cycles -> 2048 vco cycles
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;djnz = 4 cc
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DJNZ R0, $
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MOV A,OSC_CON
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JNB ACC.0, OSCR_NOTSET
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;reprogram the NDIV factor to required value
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;ORL PLL_CON, #0x08 ; VCOBYP = 1 to change N-Divider
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||||
MOV PASSWD, #0x98 ; open access to writing protected bit
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ANL PLL_CON, #0x0F
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ORL PLL_CON, #NDIV*16
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ANL PLL_CON, #0xFB ; OSCDISC = 0, reconnect oscillator to the PLL
|
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|
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;PLL lock detection
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ORL PLL_CON, #0x02 ; detect PLL lock
|
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MOV R0, #100 ; LOCK flag should be set within 200us, user need to adapt accordingly
|
||||
; assume a 10MHz XTAL for XC866/XC864 device
|
||||
; device is in prescaler mode, k = 2 therefore fsys = 5MHz
|
||||
; ## 1cclk = 1/(5MHz/3) = 600 ns
|
||||
; DJNZ requires 4 x 600ns = 2.4 us therefore 100 DJNZ -> 240us
|
||||
; for XC88x, the factor 3 (##) is changed to 4 then the calculated value is
|
||||
; 320 us based on a 10MHz XTAL
|
||||
WAIT_LOCK:
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DJNZ R0, $
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MOV A, PLL_CON
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JNB ACC.0, OSCR_NOTSET
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||||
; reconnect to PLL
|
||||
ANL PLL_CON, #0xF7 ; VCOBYP = 0
|
||||
MOV SCU_PAGE,#0
|
||||
ENDIF
|
||||
ENDIF
|
||||
|
||||
IF IDATALEN <> 0
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||||
MOV R0,#IDATALEN - 1
|
||||
CLR A
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||||
IDATALOOP: MOV @R0,A
|
||||
DJNZ R0,IDATALOOP
|
||||
ENDIF
|
||||
|
||||
IF (XC878_CHIP_16FF <> 0 || XC874_CHIP_16FF <> 0)
|
||||
MOV MEX3, #0x1F
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||||
ENDIF
|
||||
|
||||
IF (XC874_CHIP_13FF <> 0 || XC874_CHIP_16FF <> 0)
|
||||
MOV PORT_PAGE, #0x01
|
||||
ORL P3_PUDEN, #0x80
|
||||
ORL P4_PUDEN, #0xF0
|
||||
MOV PORT_PAGE, #0x00
|
||||
ENDIF
|
||||
|
||||
|
||||
|
||||
IF XDATALEN <> 0
|
||||
MOV DPTR,#XDATASTART
|
||||
MOV R7,#LOW (XDATALEN)
|
||||
IF (LOW (XDATALEN)) <> 0
|
||||
MOV R6,#(HIGH (XDATALEN)) +1
|
||||
ELSE
|
||||
MOV R6,#HIGH (XDATALEN)
|
||||
ENDIF
|
||||
CLR A
|
||||
XDATALOOP: MOVX @DPTR,A
|
||||
INC DPTR
|
||||
DJNZ R7,XDATALOOP
|
||||
DJNZ R6,XDATALOOP
|
||||
ENDIF
|
||||
|
||||
IF PPAGEENABLE <> 0
|
||||
MOV SCU_PAGE,#3
|
||||
MOV XADDRH,#PPAGE
|
||||
MOV SCU_PAGE,#0
|
||||
ENDIF
|
||||
|
||||
IF PDATALEN <> 0
|
||||
MOV R0,#LOW (PDATASTART)
|
||||
MOV R7,#LOW (PDATALEN)
|
||||
CLR A
|
||||
PDATALOOP: MOVX @R0,A
|
||||
INC R0
|
||||
DJNZ R7,PDATALOOP
|
||||
ENDIF
|
||||
|
||||
IF IBPSTACK <> 0
|
||||
EXTRN DATA (?C_IBP)
|
||||
|
||||
MOV ?C_IBP,#LOW IBPSTACKTOP
|
||||
ENDIF
|
||||
|
||||
IF XBPSTACK <> 0
|
||||
EXTRN DATA (?C_XBP)
|
||||
|
||||
MOV ?C_XBP,#HIGH XBPSTACKTOP
|
||||
MOV ?C_XBP+1,#LOW XBPSTACKTOP
|
||||
ENDIF
|
||||
|
||||
IF PBPSTACK <> 0
|
||||
EXTRN DATA (?C_PBP)
|
||||
MOV ?C_PBP,#LOW PBPSTACKTOP
|
||||
ENDIF
|
||||
|
||||
MOV SP,#?STACK-1
|
||||
|
||||
LJMP ?C_START
|
||||
|
||||
; Overwrite ?C?DPSEL address for XC866 Device
|
||||
PUBLIC ?C?DPSEL
|
||||
?C?DPSEL DATA 0A2H ; DPSEL address for Mentor M8051EW
|
||||
|
||||
IF XC864_CHIP <> 0
|
||||
; Optional ROM-table for XC864 LIN-BSL
|
||||
IF LIN_BSL <> 0
|
||||
CSEG AT 0FFCH
|
||||
DB LIN_NAC
|
||||
DB NOT(LIN_NAC)
|
||||
DB LIN_NAD
|
||||
DB NOT(LIN_NAD)
|
||||
ENDIF
|
||||
ENDIF
|
||||
|
||||
END
|
||||
Reference in New Issue
Block a user