From c3f6375140db88f0796b23d6602a095b290610db Mon Sep 17 00:00:00 2001 From: liumin Date: Tue, 21 Oct 2025 20:34:06 +0800 Subject: [PATCH] 250K-T8S --- 24c02.c | 351 +++ CAN.C | 1361 +++++++++++ CAN.H | 762 ++++++ CL2.0.asm | 4129 +++++++++++++++++++++++++++++++++ CL2.0.dav | Bin 0 -> 88725 bytes CL2.0.dpt | 3928 +++++++++++++++++++++++++++++++ CL2.0.plg | 1543 ++++++++++++ CL2.0.rtf | 1141 +++++++++ CL2.0.uvgui.Administrator | 2488 ++++++++++++++++++++ CL2.0.uvgui.liuminVir | 1896 +++++++++++++++ CL2.0.uvgui.liuminVir.bak | 1878 +++++++++++++++ CL2.0.uvgui_Administrator.bak | 2488 ++++++++++++++++++++ CL2.0.uvopt | 374 +++ CL2.0.uvproj | 445 ++++ CL2.0_uvopt.bak | 1702 ++++++++++++++ CL2.0_uvproj.bak | 410 ++++ Config.H | 248 ++ Config.H.bak | 247 ++ ExtDll.iex | 2 + IO.C | 322 +++ IO.H | 248 ++ MAIN.C | 261 +++ MAIN.H | 625 +++++ PS.C | 296 +++ PS.H | 202 ++ RTC.c | 238 ++ RTC.h | 64 + SHARED_INT.C | 223 ++ SHARED_INT.H | 122 + SSC.C | 264 +++ SSC.H | 107 + START_XC.a51 | 505 ++++ SwDriver.C | 496 ++++ SwDriver.C.bak | 893 +++++++ SwDriver.H | 122 + T2.C | 172 ++ T2.H | 104 + UART.C | 350 +++ UART.H | 127 + UART1.C | 261 +++ UART1.H | 153 ++ User.c | 508 ++++ User.c.bak | 330 +++ WDT.C | 204 ++ WDT.H | 130 ++ XC88x_FLADDR.H | 876 +++++++ XC88x_FLHANDLER.ASM | 166 ++ XC8Memory.c | 134 ++ XC8Memory.h | 72 + boot.H | 79 + boot.c | 129 + temperature.C | 189 ++ temperature.h | 89 + user.H | 164 ++ user.H.bak | 57 + 55 files changed, 34675 insertions(+) create mode 100644 24c02.c create mode 100644 CAN.C create mode 100644 CAN.H create mode 100644 CL2.0.asm create mode 100644 CL2.0.dav create mode 100644 CL2.0.dpt create mode 100644 CL2.0.plg create mode 100644 CL2.0.rtf create mode 100644 CL2.0.uvgui.Administrator create mode 100644 CL2.0.uvgui.liuminVir create mode 100644 CL2.0.uvgui.liuminVir.bak create mode 100644 CL2.0.uvgui_Administrator.bak create mode 100644 CL2.0.uvopt create mode 100644 CL2.0.uvproj create mode 100644 CL2.0_uvopt.bak create mode 100644 CL2.0_uvproj.bak create mode 100644 Config.H create mode 100644 Config.H.bak create mode 100644 ExtDll.iex create mode 100644 IO.C create mode 100644 IO.H create mode 100644 MAIN.C create mode 100644 MAIN.H create mode 100644 PS.C create mode 100644 PS.H create mode 100644 RTC.c create mode 100644 RTC.h create mode 100644 SHARED_INT.C create mode 100644 SHARED_INT.H create mode 100644 SSC.C create mode 100644 SSC.H create mode 100644 START_XC.a51 create mode 100644 SwDriver.C create mode 100644 SwDriver.C.bak create mode 100644 SwDriver.H create mode 100644 T2.C create mode 100644 T2.H create mode 100644 UART.C create mode 100644 UART.H create mode 100644 UART1.C create mode 100644 UART1.H create mode 100644 User.c create mode 100644 User.c.bak create mode 100644 WDT.C create mode 100644 WDT.H create mode 100644 XC88x_FLADDR.H create mode 100644 XC88x_FLHANDLER.ASM create mode 100644 XC8Memory.c create mode 100644 XC8Memory.h create mode 100644 boot.H create mode 100644 boot.c create mode 100644 temperature.C create mode 100644 temperature.h create mode 100644 user.H create mode 100644 user.H.bak diff --git a/24c02.c b/24c02.c new file mode 100644 index 0000000..563d1d3 --- /dev/null +++ b/24c02.c @@ -0,0 +1,351 @@ + +#include "MAIN.H" + + +#define _nop_() udelay(1); +#define somenop {_nop_();_nop_();_nop_();_nop_();_nop_();} +#define bit bool + +#define MASTER_TEST_LEN 100//连续最多发送100个字节的数据 + + + + + + +////FM25CL64指令定义 +#define FM25CL64_WREN 0x06 //使能 +#define FM25CL64_WRDI 0x04 //失能 +#define FM25CL64_RDSR 0x05 //读状态 +#define FM25CL64_WRSR 0x01 //写状态 +#define FM25CL64_READ 0x03 //读数据 +#define FM25CL64_WRITE 0x02 //写数据 + +#define EN_24C02 1 + +#define MAX_FM25CL64_LEN 8192//8k字节 + + + + + + +void iic_start(void) +{ + SDAOut(1); + _nop_(); + SCLOut(1); + somenop; + SDAOut(0); + somenop; + SCLOut(0); +} + +void iic_stop(void) +{ + SDAOut(0); + _nop_(); + SCLOut(1); + somenop; + SDAOut(1); +} + +void iic_ack(bit ackbit) +{ + if(ackbit) + SDAOut(0); + else + SDAOut(1); + somenop; + SCLOut(1); + somenop; + SCLOut(0); + SDAOut(1); + somenop; +} + +bit iic_waitack(void) +{ + SDAOut(1); + somenop; + SCLOut(1); +// sdrv_pinctrl_set_input_select(GPIO_Y3, PIN_IS_CMOS_SCHMITT); +// sdrv_gpio_set_pin_direction(GPIO_Y3, GPIO_DIR_IN); + somenop; + if(sdrv_gpio_read_pin_input_level(GPIO_Y3)) + { + SCLOut(0); + iic_stop(); + return 0; + } + else + { + SCLOut(0); + return 1; + } +} + +void iic_sendbyte(unsigned char byt) +{ + unsigned char i; + for(i=0;i<8;i++) + { + if(byt&0x80) + SDAOut(1); + else + SDAOut(0); + somenop; + SCLOut(1); + byt <<= 1; + somenop; + SCLOut(0); + } +} + +unsigned char iic_recbyte(void) +{ + unsigned char da; + unsigned char i; + for(i=0;i<8;i++) + { + SCLOut(1); +// sdrv_pinctrl_set_input_select(GPIO_Y3, PIN_IS_CMOS_SCHMITT); +// sdrv_gpio_set_pin_direction(GPIO_Y3, GPIO_DIR_IN); + somenop; + da <<= 1; + +// P1_IOCR01 = 0x0020; // load port control register 1 + if(sdrv_gpio_read_pin_input_level(GPIO_Y3)) + da |= 0x01; + SCLOut(0); + somenop; + } + return da; +} + +void wrbyte_24c02(unsigned int add,unsigned char dat) +{ +#if EN_24C02 + unsigned char eeprom_page = 0; + unsigned char eeprom_add = 0; + unsigned char device_add = 0; +//------------------------------------------------- + eeprom_page = add/256;//页 + eeprom_add = add%256; + if(eeprom_page >= 3)//目前E2一共4页。1k + { + eeprom_page = 3; + } + // Device Address 1100 0 p1 p0 R/W + device_add = (0xa0 | (eeprom_page << 1));// + +// ssdk_printf(SSDK_CRIT, "eeprom_page:0x%x\r\n", eeprom_page); +// ssdk_printf(SSDK_CRIT, "eeprom_add:0x%x\r\n", eeprom_add); +// ssdk_printf(SSDK_CRIT, "device_add:0x%x\r\n", device_add); + + iic_start(); + iic_sendbyte(device_add); + iic_waitack(); + iic_sendbyte(eeprom_add); + iic_waitack(); + iic_sendbyte(dat); + iic_waitack(); + iic_stop(); +#else + if(add >= MAX_FM25CL64_LEN)//最大地址限制 + { + printf("E2 len error!\r\n"); + } + else + { + m_tx_buf_u8[0] = FM25CL64_WREN;//写使能 + if (sdrv_spi_sync_transmit(&g_master, m_tx_buf_u8, m_rx_buf_u8,1,1)) + { + printf("E2 write Failed!\r\n"); + } + + m_tx_buf_u8[0] = FM25CL64_WRITE;//写数据 + m_tx_buf_u8[1] = (uint8_t)( add >> 8);// 高8位地址 + m_tx_buf_u8[2] = (uint8_t)( add );// + m_tx_buf_u8[3] = dat;// + + if (sdrv_spi_sync_transmit(&g_master, m_tx_buf_u8, m_rx_buf_u8,4,4)) + { + printf("E2 write Failed!\r\n"); + } + } +#endif +} + +unsigned char rdbyte_24c02(unsigned int add) +{ + +#if EN_24C02 + unsigned char eeprom_page = 0; + unsigned char eeprom_add = 0; + unsigned char device_add = 0; + unsigned char da; +//------------------------------------------------- + + eeprom_page = add/256;//页 + eeprom_add = add%256; + if(eeprom_page >= 3)//目前E2一共4页。1k + { + eeprom_page = 3; + } + + // Device Address 1100 000 R/W + iic_start(); + device_add = (0xa0 | (eeprom_page << 1));// 伪写操作 + iic_sendbyte(device_add); + iic_waitack(); + iic_sendbyte(eeprom_add); + iic_waitack(); + iic_start(); + + device_add = (0xa1 | (eeprom_page << 1));// + + ssdk_printf(SSDK_CRIT, "device_add:0x%x\r\n", device_add); + + iic_sendbyte(device_add); + iic_waitack(); + da = iic_recbyte(); + iic_ack(0); + iic_stop(); +//CAN_sendAck(add, da); + return da; +#else + if(add >= MAX_FM25CL64_LEN)//最大地址限制 + { + printf("E2 len error!\r\n"); + } + else + { + m_tx_buf_u8[0] = FM25CL64_READ;//读数据 + m_tx_buf_u8[1] = (uint8_t)( add >> 8);// 高8位地址 + m_tx_buf_u8[2] = (uint8_t)( add );// + m_tx_buf_u8[3] = 0xFF;// + + if (sdrv_spi_sync_transmit(&g_master, m_tx_buf_u8, m_rx_buf_u8,4,4)) + { + printf("E2 write Failed!\r\n"); + } + + return m_rx_buf_u8[3]; + } +#endif + return 0xFF; +} + + +#ifdef _EEROM_CRC_ +#define POLY 0x1021 +/** +* Calculating CRC-16 in 'C' +* @para addr, start of data +* @para num, length of data +* @para crc, incoming CRC +*/ +unsigned int crc16(unsigned char *addr, int num, unsigned int crc) +{ + int i; + for (; num > 0; num--) /* Step through bytes in memory */ + { + crc = crc ^ ((*addr) << 8); /* Fetch byte from memory, XOR into CRC top byte*/ + addr++; + for (i = 0; i < 8; i++) /* Prepare to rotate 8 bits */ + { + if (crc & 0x8000) /* b15 is set... */ + crc = (crc << 1) ^ POLY; /* rotate and XOR with polynomic */ + else /* b15 is clear... */ + crc <<= 1; /* just rotate */ + } /* Loop for 8 bits */ + crc &= 0xFFFF; /* Ensure CRC remains 16-bit value */ + } /* Loop until num=0 */ + return(crc); /* Return updated CRC */ +} + +//写入正确会自动写一个备份，写入有问题就不会写备份 +unsigned char wrEE_CRC_Bak(unsigned char add,unsigned char *eeData,unsigned char len,unsigned char addbak) +{ + uword crc_Res; + unsigned char index; + unsigned char flagEEwrOK; + + crc_Res = crc16(eeData, len-2, 0xffff); //计算数据的校验 + eeData[len-2] = (ubyte)(crc_Res ); + eeData[len-1] = (ubyte)(crc_Res >> 8); + + for(index=0;indexWrite the address of the MultiCAN kernel register to the +// CAN_ADL and CAN_ADH registers. +// use macro : CAN_vWriteCANAddress. +// ->Write the data to the +// CAN_DATA0/CAN_DATA1/CAN_DATA2/CAN_DATA3 registers. +// ->Write the register CAN_ADCON, including setting the valid +// bit of the data registers and setting register bit RWEN to +// 1. +// ->The valid data will be written to the MultiCAN kernel +// only once. Register bit BSY will become 1. +// ->When Register bit BSY becomes 0, the transmission is +// finished. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ulValue: +// 32-bit Data +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +// USER CODE BEGIN (WriteAMData,1) + +// USER CODE END + +void CAN_vWriteAMData(ulong ulValue) +{ + un_32bit ulData; + ulData.ulVal = ulValue; + + CAN_DATA0 = ulData.ubDB[3]; // load CAN Data Register 0 + CAN_DATA1 = ulData.ubDB[2]; // load CAN Data Register 1 + CAN_DATA2 = ulData.ubDB[1]; // load CAN Data Register 2 + CAN_DATA3 = ulData.ubDB[0]; // load CAN Data Register 3 + CAN_vWriteEN(ALL_DATA_VALID); // Writemode is Enabled +} // End of function CAN_vWriteAMData + +//**************************************************************************** +// @Function void CAN_vSetListCommand(ulong ulVal) +// +//---------------------------------------------------------------------------- +// @Description This function write's 32-bit Data to CAN_PANCTR Register. +// +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ulVal: +// 32-bit Data +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +// USER CODE BEGIN (SetListCommand,1) + +// USER CODE END + +void CAN_vSetListCommand(ulong ulVal) +{ + CAN_vWriteAMData(ulVal); // - load Panel Control Register + CAN_DATA1 = CAN_PANCTR_BUSY; + while(CAN_DATA1 & CAN_PANCTR_BUSY){ // wait until Panel has finished the + // initialisation + CAN_ADCON &= ~0x01; + } +} // End of function CAN_vSetListCommand + +//**************************************************************************** +// @Function void CAN_vGetMsgObj(ubyte ubObjNr, stCAN_SWObj *pstObj) +// +//---------------------------------------------------------------------------- +// @Description This function fills the forwarded SW message object with +// the content of the chosen HW message object. +// +// The structure of the SW message object is defined in the +// header file CAN.H (see stCAN_SWObj). +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object to be read (0-31) +// @Parameters *pstObj: +// Pointer on a message object to be filled by this function +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +// USER CODE BEGIN (GetMsgObj,1) + +// USER CODE END + +void CAN_vGetMsgObj(ubyte ubObjNr, stCAN_SWObj *pstObj) +{ +ubyte ubTemp; + + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + + //----- get DLC ------------------------------------------------------- + + CAN_vWriteCANAddress(CAN_MOFCR(ubObjNr)); + CAN_vReadEN(); // Readmode is Enabled + + pstObj->ubMOdlc = CAN_DATA3;//MOFCRn[31-24] DLC + + //----- get MODATAL --------------------------------------------------- + CAN_vWriteCANAddress(CAN_MODATAL(ubObjNr)); + + CAN_vReadEN(); // Readmode is Enabled + pstObj->ulDATAL.ubDB[3] = CAN_DATA0; // Read CAN Data Register 0 + pstObj->ulDATAL.ubDB[2] = CAN_DATA1; // Read CAN Data Register 1 + pstObj->ulDATAL.ubDB[1] = CAN_DATA2; // Read CAN Data Register 2 + pstObj->ulDATAL.ubDB[0] = CAN_DATA3; // Read CAN Data Register 3 + + // CAN Address pointing to the CAN_MODATAH + CAN_ADCON = ADR_INC; + + //----- get MODATAH --------------------------------------------------- + + CAN_vReadEN(); // Readmode is Enabled + pstObj->ulDATAH.ubDB[3] = CAN_DATA0; // Read CAN Data Register 0 + pstObj->ulDATAH.ubDB[2] = CAN_DATA1; // Read CAN Data Register 1 + pstObj->ulDATAH.ubDB[1] = CAN_DATA2; // Read CAN Data Register 2 + pstObj->ulDATAH.ubDB[0] = CAN_DATA3; // Read CAN Data Register 3 + + //----- get DIR ------------------------------------------------------- + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); + CAN_vReadEN(); // Readmode is Enabled + + if(CAN_DATA1 & 0x08) // if transmit object (MOSTAT_DIR) + { + pstObj->ubMOcfg = (pstObj->ubMOcfg | 0x08); // set DIR + } + + //----- get XID - Extended Identifier --------------------------------- + + // CAN Address pointing to the CAN_MOARn + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + CAN_vReadEN(); // ReadMode is Enabled + + if(CAN_DATA3 & 0x20) // if extended identifier + { + + //----- get XID - Extended Identifier (MOARn) ------------------------ + pstObj->ulID.ubDB[3] = CAN_DATA0; // MOARn[7-0] + pstObj->ulID.ubDB[2] = CAN_DATA1; // MOARn[15-8] + pstObj->ulID.ubDB[1] = CAN_DATA2; // MOARn[23-16] + pstObj->ulID.ubDB[0] = (CAN_DATA3 & 0x1f); // MOARn[31-24] + + // CAN Address pointing to the CAN_MODATAH + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MODATAL + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MOAMR + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + CAN_vReadEN(); // ReadMode is Enabled + + //----- get XID - Extended Acceptance Mask (MOAMRn) ----------------- + pstObj->ulMask.ubDB[3] = CAN_DATA0; // MOAMRn[7-0] + pstObj->ulMask.ubDB[2] = CAN_DATA1; // MOAMRn[15-8] + pstObj->ulMask.ubDB[1] = CAN_DATA2; // MOAMRn[23-16] + pstObj->ulMask.ubDB[0] = (CAN_DATA3 & 0x1f); // MOAMRn[31-24] + + pstObj->ubMOcfg = (pstObj->ubMOcfg | 0x04); // set IDE 29-bit + } + else // standard identifier + { + //----- get - ID - Standard Identifier (MOARn) --------------------- + pstObj->ulID.ubDB[3] = (CAN_DATA2 & 0xFC) >> 2; // MOARn[23-16] + pstObj->ulID.ubDB[2] = (CAN_DATA3 & 0x1f); // MOARn[31-24] + pstObj->ulID.ubDB[1] = 0x00; // MOARn[15-8] + pstObj->ulID.ubDB[0] = 0x00; // MOARn[15-8] + + ubTemp = 0; + ubTemp = ((pstObj->ulID.ubDB[2]) & 0x03) << 6; + pstObj->ulID.ubDB[2] = (pstObj->ulID.ubDB[2] >> 2); + pstObj->ulID.ubDB[3] = (pstObj->ulID.ubDB[3] + ubTemp); + + // CAN Address pointing to the CAN_MODATAH + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MODATAL + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MOAMR + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + CAN_vReadEN(); // ReadMode is Enabled + + //----- get - ID - Acceptance Mask (MOAMRn) ----------------------- + + pstObj->ulMask.ubDB[3] = (CAN_DATA2 & 0xFC) >> 2; // MOAMRn[23-16] + pstObj->ulMask.ubDB[2] = (CAN_DATA3 & 0x1f); // MOAMRn[31-24] + pstObj->ulMask.ubDB[1] = 0x00; // MOAMRn[15-8] + pstObj->ulMask.ubDB[0] = 0x00; // MOAMRn[15-8] + + ubTemp = 0; + ubTemp = ((pstObj->ulMask.ubDB[2]) & 0x03) << 6; + pstObj->ulMask.ubDB[2] = (pstObj->ulMask.ubDB[2] >> 2); + pstObj->ulMask.ubDB[3] = (pstObj->ulMask.ubDB[3] + ubTemp); + } + + //----- get CFCVAL - CAN Frame Counter Value (MOIPRn) ----------------- + + CAN_vWriteCANAddress(CAN_MOIPR(ubObjNr)); + CAN_vReadEN(); // Readmode is Enabled + + pstObj->uwCounter.ubDB[1] = CAN_DATA2; // MOIPRn[16-23] + pstObj->uwCounter.ubDB[0] = CAN_DATA3; // MOIPRn[31-24] + + CAN_popAMRegs(); // POP the CAN Access Mediator Register +} // End of function CAN_vGetMsgObj + +//**************************************************************************** +// @Function ubyte CAN_ubRequestMsgObj(ubyte ubObjNr) +// +//---------------------------------------------------------------------------- +// @Description If a TRANSMIT OBJECT is to be reconfigured it must first be +// accessed. The access to the transmit object is exclusive. +// This function checks whether the choosen message object is +// still executing a transmit request, or if the object can be +// accessed exclusively. +// After the message object is reserved, it can be +// reconfigured by using the function CAN_vConfigMsgObj or +// CAN_vLoadData. +// Both functions enable access to the object for the CAN +// controller. +// By calling the function CAN_vTransmit transfering of data +// is started. +// +//---------------------------------------------------------------------------- +// @Returnvalue 0 message object is busy (a transfer is active), else 1 +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object (0-31) +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +// USER CODE BEGIN (RequestMsgObj,1) + +// USER CODE END + +ubyte CAN_ubRequestMsgObj(ubyte ubObjNr) +{ +ubyte ubReturn = 0; + + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); + CAN_vReadEN(); // Readmode is Enabled + + if((CAN_DATA1 & 0x01) == 0) // if reset TXRQ + { + CAN_vWriteCANData(0x00000020); // reset MSGVAL + ubReturn = 1; + } + CAN_popAMRegs(); // POP the CAN Access Mediator Register + +return(ubReturn); +} // End of function CAN_ubRequestMsgObj + +//**************************************************************************** +// @Function ubyte CAN_ubNewData(ubyte ubObjNr) +// +//---------------------------------------------------------------------------- +// @Description This function checks whether the selected RECEIVE OBJECT +// has received a new message. If so the function returns the +// value '1'. +// +//---------------------------------------------------------------------------- +// @Returnvalue 1 the message object has received a new message, else 0 +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object (0-31) +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +// USER CODE BEGIN (NewData,1) + +// USER CODE END + +ubyte CAN_ubNewData(ubyte ubObjNr) +{ +ubyte ubReturn = 0; + + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); + CAN_vReadEN(); // Readmode is Enabled + if(CAN_DATA0 & 0x08) // if NEWDAT + { + ubReturn = 1; + } + CAN_popAMRegs(); // POP the CAN Access Mediator Register + +return(ubReturn); +} // End of function CAN_ubNewData + +//**************************************************************************** +// @Function void CAN_vTransmit(ubyte ubObjNr) +// +//---------------------------------------------------------------------------- +// @Description This function triggers the CAN controller to send the +// selected message. +// If the selected message object is a TRANSMIT OBJECT then +// this function triggers the sending of a data frame. If +// however the selected message object is a RECEIVE OBJECT +// this function triggers the sending of a remote frame. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object (0-31) +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +// USER CODE BEGIN (Transmit,1) + +// USER CODE END + +void CAN_vTransmit(ubyte ubObjNr) +{ + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); //Addressing CAN_MOCTR register + CAN_vWriteCANData(0x07200000); // set TXRQ,TXEN0,TXEN1,MSGVAL + + CAN_popAMRegs(); // POP the CAN Access Mediator Register + +} // End of function CAN_vTransmit + +//**************************************************************************** +// @Function void CAN_vLoadData(ubyte ubObjNr, ulong *ulpubData) +// +//---------------------------------------------------------------------------- +// @Description If a hardware TRANSMIT OBJECT has to be loaded with data +// but not with a new identifier, this function may be used +// instead of the function CAN_vConfigMsgObj. The message +// object should be accessed by calling the function +// CAN_ubRequestMsgObj before calling this function. This +// prevents the CAN controller from working with invalid data. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object to be configured (0-31) +// @Parameters *ulpubData: +// Pointer on a data buffer +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +// USER CODE BEGIN (LoadData,1) + +// USER CODE END + +void CAN_vLoadData(ubyte ubObjNr, ulong *ulpubData) +{ + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); // Addressing CAN_MOCTRn register + CAN_vWriteCANData(0x00080000); // Set NEWDATA + + // CAN Address pointing to the CAN_MOARn + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MODATAHn + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + // CAN Address pointing to the CAN_MODATALn + CAN_ADCON = ADR_DEC; // Auto Decrement the current address(-1) + + CAN_vWriteCANData(*ulpubData); // Loading CAN_MODATALn + + // CAN Address pointing to the CAN_MODATAH + CAN_ADCON = ADR_INC; // Auto Increment the current address(+1) + + ulpubData++; + + CAN_vWriteCANData(*ulpubData); // Loading CAN_MODATAHn + + // CAN Address pointing to the CAN_MOARn + CAN_ADCON = ADR_INC; // Auto Increment the current address(+1) + + // CAN Address pointing to the CAN_MOCTRn + CAN_ADCON = ADR_INC; // Auto Increment the current address(+1) + + CAN_vWriteCANData(0x00200040); // reset RTSEL, set MSGVAL + + CAN_popAMRegs(); // POP the CAN Access Mediator Register + +} // End of function CAN_vLoadData + +//**************************************************************************** +// @Function void CAN_vReleaseObj(ubyte ubObjNr) +// +//---------------------------------------------------------------------------- +// @Description This function resets the NEWDAT flag of the selected +// RECEIVE OBJECT, so that the CAN controller have access to +// it. This function must be called if the function +// CAN_ubNewData detects, that new data are present in the +// message object and the actual data have been read by +// calling the function CAN_vGetMsgObj. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ubObjNr: +// Number of the message object (0-31) +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +// USER CODE BEGIN (ReleaseObj,1) + +// USER CODE END + +void CAN_vReleaseObj(ubyte ubObjNr) +{ + + CAN_pushAMRegs(); // PUSH the CAN Access Mediator Register + CAN_vWriteCANAddress(CAN_MOCTR(ubObjNr)); // Addressing CAN_MOCTRn register + CAN_vWriteCANData(0x00000008); // reset NEWDAT + + CAN_popAMRegs(); // POP the CAN Access Mediator Register +} // End of function CAN_vReleaseObj + + +// USER CODE BEGIN (CAN_General,10) + +// USER CODE END + diff --git a/CAN.H b/CAN.H new file mode 100644 index 0000000..b9cc6f6 --- /dev/null +++ b/CAN.H @@ -0,0 +1,762 @@ +//**************************************************************************** +// @Module MultiCAN Controller +// @Filename CAN.H +// @Project CL2.0.dav +//---------------------------------------------------------------------------- +// @Controller Infineon XC886CLM-8FF +// +// @Compiler Keil +// +// @Codegenerator 1.3 +// +// @Description: This file contains all function prototypes and macros for +// the CAN module. +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 20:45:35 +// +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,1) + +// USER CODE END + + + +#ifndef _CAN_H_ +#define _CAN_H_ + +//**************************************************************************** +// @Project Includes +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,2) + +// USER CODE END + + +//**************************************************************************** +// @Macros +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,3) + +// USER CODE END + + +//**************************************************************************** +// @Defines +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,4) + +// USER CODE END + + +//**************************************************************************** +// @Typedefs +//**************************************************************************** + + +//**************************************************************************** +// @Declaration of SFRs +//**************************************************************************** + + +#define CAN_LIST0 0x0040 +#define CAN_LIST1 0x0041 +#define CAN_LIST2 0x0042 +#define CAN_LIST3 0x0043 +#define CAN_LIST4 0x0044 +#define CAN_LIST5 0x0045 +#define CAN_LIST6 0x0046 +#define CAN_LIST7 0x0047 +#define CAN_MCR 0x0072 +#define CAN_MITR 0x0073 +#define CAN_MOAMR0 0x0403 +#define CAN_MOAMR1 0x040b +#define CAN_MOAMR10 0x0453 +#define CAN_MOAMR11 0x045B +#define CAN_MOAMR12 0x0463 +#define CAN_MOAMR13 0x046B +#define CAN_MOAMR14 0x0473 +#define CAN_MOAMR15 0x047B +#define CAN_MOAMR16 0x0483 +#define CAN_MOAMR17 0x048B +#define CAN_MOAMR18 0x0493 +#define CAN_MOAMR19 0x049B +#define CAN_MOAMR2 0x0413 +#define CAN_MOAMR20 0x04A3 +#define CAN_MOAMR21 0x04AB +#define CAN_MOAMR22 0x04B3 +#define CAN_MOAMR23 0x04BB +#define CAN_MOAMR24 0x04C3 +#define CAN_MOAMR25 0x04CB +#define CAN_MOAMR26 0x04D3 +#define CAN_MOAMR27 0x04DB +#define CAN_MOAMR28 0x04E3 +#define CAN_MOAMR29 0x04EB +#define CAN_MOAMR3 0x041B +#define CAN_MOAMR30 0x04F3 +#define CAN_MOAMR31 0x04FB +#define CAN_MOAMR4 0x0423 +#define CAN_MOAMR5 0x042B +#define CAN_MOAMR6 0x0433 +#define CAN_MOAMR7 0x043B +#define CAN_MOAMR8 0x0443 +#define CAN_MOAMR9 0x044B +#define CAN_MOAR0 0x0406 +#define CAN_MOAR1 0x040e +#define CAN_MOAR10 0x0456 +#define CAN_MOAR11 0x045E +#define CAN_MOAR12 0x0466 +#define CAN_MOAR13 0x046E +#define CAN_MOAR14 0x0476 +#define CAN_MOAR15 0x047E +#define CAN_MOAR16 0x0486 +#define CAN_MOAR17 0x048E +#define CAN_MOAR18 0x0496 +#define CAN_MOAR19 0x049E +#define CAN_MOAR2 0x0416 +#define CAN_MOAR20 0x04A6 +#define CAN_MOAR21 0x04AE +#define CAN_MOAR22 0x04B6 +#define CAN_MOAR23 0x04BE +#define CAN_MOAR24 0x04C6 +#define CAN_MOAR25 0x04CE +#define CAN_MOAR26 0x04D6 +#define CAN_MOAR27 0x04DE +#define CAN_MOAR28 0x04E6 +#define CAN_MOAR29 0x04EE +#define CAN_MOAR3 0x041E +#define CAN_MOAR30 0x04F6 +#define CAN_MOAR31 0x04FE +#define CAN_MOAR4 0x0426 +#define CAN_MOAR5 0x042E +#define CAN_MOAR6 0x0436 +#define CAN_MOAR7 0x043E +#define CAN_MOAR8 0x0446 +#define CAN_MOAR9 0x044E +#define CAN_MOCTR0 0x0407 +#define CAN_MOCTR1 0x040f +#define CAN_MOCTR10 0x0457 +#define CAN_MOCTR11 0x045F +#define CAN_MOCTR12 0x0467 +#define CAN_MOCTR13 0x046F +#define CAN_MOCTR14 0x0477 +#define CAN_MOCTR15 0x047F +#define CAN_MOCTR16 0x0487 +#define CAN_MOCTR17 0x048F +#define CAN_MOCTR18 0x0497 +#define CAN_MOCTR19 0x049F +#define CAN_MOCTR2 0x0417 +#define CAN_MOCTR20 0x04A7 +#define CAN_MOCTR21 0x04AF +#define CAN_MOCTR22 0x04B7 +#define CAN_MOCTR23 0x04BF +#define CAN_MOCTR24 0x04C7 +#define CAN_MOCTR25 0x04CF +#define CAN_MOCTR26 0x04D7 +#define CAN_MOCTR27 0x04DF +#define CAN_MOCTR28 0x04E7 +#define CAN_MOCTR29 0x04EF +#define CAN_MOCTR3 0x041F +#define CAN_MOCTR30 0x04F7 +#define CAN_MOCTR31 0x04FF +#define CAN_MOCTR4 0x0427 +#define CAN_MOCTR5 0x042F +#define CAN_MOCTR6 0x0437 +#define CAN_MOCTR7 0x043F +#define CAN_MOCTR8 0x0447 +#define CAN_MOCTR9 0x044F +#define CAN_MODATAH0 0x0405 +#define CAN_MODATAH1 0x040d +#define CAN_MODATAH10 0x0455 +#define CAN_MODATAH11 0x045D +#define CAN_MODATAH12 0x0465 +#define CAN_MODATAH13 0x046D +#define CAN_MODATAH14 0x0475 +#define CAN_MODATAH15 0x047D +#define CAN_MODATAH16 0x0485 +#define CAN_MODATAH17 0x048D +#define CAN_MODATAH18 0x0495 +#define CAN_MODATAH19 0x049D +#define CAN_MODATAH2 0x0415 +#define CAN_MODATAH20 0x04A5 +#define CAN_MODATAH21 0x04AD +#define CAN_MODATAH22 0x04B5 +#define CAN_MODATAH23 0x04BD +#define CAN_MODATAH24 0x04C5 +#define CAN_MODATAH25 0x04CD +#define CAN_MODATAH26 0x04D5 +#define CAN_MODATAH27 0x04DD +#define CAN_MODATAH28 0x04E5 +#define CAN_MODATAH29 0x04ED +#define CAN_MODATAH3 0x041D +#define CAN_MODATAH30 0x04F5 +#define CAN_MODATAH31 0x04FD +#define CAN_MODATAH4 0x0425 +#define CAN_MODATAH5 0x042D +#define CAN_MODATAH6 0x0435 +#define CAN_MODATAH7 0x043D +#define CAN_MODATAH8 0x0445 +#define CAN_MODATAH9 0x044D +#define CAN_MODATAL0 0x0404 +#define CAN_MODATAL1 0x040c +#define CAN_MODATAL10 0x0454 +#define CAN_MODATAL11 0x045C +#define CAN_MODATAL12 0x0464 +#define CAN_MODATAL13 0x046C +#define CAN_MODATAL14 0x0474 +#define CAN_MODATAL15 0x047C +#define CAN_MODATAL16 0x0484 +#define CAN_MODATAL17 0x048C +#define CAN_MODATAL18 0x0494 +#define CAN_MODATAL19 0x049C +#define CAN_MODATAL2 0x0414 +#define CAN_MODATAL20 0x04A4 +#define CAN_MODATAL21 0x04AC +#define CAN_MODATAL22 0x04B4 +#define CAN_MODATAL23 0x04BC +#define CAN_MODATAL24 0x04C4 +#define CAN_MODATAL25 0x04CC +#define CAN_MODATAL26 0x04D4 +#define CAN_MODATAL27 0x04DC +#define CAN_MODATAL28 0x04E4 +#define CAN_MODATAL29 0x04EC +#define CAN_MODATAL3 0x041C +#define CAN_MODATAL30 0x04F4 +#define CAN_MODATAL31 0x04FC +#define CAN_MODATAL4 0x0424 +#define CAN_MODATAL5 0x042C +#define CAN_MODATAL6 0x0434 +#define CAN_MODATAL7 0x043C +#define CAN_MODATAL8 0x0444 +#define CAN_MODATAL9 0x044C +#define CAN_MOFCR0 0x0400 +#define CAN_MOFCR1 0x0408 +#define CAN_MOFCR10 0x0450 +#define CAN_MOFCR11 0x0458 +#define CAN_MOFCR12 0x0460 +#define CAN_MOFCR13 0x0468 +#define CAN_MOFCR14 0x0470 +#define CAN_MOFCR15 0x0478 +#define CAN_MOFCR16 0x0480 +#define CAN_MOFCR17 0x0488 +#define CAN_MOFCR18 0x0490 +#define CAN_MOFCR19 0x0498 +#define CAN_MOFCR2 0x0410 +#define CAN_MOFCR20 0x04A0 +#define CAN_MOFCR21 0x04A8 +#define CAN_MOFCR22 0x04B0 +#define CAN_MOFCR23 0x04B8 +#define CAN_MOFCR24 0x04C0 +#define CAN_MOFCR25 0x04C8 +#define CAN_MOFCR26 0x04D0 +#define CAN_MOFCR27 0x04D8 +#define CAN_MOFCR28 0x04E0 +#define CAN_MOFCR29 0x04E8 +#define CAN_MOFCR3 0x0418 +#define CAN_MOFCR30 0x04F0 +#define CAN_MOFCR31 0x04F8 +#define CAN_MOFCR4 0x0420 +#define CAN_MOFCR5 0x0428 +#define CAN_MOFCR6 0x0430 +#define CAN_MOFCR7 0x0438 +#define CAN_MOFCR8 0x0440 +#define CAN_MOFCR9 0x0448 +#define CAN_MOFGPR0 0x0401 +#define CAN_MOFGPR1 0x0409 +#define CAN_MOFGPR10 0x0451 +#define CAN_MOFGPR11 0x0459 +#define CAN_MOFGPR12 0x0461 +#define CAN_MOFGPR13 0x0469 +#define CAN_MOFGPR14 0x0471 +#define CAN_MOFGPR15 0x0479 +#define CAN_MOFGPR16 0x0481 +#define CAN_MOFGPR17 0x0489 +#define CAN_MOFGPR18 0x0491 +#define CAN_MOFGPR19 0x0499 +#define CAN_MOFGPR2 0x0411 +#define CAN_MOFGPR20 0x04A1 +#define CAN_MOFGPR21 0x04A9 +#define CAN_MOFGPR22 0x04B1 +#define CAN_MOFGPR23 0x04B9 +#define CAN_MOFGPR24 0x04C1 +#define CAN_MOFGPR25 0x04C9 +#define CAN_MOFGPR26 0x04D1 +#define CAN_MOFGPR27 0x04D9 +#define CAN_MOFGPR28 0x04E1 +#define CAN_MOFGPR29 0x04E9 +#define CAN_MOFGPR3 0x0419 +#define CAN_MOFGPR30 0x04F1 +#define CAN_MOFGPR31 0x04F9 +#define CAN_MOFGPR4 0x0421 +#define CAN_MOFGPR5 0x0429 +#define CAN_MOFGPR6 0x0431 +#define CAN_MOFGPR7 0x0439 +#define CAN_MOFGPR8 0x0441 +#define CAN_MOFGPR9 0x0449 +#define CAN_MOIPR0 0x0402 +#define CAN_MOIPR1 0x040a +#define CAN_MOIPR10 0x0452 +#define CAN_MOIPR11 0x045A +#define CAN_MOIPR12 0x0462 +#define CAN_MOIPR13 0x046A +#define CAN_MOIPR14 0x0472 +#define CAN_MOIPR15 0x047A +#define CAN_MOIPR16 0x0482 +#define CAN_MOIPR17 0x048A +#define CAN_MOIPR18 0x0492 +#define CAN_MOIPR19 0x049A +#define CAN_MOIPR2 0x0412 +#define CAN_MOIPR20 0x04A2 +#define CAN_MOIPR21 0x04AA +#define CAN_MOIPR22 0x04B2 +#define CAN_MOIPR23 0x04BA +#define CAN_MOIPR24 0x04C2 +#define CAN_MOIPR25 0x04CA +#define CAN_MOIPR26 0x04D2 +#define CAN_MOIPR27 0x04DA +#define CAN_MOIPR28 0x04E2 +#define CAN_MOIPR29 0x04EA +#define CAN_MOIPR3 0x041a +#define CAN_MOIPR30 0x04F2 +#define CAN_MOIPR31 0x04FA +#define CAN_MOIPR4 0x0422 +#define CAN_MOIPR5 0x042a +#define CAN_MOIPR6 0x0432 +#define CAN_MOIPR7 0x043A +#define CAN_MOIPR8 0x0442 +#define CAN_MOIPR9 0x044A +#define CAN_MSID0 0x0050 +#define CAN_MSID1 0x0051 +#define CAN_MSIMASK 0x0070 +#define CAN_MSPND0 0x0048 +#define CAN_MSPND1 0x0049 +#define CAN_NBTR0 0x0084 +#define CAN_NBTR1 0x00C4 +#define CAN_NCR0 0x0080 +#define CAN_NCR1 0x00C0 +#define CAN_NECNT0 0x0085 +#define CAN_NECNT1 0x00C5 +#define CAN_NFCR0 0x0086 +#define CAN_NFCR1 0x00C6 +#define CAN_NIPR0 0x0082 +#define CAN_NIPR1 0x00C2 +#define CAN_NPCR0 0x0083 +#define CAN_NPCR1 0x00C3 +#define CAN_NSR0 0x0081 +#define CAN_NSR1 0x00C1 +#define CAN_PANCTR 0x0071 + + + //------------------------------------------------------------ + //-- CAN Message Object x ------------------------------------ + //------------------------------------------------------------ + //------------------------------------------------------------ + // Note: DAvE Ignores Lower Address Lines A[1:0] + // + // MO = Message Ojbect; n = 31-0 + // MO base = 400H + n * 20H + // + // Message Object 0 Address Map... + // __________ + // |MOCTRn | -> 0x0407 + // |----------| + // |MOARn | -> 0x0406 + // |----------| + // |MODATAHn | -> 0x0405 + // |----------| + // |MODATALn | -> 0x0404 + // |----------| + // |MOAMRn | -> 0x0403 + // |----------| + // |MOOIPRn | -> 0x0402 + // |----------| + // |MOFGPRn | -> 0x0401 + // |----------| + // |MOFCRn | -> 0x0400 + // |__________| + // + //------------------------------------------------------------ + //------------------------------------------------------------ + //-- CAN Message Object x ------------------------------------ + //------------------------------------------------------------ + #define MO_BASE 0x0400 + + //------------------------------------------------------------ + //-- CAN Message Object 0-31 ------------------------------------ + //------------------------------------------------------------ + + // Message Object Nr Function Control Register + #define CAN_MOFCR(Nr) (MO_BASE + (Nr * 8)) + + // Message Object Nr FIFO/Gateway Pointer Register + #define CAN_MOFGPR(Nr) (MO_BASE + 01 + (Nr * 8)) + + // Message Object Nr Interrupt Pointer Register + #define CAN_MOIPR(Nr) (MO_BASE + 02 + (Nr * 8)) + + // Message Object Nr Acceptance Mask Register + #define CAN_MOAMR(Nr) (MO_BASE + 03 + (Nr * 8)) + + // Message Object Nr Data Register Low + #define CAN_MODATAL(Nr) (MO_BASE + 04 + (Nr * 8)) + + // Message Object Nr Data Register High + #define CAN_MODATAH(Nr) (MO_BASE + 05 + (Nr * 8)) + + // Message Object Nr Arbitration Register + #define CAN_MOAR(Nr) (MO_BASE + 06 + (Nr * 8)) + + // Message Object Nr Control Register + #define CAN_MOCTR(Nr) (MO_BASE + 07 + (Nr * 8)) + + //------------------------------------------------------------ + //-- CAN Node Registers 0-1 ---------------------------------- + //------------------------------------------------------------ + + // Node x Error Counter Register + #define CAN_NECNT(Nr) (CAN_NECNT0 + (Nr * 0x40)) + + //**************************************************************************** + // @Defines + //**************************************************************************** + + // Panel Busy Flag +#define CAN_PANCTR_BUSY 0x01 + +// Message Object Status Register +#define MOSTAT_RXPND 0x01 +#define MOSTAT_TXPND 0x02 +#define MOSTAT_NEWDAT 0x08 +#define MOSTAT_MSGLST 0x10 +#define MOSTAT_RST_MNR 0x19 + + // MultiCAN Access Mediator Registers + + // ADCON Read is enabled +#define ADCON_R 0x00 + + // ADCON Write is enabled +#define ADCON_W 0x01 + + // Data Transmission Busy +#define CAN_ADCON_BSY 0x02 + + // Auto increment the current address(+1) +#define ADR_INC 0x04 + + // Auto increment the current address(+8) +#define ADR_INC8 0x0C + + // Auto decrement the current address(-1) +#define ADR_DEC 0x08 + + // CAN Data 0 Valid +#define D0_VALID 0x10 + + // CAN Data 1 Valid +#define D1_VALID 0x20 + + // CAN Data 2 Valid +#define D2_VALID 0x40 + + // CAN Data 3 Valid +#define D3_VALID 0x80 + + // CAN Data 0-3 Valid +#define ALL_DATA_VALID 0xF0 + + + /// ------------------------------------------------------------------------- + /// @Definition of a union for the CAN data structure + /// ------------------------------------------------------------------------- + + // The following data type used for converting 32-bit data to Four 8-bit data types + // and vica-versa. This is used for accessing MultiCAN Kernel to Access Mediator + // Registers. The data type has the following fields: + // + // 31 24 23 16 15 8 7 0 + // |------------------------------------------------| + // | DB0 | DB1 | DB2 | DB3 | + // |------------------------------------------------| + // | | + // | <------------------ ulVal -------------------> | + // + +typedef union ulValue { + ulong ulVal; // 32-bit Data Type + ubyte ubDB[4]; // Four 8-bit Data Type +} un_32bit; + + + // The following data type used for converting 16-bit data to Two 8-bit data types + // and vica-versa. The data type has the following fields: + // + // 15 8 7 0 + // |----------------------| + // | DB0 | DB1 | + // |----------------------| + // | | + // | <----- uwVal ------> | + // + +typedef union uwValue { + uword uwVal; // 16-bit Data Type + ubyte ubDB[2]; // Two 8-bit Data Type +} un_16bit; + + /// ------------------------------------------------------------------------- + /// @Definition of a structure for the CAN data + /// ------------------------------------------------------------------------- + + // The following data type serves as a software message object. Each access to + // a hardware message object has to be made by forward a pointer to a software + // message object (MCAN_SWObj). The data type has the following fields: + // + // ubMOdlc: + // this byte has the same structure as the message configuration register of a + // MOFCRn message object. It contains the ' Data Lenght Code (DLC)' + // + // 7 6 5 4 3 2 1 0 + // |------------------------------------------------| + // | 0 | DLC | + // |------------------------------------------------| + // + // ubMOcfg: + // this byte contains the 'Extended Identifier (IDE)', the 'Message Direction (DIR)', + // the 'Node Select (NODE)' And the 'Remote Monitoring Mode (RMM)' + // + // + // 7 6 5 4 3 2 1 0 + // |------------------------------------------------| + // | | DIR | XTD | NODE | RMM | + // |------------------------------------------------| + // + // ulID: + // this field is four bytes long and contains either the 11-bit identifier + // or the 29-bit identifier + // + // ulMask: + // this field is four bytes long and contains either the 11-bit mask + // or the 29-bit mask + // + // ulDATAL: + // contains the lowest 4 bytes of message object + // + // ulDATAH: + // contains the upper 4 bytes of message object + // + // uwCounter: + // this field is two bytes long and contains the counter value + // + +typedef struct +{ + ubyte ubMOdlc; // message object function control register[31-24] + ubyte ubMOcfg; // message object configuration + un_32bit ulID; // standard (11-bit)/extended (29-bit) identifier + un_32bit ulMask; // standard (11-bit)/extended (29-bit) mask + un_32bit ulDATAL; // 32-bit data Lower bytes + un_32bit ulDATAH; // 32-bit data Higher bytes + un_16bit uwCounter; // frame counter(MOIPRn[31-16] +}stCAN_SWObj; + + +// USER CODE BEGIN (CAN_Header,5) + +// USER CODE END + + +//**************************************************************************** +// @Imported Global Variables +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,6) + +// USER CODE END + + +//**************************************************************************** +// @Global Variables +//**************************************************************************** + +// USER CODE BEGIN (CAN_Header,7) + +// USER CODE END + + +//**************************************************************************** +// @Prototypes Of Global Functions +//**************************************************************************** + +void CAN_vInit(void); +void CAN_vGetMsgObj(ubyte ubObjNr, stCAN_SWObj *pstObj); +ubyte CAN_ubRequestMsgObj(ubyte ubObjNr); +ubyte CAN_ubNewData(ubyte ubObjNr); +void CAN_vTransmit(ubyte ubObjNr); +void CAN_vLoadData(ubyte ubObjNr, ulong *ulpubData); +void CAN_vReleaseObj(ubyte ubObjNr); +void CAN_vWriteAMData(ulong ulValue); +void CAN_vSetListCommand(ulong ulVal); + + +// USER CODE BEGIN (CAN_Header,8) + +// USER CODE END + + +//**************************************************************************** +// @Macro CAN_vReadEN() +// +//---------------------------------------------------------------------------- +// @Description This macro enables Read mode (CAN Address/Data Control +// Register). +// +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters None +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +#define CAN_vReadEN() CAN_ADCON = 0x00; while(CAN_ADCON & CAN_ADCON_BSY) + +//**************************************************************************** +// @Macro CAN_vWriteEN(ubyte ubDCtrl) +// +//---------------------------------------------------------------------------- +// @Description This macro enables Write mode (CAN Address/Data Control +// Register). +// +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ubDCtrl: +// Data Control Flags +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +#define CAN_vWriteEN(ubDCtrl) CAN_ADCON = ((ubDCtrl) | ADCON_W); while(CAN_ADCON & CAN_ADCON_BSY) + +//**************************************************************************** +// @Macro CAN_vWriteCANAddress(uword uwAdr) +// +//---------------------------------------------------------------------------- +// @Description This macro writes 16-bit CAN address to CAN Address +// Register Low and High respectively. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters uwAdr: +// 16-bit Address +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +#define CAN_vWriteCANAddress(uwAdr) CAN_ADLH = uwAdr + +//**************************************************************************** +// @Macro CAN_vWriteCANData(ulong ulValue) +// +//---------------------------------------------------------------------------- +// @Description This macro writes 32-bit Data to CAN Data Register's +// 0-3respectively. +// Note: +// Write Process : +// ->Write the address of the MultiCAN kernel register to the +// CAN_ADL and CAN_ADH registers. +// use macro : CAN_vWriteCANAddress. +// ->Write the data to the +// CAN_DATA0/CAN_DATA1/CAN_DATA2/CAN_DATA3 registers. +// ->Write the register CAN_ADCON, including setting the valid +// bit of the data registers and setting register bit RWEN to +// 1. +// ->The valid data will be written to the MultiCAN kernel +// only once. Register bit BSY will become 1. +// ->When Register bit BSY becomes 0, the transmission is +// finished. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters ulValue: +// 32-bit Data +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +#define CAN_vWriteCANData(ulValue) CAN_DATA01 = (ulValue & 0xFFFF); \ + CAN_DATA23 = (ulValue >> 16) & 0xFFFF; \ + CAN_vWriteEN(ALL_DATA_VALID) + +//**************************************************************************** +// @Macro CAN_pushAMRegs/_popAMRegs() +// +//---------------------------------------------------------------------------- +// @Description The macro CAN_pushAMRegs() PUSH the CAN Access Mediator +// Registers. +// The macro CAN_popAMRegs() POP the CAN Access Mediator +// Registers. +// Note: +// This macro is used in CAN ISR/Function's to protect Access +// Mediator Register +// MultiCAN Access Mediator Registers: +// ADL, ADH, DATA0, DATA1, DATA2, DATA3. +// +// The _push_/_pop_ routine inserts a PUSH/POP instruction +// into the program saving the contents of the Special +// Function Register(sfr) on the Stack. +// +//---------------------------------------------------------------------------- +// @Returnvalue None +// +//---------------------------------------------------------------------------- +// @Parameters None +// +//---------------------------------------------------------------------------- +// @Date 2025/1/18 +// +//**************************************************************************** + +#define CAN_pushAMRegs() while(CAN_ADCON & CAN_ADCON_BSY); \ + _push_(CAN_ADL); _push_(CAN_ADH); \ + _push_(CAN_DATA0); _push_(CAN_DATA1); \ + _push_(CAN_DATA2); _push_(CAN_DATA3) + +#define CAN_popAMRegs() _pop_(CAN_DATA3); _pop_(CAN_DATA2); \ + _pop_(CAN_DATA1); _pop_(CAN_DATA0); \ + _pop_(CAN_ADH); _pop_(CAN_ADL) + +//**************************************************************************** +// @Interrupt Vectors +//**************************************************************************** + +// Shared interrupt vector definitions are defined in SHARED_INT.H + + +// USER CODE BEGIN (CAN_Header,9) + +// USER CODE END + + +#endif // ifndef _CAN_H_ diff --git a/CL2.0.asm b/CL2.0.asm new file mode 100644 index 0000000..d5faaf0 --- /dev/null +++ b/CL2.0.asm @@ -0,0 +1,4129 @@ +;**************************************************************************** +; Filename CL2.0.asm +; Project CL2.0.dav +;---------------------------------------------------------------------------- +; Description This file contains the assembler formatted information +; about the actual project values. It will be used by your +; programming environment. +; +; PLEASE DO NOT MODIFY THIS FILE ! +; +;---------------------------------------------------------------------------- +; Date 2025/1/18 20:45:36 +; +;**************************************************************************** + + +; RMAP=x -CPU Accumulator Register +ACC_ACC0 SET 0 +ACC_ACC1 SET 0 +ACC_ACC2 SET 0 +ACC_ACC3 SET 0 +ACC_ACC4 SET 0 +ACC_ACC5 SET 0 +ACC_ACC6 SET 0 +ACC_ACC7 SET 0 + +; RMAP=0 PAGE=1-ADC Channel 0 Control Register +ADC_CHCTR0_LCC SET 0 +ADC_CHCTR0_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 1 Control Register +ADC_CHCTR1_LCC SET 0 +ADC_CHCTR1_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 2 Control Register +ADC_CHCTR2_LCC SET 0 +ADC_CHCTR2_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 3 Control Register +ADC_CHCTR3_LCC SET 0 +ADC_CHCTR3_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 4 Control Register +ADC_CHCTR4_LCC SET 0 +ADC_CHCTR4_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 5 Control Register +ADC_CHCTR5_LCC SET 0 +ADC_CHCTR5_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 6 Control Register +ADC_CHCTR6_LCC SET 0 +ADC_CHCTR6_RESRSEL SET 0 + +; RMAP=0 PAGE=1-ADC Channel 7 Control Register +ADC_CHCTR7_LCC SET 0 +ADC_CHCTR7_RESRSEL SET 0 + +; RMAP=0 PAGE=5-ADC Channel Interrupt Clear Register +ADC_CHINCR_CHINC0 SET 0 +ADC_CHINCR_CHINC1 SET 0 +ADC_CHINCR_CHINC2 SET 0 +ADC_CHINCR_CHINC3 SET 0 +ADC_CHINCR_CHINC4 SET 0 +ADC_CHINCR_CHINC5 SET 0 +ADC_CHINCR_CHINC6 SET 0 +ADC_CHINCR_CHINC7 SET 0 + +; RMAP=0 PAGE=5-ADC Channel Interrupt Flag Register +ADC_CHINFR_CHINF0 SET 0 +ADC_CHINFR_CHINF1 SET 0 +ADC_CHINFR_CHINF2 SET 0 +ADC_CHINFR_CHINF3 SET 0 +ADC_CHINFR_CHINF4 SET 0 +ADC_CHINFR_CHINF5 SET 0 +ADC_CHINFR_CHINF6 SET 0 +ADC_CHINFR_CHINF7 SET 0 + +; RMAP=0 PAGE=5-ADC Channel Interrupt Node Pointer Register +ADC_CHINPR_CHINP0 SET 0 +ADC_CHINPR_CHINP1 SET 0 +ADC_CHINPR_CHINP2 SET 0 +ADC_CHINPR_CHINP3 SET 0 +ADC_CHINPR_CHINP4 SET 0 +ADC_CHINPR_CHINP5 SET 0 +ADC_CHINPR_CHINP6 SET 0 +ADC_CHINPR_CHINP7 SET 0 + +; RMAP=0 PAGE=5-ADC Channel Interrupt Set Register +ADC_CHINSR_CHINS0 SET 0 +ADC_CHINSR_CHINS1 SET 0 +ADC_CHINSR_CHINS2 SET 0 +ADC_CHINSR_CHINS3 SET 0 +ADC_CHINSR_CHINS4 SET 0 +ADC_CHINSR_CHINS5 SET 0 +ADC_CHINSR_CHINS6 SET 0 +ADC_CHINSR_CHINS7 SET 0 + +; RMAP=0 PAGE=6-ADC Source 1 Conversion Request Control Register +ADC_CRCR1_CH4 SET 0 +ADC_CRCR1_CH5 SET 0 +ADC_CRCR1_CH6 SET 0 +ADC_CRCR1_CH7 SET 0 + +; RMAP=0 PAGE=6-ADC Source 1 Conversion Request Mode Register +ADC_CRMR1_0 SET 0 +ADC_CRMR1_CLRPND SET 0 +ADC_CRMR1_ENGT SET 0 +ADC_CRMR1_ENSI SET 0 +ADC_CRMR1_ENTR SET 0 +ADC_CRMR1_LDEV SET 0 +ADC_CRMR1_RSV SET 0 +ADC_CRMR1_SCAN SET 0 + +; RMAP=0 PAGE=6-ADC Source 1 Conversion Request Pending Register +ADC_CRPR1_CHP4 SET 0 +ADC_CRPR1_CHP5 SET 0 +ADC_CRPR1_CHP6 SET 0 +ADC_CRPR1_CHP7 SET 0 + +; RMAP=0 PAGE=0-ADC External Trigger Control Register +ADC_ETRCR_ETRSEL0 SET 0 +ADC_ETRCR_ETRSEL1 SET 0 +ADC_ETRCR_SYNEN0 SET 0 +ADC_ETRCR_SYNEN1 SET 0 + +; RMAP=0 PAGE=5-ADC Event Interrupt Clear Register +ADC_EVINCR_EVINC0 SET 0 +ADC_EVINCR_EVINC1 SET 0 +ADC_EVINCR_EVINC4 SET 0 +ADC_EVINCR_EVINC5 SET 0 +ADC_EVINCR_EVINC6 SET 0 +ADC_EVINCR_EVINC7 SET 0 + +; RMAP=0 PAGE=5-ADC Event Interrupt Flag Register +ADC_EVINFR_EVINF0 SET 0 +ADC_EVINFR_EVINF1 SET 0 +ADC_EVINFR_EVINF4 SET 0 +ADC_EVINFR_EVINF5 SET 0 +ADC_EVINFR_EVINF6 SET 0 +ADC_EVINFR_EVINF7 SET 0 + +; RMAP=0 PAGE=5-ADC Event Interrupt Node Pointer Register +ADC_EVINPR_EVINP0 SET 0 +ADC_EVINPR_EVINP1 SET 0 +ADC_EVINPR_EVINP4 SET 0 +ADC_EVINPR_EVINP5 SET 0 +ADC_EVINPR_EVINP6 SET 0 +ADC_EVINPR_EVINP7 SET 0 + +; RMAP=0 PAGE=5-ADC Event Interrupt Set Flag Register +ADC_EVINSR_EVINS0 SET 0 +ADC_EVINSR_EVINS1 SET 0 +ADC_EVINSR_EVINS4 SET 0 +ADC_EVINSR_EVINS5 SET 0 +ADC_EVINSR_EVINS6 SET 0 +ADC_EVINSR_EVINS7 SET 0 + +; RMAP=0 PAGE=0-ADC Global Control Register +ADC_GLOBCTR_ANON SET 0 +ADC_GLOBCTR_CTC SET 3 +ADC_GLOBCTR_DW SET 0 + +; RMAP=0 PAGE=0-ADC Global Status Register +ADC_GLOBSTR_BUSY SET 0 +ADC_GLOBSTR_CHNR SET 0 +ADC_GLOBSTR_SAMPLE SET 0 + +; RMAP=0 PAGE=0-ADC Input Class 0 Register +ADC_INPCR0_STC SET 0 + +; RMAP=0 PAGE=0-ADC Limit Check Boundary Register +ADC_LCBR_BOUND0 SET 7 +ADC_LCBR_BOUND1 SET 11 + +; RMAP=0 -ADC Page Register +ADC_PAGE_OP SET 0 +ADC_PAGE_PAGE SET 0 +ADC_PAGE_STNR SET 0 + +; RMAP=0 PAGE=0-ADC Priority and Arbitration Register +ADC_PRAR_ARBM SET 0 +ADC_PRAR_ASEN0 SET 0 +ADC_PRAR_ASEN1 SET 0 +ADC_PRAR_CSM0 SET 0 +ADC_PRAR_CSM1 SET 0 +ADC_PRAR_PRIO0 SET 0 +ADC_PRAR_PRIO1 SET 0 + +; RMAP=0 PAGE=6-ADC Source 0 Queue 0 Register +ADC_Q0R0_ENSI SET 0 +ADC_Q0R0_EXTR SET 0 +ADC_Q0R0_REQCHNR SET 0 +ADC_Q0R0_RF SET 0 +ADC_Q0R0_V SET 0 + +; RMAP=0 PAGE=6-ADC Source 0 Queue Backup Register +ADC_QBUR0_ENSI SET 0 +ADC_QBUR0_EXTR SET 0 +ADC_QBUR0_REQCHNR SET 0 +ADC_QBUR0_RF SET 0 +ADC_QBUR0_V SET 0 + +; RMAP=0 PAGE=6-ADC Source 0 Queue Input Register +ADC_QINR0_ENSI SET 0 +ADC_QINR0_EXTR SET 0 +ADC_QINR0_REQCHNR SET 0 +ADC_QINR0_RF SET 0 + +; RMAP=0 PAGE=6-ADC Source 0 Queue Mode Register +ADC_QMR0_0 SET 0 +ADC_QMR0_CEV SET 0 +ADC_QMR0_CLRV SET 0 +ADC_QMR0_ENGT SET 0 +ADC_QMR0_ENTR SET 0 +ADC_QMR0_FLUSH SET 0 +ADC_QMR0_TREV SET 0 + +; RMAP=0 PAGE=6-ADC Source 0 Queue Status Register +ADC_QSR0_EMPTY SET 0 +ADC_QSR0_EV SET 0 +ADC_QSR0_FILL SET 0 +ADC_QSR0_RSV SET 0 + +; RMAP=0 PAGE=4-ADC Result 0 Control Register +ADC_RCR0_DRCTR SET 0 +ADC_RCR0_IEN SET 0 +ADC_RCR0_VFCTR SET 0 +ADC_RCR0_WFR SET 0 + +; RMAP=0 PAGE=4-ADC Result 1 Control Register +ADC_RCR1_DRCTR SET 0 +ADC_RCR1_IEN SET 0 +ADC_RCR1_VFCTR SET 0 +ADC_RCR1_WFR SET 0 + +; RMAP=0 PAGE=4-ADC Result 2 Control Register +ADC_RCR2_DRCTR SET 0 +ADC_RCR2_IEN SET 0 +ADC_RCR2_VFCTR SET 0 +ADC_RCR2_WFR SET 0 + +; RMAP=0 PAGE=4-ADC Result 3 Control Register +ADC_RCR3_DRCTR SET 0 +ADC_RCR3_IEN SET 0 +ADC_RCR3_VFCTR SET 0 +ADC_RCR3_WFR SET 0 + +; RMAP=0 PAGE=2-ADC Result 0 Register High +ADC_RESR0H_RESULT SET 0 + +; RMAP=0 PAGE=2-ADC Result 0 Register Low +ADC_RESR0L_CHNR SET 0 +ADC_RESR0L_DRC SET 0 +ADC_RESR0L_RESULT SET 0 +ADC_RESR0L_VF SET 0 + +; RMAP=0 PAGE=2-ADC Result 1 Register High +ADC_RESR1H_RESULT SET 0 + +; RMAP=0 PAGE=2-ADC Result 1 Register Low +ADC_RESR1L_CHNR SET 0 +ADC_RESR1L_DRC SET 0 +ADC_RESR1L_RESULT SET 0 +ADC_RESR1L_VF SET 0 + +; RMAP=0 PAGE=2-ADC Result 2 Register High +ADC_RESR2H_RESULT SET 0 + +; RMAP=0 PAGE=2-ADC Result 2 Register Low +ADC_RESR2L_CHNR SET 0 +ADC_RESR2L_DRC SET 0 +ADC_RESR2L_RESULT SET 0 +ADC_RESR2L_VF SET 0 + +; RMAP=0 PAGE=2-ADC Result 3 Register High +ADC_RESR3H_RESULT SET 0 + +; RMAP=0 PAGE=2-ADC Result 3 Register Low +ADC_RESR3L_CHNR SET 0 +ADC_RESR3L_DRC SET 0 +ADC_RESR3L_RESULT SET 0 +ADC_RESR3L_VF SET 0 + +; RMAP=0 PAGE=3-ADC Result 0 View A Register High +ADC_RESRA0H_RESULT SET 0 + +; RMAP=0 PAGE=3-ADC Result 0 View A Register Low +ADC_RESRA0L_CHNR SET 0 +ADC_RESRA0L_DRC SET 0 +ADC_RESRA0L_RESULT SET 0 +ADC_RESRA0L_VF SET 0 + +; RMAP=0 PAGE=3-ADC Result 1 View A Register High +ADC_RESRA1H_RESULT SET 0 + +; RMAP=0 PAGE=3-ADC Result 1 View A Register Low +ADC_RESRA1L_CHNR SET 0 +ADC_RESRA1L_DRC SET 0 +ADC_RESRA1L_RESULT SET 0 +ADC_RESRA1L_VF SET 0 + +; RMAP=0 PAGE=3-ADC Result 2 View A Register High +ADC_RESRA2H_RESULT SET 0 + +; RMAP=0 PAGE=3-ADC Result 2 View A Register Low +ADC_RESRA2L_CHNR SET 0 +ADC_RESRA2L_DRC SET 0 +ADC_RESRA2L_RESULT SET 0 +ADC_RESRA2L_VF SET 0 + +; RMAP=0 PAGE=3-ADC Result 3 View A Register High +ADC_RESRA3H_RESULT SET 0 + +; RMAP=0 PAGE=3-ADC Result 3 View A Register Low +ADC_RESRA3L_CHNR SET 0 +ADC_RESRA3L_DRC SET 0 +ADC_RESRA3L_RESULT SET 0 +ADC_RESRA3L_VF SET 0 + +; RMAP=0 PAGE=4-ADC Valid Flag Clear Register +ADC_VFCR_VFC0 SET 0 +ADC_VFCR_VFC1 SET 0 +ADC_VFCR_VFC2 SET 0 +ADC_VFCR_VFC3 SET 0 + +; RMAP=0 PAGE=0-SCU Baud Rate Control Register +BCON_BGSEL SET 0 +BCON_BRDIS SET 0 +BCON_BRPRE SET 0 +BCON_R SET 0 + +; RMAP=0 PAGE=0-SCU Baud Rate Timer/Reload Register +BG_BR_VALUE SET 1 + +; RMAP=x -CPU B Register +B_B0 SET 0 +B_B1 SET 0 +B_B2 SET 0 +B_B3 SET 0 +B_B4 SET 0 +B_B5 SET 0 +B_B6 SET 0 +B_B7 SET 0 + +; RMAP=0 -MultiCAN Serial Channel Control Register +CAN_ADCON_AUAD SET 0 +CAN_ADCON_BSY SET 0 +CAN_ADCON_RWEN SET 0 +CAN_ADCON_V0 SET 0 +CAN_ADCON_V1 SET 0 +CAN_ADCON_V2 SET 0 +CAN_ADCON_V3 SET 0 + +; RMAP=0 -MultiCAN Baud Rate Control Register +CAN_ADH_CA10 SET 0 +CAN_ADH_CA11 SET 0 +CAN_ADH_CA12 SET 0 +CAN_ADH_CA13 SET 0 + +; RMAP=0 -MultiCAN Serial Data Buffer Register +CAN_ADL_CA2 SET 0 +CAN_ADL_CA3 SET 0 +CAN_ADL_CA4 SET 0 +CAN_ADL_CA5 SET 0 +CAN_ADL_CA6 SET 0 +CAN_ADL_CA7 SET 0 +CAN_ADL_CA8 SET 0 +CAN_ADL_CA9 SET 0 + +; RMAP=0 -MultiCAN CAN Data Register 0 +CAN_DATA0_CD[7:0] SET 0 + +; RMAP=0 -MultiCAN CAN Data Register 1 +CAN_DATA1_CD[15:8] SET 0 + +; RMAP=0 -MultiCAN CAN Data Register 2 +CAN_DATA2_CD SET 0 + +; RMAP=0 -MultiCAN CAN Data Register 3 +CAN_DATA3_CD SET 0 + +; List Register 0 +CAN_LIST0_0 SET 0 +CAN_LIST0_BEGIN SET 0 +CAN_LIST0_EMPTY SET 0 +CAN_LIST0_END SET 0 +CAN_LIST0_SIZE SET 0 + +; List Register 1 +CAN_LIST1_0 SET 0 +CAN_LIST1_BEGIN SET 0 +CAN_LIST1_EMPTY SET 0 +CAN_LIST1_END SET 0 +CAN_LIST1_SIZE SET 0 + +; List Register 2 +CAN_LIST2_0 SET 0 +CAN_LIST2_BEGIN SET 0 +CAN_LIST2_EMPTY SET 0 +CAN_LIST2_END SET 0 +CAN_LIST2_SIZE SET 0 + +; List Register 3 +CAN_LIST3_0 SET 0 +CAN_LIST3_BEGIN SET 0 +CAN_LIST3_EMPTY SET 0 +CAN_LIST3_END SET 0 +CAN_LIST3_SIZE SET 0 + +; List Register 4 +CAN_LIST4_0 SET 0 +CAN_LIST4_BEGIN SET 0 +CAN_LIST4_EMPTY SET 0 +CAN_LIST4_END SET 0 +CAN_LIST4_SIZE SET 0 + +; List Register 5 +CAN_LIST5_0 SET 0 +CAN_LIST5_BEGIN SET 0 +CAN_LIST5_EMPTY SET 0 +CAN_LIST5_END SET 0 +CAN_LIST5_SIZE SET 0 + +; List Register 6 +CAN_LIST6_0 SET 0 +CAN_LIST6_BEGIN SET 0 +CAN_LIST6_EMPTY SET 0 +CAN_LIST6_END SET 0 +CAN_LIST6_SIZE SET 0 + +; List Register 7 +CAN_LIST7_0 SET 0 +CAN_LIST7_BEGIN SET 0 +CAN_LIST7_EMPTY SET 0 +CAN_LIST7_END SET 0 +CAN_LIST7_SIZE SET 0 + +; MultiCAN Module Control Register +CAN_MCR_0 SET 0 +CAN_MCR_0 SET 0 +CAN_MCR_MPSEL SET 0 + +; Module Interrupt Trigger Register +CAN_MITR_IT[31:8] SET 0 +CAN_MITR_IT[7:0] SET 0 + +; CAN Message Object 0 Acceptance Mask Register +CAN_MOAMR0_0 SET 0 +CAN_MOAMR0_AM SET 536870911 +CAN_MOAMR0_MIDE SET 1 + +; CAN Message Object 10 Acceptance Mask Register +CAN_MOAMR10_0 SET 0 +CAN_MOAMR10_AM SET 536870911 +CAN_MOAMR10_MIDE SET 1 + +; CAN Message Object 11 Acceptance Mask Register +CAN_MOAMR11_0 SET 0 +CAN_MOAMR11_AM SET 536870911 +CAN_MOAMR11_MIDE SET 1 + +; CAN Message Object 12 Acceptance Mask Register +CAN_MOAMR12_0 SET 0 +CAN_MOAMR12_AM SET 536870911 +CAN_MOAMR12_MIDE SET 1 + +; CAN Message Object 13 Acceptance Mask Register +CAN_MOAMR13_0 SET 0 +CAN_MOAMR13_AM SET 536870911 +CAN_MOAMR13_MIDE SET 1 + +; CAN Message Object 14 Acceptance Mask Register +CAN_MOAMR14_0 SET 0 +CAN_MOAMR14_AM SET 536870911 +CAN_MOAMR14_MIDE SET 1 + +; CAN Message Object 15 Acceptance Mask Register +CAN_MOAMR15_0 SET 0 +CAN_MOAMR15_AM SET 536870911 +CAN_MOAMR15_MIDE SET 1 + +; CAN Message Object 16 Acceptance Mask Register +CAN_MOAMR16_0 SET 0 +CAN_MOAMR16_AM SET 536870911 +CAN_MOAMR16_MIDE SET 1 + +; CAN Message Object 17 Acceptance Mask Register +CAN_MOAMR17_0 SET 0 +CAN_MOAMR17_AM SET 536870911 +CAN_MOAMR17_MIDE SET 1 + +; CAN Message Object 18 Acceptance Mask Register +CAN_MOAMR18_0 SET 0 +CAN_MOAMR18_AM SET 536870911 +CAN_MOAMR18_MIDE SET 1 + +; CAN Message Object 19 Acceptance Mask Register +CAN_MOAMR19_0 SET 0 +CAN_MOAMR19_AM SET 536870911 +CAN_MOAMR19_MIDE SET 1 + +; CAN Message Object 1 Acceptance Mask Register +CAN_MOAMR1_0 SET 0 +CAN_MOAMR1_AM SET 536870911 +CAN_MOAMR1_MIDE SET 1 + +; CAN Message Object 20 Acceptance Mask Register +CAN_MOAMR20_0 SET 0 +CAN_MOAMR20_AM SET 536870911 +CAN_MOAMR20_MIDE SET 1 + +; CAN Message Object 21 Acceptance Mask Register +CAN_MOAMR21_0 SET 0 +CAN_MOAMR21_AM SET 536870911 +CAN_MOAMR21_MIDE SET 1 + +; CAN Message Object 22 Acceptance Mask Register +CAN_MOAMR22_0 SET 0 +CAN_MOAMR22_AM SET 536870911 +CAN_MOAMR22_MIDE SET 1 + +; CAN Message Object 23 Acceptance Mask Register +CAN_MOAMR23_0 SET 0 +CAN_MOAMR23_AM SET 536870911 +CAN_MOAMR23_MIDE SET 1 + +; CAN Message Object 24 Acceptance Mask Register +CAN_MOAMR24_0 SET 0 +CAN_MOAMR24_AM SET 536870911 +CAN_MOAMR24_MIDE SET 1 + +; CAN Message Object 25 Acceptance Mask Register +CAN_MOAMR25_0 SET 0 +CAN_MOAMR25_AM SET 536870911 +CAN_MOAMR25_MIDE SET 1 + +; CAN Message Object 26 Acceptance Mask Register +CAN_MOAMR26_0 SET 0 +CAN_MOAMR26_AM SET 536870911 +CAN_MOAMR26_MIDE SET 1 + +; CAN Message Object 27 Acceptance Mask Register +CAN_MOAMR27_0 SET 0 +CAN_MOAMR27_AM SET 536870911 +CAN_MOAMR27_MIDE SET 1 + +; CAN Message Object 28 Acceptance Mask Register +CAN_MOAMR28_0 SET 0 +CAN_MOAMR28_AM SET 536870911 +CAN_MOAMR28_MIDE SET 1 + +; CAN Message Object 29 Acceptance Mask Register +CAN_MOAMR29_0 SET 0 +CAN_MOAMR29_AM SET 536870911 +CAN_MOAMR29_MIDE SET 1 + +; CAN Message Object 2 Acceptance Mask Register +CAN_MOAMR2_0 SET 0 +CAN_MOAMR2_AM SET 536870911 +CAN_MOAMR2_MIDE SET 1 + +; CAN Message Object 30 Acceptance Mask Register +CAN_MOAMR30_0 SET 0 +CAN_MOAMR30_AM SET 536870911 +CAN_MOAMR30_MIDE SET 1 + +; CAN Message Object 31 Acceptance Mask Register +CAN_MOAMR31_0 SET 0 +CAN_MOAMR31_AM SET 536870911 +CAN_MOAMR31_MIDE SET 1 + +; CAN Message Object 3 Acceptance Mask Register +CAN_MOAMR3_0 SET 0 +CAN_MOAMR3_AM SET 536870911 +CAN_MOAMR3_MIDE SET 1 + +; CAN Message Object 4 Acceptance Mask Register +CAN_MOAMR4_0 SET 0 +CAN_MOAMR4_AM SET 536870911 +CAN_MOAMR4_MIDE SET 1 + +; CAN Message Object 5 Acceptance Mask Register +CAN_MOAMR5_0 SET 0 +CAN_MOAMR5_AM SET 536870911 +CAN_MOAMR5_MIDE SET 1 + +; CAN Message Object 6 Acceptance Mask Register +CAN_MOAMR6_0 SET 0 +CAN_MOAMR6_AM SET 536870911 +CAN_MOAMR6_MIDE SET 1 + +; CAN Message Object 7 Acceptance Mask Register +CAN_MOAMR7_0 SET 0 +CAN_MOAMR7_AM SET 536870911 +CAN_MOAMR7_MIDE SET 1 + +; CAN Message Object 8 Acceptance Mask Register +CAN_MOAMR8_0 SET 0 +CAN_MOAMR8_AM SET 536870911 +CAN_MOAMR8_MIDE SET 1 + +; CAN Message Object 9 Acceptance Mask Register +CAN_MOAMR9_0 SET 0 +CAN_MOAMR9_AM SET 536870911 +CAN_MOAMR9_MIDE SET 1 + +; CAN Message Object 0 Arbitration Register +CAN_MOAR0_ID SET 268435457 +CAN_MOAR0_IDE SET 1 +CAN_MOAR0_PRI SET 3 + +; CAN Message Object 10 Arbitration Register +CAN_MOAR10_ID SET 0 +CAN_MOAR10_IDE SET 0 +CAN_MOAR10_PRI SET 3 + +; CAN Message Object 11 Arbitration Register +CAN_MOAR11_ID SET 0 +CAN_MOAR11_IDE SET 0 +CAN_MOAR11_PRI SET 3 + +; CAN Message Object 12 Arbitration Register +CAN_MOAR12_ID SET 0 +CAN_MOAR12_IDE SET 0 +CAN_MOAR12_PRI SET 3 + +; CAN Message Object 13 Arbitration Register +CAN_MOAR13_ID SET 0 +CAN_MOAR13_IDE SET 0 +CAN_MOAR13_PRI SET 3 + +; CAN Message Object 14 Arbitration Register +CAN_MOAR14_ID SET 0 +CAN_MOAR14_IDE SET 0 +CAN_MOAR14_PRI SET 3 + +; CAN Message Object 15 Arbitration Register +CAN_MOAR15_ID SET 0 +CAN_MOAR15_IDE SET 0 +CAN_MOAR15_PRI SET 3 + +; CAN Message Object 16 Arbitration Register +CAN_MOAR16_ID SET 0 +CAN_MOAR16_IDE SET 0 +CAN_MOAR16_PRI SET 3 + +; CAN Message Object 17 Arbitration Register +CAN_MOAR17_ID SET 0 +CAN_MOAR17_IDE SET 0 +CAN_MOAR17_PRI SET 3 + +; CAN Message Object 18 Arbitration Register +CAN_MOAR18_ID SET 0 +CAN_MOAR18_IDE SET 0 +CAN_MOAR18_PRI SET 3 + +; CAN Message Object 19 Arbitration Register +CAN_MOAR19_ID SET 0 +CAN_MOAR19_IDE SET 0 +CAN_MOAR19_PRI SET 3 + +; CAN Message Object 1 Arbitration Register +CAN_MOAR1_ID SET 268435458 +CAN_MOAR1_IDE SET 1 +CAN_MOAR1_PRI SET 3 + +; CAN Message Object 20 Arbitration Register +CAN_MOAR20_ID SET 0 +CAN_MOAR20_IDE SET 0 +CAN_MOAR20_PRI SET 3 + +; CAN Message Object 21 Arbitration Register +CAN_MOAR21_ID SET 0 +CAN_MOAR21_IDE SET 0 +CAN_MOAR21_PRI SET 3 + +; CAN Message Object 22 Arbitration Register +CAN_MOAR22_ID SET 0 +CAN_MOAR22_IDE SET 0 +CAN_MOAR22_PRI SET 3 + +; CAN Message Object 23 Arbitration Register +CAN_MOAR23_ID SET 0 +CAN_MOAR23_IDE SET 0 +CAN_MOAR23_PRI SET 3 + +; CAN Message Object 24 Arbitration Register +CAN_MOAR24_ID SET 0 +CAN_MOAR24_IDE SET 0 +CAN_MOAR24_PRI SET 3 + +; CAN Message Object 25 Arbitration Register +CAN_MOAR25_ID SET 0 +CAN_MOAR25_IDE SET 0 +CAN_MOAR25_PRI SET 3 + +; CAN Message Object 26 Arbitration Register +CAN_MOAR26_ID SET 0 +CAN_MOAR26_IDE SET 0 +CAN_MOAR26_PRI SET 3 + +; CAN Message Object 27 Arbitration Register +CAN_MOAR27_ID SET 0 +CAN_MOAR27_IDE SET 0 +CAN_MOAR27_PRI SET 3 + +; CAN Message Object 28 Arbitration Register +CAN_MOAR28_ID SET 0 +CAN_MOAR28_IDE SET 0 +CAN_MOAR28_PRI SET 3 + +; CAN Message Object 29 Arbitration Register +CAN_MOAR29_ID SET 0 +CAN_MOAR29_IDE SET 0 +CAN_MOAR29_PRI SET 3 + +; CAN Message Object 2 Arbitration Register +CAN_MOAR2_ID SET 536870911 +CAN_MOAR2_IDE SET 1 +CAN_MOAR2_PRI SET 3 + +; CAN Message Object 30 Arbitration Register +CAN_MOAR30_ID SET 0 +CAN_MOAR30_IDE SET 0 +CAN_MOAR30_PRI SET 3 + +; CAN Message Object 31 Arbitration Register +CAN_MOAR31_ID SET 0 +CAN_MOAR31_IDE SET 0 +CAN_MOAR31_PRI SET 3 + +; CAN Message Object 3 Arbitration Register +CAN_MOAR3_ID SET 0 +CAN_MOAR3_IDE SET 0 +CAN_MOAR3_PRI SET 3 + +; CAN Message Object 4 Arbitration Register +CAN_MOAR4_ID SET 0 +CAN_MOAR4_IDE SET 0 +CAN_MOAR4_PRI SET 3 + +; CAN Message Object 5 Arbitration Register +CAN_MOAR5_ID SET 3 +CAN_MOAR5_IDE SET 1 +CAN_MOAR5_PRI SET 3 + +; CAN Message Object 6 Arbitration Register +CAN_MOAR6_ID SET 285212673 +CAN_MOAR6_IDE SET 1 +CAN_MOAR6_PRI SET 3 + +; CAN Message Object 7 Arbitration Register +CAN_MOAR7_ID SET 285212674 +CAN_MOAR7_IDE SET 1 +CAN_MOAR7_PRI SET 3 + +; CAN Message Object 8 Arbitration Register +CAN_MOAR8_ID SET 285212675 +CAN_MOAR8_IDE SET 1 +CAN_MOAR8_PRI SET 3 + +; CAN Message Object 9 Arbitration Register +CAN_MOAR9_ID SET 536870896 +CAN_MOAR9_IDE SET 1 +CAN_MOAR9_PRI SET 3 + +; CAN Message Object 0 Control Register +CAN_MOCTR0_CTRL SET 0 +CAN_MOCTR0_DIR SET 1 +CAN_MOCTR0_LIST SET 0 +CAN_MOCTR0_MSGLST SET 0 +CAN_MOCTR0_MSGVAL SET 0 +CAN_MOCTR0_NEWDAT SET 0 +CAN_MOCTR0_RTSEL SET 0 +CAN_MOCTR0_RXEN SET 0 +CAN_MOCTR0_RXPND SET 0 +CAN_MOCTR0_RXUPD SET 0 +CAN_MOCTR0_TXEN0 SET 0 +CAN_MOCTR0_TXEN1 SET 0 +CAN_MOCTR0_TXPND SET 0 +CAN_MOCTR0_TXRQ SET 0 + +; CAN Message Object 10 Control Register +CAN_MOCTR10_CTRL SET 0 +CAN_MOCTR10_DIR SET 0 +CAN_MOCTR10_LIST SET 0 +CAN_MOCTR10_MSGLST SET 0 +CAN_MOCTR10_MSGVAL SET 0 +CAN_MOCTR10_NEWDAT SET 0 +CAN_MOCTR10_RTSEL SET 0 +CAN_MOCTR10_RXEN SET 0 +CAN_MOCTR10_RXPND SET 0 +CAN_MOCTR10_RXUPD SET 0 +CAN_MOCTR10_TXEN0 SET 0 +CAN_MOCTR10_TXEN1 SET 0 +CAN_MOCTR10_TXPND SET 0 +CAN_MOCTR10_TXRQ SET 0 + +; CAN Message Object 11 Control Register +CAN_MOCTR11_CTRL SET 0 +CAN_MOCTR11_DIR SET 0 +CAN_MOCTR11_LIST SET 0 +CAN_MOCTR11_MSGLST SET 0 +CAN_MOCTR11_MSGVAL SET 0 +CAN_MOCTR11_NEWDAT SET 0 +CAN_MOCTR11_RTSEL SET 0 +CAN_MOCTR11_RXEN SET 0 +CAN_MOCTR11_RXPND SET 0 +CAN_MOCTR11_RXUPD SET 0 +CAN_MOCTR11_TXEN0 SET 0 +CAN_MOCTR11_TXEN1 SET 0 +CAN_MOCTR11_TXPND SET 0 +CAN_MOCTR11_TXRQ SET 0 + +; CAN Message Object 12 Control Register +CAN_MOCTR12_CTRL SET 0 +CAN_MOCTR12_DIR SET 0 +CAN_MOCTR12_LIST SET 0 +CAN_MOCTR12_MSGLST SET 0 +CAN_MOCTR12_MSGVAL SET 0 +CAN_MOCTR12_NEWDAT SET 0 +CAN_MOCTR12_RTSEL SET 0 +CAN_MOCTR12_RXEN SET 0 +CAN_MOCTR12_RXPND SET 0 +CAN_MOCTR12_RXUPD SET 0 +CAN_MOCTR12_TXEN0 SET 0 +CAN_MOCTR12_TXEN1 SET 0 +CAN_MOCTR12_TXPND SET 0 +CAN_MOCTR12_TXRQ SET 0 + +; CAN Message Object 13 Control Register +CAN_MOCTR13_CTRL SET 0 +CAN_MOCTR13_DIR SET 0 +CAN_MOCTR13_LIST SET 0 +CAN_MOCTR13_MSGLST SET 0 +CAN_MOCTR13_MSGVAL SET 0 +CAN_MOCTR13_NEWDAT SET 0 +CAN_MOCTR13_RTSEL SET 0 +CAN_MOCTR13_RXEN SET 0 +CAN_MOCTR13_RXPND SET 0 +CAN_MOCTR13_RXUPD SET 0 +CAN_MOCTR13_TXEN0 SET 0 +CAN_MOCTR13_TXEN1 SET 0 +CAN_MOCTR13_TXPND SET 0 +CAN_MOCTR13_TXRQ SET 0 + +; CAN Message Object 14 Control Register +CAN_MOCTR14_CTRL SET 0 +CAN_MOCTR14_DIR SET 0 +CAN_MOCTR14_LIST SET 0 +CAN_MOCTR14_MSGLST SET 0 +CAN_MOCTR14_MSGVAL SET 0 +CAN_MOCTR14_NEWDAT SET 0 +CAN_MOCTR14_RTSEL SET 0 +CAN_MOCTR14_RXEN SET 0 +CAN_MOCTR14_RXPND SET 0 +CAN_MOCTR14_RXUPD SET 0 +CAN_MOCTR14_TXEN0 SET 0 +CAN_MOCTR14_TXEN1 SET 0 +CAN_MOCTR14_TXPND SET 0 +CAN_MOCTR14_TXRQ SET 0 + +; CAN Message Object 15 Control Register +CAN_MOCTR15_CTRL SET 0 +CAN_MOCTR15_DIR SET 0 +CAN_MOCTR15_LIST SET 0 +CAN_MOCTR15_MSGLST SET 0 +CAN_MOCTR15_MSGVAL SET 0 +CAN_MOCTR15_NEWDAT SET 0 +CAN_MOCTR15_RTSEL SET 0 +CAN_MOCTR15_RXEN SET 0 +CAN_MOCTR15_RXPND SET 0 +CAN_MOCTR15_RXUPD SET 0 +CAN_MOCTR15_TXEN0 SET 0 +CAN_MOCTR15_TXEN1 SET 0 +CAN_MOCTR15_TXPND SET 0 +CAN_MOCTR15_TXRQ SET 0 + +; CAN Message Object 16 Control Register +CAN_MOCTR16_CTRL SET 0 +CAN_MOCTR16_DIR SET 0 +CAN_MOCTR16_LIST SET 0 +CAN_MOCTR16_MSGLST SET 0 +CAN_MOCTR16_MSGVAL SET 0 +CAN_MOCTR16_NEWDAT SET 0 +CAN_MOCTR16_RTSEL SET 0 +CAN_MOCTR16_RXEN SET 0 +CAN_MOCTR16_RXPND SET 0 +CAN_MOCTR16_RXUPD SET 0 +CAN_MOCTR16_TXEN0 SET 0 +CAN_MOCTR16_TXEN1 SET 0 +CAN_MOCTR16_TXPND SET 0 +CAN_MOCTR16_TXRQ SET 0 + +; CAN Message Object 17 Control Register +CAN_MOCTR17_CTRL SET 0 +CAN_MOCTR17_DIR SET 0 +CAN_MOCTR17_LIST SET 0 +CAN_MOCTR17_MSGLST SET 0 +CAN_MOCTR17_MSGVAL SET 0 +CAN_MOCTR17_NEWDAT SET 0 +CAN_MOCTR17_RTSEL SET 0 +CAN_MOCTR17_RXEN SET 0 +CAN_MOCTR17_RXPND SET 0 +CAN_MOCTR17_RXUPD SET 0 +CAN_MOCTR17_TXEN0 SET 0 +CAN_MOCTR17_TXEN1 SET 0 +CAN_MOCTR17_TXPND SET 0 +CAN_MOCTR17_TXRQ SET 0 + +; CAN Message Object 18 Control Register +CAN_MOCTR18_CTRL SET 0 +CAN_MOCTR18_DIR SET 0 +CAN_MOCTR18_LIST SET 0 +CAN_MOCTR18_MSGLST SET 0 +CAN_MOCTR18_MSGVAL SET 0 +CAN_MOCTR18_NEWDAT SET 0 +CAN_MOCTR18_RTSEL SET 0 +CAN_MOCTR18_RXEN SET 0 +CAN_MOCTR18_RXPND SET 0 +CAN_MOCTR18_RXUPD SET 0 +CAN_MOCTR18_TXEN0 SET 0 +CAN_MOCTR18_TXEN1 SET 0 +CAN_MOCTR18_TXPND SET 0 +CAN_MOCTR18_TXRQ SET 0 + +; CAN Message Object 19 Control Register +CAN_MOCTR19_CTRL SET 0 +CAN_MOCTR19_DIR SET 0 +CAN_MOCTR19_LIST SET 0 +CAN_MOCTR19_MSGLST SET 0 +CAN_MOCTR19_MSGVAL SET 0 +CAN_MOCTR19_NEWDAT SET 0 +CAN_MOCTR19_RTSEL SET 0 +CAN_MOCTR19_RXEN SET 0 +CAN_MOCTR19_RXPND SET 0 +CAN_MOCTR19_RXUPD SET 0 +CAN_MOCTR19_TXEN0 SET 0 +CAN_MOCTR19_TXEN1 SET 0 +CAN_MOCTR19_TXPND SET 0 +CAN_MOCTR19_TXRQ SET 0 + +; CAN Message Object 1 Control Register +CAN_MOCTR1_CTRL SET 0 +CAN_MOCTR1_DIR SET 0 +CAN_MOCTR1_LIST SET 0 +CAN_MOCTR1_MSGLST SET 0 +CAN_MOCTR1_MSGVAL SET 0 +CAN_MOCTR1_NEWDAT SET 0 +CAN_MOCTR1_RTSEL SET 0 +CAN_MOCTR1_RXEN SET 0 +CAN_MOCTR1_RXPND SET 0 +CAN_MOCTR1_RXUPD SET 0 +CAN_MOCTR1_TXEN0 SET 0 +CAN_MOCTR1_TXEN1 SET 0 +CAN_MOCTR1_TXPND SET 0 +CAN_MOCTR1_TXRQ SET 0 + +; CAN Message Object 20 Control Register +CAN_MOCTR20_CTRL SET 0 +CAN_MOCTR20_DIR SET 0 +CAN_MOCTR20_LIST SET 0 +CAN_MOCTR20_MSGLST SET 0 +CAN_MOCTR20_MSGVAL SET 0 +CAN_MOCTR20_NEWDAT SET 0 +CAN_MOCTR20_RTSEL SET 0 +CAN_MOCTR20_RXEN SET 0 +CAN_MOCTR20_RXPND SET 0 +CAN_MOCTR20_RXUPD SET 0 +CAN_MOCTR20_TXEN0 SET 0 +CAN_MOCTR20_TXEN1 SET 0 +CAN_MOCTR20_TXPND SET 0 +CAN_MOCTR20_TXRQ SET 0 + +; CAN Message Object 21 Control Register +CAN_MOCTR21_CTRL SET 0 +CAN_MOCTR21_DIR SET 0 +CAN_MOCTR21_LIST SET 0 +CAN_MOCTR21_MSGLST SET 0 +CAN_MOCTR21_MSGVAL SET 0 +CAN_MOCTR21_NEWDAT SET 0 +CAN_MOCTR21_RTSEL SET 0 +CAN_MOCTR21_RXEN SET 0 +CAN_MOCTR21_RXPND SET 0 +CAN_MOCTR21_RXUPD SET 0 +CAN_MOCTR21_TXEN0 SET 0 +CAN_MOCTR21_TXEN1 SET 0 +CAN_MOCTR21_TXPND SET 0 +CAN_MOCTR21_TXRQ SET 0 + +; CAN Message Object 22 Control Register +CAN_MOCTR22_CTRL SET 0 +CAN_MOCTR22_DIR SET 0 +CAN_MOCTR22_LIST SET 0 +CAN_MOCTR22_MSGLST SET 0 +CAN_MOCTR22_MSGVAL SET 0 +CAN_MOCTR22_NEWDAT SET 0 +CAN_MOCTR22_RTSEL SET 0 +CAN_MOCTR22_RXEN SET 0 +CAN_MOCTR22_RXPND SET 0 +CAN_MOCTR22_RXUPD SET 0 +CAN_MOCTR22_TXEN0 SET 0 +CAN_MOCTR22_TXEN1 SET 0 +CAN_MOCTR22_TXPND SET 0 +CAN_MOCTR22_TXRQ SET 0 + +; CAN Message Object 23 Control Register +CAN_MOCTR23_CTRL SET 0 +CAN_MOCTR23_DIR SET 0 +CAN_MOCTR23_LIST SET 0 +CAN_MOCTR23_MSGLST SET 0 +CAN_MOCTR23_MSGVAL SET 0 +CAN_MOCTR23_NEWDAT SET 0 +CAN_MOCTR23_RTSEL SET 0 +CAN_MOCTR23_RXEN SET 0 +CAN_MOCTR23_RXPND SET 0 +CAN_MOCTR23_RXUPD SET 0 +CAN_MOCTR23_TXEN0 SET 0 +CAN_MOCTR23_TXEN1 SET 0 +CAN_MOCTR23_TXPND SET 0 +CAN_MOCTR23_TXRQ SET 0 + +; CAN Message Object 24 Control Register +CAN_MOCTR24_CTRL SET 0 +CAN_MOCTR24_DIR SET 0 +CAN_MOCTR24_LIST SET 0 +CAN_MOCTR24_MSGLST SET 0 +CAN_MOCTR24_MSGVAL SET 0 +CAN_MOCTR24_NEWDAT SET 0 +CAN_MOCTR24_RTSEL SET 0 +CAN_MOCTR24_RXEN SET 0 +CAN_MOCTR24_RXPND SET 0 +CAN_MOCTR24_RXUPD SET 0 +CAN_MOCTR24_TXEN0 SET 0 +CAN_MOCTR24_TXEN1 SET 0 +CAN_MOCTR24_TXPND SET 0 +CAN_MOCTR24_TXRQ SET 0 + +; CAN Message Object 25 Control Register +CAN_MOCTR25_CTRL SET 0 +CAN_MOCTR25_DIR SET 0 +CAN_MOCTR25_LIST SET 0 +CAN_MOCTR25_MSGLST SET 0 +CAN_MOCTR25_MSGVAL SET 0 +CAN_MOCTR25_NEWDAT SET 0 +CAN_MOCTR25_RTSEL SET 0 +CAN_MOCTR25_RXEN SET 0 +CAN_MOCTR25_RXPND SET 0 +CAN_MOCTR25_RXUPD SET 0 +CAN_MOCTR25_TXEN0 SET 0 +CAN_MOCTR25_TXEN1 SET 0 +CAN_MOCTR25_TXPND SET 0 +CAN_MOCTR25_TXRQ SET 0 + +; CAN Message Object 26 Control Register +CAN_MOCTR26_CTRL SET 0 +CAN_MOCTR26_DIR SET 0 +CAN_MOCTR26_LIST SET 0 +CAN_MOCTR26_MSGLST SET 0 +CAN_MOCTR26_MSGVAL SET 0 +CAN_MOCTR26_NEWDAT SET 0 +CAN_MOCTR26_RTSEL SET 0 +CAN_MOCTR26_RXEN SET 0 +CAN_MOCTR26_RXPND SET 0 +CAN_MOCTR26_RXUPD SET 0 +CAN_MOCTR26_TXEN0 SET 0 +CAN_MOCTR26_TXEN1 SET 0 +CAN_MOCTR26_TXPND SET 0 +CAN_MOCTR26_TXRQ SET 0 + +; CAN Message Object 27 Control Register +CAN_MOCTR27_CTRL SET 0 +CAN_MOCTR27_DIR SET 0 +CAN_MOCTR27_LIST SET 0 +CAN_MOCTR27_MSGLST SET 0 +CAN_MOCTR27_MSGVAL SET 0 +CAN_MOCTR27_NEWDAT SET 0 +CAN_MOCTR27_RTSEL SET 0 +CAN_MOCTR27_RXEN SET 0 +CAN_MOCTR27_RXPND SET 0 +CAN_MOCTR27_RXUPD SET 0 +CAN_MOCTR27_TXEN0 SET 0 +CAN_MOCTR27_TXEN1 SET 0 +CAN_MOCTR27_TXPND SET 0 +CAN_MOCTR27_TXRQ SET 0 + +; CAN Message Object 28 Control Register +CAN_MOCTR28_CTRL SET 0 +CAN_MOCTR28_DIR SET 0 +CAN_MOCTR28_LIST SET 0 +CAN_MOCTR28_MSGLST SET 0 +CAN_MOCTR28_MSGVAL SET 0 +CAN_MOCTR28_NEWDAT SET 0 +CAN_MOCTR28_RTSEL SET 0 +CAN_MOCTR28_RXEN SET 0 +CAN_MOCTR28_RXPND SET 0 +CAN_MOCTR28_RXUPD SET 0 +CAN_MOCTR28_TXEN0 SET 0 +CAN_MOCTR28_TXEN1 SET 0 +CAN_MOCTR28_TXPND SET 0 +CAN_MOCTR28_TXRQ SET 0 + +; CAN Message Object 29 Control Register +CAN_MOCTR29_CTRL SET 0 +CAN_MOCTR29_DIR SET 0 +CAN_MOCTR29_LIST SET 0 +CAN_MOCTR29_MSGLST SET 0 +CAN_MOCTR29_MSGVAL SET 0 +CAN_MOCTR29_NEWDAT SET 0 +CAN_MOCTR29_RTSEL SET 0 +CAN_MOCTR29_RXEN SET 0 +CAN_MOCTR29_RXPND SET 0 +CAN_MOCTR29_RXUPD SET 0 +CAN_MOCTR29_TXEN0 SET 0 +CAN_MOCTR29_TXEN1 SET 0 +CAN_MOCTR29_TXPND SET 0 +CAN_MOCTR29_TXRQ SET 0 + +; CAN Message Object 2 Control Register +CAN_MOCTR2_CTRL SET 0 +CAN_MOCTR2_DIR SET 1 +CAN_MOCTR2_LIST SET 0 +CAN_MOCTR2_MSGLST SET 0 +CAN_MOCTR2_MSGVAL SET 0 +CAN_MOCTR2_NEWDAT SET 0 +CAN_MOCTR2_RTSEL SET 0 +CAN_MOCTR2_RXEN SET 0 +CAN_MOCTR2_RXPND SET 0 +CAN_MOCTR2_RXUPD SET 0 +CAN_MOCTR2_TXEN0 SET 0 +CAN_MOCTR2_TXEN1 SET 0 +CAN_MOCTR2_TXPND SET 0 +CAN_MOCTR2_TXRQ SET 0 + +; CAN Message Object 30 Control Register +CAN_MOCTR30_CTRL SET 0 +CAN_MOCTR30_DIR SET 0 +CAN_MOCTR30_LIST SET 0 +CAN_MOCTR30_MSGLST SET 0 +CAN_MOCTR30_MSGVAL SET 0 +CAN_MOCTR30_NEWDAT SET 0 +CAN_MOCTR30_RTSEL SET 0 +CAN_MOCTR30_RXEN SET 0 +CAN_MOCTR30_RXPND SET 0 +CAN_MOCTR30_RXUPD SET 0 +CAN_MOCTR30_TXEN0 SET 0 +CAN_MOCTR30_TXEN1 SET 0 +CAN_MOCTR30_TXPND SET 0 +CAN_MOCTR30_TXRQ SET 0 + +; CAN Message Object 31 Control Register +CAN_MOCTR31_CTRL SET 0 +CAN_MOCTR31_DIR SET 0 +CAN_MOCTR31_LIST SET 0 +CAN_MOCTR31_MSGLST SET 0 +CAN_MOCTR31_MSGVAL SET 0 +CAN_MOCTR31_NEWDAT SET 0 +CAN_MOCTR31_RTSEL SET 0 +CAN_MOCTR31_RXEN SET 0 +CAN_MOCTR31_RXPND SET 0 +CAN_MOCTR31_RXUPD SET 0 +CAN_MOCTR31_TXEN0 SET 0 +CAN_MOCTR31_TXEN1 SET 0 +CAN_MOCTR31_TXPND SET 0 +CAN_MOCTR31_TXRQ SET 0 + +; CAN Message Object 3 Control Register +CAN_MOCTR3_CTRL SET 0 +CAN_MOCTR3_DIR SET 0 +CAN_MOCTR3_LIST SET 0 +CAN_MOCTR3_MSGLST SET 0 +CAN_MOCTR3_MSGVAL SET 0 +CAN_MOCTR3_NEWDAT SET 0 +CAN_MOCTR3_RTSEL SET 0 +CAN_MOCTR3_RXEN SET 0 +CAN_MOCTR3_RXPND SET 0 +CAN_MOCTR3_RXUPD SET 0 +CAN_MOCTR3_TXEN0 SET 0 +CAN_MOCTR3_TXEN1 SET 0 +CAN_MOCTR3_TXPND SET 0 +CAN_MOCTR3_TXRQ SET 0 + +; CAN Message Object 4 Control Register +CAN_MOCTR4_CTRL SET 0 +CAN_MOCTR4_DIR SET 0 +CAN_MOCTR4_LIST SET 0 +CAN_MOCTR4_MSGLST SET 0 +CAN_MOCTR4_MSGVAL SET 0 +CAN_MOCTR4_NEWDAT SET 0 +CAN_MOCTR4_RTSEL SET 0 +CAN_MOCTR4_RXEN SET 0 +CAN_MOCTR4_RXPND SET 0 +CAN_MOCTR4_RXUPD SET 0 +CAN_MOCTR4_TXEN0 SET 0 +CAN_MOCTR4_TXEN1 SET 0 +CAN_MOCTR4_TXPND SET 0 +CAN_MOCTR4_TXRQ SET 0 + +; CAN Message Object 5 Control Register +CAN_MOCTR5_CTRL SET 1544 +CAN_MOCTR5_DIR SET 0 +CAN_MOCTR5_LIST SET 1 +CAN_MOCTR5_MSGLST SET 0 +CAN_MOCTR5_MSGVAL SET 1 +CAN_MOCTR5_NEWDAT SET 0 +CAN_MOCTR5_RTSEL SET 0 +CAN_MOCTR5_RXEN SET 0 +CAN_MOCTR5_RXPND SET 0 +CAN_MOCTR5_RXUPD SET 0 +CAN_MOCTR5_TXEN0 SET 0 +CAN_MOCTR5_TXEN1 SET 0 +CAN_MOCTR5_TXPND SET 0 +CAN_MOCTR5_TXRQ SET 0 + +; CAN Message Object 6 Control Register +CAN_MOCTR6_CTRL SET 1797 +CAN_MOCTR6_DIR SET 1 +CAN_MOCTR6_LIST SET 1 +CAN_MOCTR6_MSGLST SET 0 +CAN_MOCTR6_MSGVAL SET 1 +CAN_MOCTR6_NEWDAT SET 0 +CAN_MOCTR6_RTSEL SET 0 +CAN_MOCTR6_RXEN SET 0 +CAN_MOCTR6_RXPND SET 0 +CAN_MOCTR6_RXUPD SET 0 +CAN_MOCTR6_TXEN0 SET 0 +CAN_MOCTR6_TXEN1 SET 0 +CAN_MOCTR6_TXPND SET 0 +CAN_MOCTR6_TXRQ SET 0 + +; CAN Message Object 7 Control Register +CAN_MOCTR7_CTRL SET 2310 +CAN_MOCTR7_DIR SET 0 +CAN_MOCTR7_LIST SET 1 +CAN_MOCTR7_MSGLST SET 0 +CAN_MOCTR7_MSGVAL SET 1 +CAN_MOCTR7_NEWDAT SET 0 +CAN_MOCTR7_RTSEL SET 0 +CAN_MOCTR7_RXEN SET 0 +CAN_MOCTR7_RXPND SET 0 +CAN_MOCTR7_RXUPD SET 0 +CAN_MOCTR7_TXEN0 SET 0 +CAN_MOCTR7_TXEN1 SET 0 +CAN_MOCTR7_TXPND SET 0 +CAN_MOCTR7_TXRQ SET 0 + +; CAN Message Object 8 Control Register +CAN_MOCTR8_CTRL SET 1288 +CAN_MOCTR8_DIR SET 0 +CAN_MOCTR8_LIST SET 1 +CAN_MOCTR8_MSGLST SET 0 +CAN_MOCTR8_MSGVAL SET 1 +CAN_MOCTR8_NEWDAT SET 0 +CAN_MOCTR8_RTSEL SET 0 +CAN_MOCTR8_RXEN SET 0 +CAN_MOCTR8_RXPND SET 0 +CAN_MOCTR8_RXUPD SET 0 +CAN_MOCTR8_TXEN0 SET 0 +CAN_MOCTR8_TXEN1 SET 0 +CAN_MOCTR8_TXPND SET 0 +CAN_MOCTR8_TXRQ SET 0 + +; CAN Message Object 9 Control Register +CAN_MOCTR9_CTRL SET 2311 +CAN_MOCTR9_DIR SET 1 +CAN_MOCTR9_LIST SET 1 +CAN_MOCTR9_MSGLST SET 0 +CAN_MOCTR9_MSGVAL SET 1 +CAN_MOCTR9_NEWDAT SET 0 +CAN_MOCTR9_RTSEL SET 0 +CAN_MOCTR9_RXEN SET 0 +CAN_MOCTR9_RXPND SET 0 +CAN_MOCTR9_RXUPD SET 0 +CAN_MOCTR9_TXEN0 SET 0 +CAN_MOCTR9_TXEN1 SET 0 +CAN_MOCTR9_TXPND SET 0 +CAN_MOCTR9_TXRQ SET 0 + +; CAN Message Object 0 Data Register High +CAN_MODATAH0_DB4 SET 0 +CAN_MODATAH0_DB5 SET 0 +CAN_MODATAH0_DB6 SET 0 +CAN_MODATAH0_DB7 SET 0 + +; CAN Message Object 10 Data Register High +CAN_MODATAH10_DB4 SET 0 +CAN_MODATAH10_DB5 SET 0 +CAN_MODATAH10_DB6 SET 0 +CAN_MODATAH10_DB7 SET 0 + +; CAN Message Object 11 Data Register High +CAN_MODATAH11_DB4 SET 0 +CAN_MODATAH11_DB5 SET 0 +CAN_MODATAH11_DB6 SET 0 +CAN_MODATAH11_DB7 SET 0 + +; CAN Message Object 12 Data Register High +CAN_MODATAH12_DB4 SET 0 +CAN_MODATAH12_DB5 SET 0 +CAN_MODATAH12_DB6 SET 0 +CAN_MODATAH12_DB7 SET 0 + +; CAN Message Object 13 Data Register High +CAN_MODATAH13_DB4 SET 0 +CAN_MODATAH13_DB5 SET 0 +CAN_MODATAH13_DB6 SET 0 +CAN_MODATAH13_DB7 SET 0 + +; CAN Message Object 14 Data Register High +CAN_MODATAH14_DB4 SET 0 +CAN_MODATAH14_DB5 SET 0 +CAN_MODATAH14_DB6 SET 0 +CAN_MODATAH14_DB7 SET 0 + +; CAN Message Object 15 Data Register High +CAN_MODATAH15_DB4 SET 0 +CAN_MODATAH15_DB5 SET 0 +CAN_MODATAH15_DB6 SET 0 +CAN_MODATAH15_DB7 SET 0 + +; CAN Message Object 16 Data Register High +CAN_MODATAH16_DB4 SET 0 +CAN_MODATAH16_DB5 SET 0 +CAN_MODATAH16_DB6 SET 0 +CAN_MODATAH16_DB7 SET 0 + +; CAN Message Object 17 Data Register High +CAN_MODATAH17_DB4 SET 0 +CAN_MODATAH17_DB5 SET 0 +CAN_MODATAH17_DB6 SET 0 +CAN_MODATAH17_DB7 SET 0 + +; CAN Message Object 18 Data Register High +CAN_MODATAH18_DB4 SET 0 +CAN_MODATAH18_DB5 SET 0 +CAN_MODATAH18_DB6 SET 0 +CAN_MODATAH18_DB7 SET 0 + +; CAN Message Object 19 Data Register High +CAN_MODATAH19_DB4 SET 0 +CAN_MODATAH19_DB5 SET 0 +CAN_MODATAH19_DB6 SET 0 +CAN_MODATAH19_DB7 SET 0 + +; CAN Message Object 1 Data Register High +CAN_MODATAH1_DB4 SET 0 +CAN_MODATAH1_DB5 SET 0 +CAN_MODATAH1_DB6 SET 0 +CAN_MODATAH1_DB7 SET 0 + +; CAN Message Object 20 Data Register High +CAN_MODATAH20_DB4 SET 0 +CAN_MODATAH20_DB5 SET 0 +CAN_MODATAH20_DB6 SET 0 +CAN_MODATAH20_DB7 SET 0 + +; CAN Message Object 21 Data Register High +CAN_MODATAH21_DB4 SET 0 +CAN_MODATAH21_DB5 SET 0 +CAN_MODATAH21_DB6 SET 0 +CAN_MODATAH21_DB7 SET 0 + +; CAN Message Object 22 Data Register High +CAN_MODATAH22_DB4 SET 0 +CAN_MODATAH22_DB5 SET 0 +CAN_MODATAH22_DB6 SET 0 +CAN_MODATAH22_DB7 SET 0 + +; CAN Message Object 23 Data Register High +CAN_MODATAH23_DB4 SET 0 +CAN_MODATAH23_DB5 SET 0 +CAN_MODATAH23_DB6 SET 0 +CAN_MODATAH23_DB7 SET 0 + +; CAN Message Object 24 Data Register High +CAN_MODATAH24_DB4 SET 0 +CAN_MODATAH24_DB5 SET 0 +CAN_MODATAH24_DB6 SET 0 +CAN_MODATAH24_DB7 SET 0 + +; CAN Message Object 25 Data Register High +CAN_MODATAH25_DB4 SET 0 +CAN_MODATAH25_DB5 SET 0 +CAN_MODATAH25_DB6 SET 0 +CAN_MODATAH25_DB7 SET 0 + +; CAN Message Object 26 Data Register High +CAN_MODATAH26_DB4 SET 0 +CAN_MODATAH26_DB5 SET 0 +CAN_MODATAH26_DB6 SET 0 +CAN_MODATAH26_DB7 SET 0 + +; CAN Message Object 27 Data Register High +CAN_MODATAH27_DB4 SET 0 +CAN_MODATAH27_DB5 SET 0 +CAN_MODATAH27_DB6 SET 0 +CAN_MODATAH27_DB7 SET 0 + +; CAN Message Object 28 Data Register High +CAN_MODATAH28_DB4 SET 0 +CAN_MODATAH28_DB5 SET 0 +CAN_MODATAH28_DB6 SET 0 +CAN_MODATAH28_DB7 SET 0 + +; CAN Message Object 29 Data Register High +CAN_MODATAH29_DB4 SET 0 +CAN_MODATAH29_DB5 SET 0 +CAN_MODATAH29_DB6 SET 0 +CAN_MODATAH29_DB7 SET 0 + +; CAN Message Object 2 Data Register High +CAN_MODATAH2_DB4 SET 0 +CAN_MODATAH2_DB5 SET 0 +CAN_MODATAH2_DB6 SET 0 +CAN_MODATAH2_DB7 SET 0 + +; CAN Message Object 30 Data Register High +CAN_MODATAH30_DB4 SET 0 +CAN_MODATAH30_DB5 SET 0 +CAN_MODATAH30_DB6 SET 0 +CAN_MODATAH30_DB7 SET 0 + +; CAN Message Object 31 Data Register High +CAN_MODATAH31_DB4 SET 0 +CAN_MODATAH31_DB5 SET 0 +CAN_MODATAH31_DB6 SET 0 +CAN_MODATAH31_DB7 SET 0 + +; CAN Message Object 3 Data Register High +CAN_MODATAH3_DB4 SET 0 +CAN_MODATAH3_DB5 SET 0 +CAN_MODATAH3_DB6 SET 0 +CAN_MODATAH3_DB7 SET 0 + +; CAN Message Object 4 Data Register High +CAN_MODATAH4_DB4 SET 0 +CAN_MODATAH4_DB5 SET 0 +CAN_MODATAH4_DB6 SET 0 +CAN_MODATAH4_DB7 SET 0 + +; CAN Message Object 5 Data Register High +CAN_MODATAH5_DB4 SET 0 +CAN_MODATAH5_DB5 SET 0 +CAN_MODATAH5_DB6 SET 0 +CAN_MODATAH5_DB7 SET 0 + +; CAN Message Object 6 Data Register High +CAN_MODATAH6_DB4 SET 0 +CAN_MODATAH6_DB5 SET 0 +CAN_MODATAH6_DB6 SET 0 +CAN_MODATAH6_DB7 SET 0 + +; CAN Message Object 7 Data Register High +CAN_MODATAH7_DB4 SET 0 +CAN_MODATAH7_DB5 SET 0 +CAN_MODATAH7_DB6 SET 0 +CAN_MODATAH7_DB7 SET 0 + +; CAN Message Object 8 Data Register High +CAN_MODATAH8_DB4 SET 0 +CAN_MODATAH8_DB5 SET 0 +CAN_MODATAH8_DB6 SET 0 +CAN_MODATAH8_DB7 SET 0 + +; CAN Message Object 9 Data Register High +CAN_MODATAH9_DB4 SET 0 +CAN_MODATAH9_DB5 SET 0 +CAN_MODATAH9_DB6 SET 0 +CAN_MODATAH9_DB7 SET 0 + +; CAN Message Object 0 Data Register Low +CAN_MODATAL0_DB0 SET 0 +CAN_MODATAL0_DB1 SET 0 +CAN_MODATAL0_DB2 SET 0 +CAN_MODATAL0_DB3 SET 0 + +; CAN Message Object 10 Data Register Low +CAN_MODATAL10_DB0 SET 0 +CAN_MODATAL10_DB1 SET 0 +CAN_MODATAL10_DB2 SET 0 +CAN_MODATAL10_DB3 SET 0 + +; CAN Message Object 11 Data Register Low +CAN_MODATAL11_DB0 SET 0 +CAN_MODATAL11_DB1 SET 0 +CAN_MODATAL11_DB2 SET 0 +CAN_MODATAL11_DB3 SET 0 + +; CAN Message Object 12 Data Register Low +CAN_MODATAL12_DB0 SET 0 +CAN_MODATAL12_DB1 SET 0 +CAN_MODATAL12_DB2 SET 0 +CAN_MODATAL12_DB3 SET 0 + +; CAN Message Object 13 Data Register Low +CAN_MODATAL13_DB0 SET 0 +CAN_MODATAL13_DB1 SET 0 +CAN_MODATAL13_DB2 SET 0 +CAN_MODATAL13_DB3 SET 0 + +; CAN Message Object 14 Data Register Low +CAN_MODATAL14_DB0 SET 0 +CAN_MODATAL14_DB1 SET 0 +CAN_MODATAL14_DB2 SET 0 +CAN_MODATAL14_DB3 SET 0 + +; CAN Message Object 15 Data Register Low +CAN_MODATAL15_DB0 SET 0 +CAN_MODATAL15_DB1 SET 0 +CAN_MODATAL15_DB2 SET 0 +CAN_MODATAL15_DB3 SET 0 + +; CAN Message Object 16 Data Register Low +CAN_MODATAL16_DB0 SET 0 +CAN_MODATAL16_DB1 SET 0 +CAN_MODATAL16_DB2 SET 0 +CAN_MODATAL16_DB3 SET 0 + +; CAN Message Object 17 Data Register Low +CAN_MODATAL17_DB0 SET 0 +CAN_MODATAL17_DB1 SET 0 +CAN_MODATAL17_DB2 SET 0 +CAN_MODATAL17_DB3 SET 0 + +; CAN Message Object 18 Data Register Low +CAN_MODATAL18_DB0 SET 0 +CAN_MODATAL18_DB1 SET 0 +CAN_MODATAL18_DB2 SET 0 +CAN_MODATAL18_DB3 SET 0 + +; CAN Message Object 19 Data Register Low +CAN_MODATAL19_DB0 SET 0 +CAN_MODATAL19_DB1 SET 0 +CAN_MODATAL19_DB2 SET 0 +CAN_MODATAL19_DB3 SET 0 + +; CAN Message Object 1 Data Register Low +CAN_MODATAL1_DB0 SET 0 +CAN_MODATAL1_DB1 SET 0 +CAN_MODATAL1_DB2 SET 0 +CAN_MODATAL1_DB3 SET 0 + +; CAN Message Object 20 Data Register Low +CAN_MODATAL20_DB0 SET 0 +CAN_MODATAL20_DB1 SET 0 +CAN_MODATAL20_DB2 SET 0 +CAN_MODATAL20_DB3 SET 0 + +; CAN Message Object 21 Data Register Low +CAN_MODATAL21_DB0 SET 0 +CAN_MODATAL21_DB1 SET 0 +CAN_MODATAL21_DB2 SET 0 +CAN_MODATAL21_DB3 SET 0 + +; CAN Message Object 22 Data Register Low +CAN_MODATAL22_DB0 SET 0 +CAN_MODATAL22_DB1 SET 0 +CAN_MODATAL22_DB2 SET 0 +CAN_MODATAL22_DB3 SET 0 + +; CAN Message Object 23 Data Register Low +CAN_MODATAL23_DB0 SET 0 +CAN_MODATAL23_DB1 SET 0 +CAN_MODATAL23_DB2 SET 0 +CAN_MODATAL23_DB3 SET 0 + +; CAN Message Object 24 Data Register Low +CAN_MODATAL24_DB0 SET 0 +CAN_MODATAL24_DB1 SET 0 +CAN_MODATAL24_DB2 SET 0 +CAN_MODATAL24_DB3 SET 0 + +; CAN Message Object 25 Data Register Low +CAN_MODATAL25_DB0 SET 0 +CAN_MODATAL25_DB1 SET 0 +CAN_MODATAL25_DB2 SET 0 +CAN_MODATAL25_DB3 SET 0 + +; CAN Message Object 26 Data Register Low +CAN_MODATAL26_DB0 SET 0 +CAN_MODATAL26_DB1 SET 0 +CAN_MODATAL26_DB2 SET 0 +CAN_MODATAL26_DB3 SET 0 + +; CAN Message Object 27 Data Register Low +CAN_MODATAL27_DB0 SET 0 +CAN_MODATAL27_DB1 SET 0 +CAN_MODATAL27_DB2 SET 0 +CAN_MODATAL27_DB3 SET 0 + +; CAN Message Object 28 Data Register Low +CAN_MODATAL28_DB0 SET 0 +CAN_MODATAL28_DB1 SET 0 +CAN_MODATAL28_DB2 SET 0 +CAN_MODATAL28_DB3 SET 0 + +; CAN Message Object 29 Data Register Low +CAN_MODATAL29_DB0 SET 0 +CAN_MODATAL29_DB1 SET 0 +CAN_MODATAL29_DB2 SET 0 +CAN_MODATAL29_DB3 SET 0 + +; CAN Message Object 2 Data Register Low +CAN_MODATAL2_DB0 SET 0 +CAN_MODATAL2_DB1 SET 0 +CAN_MODATAL2_DB2 SET 0 +CAN_MODATAL2_DB3 SET 0 + +; CAN Message Object 30 Data Register Low +CAN_MODATAL30_DB0 SET 0 +CAN_MODATAL30_DB1 SET 0 +CAN_MODATAL30_DB2 SET 0 +CAN_MODATAL30_DB3 SET 0 + +; CAN Message Object 31 Data Register Low +CAN_MODATAL31_DB0 SET 0 +CAN_MODATAL31_DB1 SET 0 +CAN_MODATAL31_DB2 SET 0 +CAN_MODATAL31_DB3 SET 0 + +; CAN Message Object 3 Data Register Low +CAN_MODATAL3_DB0 SET 0 +CAN_MODATAL3_DB1 SET 0 +CAN_MODATAL3_DB2 SET 0 +CAN_MODATAL3_DB3 SET 0 + +; CAN Message Object 4 Data Register Low +CAN_MODATAL4_DB0 SET 0 +CAN_MODATAL4_DB1 SET 0 +CAN_MODATAL4_DB2 SET 0 +CAN_MODATAL4_DB3 SET 0 + +; CAN Message Object 5 Data Register Low +CAN_MODATAL5_DB0 SET 0 +CAN_MODATAL5_DB1 SET 0 +CAN_MODATAL5_DB2 SET 0 +CAN_MODATAL5_DB3 SET 0 + +; CAN Message Object 6 Data Register Low +CAN_MODATAL6_DB0 SET 0 +CAN_MODATAL6_DB1 SET 0 +CAN_MODATAL6_DB2 SET 0 +CAN_MODATAL6_DB3 SET 0 + +; CAN Message Object 7 Data Register Low +CAN_MODATAL7_DB0 SET 0 +CAN_MODATAL7_DB1 SET 0 +CAN_MODATAL7_DB2 SET 0 +CAN_MODATAL7_DB3 SET 0 + +; CAN Message Object 8 Data Register Low +CAN_MODATAL8_DB0 SET 0 +CAN_MODATAL8_DB1 SET 0 +CAN_MODATAL8_DB2 SET 0 +CAN_MODATAL8_DB3 SET 0 + +; CAN Message Object 9 Data Register Low +CAN_MODATAL9_DB0 SET 0 +CAN_MODATAL9_DB1 SET 0 +CAN_MODATAL9_DB2 SET 0 +CAN_MODATAL9_DB3 SET 0 + +; CAN Message Object 0 Function Control Register +CAN_MOFCR0_0 SET 0 +CAN_MOFCR0_0 SET 0 +CAN_MOFCR0_0 SET 0 +CAN_MOFCR0_0 SET 0 +CAN_MOFCR0_DATC SET 0 +CAN_MOFCR0_DLC SET 8 +CAN_MOFCR0_DLCC SET 0 +CAN_MOFCR0_FRREN SET 0 +CAN_MOFCR0_GDFS SET 0 +CAN_MOFCR0_IDC SET 0 +CAN_MOFCR0_MMC SET 0 +CAN_MOFCR0_OVIE SET 0 +CAN_MOFCR0_RMM SET 0 +CAN_MOFCR0_RXIE SET 0 +CAN_MOFCR0_SDT SET 0 +CAN_MOFCR0_STT SET 0 +CAN_MOFCR0_TXIE SET 0 + +; CAN Message Object 10 Function Control Register +CAN_MOFCR10_0 SET 0 +CAN_MOFCR10_0 SET 0 +CAN_MOFCR10_0 SET 0 +CAN_MOFCR10_0 SET 0 +CAN_MOFCR10_DATC SET 0 +CAN_MOFCR10_DLC SET 0 +CAN_MOFCR10_DLCC SET 0 +CAN_MOFCR10_FRREN SET 0 +CAN_MOFCR10_GDFS SET 0 +CAN_MOFCR10_IDC SET 0 +CAN_MOFCR10_MMC SET 0 +CAN_MOFCR10_OVIE SET 0 +CAN_MOFCR10_RMM SET 0 +CAN_MOFCR10_RXIE SET 0 +CAN_MOFCR10_SDT SET 0 +CAN_MOFCR10_STT SET 0 +CAN_MOFCR10_TXIE SET 0 + +; CAN Message Object 11 Function Control Register +CAN_MOFCR11_0 SET 0 +CAN_MOFCR11_0 SET 0 +CAN_MOFCR11_0 SET 0 +CAN_MOFCR11_0 SET 0 +CAN_MOFCR11_DATC SET 0 +CAN_MOFCR11_DLC SET 0 +CAN_MOFCR11_DLCC SET 0 +CAN_MOFCR11_FRREN SET 0 +CAN_MOFCR11_GDFS SET 0 +CAN_MOFCR11_IDC SET 0 +CAN_MOFCR11_MMC SET 0 +CAN_MOFCR11_OVIE SET 0 +CAN_MOFCR11_RMM SET 0 +CAN_MOFCR11_RXIE SET 0 +CAN_MOFCR11_SDT SET 0 +CAN_MOFCR11_STT SET 0 +CAN_MOFCR11_TXIE SET 0 + +; CAN Message Object 12 Function Control Register +CAN_MOFCR12_0 SET 0 +CAN_MOFCR12_0 SET 0 +CAN_MOFCR12_0 SET 0 +CAN_MOFCR12_0 SET 0 +CAN_MOFCR12_DATC SET 0 +CAN_MOFCR12_DLC SET 0 +CAN_MOFCR12_DLCC SET 0 +CAN_MOFCR12_FRREN SET 0 +CAN_MOFCR12_GDFS SET 0 +CAN_MOFCR12_IDC SET 0 +CAN_MOFCR12_MMC SET 0 +CAN_MOFCR12_OVIE SET 0 +CAN_MOFCR12_RMM SET 0 +CAN_MOFCR12_RXIE SET 0 +CAN_MOFCR12_SDT SET 0 +CAN_MOFCR12_STT SET 0 +CAN_MOFCR12_TXIE SET 0 + +; CAN Message Object 13 Function Control Register +CAN_MOFCR13_0 SET 0 +CAN_MOFCR13_0 SET 0 +CAN_MOFCR13_0 SET 0 +CAN_MOFCR13_0 SET 0 +CAN_MOFCR13_DATC SET 0 +CAN_MOFCR13_DLC SET 0 +CAN_MOFCR13_DLCC SET 0 +CAN_MOFCR13_FRREN SET 0 +CAN_MOFCR13_GDFS SET 0 +CAN_MOFCR13_IDC SET 0 +CAN_MOFCR13_MMC SET 0 +CAN_MOFCR13_OVIE SET 0 +CAN_MOFCR13_RMM SET 0 +CAN_MOFCR13_RXIE SET 0 +CAN_MOFCR13_SDT SET 0 +CAN_MOFCR13_STT SET 0 +CAN_MOFCR13_TXIE SET 0 + +; CAN Message Object 14 Function Control Register +CAN_MOFCR14_0 SET 0 +CAN_MOFCR14_0 SET 0 +CAN_MOFCR14_0 SET 0 +CAN_MOFCR14_0 SET 0 +CAN_MOFCR14_DATC SET 0 +CAN_MOFCR14_DLC SET 0 +CAN_MOFCR14_DLCC SET 0 +CAN_MOFCR14_FRREN SET 0 +CAN_MOFCR14_GDFS SET 0 +CAN_MOFCR14_IDC SET 0 +CAN_MOFCR14_MMC SET 0 +CAN_MOFCR14_OVIE SET 0 +CAN_MOFCR14_RMM SET 0 +CAN_MOFCR14_RXIE SET 0 +CAN_MOFCR14_SDT SET 0 +CAN_MOFCR14_STT SET 0 +CAN_MOFCR14_TXIE SET 0 + +; CAN Message Object 15 Function Control Register +CAN_MOFCR15_0 SET 0 +CAN_MOFCR15_0 SET 0 +CAN_MOFCR15_0 SET 0 +CAN_MOFCR15_0 SET 0 +CAN_MOFCR15_DATC SET 0 +CAN_MOFCR15_DLC SET 0 +CAN_MOFCR15_DLCC SET 0 +CAN_MOFCR15_FRREN SET 0 +CAN_MOFCR15_GDFS SET 0 +CAN_MOFCR15_IDC SET 0 +CAN_MOFCR15_MMC SET 0 +CAN_MOFCR15_OVIE SET 0 +CAN_MOFCR15_RMM SET 0 +CAN_MOFCR15_RXIE SET 0 +CAN_MOFCR15_SDT SET 0 +CAN_MOFCR15_STT SET 0 +CAN_MOFCR15_TXIE SET 0 + +; CAN Message Object 16 Function Control Register +CAN_MOFCR16_0 SET 0 +CAN_MOFCR16_0 SET 0 +CAN_MOFCR16_0 SET 0 +CAN_MOFCR16_0 SET 0 +CAN_MOFCR16_DATC SET 0 +CAN_MOFCR16_DLC SET 0 +CAN_MOFCR16_DLCC SET 0 +CAN_MOFCR16_FRREN SET 0 +CAN_MOFCR16_GDFS SET 0 +CAN_MOFCR16_IDC SET 0 +CAN_MOFCR16_MMC SET 0 +CAN_MOFCR16_OVIE SET 0 +CAN_MOFCR16_RMM SET 0 +CAN_MOFCR16_RXIE SET 0 +CAN_MOFCR16_SDT SET 0 +CAN_MOFCR16_STT SET 0 +CAN_MOFCR16_TXIE SET 0 + +; CAN Message Object 17 Function Control Register +CAN_MOFCR17_0 SET 0 +CAN_MOFCR17_0 SET 0 +CAN_MOFCR17_0 SET 0 +CAN_MOFCR17_0 SET 0 +CAN_MOFCR17_DATC SET 0 +CAN_MOFCR17_DLC SET 0 +CAN_MOFCR17_DLCC SET 0 +CAN_MOFCR17_FRREN SET 0 +CAN_MOFCR17_GDFS SET 0 +CAN_MOFCR17_IDC SET 0 +CAN_MOFCR17_MMC SET 0 +CAN_MOFCR17_OVIE SET 0 +CAN_MOFCR17_RMM SET 0 +CAN_MOFCR17_RXIE SET 0 +CAN_MOFCR17_SDT SET 0 +CAN_MOFCR17_STT SET 0 +CAN_MOFCR17_TXIE SET 0 + +; CAN Message Object 18 Function Control Register +CAN_MOFCR18_0 SET 0 +CAN_MOFCR18_0 SET 0 +CAN_MOFCR18_0 SET 0 +CAN_MOFCR18_0 SET 0 +CAN_MOFCR18_DATC SET 0 +CAN_MOFCR18_DLC SET 0 +CAN_MOFCR18_DLCC SET 0 +CAN_MOFCR18_FRREN SET 0 +CAN_MOFCR18_GDFS SET 0 +CAN_MOFCR18_IDC SET 0 +CAN_MOFCR18_MMC SET 0 +CAN_MOFCR18_OVIE SET 0 +CAN_MOFCR18_RMM SET 0 +CAN_MOFCR18_RXIE SET 0 +CAN_MOFCR18_SDT SET 0 +CAN_MOFCR18_STT SET 0 +CAN_MOFCR18_TXIE SET 0 + +; CAN Message Object 19 Function Control Register +CAN_MOFCR19_0 SET 0 +CAN_MOFCR19_0 SET 0 +CAN_MOFCR19_0 SET 0 +CAN_MOFCR19_0 SET 0 +CAN_MOFCR19_DATC SET 0 +CAN_MOFCR19_DLC SET 0 +CAN_MOFCR19_DLCC SET 0 +CAN_MOFCR19_FRREN SET 0 +CAN_MOFCR19_GDFS SET 0 +CAN_MOFCR19_IDC SET 0 +CAN_MOFCR19_MMC SET 0 +CAN_MOFCR19_OVIE SET 0 +CAN_MOFCR19_RMM SET 0 +CAN_MOFCR19_RXIE SET 0 +CAN_MOFCR19_SDT SET 0 +CAN_MOFCR19_STT SET 0 +CAN_MOFCR19_TXIE SET 0 + +; CAN Message Object 1 Function Control Register +CAN_MOFCR1_0 SET 0 +CAN_MOFCR1_0 SET 0 +CAN_MOFCR1_0 SET 0 +CAN_MOFCR1_0 SET 0 +CAN_MOFCR1_DATC SET 0 +CAN_MOFCR1_DLC SET 8 +CAN_MOFCR1_DLCC SET 0 +CAN_MOFCR1_FRREN SET 0 +CAN_MOFCR1_GDFS SET 0 +CAN_MOFCR1_IDC SET 0 +CAN_MOFCR1_MMC SET 0 +CAN_MOFCR1_OVIE SET 0 +CAN_MOFCR1_RMM SET 0 +CAN_MOFCR1_RXIE SET 0 +CAN_MOFCR1_SDT SET 0 +CAN_MOFCR1_STT SET 0 +CAN_MOFCR1_TXIE SET 0 + +; CAN Message Object 20 Function Control Register +CAN_MOFCR20_0 SET 0 +CAN_MOFCR20_0 SET 0 +CAN_MOFCR20_0 SET 0 +CAN_MOFCR20_0 SET 0 +CAN_MOFCR20_DATC SET 0 +CAN_MOFCR20_DLC SET 0 +CAN_MOFCR20_DLCC SET 0 +CAN_MOFCR20_FRREN SET 0 +CAN_MOFCR20_GDFS SET 0 +CAN_MOFCR20_IDC SET 0 +CAN_MOFCR20_MMC SET 0 +CAN_MOFCR20_OVIE SET 0 +CAN_MOFCR20_RMM SET 0 +CAN_MOFCR20_RXIE SET 0 +CAN_MOFCR20_SDT SET 0 +CAN_MOFCR20_STT SET 0 +CAN_MOFCR20_TXIE SET 0 + +; CAN Message Object 21 Function Control Register +CAN_MOFCR21_0 SET 0 +CAN_MOFCR21_0 SET 0 +CAN_MOFCR21_0 SET 0 +CAN_MOFCR21_0 SET 0 +CAN_MOFCR21_DATC SET 0 +CAN_MOFCR21_DLC SET 0 +CAN_MOFCR21_DLCC SET 0 +CAN_MOFCR21_FRREN SET 0 +CAN_MOFCR21_GDFS SET 0 +CAN_MOFCR21_IDC SET 0 +CAN_MOFCR21_MMC SET 0 +CAN_MOFCR21_OVIE SET 0 +CAN_MOFCR21_RMM SET 0 +CAN_MOFCR21_RXIE SET 0 +CAN_MOFCR21_SDT SET 0 +CAN_MOFCR21_STT SET 0 +CAN_MOFCR21_TXIE SET 0 + +; CAN Message Object 22 Function Control Register +CAN_MOFCR22_0 SET 0 +CAN_MOFCR22_0 SET 0 +CAN_MOFCR22_0 SET 0 +CAN_MOFCR22_0 SET 0 +CAN_MOFCR22_DATC SET 0 +CAN_MOFCR22_DLC SET 0 +CAN_MOFCR22_DLCC SET 0 +CAN_MOFCR22_FRREN SET 0 +CAN_MOFCR22_GDFS SET 0 +CAN_MOFCR22_IDC SET 0 +CAN_MOFCR22_MMC SET 0 +CAN_MOFCR22_OVIE SET 0 +CAN_MOFCR22_RMM SET 0 +CAN_MOFCR22_RXIE SET 0 +CAN_MOFCR22_SDT SET 0 +CAN_MOFCR22_STT SET 0 +CAN_MOFCR22_TXIE SET 0 + +; CAN Message Object 23 Function Control Register +CAN_MOFCR23_0 SET 0 +CAN_MOFCR23_0 SET 0 +CAN_MOFCR23_0 SET 0 +CAN_MOFCR23_0 SET 0 +CAN_MOFCR23_DATC SET 0 +CAN_MOFCR23_DLC SET 0 +CAN_MOFCR23_DLCC SET 0 +CAN_MOFCR23_FRREN SET 0 +CAN_MOFCR23_GDFS SET 0 +CAN_MOFCR23_IDC SET 0 +CAN_MOFCR23_MMC SET 0 +CAN_MOFCR23_OVIE SET 0 +CAN_MOFCR23_RMM SET 0 +CAN_MOFCR23_RXIE SET 0 +CAN_MOFCR23_SDT SET 0 +CAN_MOFCR23_STT SET 0 +CAN_MOFCR23_TXIE SET 0 + +; CAN Message Object 24 Function Control Register +CAN_MOFCR24_0 SET 0 +CAN_MOFCR24_0 SET 0 +CAN_MOFCR24_0 SET 0 +CAN_MOFCR24_0 SET 0 +CAN_MOFCR24_DATC SET 0 +CAN_MOFCR24_DLC SET 0 +CAN_MOFCR24_DLCC SET 0 +CAN_MOFCR24_FRREN SET 0 +CAN_MOFCR24_GDFS SET 0 +CAN_MOFCR24_IDC SET 0 +CAN_MOFCR24_MMC SET 0 +CAN_MOFCR24_OVIE SET 0 +CAN_MOFCR24_RMM SET 0 +CAN_MOFCR24_RXIE SET 0 +CAN_MOFCR24_SDT SET 0 +CAN_MOFCR24_STT SET 0 +CAN_MOFCR24_TXIE SET 0 + +; CAN Message Object 25 Function Control Register +CAN_MOFCR25_0 SET 0 +CAN_MOFCR25_0 SET 0 +CAN_MOFCR25_0 SET 0 +CAN_MOFCR25_0 SET 0 +CAN_MOFCR25_DATC SET 0 +CAN_MOFCR25_DLC SET 0 +CAN_MOFCR25_DLCC SET 0 +CAN_MOFCR25_FRREN SET 0 +CAN_MOFCR25_GDFS SET 0 +CAN_MOFCR25_IDC SET 0 +CAN_MOFCR25_MMC SET 0 +CAN_MOFCR25_OVIE SET 0 +CAN_MOFCR25_RMM SET 0 +CAN_MOFCR25_RXIE SET 0 +CAN_MOFCR25_SDT SET 0 +CAN_MOFCR25_STT SET 0 +CAN_MOFCR25_TXIE SET 0 + +; CAN Message Object 26 Function Control Register +CAN_MOFCR26_0 SET 0 +CAN_MOFCR26_0 SET 0 +CAN_MOFCR26_0 SET 0 +CAN_MOFCR26_0 SET 0 +CAN_MOFCR26_DATC SET 0 +CAN_MOFCR26_DLC SET 0 +CAN_MOFCR26_DLCC SET 0 +CAN_MOFCR26_FRREN SET 0 +CAN_MOFCR26_GDFS SET 0 +CAN_MOFCR26_IDC SET 0 +CAN_MOFCR26_MMC SET 0 +CAN_MOFCR26_OVIE SET 0 +CAN_MOFCR26_RMM SET 0 +CAN_MOFCR26_RXIE SET 0 +CAN_MOFCR26_SDT SET 0 +CAN_MOFCR26_STT SET 0 +CAN_MOFCR26_TXIE SET 0 + +; CAN Message Object 27 Function Control Register +CAN_MOFCR27_0 SET 0 +CAN_MOFCR27_0 SET 0 +CAN_MOFCR27_0 SET 0 +CAN_MOFCR27_0 SET 0 +CAN_MOFCR27_DATC SET 0 +CAN_MOFCR27_DLC SET 0 +CAN_MOFCR27_DLCC SET 0 +CAN_MOFCR27_FRREN SET 0 +CAN_MOFCR27_GDFS SET 0 +CAN_MOFCR27_IDC SET 0 +CAN_MOFCR27_MMC SET 0 +CAN_MOFCR27_OVIE SET 0 +CAN_MOFCR27_RMM SET 0 +CAN_MOFCR27_RXIE SET 0 +CAN_MOFCR27_SDT SET 0 +CAN_MOFCR27_STT SET 0 +CAN_MOFCR27_TXIE SET 0 + +; CAN Message Object 28 Function Control Register +CAN_MOFCR28_0 SET 0 +CAN_MOFCR28_0 SET 0 +CAN_MOFCR28_0 SET 0 +CAN_MOFCR28_0 SET 0 +CAN_MOFCR28_DATC SET 0 +CAN_MOFCR28_DLC SET 0 +CAN_MOFCR28_DLCC SET 0 +CAN_MOFCR28_FRREN SET 0 +CAN_MOFCR28_GDFS SET 0 +CAN_MOFCR28_IDC SET 0 +CAN_MOFCR28_MMC SET 0 +CAN_MOFCR28_OVIE SET 0 +CAN_MOFCR28_RMM SET 0 +CAN_MOFCR28_RXIE SET 0 +CAN_MOFCR28_SDT SET 0 +CAN_MOFCR28_STT SET 0 +CAN_MOFCR28_TXIE SET 0 + +; CAN Message Object 29 Function Control Register +CAN_MOFCR29_0 SET 0 +CAN_MOFCR29_0 SET 0 +CAN_MOFCR29_0 SET 0 +CAN_MOFCR29_0 SET 0 +CAN_MOFCR29_DATC SET 0 +CAN_MOFCR29_DLC SET 0 +CAN_MOFCR29_DLCC SET 0 +CAN_MOFCR29_FRREN SET 0 +CAN_MOFCR29_GDFS SET 0 +CAN_MOFCR29_IDC SET 0 +CAN_MOFCR29_MMC SET 0 +CAN_MOFCR29_OVIE SET 0 +CAN_MOFCR29_RMM SET 0 +CAN_MOFCR29_RXIE SET 0 +CAN_MOFCR29_SDT SET 0 +CAN_MOFCR29_STT SET 0 +CAN_MOFCR29_TXIE SET 0 + +; CAN Message Object 2 Function Control Register +CAN_MOFCR2_0 SET 0 +CAN_MOFCR2_0 SET 0 +CAN_MOFCR2_0 SET 0 +CAN_MOFCR2_0 SET 0 +CAN_MOFCR2_DATC SET 0 +CAN_MOFCR2_DLC SET 8 +CAN_MOFCR2_DLCC SET 0 +CAN_MOFCR2_FRREN SET 0 +CAN_MOFCR2_GDFS SET 0 +CAN_MOFCR2_IDC SET 0 +CAN_MOFCR2_MMC SET 0 +CAN_MOFCR2_OVIE SET 0 +CAN_MOFCR2_RMM SET 0 +CAN_MOFCR2_RXIE SET 0 +CAN_MOFCR2_SDT SET 0 +CAN_MOFCR2_STT SET 0 +CAN_MOFCR2_TXIE SET 0 + +; CAN Message Object 30 Function Control Register +CAN_MOFCR30_0 SET 0 +CAN_MOFCR30_0 SET 0 +CAN_MOFCR30_0 SET 0 +CAN_MOFCR30_0 SET 0 +CAN_MOFCR30_DATC SET 0 +CAN_MOFCR30_DLC SET 0 +CAN_MOFCR30_DLCC SET 0 +CAN_MOFCR30_FRREN SET 0 +CAN_MOFCR30_GDFS SET 0 +CAN_MOFCR30_IDC SET 0 +CAN_MOFCR30_MMC SET 0 +CAN_MOFCR30_OVIE SET 0 +CAN_MOFCR30_RMM SET 0 +CAN_MOFCR30_RXIE SET 0 +CAN_MOFCR30_SDT SET 0 +CAN_MOFCR30_STT SET 0 +CAN_MOFCR30_TXIE SET 0 + +; CAN Message Object 31 Function Control Register +CAN_MOFCR31_0 SET 0 +CAN_MOFCR31_0 SET 0 +CAN_MOFCR31_0 SET 0 +CAN_MOFCR31_0 SET 0 +CAN_MOFCR31_DATC SET 0 +CAN_MOFCR31_DLC SET 0 +CAN_MOFCR31_DLCC SET 0 +CAN_MOFCR31_FRREN SET 0 +CAN_MOFCR31_GDFS SET 0 +CAN_MOFCR31_IDC SET 0 +CAN_MOFCR31_MMC SET 0 +CAN_MOFCR31_OVIE SET 0 +CAN_MOFCR31_RMM SET 0 +CAN_MOFCR31_RXIE SET 0 +CAN_MOFCR31_SDT SET 0 +CAN_MOFCR31_STT SET 0 +CAN_MOFCR31_TXIE SET 0 + +; CAN Message Object 3 Function Control Register +CAN_MOFCR3_0 SET 0 +CAN_MOFCR3_0 SET 0 +CAN_MOFCR3_0 SET 0 +CAN_MOFCR3_0 SET 0 +CAN_MOFCR3_DATC SET 0 +CAN_MOFCR3_DLC SET 0 +CAN_MOFCR3_DLCC SET 0 +CAN_MOFCR3_FRREN SET 0 +CAN_MOFCR3_GDFS SET 0 +CAN_MOFCR3_IDC SET 0 +CAN_MOFCR3_MMC SET 0 +CAN_MOFCR3_OVIE SET 0 +CAN_MOFCR3_RMM SET 0 +CAN_MOFCR3_RXIE SET 0 +CAN_MOFCR3_SDT SET 0 +CAN_MOFCR3_STT SET 0 +CAN_MOFCR3_TXIE SET 0 + +; CAN Message Object 4 Function Control Register +CAN_MOFCR4_0 SET 0 +CAN_MOFCR4_0 SET 0 +CAN_MOFCR4_0 SET 0 +CAN_MOFCR4_0 SET 0 +CAN_MOFCR4_DATC SET 0 +CAN_MOFCR4_DLC SET 0 +CAN_MOFCR4_DLCC SET 0 +CAN_MOFCR4_FRREN SET 0 +CAN_MOFCR4_GDFS SET 0 +CAN_MOFCR4_IDC SET 0 +CAN_MOFCR4_MMC SET 0 +CAN_MOFCR4_OVIE SET 0 +CAN_MOFCR4_RMM SET 0 +CAN_MOFCR4_RXIE SET 0 +CAN_MOFCR4_SDT SET 0 +CAN_MOFCR4_STT SET 0 +CAN_MOFCR4_TXIE SET 0 + +; CAN Message Object 5 Function Control Register +CAN_MOFCR5_0 SET 0 +CAN_MOFCR5_0 SET 0 +CAN_MOFCR5_0 SET 0 +CAN_MOFCR5_0 SET 0 +CAN_MOFCR5_DATC SET 0 +CAN_MOFCR5_DLC SET 8 +CAN_MOFCR5_DLCC SET 0 +CAN_MOFCR5_FRREN SET 0 +CAN_MOFCR5_GDFS SET 0 +CAN_MOFCR5_IDC SET 0 +CAN_MOFCR5_MMC SET 0 +CAN_MOFCR5_OVIE SET 0 +CAN_MOFCR5_RMM SET 0 +CAN_MOFCR5_RXIE SET 0 +CAN_MOFCR5_SDT SET 0 +CAN_MOFCR5_STT SET 0 +CAN_MOFCR5_TXIE SET 0 + +; CAN Message Object 6 Function Control Register +CAN_MOFCR6_0 SET 0 +CAN_MOFCR6_0 SET 0 +CAN_MOFCR6_0 SET 0 +CAN_MOFCR6_0 SET 0 +CAN_MOFCR6_DATC SET 0 +CAN_MOFCR6_DLC SET 8 +CAN_MOFCR6_DLCC SET 0 +CAN_MOFCR6_FRREN SET 0 +CAN_MOFCR6_GDFS SET 0 +CAN_MOFCR6_IDC SET 0 +CAN_MOFCR6_MMC SET 0 +CAN_MOFCR6_OVIE SET 0 +CAN_MOFCR6_RMM SET 0 +CAN_MOFCR6_RXIE SET 0 +CAN_MOFCR6_SDT SET 0 +CAN_MOFCR6_STT SET 0 +CAN_MOFCR6_TXIE SET 0 + +; CAN Message Object 7 Function Control Register +CAN_MOFCR7_0 SET 0 +CAN_MOFCR7_0 SET 0 +CAN_MOFCR7_0 SET 0 +CAN_MOFCR7_0 SET 0 +CAN_MOFCR7_DATC SET 0 +CAN_MOFCR7_DLC SET 8 +CAN_MOFCR7_DLCC SET 0 +CAN_MOFCR7_FRREN SET 0 +CAN_MOFCR7_GDFS SET 0 +CAN_MOFCR7_IDC SET 0 +CAN_MOFCR7_MMC SET 0 +CAN_MOFCR7_OVIE SET 0 +CAN_MOFCR7_RMM SET 0 +CAN_MOFCR7_RXIE SET 0 +CAN_MOFCR7_SDT SET 0 +CAN_MOFCR7_STT SET 0 +CAN_MOFCR7_TXIE SET 0 + +; CAN Message Object 8 Function Control Register +CAN_MOFCR8_0 SET 0 +CAN_MOFCR8_0 SET 0 +CAN_MOFCR8_0 SET 0 +CAN_MOFCR8_0 SET 0 +CAN_MOFCR8_DATC SET 0 +CAN_MOFCR8_DLC SET 8 +CAN_MOFCR8_DLCC SET 0 +CAN_MOFCR8_FRREN SET 0 +CAN_MOFCR8_GDFS SET 0 +CAN_MOFCR8_IDC SET 0 +CAN_MOFCR8_MMC SET 0 +CAN_MOFCR8_OVIE SET 0 +CAN_MOFCR8_RMM SET 0 +CAN_MOFCR8_RXIE SET 0 +CAN_MOFCR8_SDT SET 0 +CAN_MOFCR8_STT SET 0 +CAN_MOFCR8_TXIE SET 0 + +; CAN Message Object 9 Function Control Register +CAN_MOFCR9_0 SET 0 +CAN_MOFCR9_0 SET 0 +CAN_MOFCR9_0 SET 0 +CAN_MOFCR9_0 SET 0 +CAN_MOFCR9_DATC SET 0 +CAN_MOFCR9_DLC SET 8 +CAN_MOFCR9_DLCC SET 0 +CAN_MOFCR9_FRREN SET 0 +CAN_MOFCR9_GDFS SET 0 +CAN_MOFCR9_IDC SET 0 +CAN_MOFCR9_MMC SET 0 +CAN_MOFCR9_OVIE SET 0 +CAN_MOFCR9_RMM SET 0 +CAN_MOFCR9_RXIE SET 0 +CAN_MOFCR9_SDT SET 0 +CAN_MOFCR9_STT SET 0 +CAN_MOFCR9_TXIE SET 0 + +; CAN Message Object 0 FIFO/Gateway Pointer Register +CAN_MOFGPR0_BOT SET 255 +CAN_MOFGPR0_CUR SET 255 +CAN_MOFGPR0_SEL SET 255 +CAN_MOFGPR0_TOP SET 255 + +; CAN Message Object 10 FIFO/Gateway Pointer Register +CAN_MOFGPR10_BOT SET 255 +CAN_MOFGPR10_CUR SET 255 +CAN_MOFGPR10_SEL SET 255 +CAN_MOFGPR10_TOP SET 255 + +; CAN Message Object 11 FIFO/Gateway Pointer Register +CAN_MOFGPR11_BOT SET 255 +CAN_MOFGPR11_CUR SET 255 +CAN_MOFGPR11_SEL SET 255 +CAN_MOFGPR11_TOP SET 255 + +; CAN Message Object 12 FIFO/Gateway Pointer Register +CAN_MOFGPR12_BOT SET 255 +CAN_MOFGPR12_CUR SET 255 +CAN_MOFGPR12_SEL SET 255 +CAN_MOFGPR12_TOP SET 255 + +; CAN Message Object 13 FIFO/Gateway Pointer Register +CAN_MOFGPR13_BOT SET 255 +CAN_MOFGPR13_CUR SET 255 +CAN_MOFGPR13_SEL SET 255 +CAN_MOFGPR13_TOP SET 255 + +; CAN Message Object 14 FIFO/Gateway Pointer Register +CAN_MOFGPR14_BOT SET 255 +CAN_MOFGPR14_CUR SET 255 +CAN_MOFGPR14_SEL SET 255 +CAN_MOFGPR14_TOP SET 255 + +; CAN Message Object 15 FIFO/Gateway Pointer Register +CAN_MOFGPR15_BOT SET 255 +CAN_MOFGPR15_CUR SET 255 +CAN_MOFGPR15_SEL SET 255 +CAN_MOFGPR15_TOP SET 255 + +; CAN Message Object 16 FIFO/Gateway Pointer Register +CAN_MOFGPR16_BOT SET 255 +CAN_MOFGPR16_CUR SET 255 +CAN_MOFGPR16_SEL SET 255 +CAN_MOFGPR16_TOP SET 255 + +; CAN Message Object 17 FIFO/Gateway Pointer Register +CAN_MOFGPR17_BOT SET 255 +CAN_MOFGPR17_CUR SET 255 +CAN_MOFGPR17_SEL SET 255 +CAN_MOFGPR17_TOP SET 255 + +; CAN Message Object 18 FIFO/Gateway Pointer Register +CAN_MOFGPR18_BOT SET 255 +CAN_MOFGPR18_CUR SET 255 +CAN_MOFGPR18_SEL SET 255 +CAN_MOFGPR18_TOP SET 255 + +; CAN Message Object 19 FIFO/Gateway Pointer Register +CAN_MOFGPR19_BOT SET 255 +CAN_MOFGPR19_CUR SET 255 +CAN_MOFGPR19_SEL SET 255 +CAN_MOFGPR19_TOP SET 255 + +; CAN Message Object 1 FIFO/Gateway Pointer Register +CAN_MOFGPR1_BOT SET 255 +CAN_MOFGPR1_CUR SET 255 +CAN_MOFGPR1_SEL SET 255 +CAN_MOFGPR1_TOP SET 255 + +; CAN Message Object 20 FIFO/Gateway Pointer Register +CAN_MOFGPR20_BOT SET 255 +CAN_MOFGPR20_CUR SET 255 +CAN_MOFGPR20_SEL SET 255 +CAN_MOFGPR20_TOP SET 255 + +; CAN Message Object 21 FIFO/Gateway Pointer Register +CAN_MOFGPR21_BOT SET 255 +CAN_MOFGPR21_CUR SET 255 +CAN_MOFGPR21_SEL SET 255 +CAN_MOFGPR21_TOP SET 255 + +; CAN Message Object 22 FIFO/Gateway Pointer Register +CAN_MOFGPR22_BOT SET 255 +CAN_MOFGPR22_CUR SET 255 +CAN_MOFGPR22_SEL SET 255 +CAN_MOFGPR22_TOP SET 255 + +; CAN Message Object 23 FIFO/Gateway Pointer Register +CAN_MOFGPR23_BOT SET 255 +CAN_MOFGPR23_CUR SET 255 +CAN_MOFGPR23_SEL SET 255 +CAN_MOFGPR23_TOP SET 255 + +; CAN Message Object 24 FIFO/Gateway Pointer Register +CAN_MOFGPR24_BOT SET 255 +CAN_MOFGPR24_CUR SET 255 +CAN_MOFGPR24_SEL SET 255 +CAN_MOFGPR24_TOP SET 255 + +; CAN Message Object 25 FIFO/Gateway Pointer Register +CAN_MOFGPR25_BOT SET 255 +CAN_MOFGPR25_CUR SET 255 +CAN_MOFGPR25_SEL SET 255 +CAN_MOFGPR25_TOP SET 255 + +; CAN Message Object 26 FIFO/Gateway Pointer Register +CAN_MOFGPR26_BOT SET 255 +CAN_MOFGPR26_CUR SET 255 +CAN_MOFGPR26_SEL SET 255 +CAN_MOFGPR26_TOP SET 255 + +; CAN Message Object 27 FIFO/Gateway Pointer Register +CAN_MOFGPR27_BOT SET 255 +CAN_MOFGPR27_CUR SET 255 +CAN_MOFGPR27_SEL SET 255 +CAN_MOFGPR27_TOP SET 255 + +; CAN Message Object 28 FIFO/Gateway Pointer Register +CAN_MOFGPR28_BOT SET 255 +CAN_MOFGPR28_CUR SET 255 +CAN_MOFGPR28_SEL SET 255 +CAN_MOFGPR28_TOP SET 255 + +; CAN Message Object 29 FIFO/Gateway Pointer Register +CAN_MOFGPR29_BOT SET 255 +CAN_MOFGPR29_CUR SET 255 +CAN_MOFGPR29_SEL SET 255 +CAN_MOFGPR29_TOP SET 255 + +; CAN Message Object 2 FIFO/Gateway Pointer Register +CAN_MOFGPR2_BOT SET 255 +CAN_MOFGPR2_CUR SET 255 +CAN_MOFGPR2_SEL SET 255 +CAN_MOFGPR2_TOP SET 255 + +; CAN Message Object 30 FIFO/Gateway Pointer Register +CAN_MOFGPR30_BOT SET 255 +CAN_MOFGPR30_CUR SET 255 +CAN_MOFGPR30_SEL SET 255 +CAN_MOFGPR30_TOP SET 255 + +; CAN Message Object 31 FIFO/Gateway Pointer Register +CAN_MOFGPR31_BOT SET 255 +CAN_MOFGPR31_CUR SET 255 +CAN_MOFGPR31_SEL SET 255 +CAN_MOFGPR31_TOP SET 255 + +; CAN Message Object 3 FIFO/Gateway Pointer Register +CAN_MOFGPR3_BOT SET 255 +CAN_MOFGPR3_CUR SET 255 +CAN_MOFGPR3_SEL SET 255 +CAN_MOFGPR3_TOP SET 255 + +; CAN Message Object 4 FIFO/Gateway Pointer Register +CAN_MOFGPR4_BOT SET 255 +CAN_MOFGPR4_CUR SET 255 +CAN_MOFGPR4_SEL SET 255 +CAN_MOFGPR4_TOP SET 255 + +; CAN Message Object 5 FIFO/Gateway Pointer Register +CAN_MOFGPR5_BOT SET 255 +CAN_MOFGPR5_CUR SET 255 +CAN_MOFGPR5_SEL SET 255 +CAN_MOFGPR5_TOP SET 255 + +; CAN Message Object 6 FIFO/Gateway Pointer Register +CAN_MOFGPR6_BOT SET 255 +CAN_MOFGPR6_CUR SET 255 +CAN_MOFGPR6_SEL SET 255 +CAN_MOFGPR6_TOP SET 255 + +; CAN Message Object 7 FIFO/Gateway Pointer Register +CAN_MOFGPR7_BOT SET 255 +CAN_MOFGPR7_CUR SET 255 +CAN_MOFGPR7_SEL SET 255 +CAN_MOFGPR7_TOP SET 255 + +; CAN Message Object 8 FIFO/Gateway Pointer Register +CAN_MOFGPR8_BOT SET 255 +CAN_MOFGPR8_CUR SET 255 +CAN_MOFGPR8_SEL SET 255 +CAN_MOFGPR8_TOP SET 255 + +; CAN Message Object 9 FIFO/Gateway Pointer Register +CAN_MOFGPR9_BOT SET 255 +CAN_MOFGPR9_CUR SET 255 +CAN_MOFGPR9_SEL SET 255 +CAN_MOFGPR9_TOP SET 255 + +; CAN Message Object 0 Interrupt Pointer Register +CAN_MOIPR0_CFCVAL SET 0 +CAN_MOIPR0_MPN SET 0 +CAN_MOIPR0_RXINP SET 0 +CAN_MOIPR0_TXINP SET 0 + +; CAN Message Object 10 Interrupt Pointer Register +CAN_MOIPR10_CFCVAL SET 0 +CAN_MOIPR10_MPN SET 10 +CAN_MOIPR10_RXINP SET 0 +CAN_MOIPR10_TXINP SET 0 + +; CAN Message Object 11 Interrupt Pointer Register +CAN_MOIPR11_CFCVAL SET 0 +CAN_MOIPR11_MPN SET 11 +CAN_MOIPR11_RXINP SET 0 +CAN_MOIPR11_TXINP SET 0 + +; CAN Message Object 12 Interrupt Pointer Register +CAN_MOIPR12_CFCVAL SET 0 +CAN_MOIPR12_MPN SET 12 +CAN_MOIPR12_RXINP SET 0 +CAN_MOIPR12_TXINP SET 0 + +; CAN Message Object 13 Interrupt Pointer Register +CAN_MOIPR13_CFCVAL SET 0 +CAN_MOIPR13_MPN SET 13 +CAN_MOIPR13_RXINP SET 0 +CAN_MOIPR13_TXINP SET 0 + +; CAN Message Object 14 Interrupt Pointer Register +CAN_MOIPR14_CFCVAL SET 0 +CAN_MOIPR14_MPN SET 14 +CAN_MOIPR14_RXINP SET 0 +CAN_MOIPR14_TXINP SET 0 + +; CAN Message Object 15 Interrupt Pointer Register +CAN_MOIPR15_CFCVAL SET 0 +CAN_MOIPR15_MPN SET 15 +CAN_MOIPR15_RXINP SET 0 +CAN_MOIPR15_TXINP SET 0 + +; CAN Message Object 16 Interrupt Pointer Register +CAN_MOIPR16_CFCVAL SET 0 +CAN_MOIPR16_MPN SET 16 +CAN_MOIPR16_RXINP SET 0 +CAN_MOIPR16_TXINP SET 0 + +; CAN Message Object 17 Interrupt Pointer Register +CAN_MOIPR17_CFCVAL SET 0 +CAN_MOIPR17_MPN SET 17 +CAN_MOIPR17_RXINP SET 0 +CAN_MOIPR17_TXINP SET 0 + +; CAN Message Object 18 Interrupt Pointer Register +CAN_MOIPR18_CFCVAL SET 0 +CAN_MOIPR18_MPN SET 18 +CAN_MOIPR18_RXINP SET 0 +CAN_MOIPR18_TXINP SET 0 + +; CAN Message Object 19 Interrupt Pointer Register +CAN_MOIPR19_CFCVAL SET 0 +CAN_MOIPR19_MPN SET 19 +CAN_MOIPR19_RXINP SET 0 +CAN_MOIPR19_TXINP SET 0 + +; CAN Message Object 1 Interrupt Pointer Register +CAN_MOIPR1_CFCVAL SET 0 +CAN_MOIPR1_MPN SET 1 +CAN_MOIPR1_RXINP SET 1 +CAN_MOIPR1_TXINP SET 0 + +; CAN Message Object 20 Interrupt Pointer Register +CAN_MOIPR20_CFCVAL SET 0 +CAN_MOIPR20_MPN SET 20 +CAN_MOIPR20_RXINP SET 0 +CAN_MOIPR20_TXINP SET 0 + +; CAN Message Object 21 Interrupt Pointer Register +CAN_MOIPR21_CFCVAL SET 0 +CAN_MOIPR21_MPN SET 21 +CAN_MOIPR21_RXINP SET 0 +CAN_MOIPR21_TXINP SET 0 + +; CAN Message Object 22 Interrupt Pointer Register +CAN_MOIPR22_CFCVAL SET 0 +CAN_MOIPR22_MPN SET 22 +CAN_MOIPR22_RXINP SET 0 +CAN_MOIPR22_TXINP SET 0 + +; CAN Message Object 23 Interrupt Pointer Register +CAN_MOIPR23_CFCVAL SET 0 +CAN_MOIPR23_MPN SET 23 +CAN_MOIPR23_RXINP SET 0 +CAN_MOIPR23_TXINP SET 0 + +; CAN Message Object 24 Interrupt Pointer Register +CAN_MOIPR24_CFCVAL SET 0 +CAN_MOIPR24_MPN SET 24 +CAN_MOIPR24_RXINP SET 0 +CAN_MOIPR24_TXINP SET 0 + +; CAN Message Object 25 Interrupt Pointer Register +CAN_MOIPR25_CFCVAL SET 0 +CAN_MOIPR25_MPN SET 25 +CAN_MOIPR25_RXINP SET 0 +CAN_MOIPR25_TXINP SET 0 + +; CAN Message Object 26 Interrupt Pointer Register +CAN_MOIPR26_CFCVAL SET 0 +CAN_MOIPR26_MPN SET 26 +CAN_MOIPR26_RXINP SET 0 +CAN_MOIPR26_TXINP SET 0 + +; CAN Message Object 27 Interrupt Pointer Register +CAN_MOIPR27_CFCVAL SET 0 +CAN_MOIPR27_MPN SET 27 +CAN_MOIPR27_RXINP SET 0 +CAN_MOIPR27_TXINP SET 0 + +; CAN Message Object 28 Interrupt Pointer Register +CAN_MOIPR28_CFCVAL SET 0 +CAN_MOIPR28_MPN SET 28 +CAN_MOIPR28_RXINP SET 0 +CAN_MOIPR28_TXINP SET 0 + +; CAN Message Object 29 Interrupt Pointer Register +CAN_MOIPR29_CFCVAL SET 0 +CAN_MOIPR29_MPN SET 29 +CAN_MOIPR29_RXINP SET 0 +CAN_MOIPR29_TXINP SET 0 + +; CAN Message Object 2 Interrupt Pointer Register +CAN_MOIPR2_CFCVAL SET 0 +CAN_MOIPR2_MPN SET 2 +CAN_MOIPR2_RXINP SET 0 +CAN_MOIPR2_TXINP SET 0 + +; CAN Message Object 30 Interrupt Pointer Register +CAN_MOIPR30_CFCVAL SET 0 +CAN_MOIPR30_MPN SET 30 +CAN_MOIPR30_RXINP SET 0 +CAN_MOIPR30_TXINP SET 0 + +; CAN Message Object 31 Interrupt Pointer Register +CAN_MOIPR31_CFCVAL SET 0 +CAN_MOIPR31_MPN SET 31 +CAN_MOIPR31_RXINP SET 0 +CAN_MOIPR31_TXINP SET 0 + +; CAN Message Object 3 Interrupt Pointer Register +CAN_MOIPR3_CFCVAL SET 0 +CAN_MOIPR3_MPN SET 3 +CAN_MOIPR3_RXINP SET 0 +CAN_MOIPR3_TXINP SET 0 + +; CAN Message Object 4 Interrupt Pointer Register +CAN_MOIPR4_CFCVAL SET 0 +CAN_MOIPR4_MPN SET 4 +CAN_MOIPR4_RXINP SET 0 +CAN_MOIPR4_TXINP SET 0 + +; CAN Message Object 5 Interrupt Pointer Register +CAN_MOIPR5_CFCVAL SET 0 +CAN_MOIPR5_MPN SET 5 +CAN_MOIPR5_RXINP SET 0 +CAN_MOIPR5_TXINP SET 0 + +; CAN Message Object 6 Interrupt Pointer Register +CAN_MOIPR6_CFCVAL SET 0 +CAN_MOIPR6_MPN SET 6 +CAN_MOIPR6_RXINP SET 0 +CAN_MOIPR6_TXINP SET 0 + +; CAN Message Object 7 Interrupt Pointer Register +CAN_MOIPR7_CFCVAL SET 0 +CAN_MOIPR7_MPN SET 7 +CAN_MOIPR7_RXINP SET 0 +CAN_MOIPR7_TXINP SET 0 + +; CAN Message Object 8 Interrupt Pointer Register +CAN_MOIPR8_CFCVAL SET 0 +CAN_MOIPR8_MPN SET 8 +CAN_MOIPR8_RXINP SET 0 +CAN_MOIPR8_TXINP SET 0 + +; CAN Message Object 9 Interrupt Pointer Register +CAN_MOIPR9_CFCVAL SET 0 +CAN_MOIPR9_MPN SET 9 +CAN_MOIPR9_RXINP SET 0 +CAN_MOIPR9_TXINP SET 0 + +; Message Index Register 0 +CAN_MSID0_INDEX SET 0 + +; Message Index Register 1 +CAN_MSID1_INDEX SET 0 + +; Message Index Mask Register +CAN_MSIMASK_IM SET 0 + +; Message Pending Register 0 +CAN_MSPND0_PND SET 0 + +; Message Pending Register 1 +CAN_MSPND1_PND SET 0 + +; Node 0 Bit Timing Register +CAN_NBTR0_0 SET 0 +CAN_NBTR0_BRP SET 47 +CAN_NBTR0_DIV8 SET 0 +CAN_NBTR0_SJW SET 1 +CAN_NBTR0_TSEG1 SET 4 +CAN_NBTR0_TSEG2 SET 3 + +; Node 1 Bit Timing Register +CAN_NBTR1_0 SET 0 +CAN_NBTR1_BRP SET 31 +CAN_NBTR1_DIV8 SET 0 +CAN_NBTR1_SJW SET 1 +CAN_NBTR1_TSEG1 SET 8 +CAN_NBTR1_TSEG2 SET 1 + +; Node 0 Control Register +CAN_NCR0_0 SET 0 +CAN_NCR0_ALIE SET 0 +CAN_NCR0_CALM SET 0 +CAN_NCR0_CANDIS SET 0 +CAN_NCR0_CCE SET 0 +CAN_NCR0_INIT SET 0 +CAN_NCR0_LECIE SET 0 +CAN_NCR0_TRIE SET 0 + +; Node 1 Control Register +CAN_NCR1_0 SET 0 +CAN_NCR1_0 SET 0 +CAN_NCR1_ALIE SET 0 +CAN_NCR1_CALM SET 0 +CAN_NCR1_CANDIS SET 0 +CAN_NCR1_CCE SET 0 +CAN_NCR1_INIT SET 1 +CAN_NCR1_LECIE SET 0 +CAN_NCR1_TRIE SET 0 + +; Node 0 Error Counter Register +CAN_NECNT0_0 SET 0 +CAN_NECNT0_EWRNLVL SET 96 +CAN_NECNT0_LEINC SET 0 +CAN_NECNT0_LETD SET 0 +CAN_NECNT0_REC SET 0 +CAN_NECNT0_TEC SET 0 + +; Node 1 Error Counter Register +CAN_NECNT1_0 SET 0 +CAN_NECNT1_EWRNLVL SET 96 +CAN_NECNT1_LEINC SET 0 +CAN_NECNT1_LETD SET 0 +CAN_NECNT1_REC SET 0 +CAN_NECNT1_TEC SET 0 + +; Node 0 Frame Counter Register +CAN_NFCR0_0 SET 0 +CAN_NFCR0_0 SET 0 +CAN_NFCR0_CFC SET 0 +CAN_NFCR0_CFCIE SET 0 +CAN_NFCR0_CFCOV SET 0 +CAN_NFCR0_CFMOD SET 0 +CAN_NFCR0_CFSEL SET 0 + +; Node 1 Frame Counter Register +CAN_NFCR1_0 SET 0 +CAN_NFCR1_0 SET 0 +CAN_NFCR1_CFC SET 0 +CAN_NFCR1_CFCIE SET 0 +CAN_NFCR1_CFCOV SET 0 +CAN_NFCR1_CFMOD SET 0 +CAN_NFCR1_CFSEL SET 0 + +; Node 0 Interrupt Pointer Register +CAN_NIPR0_0 SET 0 +CAN_NIPR0_ALINP SET 0 +CAN_NIPR0_CFCINP SET 0 +CAN_NIPR0_LECINP SET 0 +CAN_NIPR0_TRINP SET 0 + +; Node 1 Interrupt Pointer Register +CAN_NIPR1_0 SET 0 +CAN_NIPR1_ALINP SET 0 +CAN_NIPR1_CFCINP SET 0 +CAN_NIPR1_LECINP SET 0 +CAN_NIPR1_TRINP SET 0 + +; Node 0 Port Control Register +CAN_NPCR0_0 SET 0 +CAN_NPCR0_0 SET 0 +CAN_NPCR0_LBM SET 0 +CAN_NPCR0_RXSEL SET 0 + +; Node 1 Port Control Register +CAN_NPCR1_0 SET 0 +CAN_NPCR1_0 SET 0 +CAN_NPCR1_LBM SET 0 +CAN_NPCR1_RXSEL SET 0 + +; Node 0 Status Register +CAN_NSR0_0 SET 0 +CAN_NSR0_ALERT SET 0 +CAN_NSR0_BOFF SET 0 +CAN_NSR0_EWRN SET 0 +CAN_NSR0_LEC SET 0 +CAN_NSR0_LLE SET 0 +CAN_NSR0_LOE SET 0 +CAN_NSR0_RXOK SET 0 +CAN_NSR0_TXOK SET 0 + +; Node 1 Status Register +CAN_NSR1_0 SET 0 +CAN_NSR1_ALERT SET 0 +CAN_NSR1_BOFF SET 0 +CAN_NSR1_EWRN SET 0 +CAN_NSR1_LEC SET 0 +CAN_NSR1_LLE SET 0 +CAN_NSR1_LOE SET 0 +CAN_NSR1_RXOK SET 0 +CAN_NSR1_TXOK SET 0 + +; Panel Control Register +CAN_PANCTR_0 SET 0 +CAN_PANCTR_BUSY SET 0 +CAN_PANCTR_PANAR1 SET 0 +CAN_PANCTR_PANAR2 SET 0 +CAN_PANCTR_PANCMD SET 0 +CAN_PANCTR_RBUSY SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC60 High +CCU6_CC60RH_CC60VH SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC60 Low +CCU6_CC60RL_CC60VL SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC60 High +CCU6_CC60SRH_CC60SH SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC60 Low +CCU6_CC60SRL_CC60SL SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC61 High +CCU6_CC61RH_CC61VH SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC61 Low +CCU6_CC61RL_CC61VL SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC61 High +CCU6_CC61SRH_CC61SH SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC61 Low +CCU6_CC61SRL_CC61SL SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC62 High +CCU6_CC62RH_CC62VH SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC62 Low +CCU6_CC62RL_CC62VL SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC62 High +CCU6_CC62SRH_CC62SH SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC62 Low +CCU6_CC62SRL_CC62SL SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC63 High +CCU6_CC63RH_CC63VH SET 0 + +; RMAP=0 PAGE=1-CCU6 Capture/Compare Register for Channel CC63 Low +CCU6_CC63RL_CC63VL SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC63 High +CCU6_CC63SRH_CC63SH SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Shadow Register for Channel CC63 Low +CCU6_CC63SRL_CC63SL SET 0 + +; RMAP=0 PAGE=0-CCU6 Compare State Modification Register High +CCU6_CMPMODIFH_MCC60R SET 0 +CCU6_CMPMODIFH_MCC61R SET 0 +CCU6_CMPMODIFH_MCC62R SET 0 +CCU6_CMPMODIFH_MCC63R SET 0 + +; RMAP=0 PAGE=0-CCU6 Compare State Modification Register Low +CCU6_CMPMODIFL_MCC60S SET 0 +CCU6_CMPMODIFL_MCC61S SET 0 +CCU6_CMPMODIFL_MCC62S SET 0 +CCU6_CMPMODIFL_MCC63S SET 0 + +; RMAP=0 PAGE=3-CCU6 Compare State Register High +CCU6_CMPSTATH_CC60PS SET 0 +CCU6_CMPSTATH_CC61PS SET 0 +CCU6_CMPSTATH_CC62PS SET 0 +CCU6_CMPSTATH_COUT60PS SET 0 +CCU6_CMPSTATH_COUT61PS SET 0 +CCU6_CMPSTATH_COUT62PS SET 0 +CCU6_CMPSTATH_COUT63PS SET 0 +CCU6_CMPSTATH_T13IM SET 0 + +; RMAP=0 PAGE=3-CCU6 Compare State Register Low +CCU6_CMPSTATL_CC60ST SET 0 +CCU6_CMPSTATL_CC61ST SET 0 +CCU6_CMPSTATL_CC62ST SET 0 +CCU6_CMPSTATL_CC63ST SET 0 +CCU6_CMPSTATL_CCPOS0 SET 0 +CCU6_CMPSTATL_CCPOS1 SET 0 +CCU6_CMPSTATL_CCPOS2 SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Enable Register High +CCU6_IENH_ENCHE SET 0 +CCU6_IENH_ENIDLE SET 0 +CCU6_IENH_ENSTR SET 0 +CCU6_IENH_ENT13CM SET 0 +CCU6_IENH_ENT13PM SET 0 +CCU6_IENH_ENTRPF SET 0 +CCU6_IENH_ENWHE SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Enable Register Low +CCU6_IENL_ENCC60F SET 0 +CCU6_IENL_ENCC60R SET 0 +CCU6_IENL_ENCC61F SET 0 +CCU6_IENL_ENCC61R SET 0 +CCU6_IENL_ENCC62F SET 0 +CCU6_IENL_ENCC62R SET 0 +CCU6_IENL_ENT12OM SET 0 +CCU6_IENL_ENT12PM SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Node Pointer Register High +CCU6_INPH_INPERR SET 0 +CCU6_INPH_INPT12 SET 0 +CCU6_INPH_INPT13 SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Node Pointer Register Low +CCU6_INPL_INPCC60 SET 0 +CCU6_INPL_INPCC61 SET 0 +CCU6_INPL_INPCC62 SET 0 +CCU6_INPL_INPCHE SET 0 + +; RMAP=0 PAGE=3-CCU6 Capture/Compare Interrupt Status Register High +CCU6_ISH_CHE SET 0 +CCU6_ISH_IDLE SET 0 +CCU6_ISH_STR SET 0 +CCU6_ISH_T13CM SET 0 +CCU6_ISH_T13PM SET 0 +CCU6_ISH_TRPF SET 0 +CCU6_ISH_TRPS SET 0 +CCU6_ISH_WHE SET 0 + +; RMAP=0 PAGE=3-CCU6 Capture/Compare Interrupt Status Register Low +CCU6_ISL_ICC60F SET 0 +CCU6_ISL_ICC60R SET 0 +CCU6_ISL_ICC61F SET 0 +CCU6_ISL_ICC61R SET 0 +CCU6_ISL_ICC62F SET 0 +CCU6_ISL_ICC62R SET 0 +CCU6_ISL_T12OM SET 0 +CCU6_ISL_T12PM SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Interrupt Status Reset Register High +CCU6_ISRH_RCHE SET 0 +CCU6_ISRH_RIDLE SET 0 +CCU6_ISRH_RSTR SET 0 +CCU6_ISRH_RT13CM SET 0 +CCU6_ISRH_RT13PM SET 0 +CCU6_ISRH_RTRPF SET 0 +CCU6_ISRH_RWHE SET 0 + +; RMAP=0 PAGE=0-CCU6 Capture/Compare Interrupt Status Reset Register Low +CCU6_ISRL_RCC60F SET 0 +CCU6_ISRL_RCC60R SET 0 +CCU6_ISRL_RCC61F SET 0 +CCU6_ISRL_RCC61R SET 0 +CCU6_ISRL_RCC62F SET 0 +CCU6_ISRL_RCC62R SET 0 +CCU6_ISRL_RT12OM SET 0 +CCU6_ISRL_RT12PM SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Status Set Register High +CCU6_ISSH_SCHE SET 0 +CCU6_ISSH_SIDLE SET 0 +CCU6_ISSH_SSTR SET 0 +CCU6_ISSH_ST13CM SET 0 +CCU6_ISSH_ST13PM SET 0 +CCU6_ISSH_STRPF SET 0 +CCU6_ISSH_SWHC SET 0 +CCU6_ISSH_SWHE SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Interrupt Status Set Register Low +CCU6_ISSL_SCC60F SET 0 +CCU6_ISSL_SCC60R SET 0 +CCU6_ISSL_SCC61F SET 0 +CCU6_ISSL_SCC61R SET 0 +CCU6_ISSL_SCC62F SET 0 +CCU6_ISSL_SCC62R SET 0 +CCU6_ISSL_ST12OM SET 0 +CCU6_ISSL_ST12PM SET 0 + +; RMAP=0 PAGE=2-CCU6 Multi-Channel Mode Control Register +CCU6_MCMCTR_SWSEL SET 0 +CCU6_MCMCTR_SWSYN SET 0 + +; RMAP=0 PAGE=3-CCU6 Multi-Channel Mode Output Register High +CCU6_MCMOUTH_CURH SET 0 +CCU6_MCMOUTH_EXPH SET 0 + +; RMAP=0 PAGE=3-CCU6 Multi-Channel Mode Output Register Low +CCU6_MCMOUTL_MCMP SET 0 +CCU6_MCMOUTL_R SET 0 + +; RMAP=0 PAGE=0-CCU6 Multi-Channel Mode Output Shadow Register High +CCU6_MCMOUTSH_CURHS SET 0 +CCU6_MCMOUTSH_EXPHS SET 0 +CCU6_MCMOUTSH_STRHP SET 0 + +; RMAP=0 PAGE=0-CCU6 Multi-Channel Mode Output Shadow Register Low +CCU6_MCMOUTSL_MCMPS SET 0 +CCU6_MCMOUTSL_STRMCM SET 0 + +; RMAP=0 PAGE=2-CCU6 Modulation Control Register High +CCU6_MODCTRH_ECT13O SET 0 +CCU6_MODCTRH_T13MODEN SET 0 + +; RMAP=0 PAGE=2-CCU6 Modulation Control Register Low +CCU6_MODCTRL_MCMEN SET 0 +CCU6_MODCTRL_T12MODEN SET 0 + +; RMAP=0 -CCU6 Page Register +CCU6_PAGE_OP SET 0 +CCU6_PAGE_PAGE SET 0 +CCU6_PAGE_STNR SET 0 + +; RMAP=0 PAGE=3-CCU6 Port Input Select 0 Register High +CCU6_PISEL0H_ISPOS0 SET 0 +CCU6_PISEL0H_ISPOS1 SET 0 +CCU6_PISEL0H_ISPOS2 SET 0 +CCU6_PISEL0H_IST12HR SET 0 + +; RMAP=0 PAGE=3-CCU6 Port Input Select 0 Register Low +CCU6_PISEL0L_ISCC60 SET 0 +CCU6_PISEL0L_ISCC61 SET 0 +CCU6_PISEL0L_ISCC62 SET 0 +CCU6_PISEL0L_ISTRP SET 0 + +; RMAP=0 PAGE=3-CCU6 Port Input Select 2 Register +CCU6_PISEL2_IST13HR SET 0 + +; RMAP=0 PAGE=2-CCU6 Passive State Level Register +CCU6_PSLR_PSL SET 0 +CCU6_PSLR_PSL63 SET 0 + +; RMAP=0 PAGE=1-CCU6 Dead-Time Control Register for Timer T12 High +CCU6_T12DTCH_DTE0 SET 0 +CCU6_T12DTCH_DTE1 SET 0 +CCU6_T12DTCH_DTE2 SET 0 +CCU6_T12DTCH_DTR0 SET 0 +CCU6_T12DTCH_DTR1 SET 0 +CCU6_T12DTCH_DTR2 SET 0 + +; RMAP=0 PAGE=1-CCU6 Dead-Time Control Register for Timer T12 Low +CCU6_T12DTCL_DTM SET 1 + +; RMAP=0 PAGE=3-CCU6 Timer T12 Counter Register High +CCU6_T12H_T12CVH SET 0 + +; RMAP=0 PAGE=3-CCU6 Timer T12 Counter Register Low +CCU6_T12L_T12CVL SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Mode Select Register High +CCU6_T12MSELH_DBYP SET 0 +CCU6_T12MSELH_HSYNC SET 0 +CCU6_T12MSELH_MSEL62 SET 0 + +; RMAP=0 PAGE=2-CCU6 Capture/Compare Mode Select Register Low +CCU6_T12MSELL_MSEL60 SET 0 +CCU6_T12MSELL_MSEL61 SET 0 + +; RMAP=0 PAGE=1-CCU6 Timer T12 Period Register High +CCU6_T12PRH_T12PVH SET 0 + +; RMAP=0 PAGE=1-CCU6 Timer T12 Period Register Low +CCU6_T12PRL_T12PVL SET 1 + +; RMAP=0 PAGE=3-CCU6 Timer T13 Counter Register High +CCU6_T13H_T13CVH SET 0 + +; RMAP=0 PAGE=3-CCU6 Timer T13 Counter Register Low +CCU6_T13L_T13CVL SET 0 + +; RMAP=0 PAGE=1-CCU6 Timer T13 Period Register High +CCU6_T13PRH_T13PVH SET 0 + +; RMAP=0 PAGE=1-CCU6 Timer T13 Period Register Low +CCU6_T13PRL_T13PVL SET 1 + +; RMAP=0 PAGE=1-CCU6 Timer Control 0 Register High +CCU6_TCTR0H_STE13 SET 0 +CCU6_TCTR0H_T13CLK SET 0 +CCU6_TCTR0H_T13PRE SET 0 +CCU6_TCTR0H_T13R SET 0 + +; RMAP=0 PAGE=1-CCU6 Timer Control 0 Register Low +CCU6_TCTR0L_CDIR SET 0 +CCU6_TCTR0L_CTM SET 0 +CCU6_TCTR0L_STE12 SET 0 +CCU6_TCTR0L_T12CLK SET 0 +CCU6_TCTR0L_T12PRE SET 0 +CCU6_TCTR0L_T12R SET 0 + +; RMAP=0 PAGE=2-CCU6 Timer Control 2 Register High +CCU6_TCTR2H_T12RSEL SET 0 +CCU6_TCTR2H_T13RSEL SET 0 + +; RMAP=0 PAGE=2-CCU6 Timer Control 2 Register Low +CCU6_TCTR2L_T12SSC SET 0 +CCU6_TCTR2L_T13SSC SET 0 +CCU6_TCTR2L_T13TEC SET 0 +CCU6_TCTR2L_T13TED SET 0 + +; RMAP=0 PAGE=0-CCU6 Timer Control 4 Register High +CCU6_TCTR4H_T13RES SET 0 +CCU6_TCTR4H_T13RR SET 0 +CCU6_TCTR4H_T13RS SET 0 +CCU6_TCTR4H_T13STD SET 0 +CCU6_TCTR4H_T13STR SET 0 + +; RMAP=0 PAGE=0-CCU6 Timer Control 4 Register Low +CCU6_TCTR4L_DTRES SET 0 +CCU6_TCTR4L_T12RES SET 0 +CCU6_TCTR4L_T12RR SET 0 +CCU6_TCTR4L_T12RS SET 0 +CCU6_TCTR4L_T12STD SET 0 +CCU6_TCTR4L_T12STR SET 0 + +; RMAP=0 PAGE=2-CCU6 Trap Control Register High +CCU6_TRPCTRH_TRPEN SET 0 +CCU6_TRPCTRH_TRPEN13 SET 0 +CCU6_TRPCTRH_TRPPEN SET 0 + +; RMAP=0 PAGE=2-CCU6 Trap Control Register Low +CCU6_TRPCTRL_TRPM0 SET 0 +CCU6_TRPCTRL_TRPM1 SET 0 +CCU6_TRPCTRL_TRPM2 SET 0 + +; RMAP=1 -CORDIC CORDIC Control Register +CD_CON_MODE SET 0 +CD_CON_MPS SET 0 +CD_CON_ROTVEC SET 0 +CD_CON_ST SET 0 +CD_CON_ST_MODE SET 0 +CD_CON_X_USIGN SET 0 + +; RMAP=1 -CORDIC CORDIC X Data High Byte +CD_CORDXH_DATAH SET 0 + +; RMAP=1 -CORDIC CORDIC X Data Low Byte +CD_CORDXL_DATAL SET 0 + +; RMAP=1 -CORDIC CORDIC Y Data High Byte +CD_CORDYH_DATAH SET 0 + +; RMAP=1 -CORDIC CORDIC Y Data Low Byte +CD_CORDYL_DATAL SET 0 + +; RMAP=1 -CORDIC CORDIC Z Data High Byte +CD_CORDZH_DATAH SET 0 + +; RMAP=1 -CORDIC CORDIC Z Data Low Byte +CD_CORDZL_DATAL SET 0 + +; RMAP=1 -CORDIC CORDIC Status and Data Control Register +CD_STATC_CD_BSY SET 0 +CD_STATC_DMAP SET 0 +CD_STATC_EOC SET 0 +CD_STATC_ERROR SET 0 +CD_STATC_INT_EN SET 0 +CD_STATC_KEEPX SET 0 +CD_STATC_KEEPY SET 0 +CD_STATC_KEEPZ SET 0 + +; RMAP=0 PAGE=1-SCU Clock Control Register +CMCON_CLKREL SET 0 +CMCON_FCCFG SET 1 +CMCON_KDIV SET 0 +CMCON_VCOSEL SET 0 + +; RMAP=0 PAGE=1-SCU Clock Output Control Register +COCON_COREL SET 0 +COCON_COUTS SET 0 +COCON_TLEN SET 0 + +; RMAP=x -CPU Data Pointer Register High +DPH_DPH0 SET 0 +DPH_DPH1 SET 0 +DPH_DPH2 SET 0 +DPH_DPH3 SET 0 +DPH_DPH4 SET 0 +DPH_DPH5 SET 0 +DPH_DPH6 SET 0 +DPH_DPH7 SET 0 + +; RMAP=x -CPU Data Pointer Register Low +DPL_DPL0 SET 0 +DPL_DPL1 SET 0 +DPL_DPL2 SET 0 +DPL_DPL3 SET 0 +DPL_DPL4 SET 0 +DPL_DPL5 SET 0 +DPL_DPL6 SET 0 +DPL_DPL7 SET 0 + +; RMAP=x -CPU Extended Operation Register +EO_DPSEL0 SET 0 +EO_TRAP_EN SET 0 + +; RMAP=0 PAGE=0-SCU External Interrupt Control Register 0 +EXICON0_EXINT0 SET 0 +EXICON0_EXINT1 SET 0 +EXICON0_EXINT2 SET 0 +EXICON0_EXINT3 SET 0 + +; RMAP=0 PAGE=0-SCU External Interrupt Control Register 1 +EXICON1_EXINT4 SET 0 +EXICON1_EXINT5 SET 0 +EXICON1_EXINT6 SET 0 + +; RMAP=0 PAGE=0-SCU Fractional Divider Control Register +FDCON_BGS SET 0 +FDCON_BRK SET 0 +FDCON_EOFSYN SET 0 +FDCON_ERRSYN SET 0 +FDCON_FDEN SET 0 +FDCON_FDM SET 0 +FDCON_NDOV SET 0 +FDCON_SYNEN SET 0 + +; RMAP=0 PAGE=0-SCU Fractional Divider Result Register +FDRES_RESULT SET 0 + +; RMAP=0 PAGE=0-SCU Fractional Divider Reload Register +FDSTEP_STEP SET 0 + +; RMAP=0 PAGE=1-SCU Flash Error Address Register High +FEAH_ECCERRADDR SET 0 + +; RMAP=0 PAGE=1-SCU Flash Error Address Register Low +FEAL_ECCERRADDR SET 0 + +; RMAP=1 -OCDS Hardware Breakpoints Data Register +HWBPDR_HWBPXX SET 0 + +; RMAP=1 -OCDS Hardware Breakpoints Select Register +HWBPSR_BPSEL SET 0 +HWBPSR_BPSEL_P SET 0 + +; RMAP=0 PAGE=1-SCU Identity Register +ID_PRODID SET 0 +ID_VERID SET 0 + +; RMAP=x -CPU Interrupt Enable Register 0 +IEN0_EA SET 1 +IEN0_ES SET 0 +IEN0_ET0 SET 0 +IEN0_ET1 SET 0 +IEN0_ET2 SET 1 +IEN0_EX0 SET 0 +IEN0_EX1 SET 0 + +; RMAP=x -CPU Module Interrupt Enable 1 Register +IEN1_EADC SET 0 +IEN1_ECCIP0 SET 0 +IEN1_ECCIP1 SET 0 +IEN1_ECCIP2 SET 0 +IEN1_ECCIP3 SET 0 +IEN1_ESSC SET 0 +IEN1_EX2 SET 0 +IEN1_EXM SET 0 + +; RMAP=x -CPU Interrupt Priority 1 Register +IP1_PADC SET 0 +IP1_PCCIP0 SET 0 +IP1_PCCIP1 SET 0 +IP1_PCCIP2 SET 0 +IP1_PCCIP3 SET 0 +IP1_PSSC SET 0 +IP1_PX2 SET 0 +IP1_PXM SET 0 + +; RMAP=x -CPU Interrupt Priority 1 High Register +IPH1_PADCH SET 0 +IPH1_PCCIP0H SET 0 +IPH1_PCCIP1H SET 0 +IPH1_PCCIP2H SET 0 +IPH1_PCCIP3H SET 0 +IPH1_PSSCH SET 0 +IPH1_PX2H SET 0 +IPH1_PXMH SET 0 + +; RMAP=x -CPU Interrupt Priority High Register +IPH_PSH SET 0 +IPH_PT0H SET 0 +IPH_PT1H SET 0 +IPH_PT2H SET 0 +IPH_PX0H SET 0 +IPH_PX1H SET 0 + +; RMAP=x -CPU Interrupt Priority Register +IP_PS SET 0 +IP_PT0 SET 0 +IP_PT1 SET 0 +IP_PT2 SET 0 +IP_PX0 SET 0 +IP_PX1 SET 0 + +; RMAP=0 PAGE=0-SCU Interrupt Request Register 0 +IRCON0_EXINT0 SET 0 +IRCON0_EXINT1 SET 0 +IRCON0_EXINT2 SET 0 +IRCON0_EXINT3 SET 0 +IRCON0_EXINT4 SET 0 +IRCON0_EXINT5 SET 0 +IRCON0_EXINT6 SET 0 + +; RMAP=0 PAGE=0-SCU Interrupt Request Register 1 +IRCON1_ADCSR0 SET 0 +IRCON1_ADCSR1 SET 0 +IRCON1_CANSRC1 SET 0 +IRCON1_CANSRC2 SET 0 +IRCON1_EIR SET 0 +IRCON1_RIR SET 0 +IRCON1_TIR SET 0 + +; RMAP=0 PAGE=0-SCU Interrupt Request Register 2 +IRCON2_CANSRC0 SET 0 +IRCON2_CANSRC3 SET 0 + +; RMAP=0 PAGE=3-SCU Interrupt Request Register 3 +IRCON3_CANSRC4 SET 0 +IRCON3_CANSRC5 SET 0 +IRCON3_CCU6SR0 SET 0 +IRCON3_CCU6SR1 SET 0 + +; RMAP=0 PAGE=3-SCU Interrupt Request Register 4 +IRCON4_CANSRC6 SET 0 +IRCON4_CANSRC7 SET 0 +IRCON4_CCU6SR2 SET 0 +IRCON4_CCU6SR3 SET 0 + +; RMAP=1 -MDU MDU Operand Register 0 +MDU_MD0_DATA SET 0 + +; RMAP=1 -MDU MDU Operand Register 1 +MDU_MD1_DATA SET 0 + +; RMAP=1 -MDU MDU Operand Register 2 +MDU_MD2_DATA SET 0 + +; RMAP=1 -MDU MDU Operand Register 3 +MDU_MD3_DATA SET 0 + +; RMAP=1 -MDU MDU Operand Register 4 +MDU_MD4_DATA SET 0 + +; RMAP=1 -MDU MDU Operand Register 5 +MDU_MD5_DATA SET 0 + +; RMAP=1 -MDU MDU Control Register +MDU_MDUCON_IE SET 0 +MDU_MDUCON_IR SET 0 +MDU_MDUCON_OPCODE SET 0 +MDU_MDUCON_RSEL SET 0 +MDU_MDUCON_START SET 0 + +; RMAP=1 -MDU MDU Status Register +MDU_MDUSTAT_IERR SET 0 +MDU_MDUSTAT_IRDY SET 0 +MDU_MDUSTAT_MDU_BSY SET 0 + +; RMAP=1 -MDU MDU Result Register 0 +MDU_MR0_DATA SET 0 + +; RMAP=1 -MDU MDU Result Register 1 +MDU_MR1_DATA SET 0 + +; RMAP=1 -MDU MDU Result Register 2 +MDU_MR2_DATA SET 0 + +; RMAP=1 -MDU MDU Result Register 3 +MDU_MR3_DATA SET 0 + +; RMAP=1 -MDU MDU Result Register 4 +MDU_MR4_DATA SET 0 + +; RMAP=1 -MDU MDU Result Register 5 +MDU_MR5_DATA SET 0 + +; RMAP=0 PAGE=1-SCU Miscellaneous Control Register +MISC_CON_DFLASHEN SET 0 + +; RMAP=1 -OCDS BreakPoints Control Register +MMBPCR_HWB0C SET 0 +MMBPCR_HWB1C SET 0 +MMBPCR_HWB2C SET 0 +MMBPCR_HWB3C SET 0 +MMBPCR_SWBC SET 0 + +; RMAP=1 -OCDS Monitor Mode Control 2 Register +MMCR2_ALTDI SET 0 +MMCR2_DSUSP SET 0 +MMCR2_EXBC SET 0 +MMCR2_JENA SET 0 +MMCR2_MBCON SET 0 +MMCR2_MMEP SET 0 +MMCR2_MMODE SET 0 +MMCR2_STMODE SET 0 + +; RMAP=1 -OCDS Monitor Mode Control Register +MMCR_MEXIT SET 0 +MMCR_MEXIT_P SET 0 +MMCR_MRAMS SET 0 +MMCR_MRAMS_P SET 0 +MMCR_MSTEP SET 0 +MMCR_RRF SET 0 +MMCR_TRF SET 0 + +; RMAP=1 -OCDS Monitor Mode Data Transfer Register Receive +MMDR_MMRR SET 0 + +; RMAP=1 -OCDS Monitor Mode Interrupt Control Register +MMICR_COMRST SET 0 +MMICR_DRETR SET 0 +MMICR_DVECT SET 0 +MMICR_MMUIE SET 0 +MMICR_MMUIE_P SET 0 +MMICR_MSTSEL SET 0 +MMICR_RRIE SET 0 +MMICR_RRIE_P SET 0 + +; RMAP=1 -OCDS Monitor Mode Status Register +MMSR_EXBF SET 0 +MMSR_HWB0F SET 0 +MMSR_HWB1F SET 0 +MMSR_HWB2F SET 0 +MMSR_HWB3F SET 0 +MMSR_MBCAM SET 0 +MMSR_MBCIN SET 0 +MMSR_SWBF SET 0 + +; RMAP=1 -OCDS Monitor Work Register 1 +MMWR1_MMWR1 SET 0 + +; RMAP=1 -OCDS Monitor Work Register 2 +MMWR2_MMWR2 SET 0 + +; RMAP=0 PAGE=3-SCU Peripheral Input Select Register 1 +MODPISEL1_EXINT6IS SET 0 +MODPISEL1_JTAGTCKS1 SET 0 +MODPISEL1_JTAGTDIS1 SET 0 +MODPISEL1_T21EXIS SET 0 +MODPISEL1_UR1RIS SET 0 + +; RMAP=0 PAGE=3-SCU Peripheral Input Select Register 2 +MODPISEL2_T0IS SET 0 +MODPISEL2_T1IS SET 0 +MODPISEL2_T21IS SET 0 +MODPISEL2_T2IS SET 0 + +; RMAP=0 PAGE=0-SCU Peripheral Input Select Register +MODPISEL_EXINT0IS SET 0 +MODPISEL_EXINT1IS SET 0 +MODPISEL_EXINT2IS SET 0 +MODPISEL_JTAGTCKS SET 0 +MODPISEL_JTAGTDIS SET 0 +MODPISEL_URRIS SET 0 +MODPISEL_URRISH SET 0 + +; RMAP=0 PAGE=3-SCU Module Suspend Control Register +MODSUSP_T12SUSP SET 0 +MODSUSP_T13SUSP SET 0 +MODSUSP_T21SUSP SET 0 +MODSUSP_T2SUSP SET 0 +MODSUSP_WDTSUSP SET 0 + +; RMAP=0 PAGE=0-SCU NMI Control Register +NMICON_NMIECC SET 0 +NMICON_NMIFLASH SET 0 +NMICON_NMIOCDS SET 0 +NMICON_NMIPLL SET 0 +NMICON_NMIVDD SET 0 +NMICON_NMIVDDP SET 0 +NMICON_NMIWDT SET 0 + +; RMAP=0 PAGE=0-SCU NMI Status Register +NMISR_FNMIECC SET 0 +NMISR_FNMIFLASH SET 0 +NMISR_FNMIOCDS SET 0 +NMISR_FNMIPLL SET 0 +NMISR_FNMIVDD SET 0 +NMISR_FNMIVDDP SET 0 +NMISR_FNMIWDT SET 0 + +; RMAP=0 PAGE=1-SCU OSC Control Register +OSC_CON_ORDRES SET 0 +OSC_CON_OSCPD SET 0 +OSC_CON_OSCR SET 0 +OSC_CON_OSCSS SET 1 +OSC_CON_XPD SET 1 + +; RMAP=0 PAGE=2-P0 P0 Alternate Select 0 Register +P0_ALTSEL0_P0 SET 0 +P0_ALTSEL0_P1 SET 0 +P0_ALTSEL0_P2 SET 0 +P0_ALTSEL0_P3 SET 0 +P0_ALTSEL0_P4 SET 0 +P0_ALTSEL0_P5 SET 0 +P0_ALTSEL0_P6 SET 0 +P0_ALTSEL0_P7 SET 0 + +; RMAP=0 PAGE=2-P0 P0 Alternate Select 1 Register +P0_ALTSEL1_P0 SET 0 +P0_ALTSEL1_P1 SET 0 +P0_ALTSEL1_P2 SET 0 +P0_ALTSEL1_P3 SET 0 +P0_ALTSEL1_P4 SET 0 +P0_ALTSEL1_P5 SET 0 +P0_ALTSEL1_P6 SET 0 +P0_ALTSEL1_P7 SET 0 + +; RMAP=0 PAGE=0-P0 P0 Data Register +P0_DATA_P0 SET 0 +P0_DATA_P1 SET 0 +P0_DATA_P2 SET 0 +P0_DATA_P3 SET 0 +P0_DATA_P4 SET 0 +P0_DATA_P5 SET 0 +P0_DATA_P6 SET 0 +P0_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P0 P0 Direction Register +P0_DIR_P0 SET 1 +P0_DIR_P1 SET 1 +P0_DIR_P2 SET 1 +P0_DIR_P3 SET 1 +P0_DIR_P4 SET 0 +P0_DIR_P5 SET 0 +P0_DIR_P6 SET 0 +P0_DIR_P7 SET 1 + +; RMAP=0 PAGE=3-P0 P0 Open Drain Control Register +P0_OD_P0 SET 0 +P0_OD_P1 SET 0 +P0_OD_P2 SET 0 +P0_OD_P3 SET 0 +P0_OD_P4 SET 0 +P0_OD_P5 SET 0 +P0_OD_P6 SET 0 +P0_OD_P7 SET 0 + +; RMAP=0 PAGE=1-P0 P0 Pull-Up/Pull-Down Enable Register +P0_PUDEN_P0 SET 1 +P0_PUDEN_P1 SET 1 +P0_PUDEN_P2 SET 1 +P0_PUDEN_P3 SET 1 +P0_PUDEN_P4 SET 0 +P0_PUDEN_P5 SET 0 +P0_PUDEN_P6 SET 1 +P0_PUDEN_P7 SET 1 + +; RMAP=0 PAGE=1-P0 P0 Pull-Up/Pull-Down Select Register +P0_PUDSEL_P0 SET 0 +P0_PUDSEL_P1 SET 0 +P0_PUDSEL_P2 SET 0 +P0_PUDSEL_P3 SET 0 +P0_PUDSEL_P4 SET 1 +P0_PUDSEL_P5 SET 1 +P0_PUDSEL_P6 SET 1 +P0_PUDSEL_P7 SET 0 + +; RMAP=0 PAGE=2-P1 P1 Alternate Select 0 Register +P1_ALTSEL0_P0 SET 0 +P1_ALTSEL0_P1 SET 1 +P1_ALTSEL0_P2 SET 0 +P1_ALTSEL0_P3 SET 0 +P1_ALTSEL0_P4 SET 0 +P1_ALTSEL0_P5 SET 0 +P1_ALTSEL0_P6 SET 0 +P1_ALTSEL0_P7 SET 0 + +; RMAP=0 PAGE=2-P1 P1 Alternate Select 1 Register +P1_ALTSEL1_P0 SET 0 +P1_ALTSEL1_P1 SET 1 +P1_ALTSEL1_P2 SET 0 +P1_ALTSEL1_P3 SET 0 +P1_ALTSEL1_P4 SET 0 +P1_ALTSEL1_P5 SET 0 +P1_ALTSEL1_P6 SET 0 +P1_ALTSEL1_P7 SET 0 + +; RMAP=0 PAGE=0-P1 P1 Data Register +P1_DATA_P0 SET 0 +P1_DATA_P1 SET 0 +P1_DATA_P2 SET 0 +P1_DATA_P3 SET 0 +P1_DATA_P4 SET 0 +P1_DATA_P5 SET 0 +P1_DATA_P6 SET 0 +P1_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P1 P1 Direction Register +P1_DIR_P0 SET 0 +P1_DIR_P1 SET 1 +P1_DIR_P2 SET 0 +P1_DIR_P3 SET 0 +P1_DIR_P4 SET 0 +P1_DIR_P5 SET 0 +P1_DIR_P6 SET 0 +P1_DIR_P7 SET 1 + +; RMAP=0 PAGE=3-P1 P1 Open Drain Control Register +P1_OD_P0 SET 0 +P1_OD_P1 SET 0 +P1_OD_P2 SET 0 +P1_OD_P3 SET 0 +P1_OD_P4 SET 0 +P1_OD_P5 SET 0 +P1_OD_P6 SET 0 +P1_OD_P7 SET 0 + +; RMAP=0 PAGE=1-P1 P1 Pull-Up/Pull-Down Enable Register +P1_PUDEN_P0 SET 1 +P1_PUDEN_P1 SET 1 +P1_PUDEN_P2 SET 0 +P1_PUDEN_P3 SET 0 +P1_PUDEN_P4 SET 0 +P1_PUDEN_P5 SET 0 +P1_PUDEN_P6 SET 1 +P1_PUDEN_P7 SET 1 + +; RMAP=0 PAGE=1-P1 P1 Pull-Up/Pull-Down Select Register +P1_PUDSEL_P0 SET 1 +P1_PUDSEL_P1 SET 1 +P1_PUDSEL_P2 SET 1 +P1_PUDSEL_P3 SET 1 +P1_PUDSEL_P4 SET 1 +P1_PUDSEL_P5 SET 1 +P1_PUDSEL_P6 SET 1 +P1_PUDSEL_P7 SET 0 + +; RMAP=0 PAGE=0-P2 P2 Data Register +P2_DATA_P0 SET 0 +P2_DATA_P1 SET 0 +P2_DATA_P2 SET 0 +P2_DATA_P3 SET 0 +P2_DATA_P4 SET 0 +P2_DATA_P5 SET 0 +P2_DATA_P6 SET 0 +P2_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P2 P2 Direction Register +P2_DIR_P0 SET 0 +P2_DIR_P1 SET 0 +P2_DIR_P2 SET 0 +P2_DIR_P3 SET 0 +P2_DIR_P4 SET 0 +P2_DIR_P5 SET 0 +P2_DIR_P6 SET 0 +P2_DIR_P7 SET 0 + +; RMAP=0 PAGE=1-P2 P2 Pull-Up/Pull-Down Enable Register +P2_PUDEN_P0 SET 0 +P2_PUDEN_P1 SET 0 +P2_PUDEN_P2 SET 0 +P2_PUDEN_P3 SET 0 +P2_PUDEN_P4 SET 1 +P2_PUDEN_P5 SET 1 +P2_PUDEN_P6 SET 1 +P2_PUDEN_P7 SET 1 + +; RMAP=0 PAGE=1-P2 P2 Pull-Up/Pull-Down Select Register +P2_PUDSEL_P0 SET 1 +P2_PUDSEL_P1 SET 1 +P2_PUDSEL_P2 SET 1 +P2_PUDSEL_P3 SET 1 +P2_PUDSEL_P4 SET 1 +P2_PUDSEL_P5 SET 1 +P2_PUDSEL_P6 SET 1 +P2_PUDSEL_P7 SET 1 + +; RMAP=0 PAGE=2-P3 P3 Alternate Select 0 Register +P3_ALTSEL0_P0 SET 0 +P3_ALTSEL0_P1 SET 0 +P3_ALTSEL0_P2 SET 0 +P3_ALTSEL0_P3 SET 0 +P3_ALTSEL0_P4 SET 0 +P3_ALTSEL0_P5 SET 0 +P3_ALTSEL0_P6 SET 0 +P3_ALTSEL0_P7 SET 0 + +; RMAP=0 PAGE=2-P3 P3 Alternate Select 1 Register +P3_ALTSEL1_P0 SET 0 +P3_ALTSEL1_P1 SET 0 +P3_ALTSEL1_P2 SET 0 +P3_ALTSEL1_P3 SET 0 +P3_ALTSEL1_P4 SET 0 +P3_ALTSEL1_P5 SET 0 +P3_ALTSEL1_P6 SET 0 +P3_ALTSEL1_P7 SET 0 + +; RMAP=0 PAGE=0-P3 P3 Data Register +P3_DATA_P0 SET 0 +P3_DATA_P1 SET 0 +P3_DATA_P2 SET 0 +P3_DATA_P3 SET 0 +P3_DATA_P4 SET 0 +P3_DATA_P5 SET 0 +P3_DATA_P6 SET 0 +P3_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P3 P3 Direction Register +P3_DIR_P0 SET 0 +P3_DIR_P1 SET 0 +P3_DIR_P2 SET 1 +P3_DIR_P3 SET 1 +P3_DIR_P4 SET 1 +P3_DIR_P5 SET 1 +P3_DIR_P6 SET 0 +P3_DIR_P7 SET 0 + +; RMAP=0 PAGE=3-P3 P3 Open Drain Control Register +P3_OD_P0 SET 0 +P3_OD_P1 SET 0 +P3_OD_P2 SET 1 +P3_OD_P3 SET 1 +P3_OD_P4 SET 1 +P3_OD_P5 SET 1 +P3_OD_P6 SET 0 +P3_OD_P7 SET 0 + +; RMAP=0 PAGE=1-P3 P3 Pull-Up/Pull-Down Enable Register +P3_PUDEN_P0 SET 1 +P3_PUDEN_P1 SET 1 +P3_PUDEN_P2 SET 0 +P3_PUDEN_P3 SET 0 +P3_PUDEN_P4 SET 0 +P3_PUDEN_P5 SET 0 +P3_PUDEN_P6 SET 0 +P3_PUDEN_P7 SET 1 + +; RMAP=0 PAGE=1-P3 P3 Pull-Up/Pull-Down Select Register +P3_PUDSEL_P0 SET 1 +P3_PUDSEL_P1 SET 1 +P3_PUDSEL_P2 SET 1 +P3_PUDSEL_P3 SET 1 +P3_PUDSEL_P4 SET 1 +P3_PUDSEL_P5 SET 1 +P3_PUDSEL_P6 SET 1 +P3_PUDSEL_P7 SET 1 + +; RMAP=0 PAGE=2-P4 P4 Alternate Select 0 Register +P4_ALTSEL0_P0 SET 0 +P4_ALTSEL0_P1 SET 0 +P4_ALTSEL0_P2 SET 0 +P4_ALTSEL0_P3 SET 0 +P4_ALTSEL0_P4 SET 0 +P4_ALTSEL0_P5 SET 0 +P4_ALTSEL0_P6 SET 0 +P4_ALTSEL0_P7 SET 0 + +; RMAP=0 PAGE=2-P4 P4 Alternate Select 1 Register +P4_ALTSEL1_P0 SET 0 +P4_ALTSEL1_P1 SET 0 +P4_ALTSEL1_P2 SET 0 +P4_ALTSEL1_P3 SET 0 +P4_ALTSEL1_P4 SET 0 +P4_ALTSEL1_P5 SET 0 +P4_ALTSEL1_P6 SET 0 +P4_ALTSEL1_P7 SET 0 + +; RMAP=0 PAGE=0-P4 P4 Data Register +P4_DATA_P0 SET 0 +P4_DATA_P1 SET 0 +P4_DATA_P2 SET 0 +P4_DATA_P3 SET 0 +P4_DATA_P4 SET 0 +P4_DATA_P5 SET 0 +P4_DATA_P6 SET 0 +P4_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P4 P4 Direction Register +P4_DIR_P0 SET 1 +P4_DIR_P1 SET 1 +P4_DIR_P2 SET 0 +P4_DIR_P3 SET 0 +P4_DIR_P4 SET 0 +P4_DIR_P5 SET 0 +P4_DIR_P6 SET 0 +P4_DIR_P7 SET 0 + +; RMAP=0 PAGE=3-P4 P4 Open Drain Control Register +P4_OD_P0 SET 0 +P4_OD_P1 SET 0 +P4_OD_P2 SET 0 +P4_OD_P3 SET 0 +P4_OD_P4 SET 0 +P4_OD_P5 SET 0 +P4_OD_P6 SET 0 +P4_OD_P7 SET 0 + +; RMAP=0 PAGE=1-P4 P4 Pull-Up/Pull-Down Enable Register +P4_PUDEN_P0 SET 1 +P4_PUDEN_P1 SET 1 +P4_PUDEN_P2 SET 1 +P4_PUDEN_P3 SET 0 +P4_PUDEN_P4 SET 0 +P4_PUDEN_P5 SET 0 +P4_PUDEN_P6 SET 0 +P4_PUDEN_P7 SET 0 + +; RMAP=0 PAGE=1-P4 P4 Pull-Up/Pull-Down Select Register +P4_PUDSEL_P0 SET 0 +P4_PUDSEL_P1 SET 0 +P4_PUDSEL_P2 SET 1 +P4_PUDSEL_P3 SET 1 +P4_PUDSEL_P4 SET 1 +P4_PUDSEL_P5 SET 1 +P4_PUDSEL_P6 SET 1 +P4_PUDSEL_P7 SET 1 + +; RMAP=0 PAGE=2-P5 P5 Alternate Select 0 Register +P5_ALTSEL0_P0 SET 0 +P5_ALTSEL0_P1 SET 0 +P5_ALTSEL0_P2 SET 0 +P5_ALTSEL0_P3 SET 0 +P5_ALTSEL0_P4 SET 0 +P5_ALTSEL0_P5 SET 0 +P5_ALTSEL0_P6 SET 0 +P5_ALTSEL0_P7 SET 0 + +; RMAP=0 PAGE=2-P5 P5 Alternate Select 1 Register +P5_ALTSEL1_P0 SET 0 +P5_ALTSEL1_P1 SET 0 +P5_ALTSEL1_P2 SET 0 +P5_ALTSEL1_P3 SET 0 +P5_ALTSEL1_P4 SET 0 +P5_ALTSEL1_P5 SET 0 +P5_ALTSEL1_P6 SET 0 +P5_ALTSEL1_P7 SET 0 + +; RMAP=0 PAGE=0-P5 P5 Data Register +P5_DATA_P0 SET 0 +P5_DATA_P1 SET 0 +P5_DATA_P2 SET 0 +P5_DATA_P3 SET 0 +P5_DATA_P4 SET 0 +P5_DATA_P5 SET 0 +P5_DATA_P6 SET 0 +P5_DATA_P7 SET 0 + +; RMAP=0 PAGE=0-P5 P5 Direction Register +P5_DIR_P0 SET 0 +P5_DIR_P1 SET 0 +P5_DIR_P2 SET 0 +P5_DIR_P3 SET 0 +P5_DIR_P4 SET 0 +P5_DIR_P5 SET 0 +P5_DIR_P6 SET 0 +P5_DIR_P7 SET 0 + +; RMAP=0 PAGE=3-P5 P5 Open Drain Control Register +P5_OD_P0 SET 0 +P5_OD_P1 SET 0 +P5_OD_P2 SET 0 +P5_OD_P3 SET 0 +P5_OD_P4 SET 0 +P5_OD_P5 SET 0 +P5_OD_P6 SET 0 +P5_OD_P7 SET 0 + +; RMAP=0 PAGE=1-P5 P5 Pull-Up/Pull-Down Enable Register +P5_PUDEN_P0 SET 0 +P5_PUDEN_P1 SET 0 +P5_PUDEN_P2 SET 0 +P5_PUDEN_P3 SET 0 +P5_PUDEN_P4 SET 0 +P5_PUDEN_P5 SET 0 +P5_PUDEN_P6 SET 0 +P5_PUDEN_P7 SET 0 + +; RMAP=0 PAGE=1-P5 P5 Pull-Up/Pull-Down Select Register +P5_PUDSEL_P0 SET 0 +P5_PUDSEL_P1 SET 0 +P5_PUDSEL_P2 SET 0 +P5_PUDSEL_P3 SET 0 +P5_PUDSEL_P4 SET 0 +P5_PUDSEL_P5 SET 0 +P5_PUDSEL_P6 SET 0 +P5_PUDSEL_P7 SET 0 + +; RMAP=0 PAGE=1-SCU Password Register +PASSWD_MODE SET 0 +PASSWD_PASS SET 0 +PASSWD_PROTECT_S SET 0 + +; RMAP=x -CPU Power Control Register +PCON_GF0 SET 0 +PCON_GF1 SET 0 +PCON_IDLE SET 0 +PCON_SMOD SET 0 + +; RMAP=0 PAGE=1-SCU PLL Control Register +PLL_CON_LOCK SET 0 +PLL_CON_NDIV SET 10 +PLL_CON_OSCDISC SET 0 +PLL_CON_RESLD SET 0 +PLL_CON_VCOBYP SET 0 + +; RMAP=0 PAGE=1-SCU Power Mode Control Register 0 +PMCON0_PD SET 0 +PMCON0_SD SET 0 +PMCON0_WDTRST SET 0 +PMCON0_WKRS SET 0 +PMCON0_WKSEL SET 0 +PMCON0_WS SET 0 + +; RMAP=0 PAGE=1-SCU Power Mode Control Register 1 +PMCON1_ADC_DIS SET 0 +PMCON1_CAN_DIS SET 0 +PMCON1_CCU_DIS SET 0 +PMCON1_CDC_DIS SET 0 +PMCON1_MDU_DIS SET 0 +PMCON1_SSC_DIS SET 1 +PMCON1_T2_DIS SET 0 + +; RMAP=0 PAGE=3-SCU Power Mode Control Register 2 +PMCON2_T21_DIS SET 0 +PMCON2_UART1_DIS SET 0 + +; RMAP=0 -PORT Page Register +PORT_PAGE_OP SET 0 +PORT_PAGE_PAGE SET 0 +PORT_PAGE_STNR SET 0 + +; RMAP=x -CPU Program Status Word Register +PSW_AC SET 0 +PSW_CY SET 0 +PSW_F0 SET 0 +PSW_F1 SET 0 +PSW_OV SET 0 +PSW_P SET 0 +PSW_RS0 SET 0 +PSW_RS1 SET 0 + +; RMAP=x -CPU Serial Data Buffer Register +SBUF_VAL SET 0 + +; RMAP=x -CPU Serial Channel Control Register +SCON_RB8 SET 0 +SCON_REN SET 0 +SCON_RI SET 0 +SCON_SM0 SET 0 +SCON_SM1 SET 0 +SCON_SM2 SET 0 +SCON_TB8 SET 0 +SCON_TI SET 0 + +; RMAP=0 -SCU Page Register +SCU_PAGE_OP SET 0 +SCU_PAGE_PAGE SET 0 +SCU_PAGE_STNR SET 0 + +; RMAP=x -CPU Stack Pointer Register +SP_SP SET 0 + +; RMAP=0 -SSC Baudrate Timer Reload Register High +SSC_BRH_BR_VALUE SET 0 + +; RMAP=0 -SSC Baudrate Timer Reload Register Low +SSC_BRL_BR_VALUE SET 0 + +; RMAP=0 -SSC Control Register High Operating Mode +SSC_CONH_O_BE SET 0 +SSC_CONH_O_BSY SET 0 +SSC_CONH_O_EN SET 0 +SSC_CONH_O_MS SET 0 +SSC_CONH_O_PE SET 0 +SSC_CONH_O_RE SET 0 +SSC_CONH_O_TE SET 0 + +; RMAP=0 -SSC Control Register High Programming Mode +SSC_CONH_P_AREN SET 0 +SSC_CONH_P_BEN SET 0 +SSC_CONH_P_EN SET 0 +SSC_CONH_P_MS SET 1 +SSC_CONH_P_PEN SET 0 +SSC_CONH_P_REN SET 0 +SSC_CONH_P_TEN SET 0 + +; RMAP=0 -SSC Control Register Low Operating Mode +SSC_CONL_O_BC SET 0 + +; RMAP=0 -SSC Control Register Low Programming Mode +SSC_CONL_P_BM SET 1 +SSC_CONL_P_HB SET 0 +SSC_CONL_P_LB SET 0 +SSC_CONL_P_PH SET 0 +SSC_CONL_P_PO SET 0 + +; RMAP=0 -SSC Port Input Select Register +SSC_PISEL_CIS SET 0 +SSC_PISEL_MIS SET 0 +SSC_PISEL_SIS SET 0 + +; RMAP=0 -SSC Receiver Buffer Register Low +SSC_RBL_RB_VALUE SET 0 + +; RMAP=0 -SSC Transmitter Buffer Register Low +SSC_TBL_TB_VALUE SET 0 + +; RMAP=x -SCU System Control Register 0 +SYSCON0_1 SET 0 +SYSCON0_IMODE SET 0 +SYSCON0_RMAP SET 0 + +; RMAP=1 -T21 Timer 2 Reload/Capture Register High +T21_RC2H_RC2 SET 0 + +; RMAP=1 -T21 Timer 2 Reload/Capture Register Low +T21_RC2L_RC2 SET 0 + +; RMAP=1 -T21 Timer 2 Control Register +T21_T2CON_C_T2 SET 0 +T21_T2CON_CP_RL2 SET 0 +T21_T2CON_EXEN2 SET 0 +T21_T2CON_EXF2 SET 0 +T21_T2CON_TF2 SET 0 +T21_T2CON_TR2 SET 0 + +; RMAP=1 -T21 Timer 2 Register High +T21_T2H_THL2 SET 0 + +; RMAP=1 -T21 Timer 2 Register Low +T21_T2L_THL2 SET 0 + +; RMAP=1 -T21 Timer 2 Mode Register +T21_T2MOD_DCEN SET 0 +T21_T2MOD_EDGESEL SET 0 +T21_T2MOD_PREN SET 0 +T21_T2MOD_T2PRE SET 0 +T21_T2MOD_T2REGS SET 0 +T21_T2MOD_T2RHEN SET 0 + +; RMAP=0 -T2 Timer 2 Reload/Capture Register High +T2_RC2H_RC2 SET 248 + +; RMAP=0 -T2 Timer 2 Reload/Capture Register Low +T2_RC2L_RC2 SET 48 + +; RMAP=0 -T2 Timer 2 Control Register +T2_T2CON_C_T2 SET 0 +T2_T2CON_CP_RL2 SET 0 +T2_T2CON_EXEN2 SET 0 +T2_T2CON_EXF2 SET 0 +T2_T2CON_TF2 SET 0 +T2_T2CON_TR2 SET 1 + +; RMAP=0 -T2 Timer 2 Register High +T2_T2H_THL2 SET 248 + +; RMAP=0 -T2 Timer 2 Register Low +T2_T2L_THL2 SET 48 + +; RMAP=0 -T2 Timer 2 Mode Register +T2_T2MOD_DCEN SET 0 +T2_T2MOD_EDGESEL SET 0 +T2_T2MOD_PREN SET 0 +T2_T2MOD_T2PRE SET 0 +T2_T2MOD_T2REGS SET 0 +T2_T2MOD_T2RHEN SET 0 + +; RMAP=x -CPU Timer Control Register +TCON_IE0 SET 0 +TCON_IE1 SET 0 +TCON_IT0 SET 0 +TCON_IT1 SET 0 +TCON_TF0 SET 0 +TCON_TF1 SET 0 +TCON_TR0 SET 0 +TCON_TR1 SET 0 + +; RMAP=x -CPU Timer 0 Register High +TH0_VAL SET 0 + +; RMAP=x -CPU Timer 1 Register High +TH1_VAL SET 0 + +; RMAP=x -CPU Timer 0 Register Low +TL0_VAL SET 0 + +; RMAP=x -CPU Timer 1 Register Low +TL1_VAL SET 0 + +; RMAP=x -CPU Timer Mode Register +TMOD_GATE0 SET 0 +TMOD_GATE1 SET 0 +TMOD_T0M SET 0 +TMOD_T0S SET 0 +TMOD_T1M SET 0 +TMOD_T1S SET 0 + +; RMAP=1 -UART1 Baud Rate Control Register +UART1_BCON_BRPRE SET 0 +UART1_BCON_R SET 0 + +; RMAP=1 -UART1 Baud Rate Timer/Reload Register +UART1_BG_BR_VALUE SET 1 + +; RMAP=1 -UART1 Fractional Divider Control Register +UART1_FDCON_FDEN SET 0 +UART1_FDCON_FDM SET 0 +UART1_FDCON_NDOV SET 0 + +; RMAP=1 -UART1 Fractional Divider Result Register +UART1_FDRES_RESULT SET 0 + +; RMAP=1 -UART1 Fractional Divider Reload Register +UART1_FDSTEP_STEP SET 0 + +; RMAP=1 -UART1 Serial Data Buffer Register +UART1_SBUF_VAL SET 0 + +; RMAP=1 -UART1 Serial Channel Control Register +UART1_SCON_RB8_1 SET 0 +UART1_SCON_REN_1 SET 0 +UART1_SCON_RI_1 SET 0 +UART1_SCON_SM0_1 SET 0 +UART1_SCON_SM1_1 SET 0 +UART1_SCON_SM2_1 SET 0 +UART1_SCON_TB8_1 SET 0 +UART1_SCON_TI_1 SET 0 + +; RMAP=1 -WDT Watchdog Timer Control Register +WDTCON_WDTEN SET 0 +WDTCON_WDTIN SET 1 +WDTCON_WDTPR SET 0 +WDTCON_WDTRS SET 0 +WDTCON_WINBEN SET 0 + +; RMAP=1 -WDT Watchdog Timer Register High +WDTH_WDT SET 0 + +; RMAP=1 -WDT Watchdog Timer Register Low +WDTL_WDT SET 0 + +; RMAP=1 -WDT Watchdog Timer Reload Register +WDTREL_WDTREL SET 219 + +; RMAP=1 -WDT Watchdog Window-Boundary Count Register +WDTWINB_WDTWINB SET 0 + +; RMAP=0 PAGE=3-SCU On-chip XRAM Address Higher Order +XADDRH_ADDRH SET 0 + diff --git a/CL2.0.dav b/CL2.0.dav new file mode 100644 index 0000000000000000000000000000000000000000..735f3c0f789223d409fa8629e4dce9e9de459fa5 GIT binary patch literal 88725 zcmbV#Nt0Yja$fd2)!pc2rh7In;)s-yBbkV)%&aODsD+)CnN^k3x%JB|pn7PsBzjQO z0}>51fdYE?KXlMRCmnQ?nSO$PhRk%5>B1wAyiuRK$KoF0QDc}kn?c1F9_}7rgvSey zx8!7WZ#vlD>+SU}$H&J<-J#5GxIkHC$ z**lKx9WDFaz~yW??snsI{KJ#2hI!W2Fi*c4=6P7dJRxhCXJ!ra6s=*Ns~J8OzfTLl zBV70$;ll3-7k)>$@H@hV-w`hSj&R}kTKrxYen+_QJHmzE5ib0WaN&1^3%?^=_#NTG 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zH1;SwWr7d%(q8f$Pha5w#TInq!`Jlv+1vQJN&a_?!~b*KDxJ`w + +
+
礦ision Build Log

+
Project:

+C:\Documents and Settings\Administrator\桌面\cl2\CL2.0.uvproj
+Project File Date:  
+
+
Output:

+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_SSC_VSENDDATA?SSC
+Program Size: data=9.0 xdata=0 code=163
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+Config.H(1006): warning C318: can't open file 'user_main.H'
+Config.H(1007): warning C318: can't open file 'FlexrayDriver.h'
+Config.H(1009): warning C318: can't open file 'CanDriver.H'
+compiling SSC.C...
+Config.H(1006): warning C318: can't open file 'user_main.H'
+Config.H(1007): warning C318: can't open file 'FlexrayDriver.h'
+Config.H(1009): warning C318: can't open file 'CanDriver.H'
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_SSC_VSENDDATA?SSC
+Program Size: data=9.0 xdata=0 code=163
+"CL2.0" - 0 Error(s), 7 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling SwDriver.C...
+SwDriver.C(240): error C200: left side of '.' requires struct/union
+SwDriver.C(777): error C202: 'P1_2': undefined identifier
+SwDriver.C(778): error C202: 'P1_3': undefined identifier
+SwDriver.C(779): error C202: 'P1_4': undefined identifier
+SwDriver.C(780): error C202: 'P1_4': undefined identifier
+SwDriver.C(781): error C202: 'P1_4': undefined identifier
+SwDriver.C(782): error C202: 'P1_4': undefined identifier
+SwDriver.C(783): error C202: 'P1_4': undefined identifier
+SwDriver.C(784): error C202: 'P1_4': undefined identifier
+SwDriver.C(785): error C202: 'P1_4': undefined identifier
+SwDriver.C(786): error C202: 'P1_4': undefined identifier
+SwDriver.C(787): error C202: 'P1_4': undefined identifier
+SwDriver.C(788): error C202: 'P1_4': undefined identifier
+SwDriver.C(789): error C202: 'P1_4': undefined identifier
+SwDriver.C(790): error C202: 'P1_4': undefined identifier
+SwDriver.C(791): error C202: 'P1_4': undefined identifier
+SwDriver.C(792): error C202: 'P1_4': undefined identifier
+SwDriver.C(793): error C202: 'P1_4': undefined identifier
+SwDriver.C(794): error C202: 'P1_4': undefined identifier
+SwDriver.C(795): error C202: 'P1_4': undefined identifier
+SwDriver.C(796): error C202: 'P1_4': undefined identifier
+SwDriver.C(797): error C202: 'P1_4': undefined identifier
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling SwDriver.C...
+SwDriver.C(240): error C200: left side of '.' requires struct/union
+SwDriver.C(777): error C202: 'P1_2': undefined identifier
+SwDriver.C(778): error C202: 'P1_3': undefined identifier
+SwDriver.C(779): error C202: 'P1_3': undefined identifier
+SwDriver.C(780): error C202: 'P1_3': undefined identifier
+SwDriver.C(781): error C202: 'P1_3': undefined identifier
+SwDriver.C(782): error C202: 'P1_3': undefined identifier
+SwDriver.C(783): error C202: 'P1_3': undefined identifier
+SwDriver.C(784): error C202: 'P1_3': undefined identifier
+SwDriver.C(785): error C202: 'P1_3': undefined identifier
+SwDriver.C(786): error C202: 'P1_3': undefined identifier
+SwDriver.C(787): error C202: 'P1_3': undefined identifier
+SwDriver.C(788): error C202: 'P1_3': undefined identifier
+SwDriver.C(789): error C202: 'P1_3': undefined identifier
+SwDriver.C(790): error C202: 'P1_3': undefined identifier
+SwDriver.C(791): error C202: 'P1_3': undefined identifier
+SwDriver.C(792): error C202: 'P1_3': undefined identifier
+SwDriver.C(793): error C202: 'P1_3': undefined identifier
+SwDriver.C(794): error C202: 'P1_3': undefined identifier
+SwDriver.C(795): error C202: 'P1_3': undefined identifier
+SwDriver.C(796): error C202: 'P1_3': undefined identifier
+SwDriver.C(797): error C202: 'P1_3': undefined identifier
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(863): warning C206: 'Mc33993DataSendRcv': missing function-prototype
+SwDriver.C(863): error C267: 'Mc33993DataSendRcv': requires ANSI-style prototype
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(806): warning C206: 'SSC_vGetData': missing function-prototype
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_SWSTASAMPLE?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_LEDLIGHT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_TOGGLEONEBIT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITSW?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993ANALOGCHSEL?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993STARCVONEBIT?SWDRIVER
+*** WARNING L1: UNRESOLVED EXTERNAL SYMBOL
+    SYMBOL:  SSC_VGETDATA
+    MODULE:  SwDriver.obj (SWDRIVER)
+*** WARNING L2: REFERENCE MADE TO UNRESOLVED EXTERNAL
+    SYMBOL:  SSC_VGETDATA
+    MODULE:  SwDriver.obj (SWDRIVER)
+    ADDRESS: 195EH
+Program Size: data=76.4 xdata=0 code=6607
+"CL2.0" - 0 Error(s), 9 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(801): warning C206: 'SSC_vSendData': missing function-prototype
+SwDriver.C(801): error C267: 'SSC_vSendData': requires ANSI-style prototype
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_SWSTASAMPLE?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_LEDLIGHT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_TOGGLEONEBIT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITSW?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993ANALOGCHSEL?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993STARCVONEBIT?SWDRIVER
+Program Size: data=76.4 xdata=0 code=6610
+"CL2.0" - 0 Error(s), 6 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_SWSTASAMPLE?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993STARCVONEBIT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=63.3 xdata=0 code=4875
+"CL2.0" - 0 Error(s), 3 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993STARCVONEBIT?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=53.3 xdata=0 code=4634
+"CL2.0" - 0 Error(s), 3 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=52.2 xdata=0 code=4066
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=52.2 xdata=0 code=4066
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=59.2 xdata=0 code=4367
+"CL2.0" - 0 Error(s), 2 Warning(s).
+"XC800_FLOAD.EXE" "C:\Documents and Settings\Administrator\桌面\cl2\CL2.HEX" f"
+--- Error: failed to execute '"XC800_FLOAD.EXE" "C:\Documents and Settings\Administrator\桌面\cl2\CL2.HEX" f"'
+Build target 'Target 1'
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=59.2 xdata=0 code=4367
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=59.2 xdata=0 code=4370
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=59.2 xdata=0 code=4301
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=59.2 xdata=0 code=4301
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5591
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+Program Size: data=67.2 xdata=0 code=5594
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5591
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5603
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5603
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5603
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5603
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5603
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=76.2 xdata=0 code=5615
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+user.H(53): error C129: missing ';' before 'UnInfCan_1'
+compiling SSC.C...
+user.H(53): error C129: missing ';' before 'UnInfCan_1'
+compiling IO.C...
+user.H(53): error C129: missing ';' before 'UnInfCan_1'
+compiling SwDriver.C...
+user.H(53): error C129: missing ';' before 'UnInfCan_1'
+compiling User.c...
+user.H(53): error C129: missing ';' before 'UnInfCan_1'
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(205): error C231: 'UnSwOut_1': redefinition
+compiling User.c...
+User.c(11): error C231: 'UnSwOut_1': redefinition
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+User.c(11): error C231: 'UnSwOut_1': redefinition
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+User.c(11): error C231: 'UnSwOut_1': redefinition
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=72.2 xdata=0 code=5609
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=72.2 xdata=0 code=5404
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=72.2 xdata=0 code=5404
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(368): error C204: 'ArrData': undefined member
+SwDriver.C(375): error C204: 'ArrData': undefined member
+SwDriver.C(376): error C204: 'ArrData': undefined member
+SwDriver.C(377): error C204: 'ArrData': undefined member
+SwDriver.C(378): error C204: 'ArrData': undefined member
+SwDriver.C(379): error C204: 'ArrData': undefined member
+SwDriver.C(380): error C204: 'ArrData': undefined member
+SwDriver.C(381): error C204: 'ArrData': undefined member
+SwDriver.C(382): error C204: 'ArrData': undefined member
+SwDriver.C(383): error C204: 'ArrData': undefined member
+SwDriver.C(384): error C204: 'ArrData': undefined member
+SwDriver.C(385): error C204: 'ArrData': undefined member
+SwDriver.C(386): error C204: 'ArrData': undefined member
+SwDriver.C(387): error C204: 'ArrData': undefined member
+SwDriver.C(388): error C204: 'ArrData': undefined member
+SwDriver.C(389): error C204: 'ArrData': undefined member
+SwDriver.C(390): error C204: 'ArrData': undefined member
+SwDriver.C(391): error C204: 'ArrData': undefined member
+SwDriver.C(392): error C204: 'ArrData': undefined member
+SwDriver.C(393): error C204: 'ArrData': undefined member
+SwDriver.C(394): error C204: 'ArrData': undefined member
+SwDriver.C(395): error C204: 'ArrData': undefined member
+compiling User.c...
+User.c(11): error C242: 'union': too many initializers
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(368): error C204: 'ArrData': undefined member
+SwDriver.C(375): error C204: 'ArrData': undefined member
+SwDriver.C(376): error C204: 'ArrData': undefined member
+SwDriver.C(377): error C204: 'ArrData': undefined member
+SwDriver.C(378): error C204: 'ArrData': undefined member
+SwDriver.C(379): error C204: 'ArrData': undefined member
+SwDriver.C(380): error C204: 'ArrData': undefined member
+SwDriver.C(381): error C204: 'ArrData': undefined member
+SwDriver.C(382): error C204: 'ArrData': undefined member
+SwDriver.C(383): error C204: 'ArrData': undefined member
+SwDriver.C(384): error C204: 'ArrData': undefined member
+SwDriver.C(385): error C204: 'ArrData': undefined member
+SwDriver.C(386): error C204: 'ArrData': undefined member
+SwDriver.C(387): error C204: 'ArrData': undefined member
+SwDriver.C(388): error C204: 'ArrData': undefined member
+SwDriver.C(389): error C204: 'ArrData': undefined member
+SwDriver.C(390): error C204: 'ArrData': undefined member
+SwDriver.C(391): error C204: 'ArrData': undefined member
+SwDriver.C(392): error C204: 'ArrData': undefined member
+SwDriver.C(393): error C204: 'ArrData': undefined member
+SwDriver.C(394): error C204: 'ArrData': undefined member
+SwDriver.C(395): error C204: 'ArrData': undefined member
+compiling User.c...
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=72.2 xdata=0 code=5404
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+SwDriver.H(8): error C141: syntax error near '*', expected ')'
+compiling SSC.C...
+SwDriver.H(8): error C141: syntax error near '*', expected ')'
+compiling IO.C...
+SwDriver.H(8): error C141: syntax error near '*', expected ')'
+compiling SwDriver.C...
+SwDriver.H(8): error C141: syntax error near '*', expected ')'
+compiling User.c...
+SwDriver.H(8): error C141: syntax error near '*', expected ')'
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(227): warning C280: 'i': unreferenced local variable
+SwDriver.C(227): warning C280: 'j': unreferenced local variable
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4073
+"CL2.0" - 0 Error(s), 4 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(227): warning C280: 'i': unreferenced local variable
+SwDriver.C(227): warning C280: 'j': unreferenced local variable
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4073
+"CL2.0" - 0 Error(s), 4 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(227): warning C280: 'i': unreferenced local variable
+SwDriver.C(227): warning C280: 'j': unreferenced local variable
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4073
+"CL2.0" - 0 Error(s), 4 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4073
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4073
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=56.2 xdata=0 code=4076
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+Config.H(67): error C238: 'fff': duplicate member
+compiling SSC.C...
+Config.H(67): error C238: 'fff': duplicate member
+compiling IO.C...
+Config.H(67): error C238: 'fff': duplicate member
+compiling SwDriver.C...
+Config.H(67): error C238: 'fff': duplicate member
+compiling User.c...
+Config.H(67): error C238: 'fff': duplicate member
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?_MC33993CMDSENDONEBIT?SWDRIVER
+Program Size: data=58.2 xdata=0 code=4093
+"CL2.0" - 0 Error(s), 2 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(264): warning C206: 'LedLight': missing function-prototype
+SwDriver.C(264): error C267: 'LedLight': requires ANSI-style prototype
+SwDriver.C(266): error C202: 'j': undefined identifier
+SwDriver.C(266): error C202: 'i': undefined identifier
+SwDriver.C(287): error C204: 'RES43': undefined member
+SwDriver.C(288): error C204: 'RES44': undefined member
+SwDriver.C(292): error C202: 'j': undefined identifier
+SwDriver.C(292): error C202: 'i': undefined identifier
+SwDriver.C(353): error C231: 'LedLight': redefinition
+SwDriver.C(390): error C231: 'LedLight': redefinition
+compiling User.c...
+User.c(11): error C242: 'union': too many initializers
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(264): warning C206: 'LedLight': missing function-prototype
+SwDriver.C(264): error C267: 'LedLight': requires ANSI-style prototype
+SwDriver.C(266): error C202: 'j': undefined identifier
+SwDriver.C(266): error C202: 'i': undefined identifier
+SwDriver.C(287): error C204: 'RES43': undefined member
+SwDriver.C(288): error C204: 'RES44': undefined member
+SwDriver.C(292): error C202: 'j': undefined identifier
+SwDriver.C(292): error C202: 'i': undefined identifier
+SwDriver.C(353): error C231: 'LedLight': redefinition
+SwDriver.C(390): error C231: 'LedLight': redefinition
+compiling User.c...
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+SwDriver.C(266): warning C206: 'LedLight': missing function-prototype
+SwDriver.C(266): error C267: 'LedLight': requires ANSI-style prototype
+SwDriver.C(355): error C231: 'LedLight': redefinition
+SwDriver.C(392): error C231: 'LedLight': redefinition
+compiling User.c...
+Target not created
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS
+    SEGMENT: ?PR?INITMC33993SEC?SWDRIVER
+Program Size: data=68.2 xdata=0 code=5692
+"CL2.0" - 0 Error(s), 1 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5695
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Load "C:\\Documents and Settings\\Administrator\\桌面\\cl2\\CL2.0" 
+Searching for DAS Server 'UDAS'...
+DAS Server 'UDAS' is installed.
+DAS Server 'UDAS' is not started yet. Trying to start it now...
+DAS Server 'UDAS' has been started successfully.
+Erasing Bank 0  Sectors: 0
+Erase Done.
+Programming Done.
+Verify Done.
+Application running ...
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
+Program Size: data=67.2 xdata=0 code=5695
+"CL2.0" - 0 Error(s), 0 Warning(s).
+Rebuild target 'Target 1'
+assembling START_XC.a51...
+compiling MAIN.C...
+compiling SSC.C...
+compiling IO.C...
+compiling SwDriver.C...
+compiling User.c...
+linking...
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+creating hex file from ".\output\CL2.0"...
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diff --git a/CL2.0.rtf b/CL2.0.rtf
new file mode 100644
index 0000000..f34f6a4
--- /dev/null
+++ b/CL2.0.rtf
@@ -0,0 +1,1141 @@
+{\rtf1\ansi\deff0\deftab720{\fonttbl{\f0\fnil MS Sans Serif;}{\f1\fnil\fcharset2 Symbol;}{\f2\fswiss\fprq2 System;}{\f3\fnil Times New Roman;}{\f4\fswiss\fprq2 Arial;}}
+{\colortbl\red0\green0\blue0;\red0\green0\blue128;\red255\green0\blue0;}
+\deflang1031\pard\plain\f4\fs28\cf0 DAvE's Project Documentation
+\par \plain\f4\fs22\cf0
+\par \plain\f4\fs22\cf0 Project: \tab\tab\b CL2.0.dav
+\par 
+\par \plain\f4\fs22\cf0 Controller: \tab\tab\b XC886CLM-8FF
+\par \plain\f4\fs22\cf0 Compiler: \tab\tab\b Keil
+\par \plain\f4\fs22\cf0 Memory Model: \tab\b COMPACT
+\par 
+\par \plain\f4\fs22\cf0 Date: \tab\tab\tab\b 2025/1/18 20:45:36
+\par 
+\par 
+\par \plain\f4\fs22\cf2\b Please read this document carefully and note
+\par \plain\f4\fs22\cf2\b the red-colored hints.
+\par 
+\par \plain\f4\fs22\cf2\b If you miss a file in the generated files list
+\par \plain\f4\fs22\cf2\b maybe you have forgotten to select the
+\par \plain\f4\fs22\cf2\b initialisation function of the related module.
+\par 
+\par \plain\f4\fs22\cf0 Generated Files:
+\plain\f4\fs20\cf0\b
+\par \tab\tab\tab MAIN.H
+\par \tab\tab\tab MAIN.C
+\par \tab\tab\tab SHARED_INT.H
+\par \tab\tab\tab SHARED_INT.C
+\par \tab\tab\tab IO.H
+\par \tab\tab\tab IO.C
+\par \tab\tab\tab T2.H
+\par \tab\tab\tab T2.C
+\par \tab\tab\tab WDT.H
+\par \tab\tab\tab WDT.C
+\par \tab\tab\tab CAN.H
+\par \tab\tab\tab CAN.C
+\par \tab\tab\tab CL2.0.ASM
+\par 
+\par 
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul Project Settings
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void MAIN_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function initializes the microcontroller. It is
+
+\par \tab \tab assumed that the SFRs are in their reset state.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void main(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the main function.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab Configuration of the System Clock:\par 
+\tab - External Osc is selected (configuration is done in the startup file\par 
+\tab 'START_XC.A51')\par 
+\tab - PLL Mode, NDIV =  24\par 
+\tab - input frequency is 8 MHz\par 
+\par 
+\tab *********************************************************************************\par 
+\tab Note : All peripheral related IO configurations are done in the\par 
+\tab respective peripheral modules (alternate functions selection)\par 
+\tab *********************************************************************************\par 
+\par 
+\tab Initialization of module 'GPIO'\par 
+\par 
+\tab Initialization of module 'Timer 2'\par 
+\par 
+\tab Initialization of module 'Watch Dog Timer'\par 
+\par 
+\tab Initialization of module 'MultiCAN Controller '\par 
+\par 
+\tab Initialization of  'Shared interrupts'\par 
+\par 
+\tab \cf2Interrupt structure 2 mode 0 is selected.\cf0\par 
+\par 
+\tab \cf2Interrupt service routine choice 2 is selected.\cf0\par 
+\par 
+
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul Shared Interrupt Routines
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void SHINT_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function initializes the shared interrupts.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void SHINT_viXINTR5Isr(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the service routine for the shared interrupt node
+
+\par \tab \tab XINTR5. XINTR5 ISR Node is shared by Timer 2, UART
+
+\par \tab \tab Fractional Divider(BRG Interrupt),MultiCAN Node 0 and LIN.
+
+\par \tab \tab Depending on the selected module interrupt it is called.
+
+\par \tab \tab T2 - Depending on the selected operating mode it is called
+
+\par \tab \tab when TF2 is set by an overflow or underflow of the timer 2
+
+\par \tab \tab register or when EXF2 is set by a negative transition on
+
+\par \tab \tab T2EX.
+
+\par \tab \tab UART - It is called after the BRG timer overflows and sets
+
+\par \tab \tab the NDOV bit.
+
+\par \tab \tab CAN -  It is called for the  Service Request Node 0 of the
+
+\par \tab \tab MultiCAN module.
+
+\par \tab \tab Please note that you have to add application specific code
+
+\par \tab \tab to this function.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b none\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab Configuration of the Shared  Interrupts:\par 
+\tab - Timer 2 Interrupt is Selected\par 
+\par 
+
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul GPIO
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab IO_ubReadPin(PinName)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro returns the status of the chosen portpin.
+
+\par \tab \tab Note:
+
+\par \tab \tab 'PinName' identifies the pin of a bit-addressable port. The
+
+\par \tab \tab default names can be changed in the port configuration
+
+\par \tab \tab dialog.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b Status of the chosen portpin\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab PinName:
+
+\par \tab \tab Pin to be read
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab IO_vSetPin(PinName)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab The chosen portpin is set to '1'.
+
+\par \tab \tab Note:
+
+\par \tab \tab 'PinName' identifies the pin of a bit-addressable port. The
+
+\par \tab \tab default names can be changed in the port configuration
+
+\par \tab \tab dialog.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab PinName:
+
+\par \tab \tab Pin to be set to '1'
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab IO_vResetPin(PinName)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab The chosen portpin is set to '0'.
+
+\par \tab \tab Note:
+
+\par \tab \tab 'PinName' identifies the pin of a bit-addressable port. The
+
+\par \tab \tab default names can be changed in the port configuration
+
+\par \tab \tab dialog.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab PinName:
+
+\par \tab \tab Pin to be set to '0'
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab IO_vTogglePin(PinName)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab The chosen portpin will be toggled.
+
+\par \tab \tab Note:
+
+\par \tab \tab 'PinName' identifies the pin of a bit-addressable port. The
+
+\par \tab \tab default names can be changed in the port configuration
+
+\par \tab \tab dialog.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab PinName:
+
+\par \tab \tab Pin to be toggled
+
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void IO_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the initialization function of the IO function
+
+\par \tab \tab library. It is assumed that the SFRs used by this library
+
+\par \tab \tab are in their reset state.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab ***********************************************************************\par 
+\tab Note : All peripheral related IO configurations are done in the\par 
+\tab respective peripheral modules (alternate functions selection)\par 
+\tab \par 
+\tab If no pins are selected DAvE assumes that registers are in default\par 
+\tab settings\par 
+\tab ***********************************************************************\par 
+\par 
+\tab Configuration of Port P0:\par 
+\tab P0.0:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P0.1:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P0.2:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P0.3:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P0.7:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\par 
+\tab Configuration of Port P1:\par 
+\tab P1.0:\par 
+\tab - is used as alternate input for the MCAN Node 0 Receiver Input\par 
+\tab - pull-up device is assigned\par 
+\tab P1.1:\par 
+\tab - is used as alternate output for the MCAN Node 0 Transmitter Output\par 
+\tab - push/pull output is selected\par 
+\tab - pull-up device is assigned\par 
+\tab P1.2:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P1.3:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P1.4:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P1.5:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P1.7:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\par 
+\tab Configuration of Port P2:\par 
+\tab P2.4:\par 
+\tab - is used as general input\par 
+\tab - input driver is enabled\par 
+\tab - pull-up device is assigned\par 
+\tab P2.5:\par 
+\tab - is used as general input\par 
+\tab - input driver is enabled\par 
+\tab - pull-up device is assigned\par 
+\tab P2.6:\par 
+\tab - is used as general input\par 
+\tab - input driver is enabled\par 
+\tab - pull-up device is assigned\par 
+\tab P2.7:\par 
+\tab - is used as general input\par 
+\tab - input driver is enabled\par 
+\tab - pull-up device is assigned\par 
+\par 
+\tab Configuration of Port P3:\par 
+\tab P3.0:\par 
+\tab - is used as general input\par 
+\tab - pull-up device is assigned\par 
+\tab P3.1:\par 
+\tab - is used as general input\par 
+\tab - pull-up device is assigned\par 
+\tab P3.2:\par 
+\tab - is used as general purpose output\par 
+\tab - open drain output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P3.3:\par 
+\tab - is used as general purpose output\par 
+\tab - open drain output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P3.4:\par 
+\tab - is used as general purpose output\par 
+\tab - open drain output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P3.5:\par 
+\tab - is used as general purpose output\par 
+\tab - open drain output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P3.6:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\tab P3.7:\par 
+\tab - is used as general input\par 
+\tab - pull-up device is assigned\par 
+\par 
+\tab Configuration of Port P4:\par 
+\tab P4.0:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P4.1:\par 
+\tab - is used as general purpose output\par 
+\tab - push/pull output is selected\par 
+\tab - the pin status is low level\par 
+\tab - pull-down device is assigned\par 
+\tab P4.3:\par 
+\tab - is used as general input\par 
+\tab - pull device is disabled (tristate)\par 
+\par 
+
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul Timer 2
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void T2_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the initialization function of the Timer 2 function
+
+\par \tab \tab library. It is assumed that the SFRs used by this library
+
+\par \tab \tab are in their reset state.
+
+\par \tab \tab The following SFRs and SFR fields will be initialized:
+
+\par \tab \tab T2_RC2H/RC2L     - reload/capture timer 2 register
+
+\par \tab \tab T2_T2H/T2L     -  timer 2 register
+
+\par \tab \tab ET2           - timer 2 interrupt enable
+
+\par \tab \tab T2_T2MOD         - timer 2 mode register
+
+\par \tab \tab CP/RL2        - Capture/Reload select
+
+\par \tab \tab EXEN2         - External enable control
+
+\par \tab \tab TR2           - Timer2 run control
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab 16-bit timer function with automatic reload when timer 2 overflows\par 
+\tab the timer 2 resolution is 1 ?s\par 
+\tab the timer 2 overflow is 1000.000 ?s\par 
+\tab timer 2 interrupt: enabled\par 
+\tab timer 2 will be started\par 
+\par 
+\tab timer 2 Interrupt enable bit is set in SHINT_vInit() function\par 
+\par 
+
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul Watch Dog Timer
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab WDT_vRefresh()\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro refreshes the watchdog timer to the reload
+
+\par \tab \tab value. The interrupts are disabled during execution of the
+
+\par \tab \tab instructions that set bit WDTRS.
+
+\par \tab \tab Note: The user has to take care that this macro is called
+
+\par \tab \tab before expiry of the watchdog timer.
+
+\par \tab \tab pls refer to the Note on WDT_vInit function Description
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void WDT_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the initialization function of the 'Watch Dog
+
+\par \tab \tab Timer' function library. It is assumed that the SFRs used
+
+\par \tab \tab by this library are in their reset state.
+
+\par \tab \tab The watchdog timer is used.
+
+\par \tab \tab The following SFR fields will be initialized:
+
+\par \tab \tab WDTREL - WDT reload value
+
+\par \tab \tab WDTIN  - WDT input frequency selection
+
+\par \tab \tab Then the watchdog timer will be refreshed.
+
+\par \tab \tab Note: The user has to take care that RMAP bit in SYSCON0 is
+
+\par \tab \tab to be set while using the registers of Watch dog timer.
+
+\par \tab \tab Registers are WDTCON,WDTWINB,WDTREL,WDTH,WDTL
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void WDT_vDisable(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function disables the WDT.
+
+\par \tab \tab pls refer to the Note on WDT_vInit function Description
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab the watchdog timer is used and it is enabled in INIT function,user has\par 
+\tab to take care of WDT refresh\par 
+\tab the RMAP bit of SYSCON0 is set\par 
+\tab the input frequency is fSYS/128\par 
+\tab the watchdog timer reload value is 0xDB\par 
+\tab the watchdog timeout period is 50 ms\par 
+\par 
+
+\par \plain\f4\fs20\cf0
+\par \plain\f4\fs28\cf0\ul MultiCAN Controller
+\par
+\par \plain\f4\fs24\cf0 Macros:\f4\fs20\cf0
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab CAN_vReadEN()\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro enables Read mode (CAN Address/Data Control
+
+\par \tab \tab Register).
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab CAN_vWriteEN(ubyte ubDCtrl)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro enables Write mode (CAN Address/Data Control
+
+\par \tab \tab Register).
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubDCtrl:
+
+\par \tab \tab Data Control Flags
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab CAN_vWriteCANAddress(uword uwAdr)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro writes 16-bit CAN address to CAN Address
+
+\par \tab \tab Register Low and High respectively.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab uwAdr:
+
+\par \tab \tab 16-bit Address
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab CAN_vWriteCANData(ulong ulValue)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This macro writes 32-bit Data to CAN Data Register's
+
+\par \tab \tab 0-3respectively.
+
+\par \tab \tab Note:
+
+\par \tab \tab Write Process :
+
+\par \tab \tab ->Write the address of the MultiCAN kernel register to the
+
+\par \tab \tab CAN_ADL and CAN_ADH registers.
+
+\par \tab \tab use macro : CAN_vWriteCANAddress.
+
+\par \tab \tab ->Write the data to the
+
+\par \tab \tab CAN_DATA0/CAN_DATA1/CAN_DATA2/CAN_DATA3 registers.
+
+\par \tab \tab ->Write the register CAN_ADCON, including setting the valid
+
+\par \tab \tab bit of the data registers and setting register bit RWEN to
+
+\par \tab \tab 1.
+
+\par \tab \tab ->The valid data will be written to the MultiCAN kernel
+
+\par \tab \tab only once. Register bit BSY will become 1.
+
+\par \tab \tab ->When Register bit BSY becomes 0, the transmission is
+
+\par \tab \tab finished.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ulValue:
+
+\par \tab \tab 32-bit Data
+
+\par
+\par
+\par \plain\f4\fs20\cf0 \tab Macro:
+\par \plain\f4\fs20\cf0\b \tab \tab CAN_pushAMRegs/_popAMRegs()\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab The macro CAN_pushAMRegs() PUSH the CAN Access Mediator
+
+\par \tab \tab Registers.
+
+\par \tab \tab The macro CAN_popAMRegs() POP the CAN Access Mediator
+
+\par \tab \tab Registers.
+
+\par \tab \tab Note:
+
+\par \tab \tab This macro is used in CAN ISR/Function's to protect Access
+
+\par \tab \tab Mediator Register
+
+\par \tab \tab MultiCAN Access Mediator Registers:
+
+\par \tab \tab ADL, ADH, DATA0, DATA1, DATA2, DATA3.
+
+\par \tab \tab The _push_/_pop_ routine inserts a PUSH/POP instruction
+
+\par \tab \tab into the program saving the contents of the Special
+
+\par \tab \tab Function Register(sfr) on the Stack.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par \plain\f4\fs24\cf0 Functions:\f4\fs20\cf0
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vInit(void)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This is the initialization function of the CAN function
+
+\par \tab \tab library. It is assumed that the SFRs used by this library
+
+\par \tab \tab are in their reset state.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab None
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vWriteAMData(ulong ulValue)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function writes 32-bit Data to CAN Data Register's
+
+\par \tab \tab 0-3respectively.
+
+\par \tab \tab Note:
+
+\par \tab \tab Write Process :
+
+\par \tab \tab ->Write the address of the MultiCAN kernel register to the
+
+\par \tab \tab CAN_ADL and CAN_ADH registers.
+
+\par \tab \tab use macro : CAN_vWriteCANAddress.
+
+\par \tab \tab ->Write the data to the
+
+\par \tab \tab CAN_DATA0/CAN_DATA1/CAN_DATA2/CAN_DATA3 registers.
+
+\par \tab \tab ->Write the register CAN_ADCON, including setting the valid
+
+\par \tab \tab bit of the data registers and setting register bit RWEN to
+
+\par \tab \tab 1.
+
+\par \tab \tab ->The valid data will be written to the MultiCAN kernel
+
+\par \tab \tab only once. Register bit BSY will become 1.
+
+\par \tab \tab ->When Register bit BSY becomes 0, the transmission is
+
+\par \tab \tab finished.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ulValue:
+
+\par \tab \tab 32-bit Data
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vSetListCommand(ulong ulVal)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function write's 32-bit Data to CAN_PANCTR Register.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ulVal:
+
+\par \tab \tab 32-bit Data
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vGetMsgObj(ubyte ubObjNr, stCAN_SWObj *pstObj)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function fills the forwarded SW message object with
+
+\par \tab \tab the content of the chosen HW message object.
+
+\par \tab \tab The structure of the SW message object is defined in the
+
+\par \tab \tab header file CAN.H (see stCAN_SWObj).
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object to be read (0-31)
+
+\par \tab \tab *pstObj:
+
+\par \tab \tab Pointer on a message object to be filled by this function
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab ubyte CAN_ubRequestMsgObj(ubyte ubObjNr)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab If a TRANSMIT OBJECT is to be reconfigured it must first be
+
+\par \tab \tab accessed. The access to the transmit object is exclusive.
+
+\par \tab \tab This function checks whether the choosen message object is
+
+\par \tab \tab still executing a transmit request, or if the object can be
+
+\par \tab \tab accessed exclusively.
+
+\par \tab \tab After the message object is reserved, it can be
+
+\par \tab \tab reconfigured by using the function CAN_vConfigMsgObj or
+
+\par \tab \tab CAN_vLoadData.
+
+\par \tab \tab Both functions enable access to the object for the CAN
+
+\par \tab \tab controller.
+
+\par \tab \tab By calling the function CAN_vTransmit transfering of data
+
+\par \tab \tab is started.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b 0 message object is busy (a transfer is active), else 1\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object (0-31)
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab ubyte CAN_ubNewData(ubyte ubObjNr)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function checks whether the selected RECEIVE OBJECT
+
+\par \tab \tab has received a new message. If so the function returns the
+
+\par \tab \tab value '1'.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b 1 the message object has received a new message, else 0\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object (0-31)
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vTransmit(ubyte ubObjNr)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function triggers the CAN controller to send the
+
+\par \tab \tab selected message.
+
+\par \tab \tab If the selected message object is a TRANSMIT OBJECT then
+
+\par \tab \tab this function triggers the sending of a data frame. If
+
+\par \tab \tab however the selected message object is a RECEIVE OBJECT
+
+\par \tab \tab this function triggers the sending of a remote frame.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object (0-31)
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vLoadData(ubyte ubObjNr, ulong *ulpubData)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab If a hardware TRANSMIT OBJECT has to be loaded with data
+
+\par \tab \tab but not with a new identifier, this function may be used
+
+\par \tab \tab instead of the function CAN_vConfigMsgObj. The message
+
+\par \tab \tab object should be accessed by calling the function
+
+\par \tab \tab CAN_ubRequestMsgObj before calling this function. This
+
+\par \tab \tab prevents the CAN controller from working with invalid data.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object to be configured (0-31)
+
+\par \tab \tab *ulpubData:
+
+\par \tab \tab Pointer on a data buffer
+
+\par
+\par \plain\f4\fs20\cf0 \tab Function:
+\par \plain\f4\fs20\cf0\b \tab \tab void CAN_vReleaseObj(ubyte ubObjNr)\plain\f4\fs20\cf0
+\par \tab Description:
+\par \plain\f4\fs20\cf0\i
+\tab \tab This function resets the NEWDAT flag of the selected
+
+\par \tab \tab RECEIVE OBJECT, so that the CAN controller have access to
+
+\par \tab \tab it. This function must be called if the function
+
+\par \tab \tab CAN_ubNewData detects, that new data are present in the
+
+\par \tab \tab message object and the actual data have been read by
+
+\par \tab \tab calling the function CAN_vGetMsgObj.
+
+\par \plain\f4\fs20\cf0 \tab Returnvalue:
+\par \tab \tab \plain\f4\fs20\cf0\b None\plain\f4\fs20\cf0
+\par \plain\f4\fs20\cf0 \tab Parameters:
+\par \plain\f4\fs20\cf0\b 
+\tab \tab ubObjNr:
+
+\par \tab \tab Number of the message object (0-31)
+
+\par
+\par \plain\f4\fs24\cf0 Initialization:
+\par \plain\f4\fs20\cf0\b
+\par
+\tab Configuration of the Module Clock:\par 
+\tab - the CAN module clock = 48.00 MHz\par 
+\tab - FCLK runs at 2 times the frequency of PCLK.\par 
+\par 
+\tab - CMCON - Clock Control Register is Configured in MAIN_vInit\par 
+\par 
+\tab Configuration of CAN Node 0:\par 
+\par 
+\tab General Configuration of the Node 0:\par 
+\tab - set INIT and CCE\par 
+\par 
+\tab - load NODE 0 interrupt pointer register\par 
+\par 
+\tab Configuration of the used CAN Input Port Pins:\par 
+\tab - Pin P1.0 is used as RXDC0_0 input\par 
+\par 
+\tab - Loop-back mode is disabled\par 
+\par 
+\tab Configuration of the Node 0 Baud Rate:\par 
+\tab - required baud rate = 100.000 kbaud\par 
+\tab - real baud rate     = 100.000 kbaud\par 
+\tab - sample point       = 60.00 %\par 
+\tab - there are 5 time quanta before sample point\par 
+\tab - there are 4 time quanta after sample point\par 
+\tab - the (re)synchronization jump width is 2 time quanta\par 
+\par 
+\tab Configuration of the Node 0 Error Counter:\par 
+\tab - the error warning threshold value (warning level) is 96\par 
+\par 
+\tab Configuration of the Frame Counter:\par 
+\tab - Frame Counter Mode: the counter is incremented upon the reception\par 
+\tab and transmission of frames\par 
+\tab - frame counter: 0x0000\par 
+\par 
+\tab Configuration of CAN Node 1:\par 
+\par 
+\tab General Configuration of the Node 1:\par 
+\tab - set INIT and CCE\par 
+\par 
+\tab Configuration of the used CAN Output Port Pins:\par 
+\tab Pin P1.1 is used as TXDC0_0 Output\par 
+\tab - NODE1 TXD Pin's are not used\par 
+\par 
+\tab Configuration of the CAN Message Object List Structure:\par 
+\par 
+\tab Allocate MOs for list 1:\par 
+\par 
+\tab Configuration of the CAN Message Objects 0 - 31:\par 
+\tab Configuration of Message Object 0:\par 
+\tab - message object 0 is not valid\par 
+\tab Configuration of Message Object 1:\par 
+\tab - message object 1 is not valid\par 
+\tab Configuration of Message Object 2:\par 
+\tab - message object 2 is not valid\par 
+\tab Configuration of Message Object 3:\par 
+\tab - message object 3 is not valid\par 
+\tab Configuration of Message Object 4:\par 
+\tab - message object 4 is not valid\par 
+\tab Configuration of Message Object 5:\par 
+\tab - message object 5 is valid\par 
+\tab - message object is used as receive object\par 
+\tab - this message object is assigned to list 1 (node 0)\par 
+\par 
+\tab - priority class 3; transmit acceptance filtering is based on the list\par 
+\tab order (like class 1)\par 
+\tab - extended 29-bit identifier\par 
+\tab - identifier 29-bit:      0x00000003\par 
+\par 
+\tab - only accept receive frames with matching IDE bit\par 
+\tab - acceptance mask 29-bit: 0x1FFFFFFF\par 
+\par 
+\tab - use message pending register 0 bit position 5\par 
+\par 
+\tab - this object is a STANDARD MESSAGE OBJECT\par 
+\tab - 8 valid data bytes\par 
+\par 
+\tab Configuration of Message Object 6:\par 
+\tab - message object 6 is valid\par 
+\tab - message object is used as transmit object\par 
+\tab - this message object is assigned to list 1 (node 0)\par 
+\par 
+\tab - priority class 3; transmit acceptance filtering is based on the list\par 
+\tab order (like class 1)\par 
+\tab - extended 29-bit identifier\par 
+\tab - identifier 29-bit:      0x11000001\par 
+\par 
+\tab - only accept receive frames with matching IDE bit\par 
+\tab - acceptance mask 29-bit: 0x1FFFFFFF\par 
+\par 
+\tab - use message pending register 0 bit position 6\par 
+\par 
+\tab - this object is a STANDARD MESSAGE OBJECT\par 
+\tab - 8 valid data bytes\par 
+\par 
+\tab Configuration of Message Object 7:\par 
+\tab - message object 7 is valid\par 
+\tab - message object is used as receive object\par 
+\tab - this message object is assigned to list 1 (node 0)\par 
+\par 
+\tab - priority class 3; transmit acceptance filtering is based on the list\par 
+\tab order (like class 1)\par 
+\tab - extended 29-bit identifier\par 
+\tab - identifier 29-bit:      0x11000002\par 
+\par 
+\tab - only accept receive frames with matching IDE bit\par 
+\tab - acceptance mask 29-bit: 0x1FFFFFFF\par 
+\par 
+\tab - use message pending register 0 bit position 7\par 
+\par 
+\tab - this object is a STANDARD MESSAGE OBJECT\par 
+\tab - 8 valid data bytes\par 
+\par 
+\tab Configuration of Message Object 8:\par 
+\tab - message object 8 is valid\par 
+\tab - message object is used as receive object\par 
+\tab - this message object is assigned to list 1 (node 0)\par 
+\par 
+\tab - priority class 3; transmit acceptance filtering is based on the list\par 
+\tab order (like class 1)\par 
+\tab - extended 29-bit identifier\par 
+\tab - identifier 29-bit:      0x11000003\par 
+\par 
+\tab - only accept receive frames with matching IDE bit\par 
+\tab - acceptance mask 29-bit: 0x1FFFFFFF\par 
+\par 
+\tab - use message pending register 0 bit position 8\par 
+\par 
+\tab - this object is a STANDARD MESSAGE OBJECT\par 
+\tab - 8 valid data bytes\par 
+\par 
+\tab Configuration of Message Object 9:\par 
+\tab - message object 9 is valid\par 
+\tab - message object is used as transmit object\par 
+\tab - this message object is assigned to list 1 (node 0)\par 
+\par 
+\tab - priority class 3; transmit acceptance filtering is based on the list\par 
+\tab order (like class 1)\par 
+\tab - extended 29-bit identifier\par 
+\tab - identifier 29-bit:      0x1FFFFFF0\par 
+\par 
+\tab - only accept receive frames with matching IDE bit\par 
+\tab - acceptance mask 29-bit: 0x1FFFFFFF\par 
+\par 
+\tab - use message pending register 0 bit position 9\par 
+\par 
+\tab - this object is a STANDARD MESSAGE OBJECT\par 
+\tab - 8 valid data bytes\par 
+\par 
+\tab Configuration of Message Object 10:\par 
+\tab - message object 10 is not valid\par 
+\tab Configuration of Message Object 11:\par 
+\tab - message object 11 is not valid\par 
+\tab Configuration of Message Object 12:\par 
+\tab - message object 12 is not valid\par 
+\tab Configuration of Message Object 13:\par 
+\tab - message object 13 is not valid\par 
+\tab Configuration of Message Object 14:\par 
+\tab - message object 14 is not valid\par 
+\tab Configuration of Message Object 15:\par 
+\tab - message object 15 is not valid\par 
+\tab Configuration of Message Object 16:\par 
+\tab - message object 16 is not valid\par 
+\tab Configuration of Message Object 17:\par 
+\tab - message object 17 is not valid\par 
+\tab Configuration of Message Object 18:\par 
+\tab - message object 18 is not valid\par 
+\tab Configuration of Message Object 19:\par 
+\tab - message object 19 is not valid\par 
+\tab Configuration of Message Object 20:\par 
+\tab - message object 20 is not valid\par 
+\tab Configuration of Message Object 21:\par 
+\tab - message object 21 is not valid\par 
+\tab Configuration of Message Object 22:\par 
+\tab - message object 22 is not valid\par 
+\tab Configuration of Message Object 23:\par 
+\tab - message object 23 is not valid\par 
+\tab Configuration of Message Object 24:\par 
+\tab - message object 24 is not valid\par 
+\tab Configuration of Message Object 25:\par 
+\tab - message object 25 is not valid\par 
+\tab Configuration of Message Object 26:\par 
+\tab - message object 26 is not valid\par 
+\tab Configuration of Message Object 27:\par 
+\tab - message object 27 is not valid\par 
+\tab Configuration of Message Object 28:\par 
+\tab - message object 28 is not valid\par 
+\tab Configuration of Message Object 29:\par 
+\tab - message object 29 is not valid\par 
+\tab Configuration of Message Object 30:\par 
+\tab - message object 30 is not valid\par 
+\tab Configuration of Message Object 31:\par 
+\tab - message object 31 is not valid\par 
+\par 
+\tab Configuration of the Interrupts:\par 
+\tab - CAN interrupt node 0 is disabled\par 
+\tab - CAN interrupt node 1 is disabled\par 
+\tab - CAN interrupt node 2 is disabled\par 
+\tab - CAN interrupt node 3 is disabled\par 
+\tab - CAN interrupt node 4 is disabled\par 
+\tab - CAN interrupt node 5 is disabled\par 
+\tab - CAN interrupt node 6 is disabled\par 
+\tab - CAN interrupt node 7 is disabled\par 
+\par 
+
+}
diff --git a/CL2.0.uvgui.Administrator b/CL2.0.uvgui.Administrator
new file mode 100644
index 0000000..2ac16cd
--- /dev/null
+++ b/CL2.0.uvgui.Administrator
@@ -0,0 +1,2488 @@
+
+
+
+  -3.1
+
+  
### uVision Project, (C) Keil Software

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diff --git a/CL2.0.uvgui.liuminVir b/CL2.0.uvgui.liuminVir
new file mode 100644
index 0000000..6ba5862
--- /dev/null
+++ b/CL2.0.uvgui.liuminVir
@@ -0,0 +1,1896 @@
+
+
+
+  -6.1
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### uVision Project, (C) Keil Software

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diff --git a/CL2.0.uvgui.liuminVir.bak b/CL2.0.uvgui.liuminVir.bak
new file mode 100644
index 0000000..d598d9f
--- /dev/null
+++ b/CL2.0.uvgui.liuminVir.bak
@@ -0,0 +1,1878 @@
+
+
+
+  -6.1
+
+  
### uVision Project, (C) Keil Software

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diff --git a/CL2.0.uvgui_Administrator.bak b/CL2.0.uvgui_Administrator.bak
new file mode 100644
index 0000000..f5b622a
--- /dev/null
+++ b/CL2.0.uvgui_Administrator.bak
@@ -0,0 +1,2488 @@
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+
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+  -3.1
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diff --git a/CL2.0.uvopt b/CL2.0.uvopt
new file mode 100644
index 0000000..dcb2fd5
--- /dev/null
+++ b/CL2.0.uvopt
@@ -0,0 +1,374 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    187610842
+    31157159
+  
+
+  
+    Target 1
+    0x0
+    MCS-51
+    
+      96000000
+      
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+        .\output\
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+        1
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+      
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+        1
+      
+      6
+      
+        
+          0
+          User's Manual
+          DATASHTS\INFINEON\XC886_UM.PDF
+        
+        
+          1
+          XC800 Instruction Set Manual
+          DATASHTS\INFINEON\XC800_IS.PDF
+        
+      
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
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+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        BIN\DAS2XC800.DLL
+      
+      
+        
+          0
+          DLGDC51
+          (5130=-1,-1,-1,-1,0)(5131=-1,-1,-1,-1,0)(5132=-1,-1,-1,-1,0)(5133=-1,-1,-1,-1,0)(5134=-1,-1,-1,-1,0)(1203=-1,-1,-1,-1,0)(5152=-1,-1,-1,-1,0)(94=-1,-1,-1,-1,0)(5150=-1,-1,-1,-1,0)(5140=-1,-1,-1,-1,0)(5141=-1,-1,-1,-1,0)(5142=-1,-1,-1,-1,0)(5143=-1,-1,-1,-1,0)(5144=-1,-1,-1,-1,0)(5145=-1,-1,-1,-1,0)(5019=-1,-1,-1,-1,0)(5020=-1,-1,-1,-1,0)(5018=-1,-1,-1,-1,0)(5021=-1,-1,-1,-1,0)(5022=-1,-1,-1,-1,0)(5151=-1,-1,-1,-1,0)(5155=-1,-1,-1,-1,0)(1219=-1,-1,-1,-1,0)(90=-1,-1,-1,-1,0)(91=-1,-1,-1,-1,0)(1207=-1,-1,-1,-1,0)(5154=-1,-1,-1,-1,0)(5153=-1,-1,-1,-1,0)(1208=-1,-1,-1,-1,0)(5156=-1,-1,-1,-1,0)(5157=-1,-1,-1,-1,0)(5158=-1,-1,-1,-1,0)(5159=-1,-1,-1,-1,0)(3047=-1,-1,-1,-1,0)(3050=-1,-1,-1,-1,0)(3060=-1,-1,-1,-1,0)(3051=-1,-1,-1,-1,0)(3061=-1,-1,-1,-1,0)
+        
+        
+          0
+          DLGTC51
+          (5130=-1,-1,-1,-1,0)(5131=-1,-1,-1,-1,0)(5132=-1,-1,-1,-1,0)(5133=-1,-1,-1,-1,0)(5134=-1,-1,-1,-1,0)(1203=-1,-1,-1,-1,0)(5152=-1,-1,-1,-1,0)(94=-1,-1,-1,-1,0)(5150=-1,-1,-1,-1,0)(5140=-1,-1,-1,-1,0)(5141=-1,-1,-1,-1,0)(5142=-1,-1,-1,-1,0)(5143=-1,-1,-1,-1,0)(5144=-1,-1,-1,-1,0)(5145=-1,-1,-1,-1,0)(5019=-1,-1,-1,-1,0)(5020=-1,-1,-1,-1,0)(5018=-1,-1,-1,-1,0)(5021=-1,-1,-1,-1,0)(5022=-1,-1,-1,-1,0)(5151=-1,-1,-1,-1,0)(5155=-1,-1,-1,-1,0)(1219=-1,-1,-1,-1,0)(90=-1,-1,-1,-1,0)(91=-1,-1,-1,-1,0)(1207=-1,-1,-1,-1,0)(5154=-1,-1,-1,-1,0)(5153=-1,-1,-1,-1,0)(1208=-1,-1,-1,-1,0)(5156=-1,-1,-1,-1,0)(5157=-1,-1,-1,-1,0)(5158=-1,-1,-1,-1,0)(5159=-1,-1,-1,-1,0)(3047=-1,-1,-1,-1,0)(3050=-1,-1,-1,-1,0)(3051=-1,-1,-1,-1,0)
+        
+        
+          0
+          DAS2XC800
+           -O255 -F29 -U768 -H"localhost" -S"UDAS" -D"MW000099A" -T4294967295
+        
+      
+      
+        
+          0
+          0
+          467
+          1
+          
0

+          0
+          0
+          0
+          0
+          0
+          0
+          C:\Users\liuminVir\Desktop\20250223-886閬ユ帶鍣╘User.c
+          
+          
+        
+      
+      
+        
+          0
+          1
+          WLBuf
+        
+      
+      
+        
+          1
+          0
+          PntSta
+          0
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+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+  
+    Dave Files
+    1
+    0
+    0
+    0
+    
+      1
+      1
+      2
+      0
+      0
+      1
+      .\START_XC.a51
+      START_XC.a51
+      0
+      0
+    
+    
+      1
+      2
+      1
+      0
+      0
+      1
+      .\MAIN.C
+      MAIN.C
+      0
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diff --git a/CL2.0.uvproj b/CL2.0.uvproj
new file mode 100644
index 0000000..cc59d80
--- /dev/null
+++ b/CL2.0.uvproj
@@ -0,0 +1,445 @@
+
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+
+  1.1
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### uVision Project, (C) Keil Software

+
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+      Target 1
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+          Infineon
+          IRAM(0-0xFF) XRAM(0xF000-0xF5FF) IROM(0-0x5FFF) IROM2(0xA000-0xBFFF) CLOCK(24000000) MOD517DP
+          XC800_FLOAD.EXE ("#H" f")
+          "LIB\START_XC88x.A51" ("Infineon XC800 Startup Code")
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+            ?C_C51STARTUP(C:0x2100), ?PR?main?MAIN
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diff --git a/CL2.0_uvopt.bak b/CL2.0_uvopt.bak
new file mode 100644
index 0000000..1d7f89e
--- /dev/null
+++ b/CL2.0_uvopt.bak
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+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    -261637721
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+          DATASHTS\INFINEON\XC886_UM.PDF
+        
+        
+          1
+          XC800 Instruction Set Manual
+          DATASHTS\INFINEON\XC800_IS.PDF
+        
+      
+      
+        S8051.DLL
+        -m8051EW
+        DCore51.DLL
+        -pXC886
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+        TCore51.DLL
+        -pXC886
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+        
+        
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+          DAS2XC800
+           -O255 -F29 -U768 -H"localhost" -S"UDAS" -D"MW000099A" -T4294967295
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+
+
diff --git a/CL2.0_uvproj.bak b/CL2.0_uvproj.bak
new file mode 100644
index 0000000..fe007f1
--- /dev/null
+++ b/CL2.0_uvproj.bak
@@ -0,0 +1,410 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      Target 1
+      0x0
+      MCS-51
+      
+        
+          XC886CLM-8FF
+          Infineon
+          IRAM(0-0xFF) XRAM(0xF000-0xF5FF) IROM(0-0x5FFF) IROM2(0xA000-0xBFFF) CLOCK(24000000) MOD517DP
+          XC800_FLOAD.EXE ("#H" f")
+          "LIB\START_XC88x.A51" ("Infineon XC800 Startup Code")
+          
+          4021
+          XC886CLM.H
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          Infineon\
+          Infineon\
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\output\
+          CL2.0
+          1
+          0
+          1
+          1
+          1
+          .\output\
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+          0
+          0
+          
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+          1
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+          0
+          0
+          0
+          3
+          
+          
+          65535
+        
+        
+          S8051.DLL
+          -m8051EW
+          DCore51.DLL
+          -pXC886
+          S8051.DLL
+          
+          TCore51.DLL
+          -pXC886
+        
+        
+          
+            0
+            0
+            0
+            0
+            16
+          
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+          
+            
+            
+            
+            
+            
+          
+          
+            
+            
+            
+            
+            
+            BIN\DAS2XC800.DLL
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            1
+            4100
+          
+          BIN\DAS2XC800.DLL
+          "XC800_FLOAD.EXE" ("#H" f")
+          
+        
+        
+          
+            2
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+            1
+            
+            RESERVE (I:0xC0-I:0xFF)
+            
+            
+            
+            
+            
+            CODE(C:0x2100-C:0x5FFF)
+            
+            ?C_C51STARTUP(C:0x2100), ?PR?main?MAIN
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Dave Files
+          
+            
+              START_XC.a51
+              2
+              .\START_XC.a51
+            
+            
+              MAIN.C
+              1
+              .\MAIN.C
+            
+            
+              IO.C
+              1
+              .\IO.C
+            
+            
+              SHARED_INT.C
+              1
+              .\SHARED_INT.C
+            
+            
+              CAN.C
+              1
+              .\CAN.C
+            
+            
+              T2.C
+              1
+              .\T2.C
+            
+            
+              WDT.C
+              1
+              .\WDT.C
+            
+          
+        
+        
+          User Files
+          
+            
+              User.c
+              1
+              .\User.c
+            
+            
+              boot.c
+              1
+              .\boot.c
+            
+            
+              XC88x_FLHANDLER.ASM
+              2
+              .\XC88x_FLHANDLER.ASM
+            
+          
+        
+      
+    
+  
+
+
diff --git a/Config.H b/Config.H
new file mode 100644
index 0000000..6a4037b
--- /dev/null
+++ b/Config.H
@@ -0,0 +1,248 @@
+#ifndef _Configfff_H_
+#define _Configfff_H_
+
+
+//-----宏定义-----------------------------------------------------------------
+//开关部分--------------------------------------------------------------
+//支持平台：
+//  ___XC164CM___ 		SSC工作于查询方式
+//  ___XC2765X___ 		SSC工作于查询方式
+#define ___XC886CLM___
+
+#define NumChipSw   2//定义MC33993芯片的数量
+#define DF_SwInNum  1//定义采集芯片的数量
+#define DF_SwOutNum 1//定义输出芯片的数量
+
+#define Tog       2
+#define On        1
+#define Off       0
+
+//#define  N       6    //N为偶数
+
+
+#define   uchar  unsigned char
+#define   ulong  unsigned long
+#define   uint   unsigned int 
+//如果有CAN数据接收，需要定义___CANRX___
+//#define ___CANRX___
+
+//看门狗
+//#define DF_WDT  P1_OUT_P0
+
+//定义
+#define SwIn01	  P1_2    // Output7
+#define SwIn02	  P1_3    // Output2
+
+#define SwOut01	  P1_4    // Output4
+
+//#define SwIn04	  P1_5    // Output3
+//#define SwIn05	  P3_6    // Output5
+//#define SwIn06	  P4_3    // Output6
+//#define SwIn07	  P3_0
+//#define SwIn08	  P2_6
+
+//#define SwOut01	  P3_2
+//#define SwOut02	  P3_4
+//#define SwOut03	  P4_0
+//#define SwOut04	  P0_7
+//#define SwOut05	  P0_0
+//#define SwOut06	  P0_1
+//#define SwOut07	  P1_3
+//#define SwOut08	  P1_5
+//#define SwOut09	  P0_3
+//#define SwOut10	  P4_1
+//#define SwOut11	  P3_5
+//#define SwOut12	  P3_3
+//#define SwOut13	  P1_4
+//#define SwOut14	  P1_2
+//#define SwOut15	  P0_2
+//#define SwOut16	  P1_7
+
+
+//开关采集数据结构，和硬件相关，硬件修改需要响应修改
+typedef union _SwSample
+{
+	struct
+	{
+		ubyte Arr[DF_SwInNum][4];
+	}ArrData;
+	struct
+	{ 
+//-------采集芯片1-------------------------------		
+		unsigned int  S6        : 1;//FlgSg0          
+		unsigned int  S5        : 1;//FlgSg1    
+		unsigned int  S4        : 1;//FlgSg2    
+		unsigned int  S3        : 1;//FlgSg3    
+		unsigned int  S1        : 1;//FlgSg4    
+		unsigned int  S2        : 1;//FlgSg5    
+		unsigned int  S41       : 1;//FlgSg6    
+		unsigned int  S15       : 1;//FlgSg7    
+		unsigned int  S16       : 1;//FlgSg8    
+		unsigned int  S17       : 1;//FlgSg9    
+		unsigned int  S18       : 1;//FlgSg10   
+		unsigned int  S20       : 1;//FlgSg11   
+		unsigned int  S19       : 1;//FlgSg12   
+		unsigned int  S42       : 1;//FlgSg13   
+		unsigned int  S10       : 1;//FlgSp0    
+		unsigned int  S9        : 1;//FlgSp1    
+		unsigned int  S8        : 1;//FlgSp2    
+		unsigned int  S7        : 1;//FlgSp3    
+		unsigned int  S14       : 1;//FlgSp4    
+		unsigned int  S13       : 1;//FlgSp5    
+		unsigned int  S12       : 1;//FlgSp6    
+		unsigned int  S11       : 1;//FlgSp7    
+		unsigned int            : 1;//FlgInt    
+		unsigned int            : 1;//FlgThem	
+		unsigned int            : 8;//	
+			
+	}BitData;
+}UnSwSample,*pUnSwSample;
+
+//LED输出数据结构
+typedef union _SwOut
+{
+	struct
+	{
+//		ubyte Arr[DF_SwOutNum][4];	//芯片数量改变需修改
+		ubyte Arr[DF_SwOutNum][4];	//芯片数量改变需修改		
+	}ArrData;
+	struct
+	{ 
+//-------输出芯片1-------------------------------		
+		unsigned int  S21  : 1;//FLGSP0          
+		unsigned int  S22  : 1;//FLGSP1          
+		unsigned int  S23  : 1;//FLGSP2          
+		unsigned int  S24  : 1;//FLGSP3          
+		unsigned int  S34  : 1;//FLGSP4          
+		unsigned int  S33  : 1;//FLGSP5          
+		unsigned int  S32  : 1;//FLGSP6          
+		unsigned int  S31  : 1;//FLGSP7 		
+		unsigned int  S25  : 1;//FLGSG0          
+		unsigned int  S26  : 1;//FLGSG1          
+		unsigned int  S27  : 1;//FLGSG2          
+		unsigned int  S28  : 1;//FLGSG3          
+		unsigned int  S30  : 1;//FLGSG4          
+		unsigned int  S29  : 1;//FLGSG5          
+		unsigned int  S43  : 1;//FLGSG6   
+		unsigned int  S35  : 1;//FLGSG7 
+		unsigned int  S36  : 1;//FLGSG8   
+		unsigned int  S37  : 1;//FLGSG9   
+		unsigned int  S38  : 1;//FLGSG10  
+		unsigned int  S40  : 1;//FLGSG11  
+		unsigned int  S39  : 1;//FLGSG12  
+		unsigned int  S44  : 1;//FLGSG13  
+		unsigned int           : 1;	
+		unsigned int           : 1;	  
+		unsigned int           : 8;
+//-------------------------------------------------			
+	}BitData;
+}UnSwOut,*pUnSwOut;
+
+
+//CAN部分--------------------------------------------------------------
+#define NumTxCan 1
+#define NumRxCan 1//15
+#define NumTxCanMoS 16 //发送消息存放的消息对象起始
+#define NumRxCanMoS 0 //接收消息存放的消息对象起始
+#define ___CANRX___ 
+
+//CAN信息结构
+typedef union _InfCan
+{
+	struct
+	{
+		ubyte Arr[1][8];
+		ubyte ArrRX[2][8];
+	}ArrData;
+	struct
+	{
+//----------发送0-0x14000001 -------------------------------------------
+		unsigned int	 Sta09        : 1  ; //FlgSp1 
+		unsigned int	 Sta10        : 1  ; //FlgSp0 
+		unsigned int	 Sta11        : 1  ; //FlgSp7 
+		unsigned int	 Sta12        : 1  ; //FlgSp6 
+		unsigned int	 Sta13        : 1  ; //FlgSp5 
+		unsigned int	 Sta14        : 1  ; //FlgSp4 
+
+		unsigned int	 Sta15        : 1  ; //FlgSg7 
+		unsigned int	 Sta16        : 1  ; //FlgSg8		
+	               
+		unsigned int   Sta01        : 1  ; //FlgSg4 
+		unsigned int	 Sta02        : 1  ; //FlgSg5 
+		unsigned int	 Sta03        : 1  ; //FlgSg3 
+		unsigned int	 Sta04        : 1  ; //FlgSg2 
+    unsigned int	 Sta05        : 1  ; //FlgSg1 
+		unsigned int	 Sta06        : 1  ; //FlgSg0 
+		unsigned int	 Sta07        : 1  ; //FlgSp3 
+		unsigned int	 Sta08        : 1  ; //FlgSp2 		
+
+		unsigned int   CanTx3       : 8  ;  ////
+
+		unsigned int   Dia01        : 1  ; //FlgSg4 
+		unsigned int	 Dia02        : 1  ; //FlgSg5 
+		unsigned int	 Dia03        : 1  ; //FlgSg3 
+		unsigned int	 Dia04        : 1  ; //FlgSg2 
+    unsigned int	 Dia05        : 1  ; //FlgSg1 
+		unsigned int	 Dia06        : 1  ; //FlgSg0 
+		unsigned int	 Dia07        : 1  ; //FlgSp3 
+		unsigned int	 Dia08        : 1  ; //FlgSp2 
+	
+		unsigned int   CanTx5       : 8  ;  ////
+		unsigned int   CanTx4       : 8  ;  ////	
+		unsigned int   CanTx7       : 8  ;  ////
+		unsigned int   CanTx6       : 8  ;  ////		
+																						
+//----------接收0x14000002 -------------------------------------------- 
+		unsigned int	 D29        : 1  ; //FlgSp1 
+		unsigned int	 D30        : 1  ; //FlgSp0 
+		unsigned int	 D31        : 1  ; //FlgSp7 
+		unsigned int	 D32        : 1  ; //FlgSp6 
+		unsigned int	 D33        : 1  ; //FlgSp5 
+		unsigned int	 D34        : 1  ; //FlgSp4 
+		unsigned int	 D35        : 1  ; //FlgSg7 
+		unsigned int	 D36        : 1  ; //FlgSg8		
+	               
+		unsigned int   D21        : 1  ; //FlgSg4 
+		unsigned int	 D22        : 1  ; //FlgSg5 
+		unsigned int	 D23        : 1  ; //FlgSg3 
+		unsigned int	 D24        : 1  ; //FlgSg2 
+    unsigned int	 D25        : 1  ; //FlgSg1 
+		unsigned int	 D26        : 1  ; //FlgSg0 
+		unsigned int	 D27        : 1  ; //FlgSp3 
+		unsigned int	 D28        : 1  ; //FlgSp2 		
+
+		unsigned int   CanRx3     : 8  ;  ////
+		unsigned int   CanRx2     : 8  ;  ////	
+		unsigned int   CanRx5     : 8  ;  ////
+		unsigned int   CanRx4     : 8  ;  ////	
+		unsigned int   CanRx7     : 8  ;  ////
+		unsigned int   CanRx6     : 8  ;  ////
+
+//----------接收0x14000003 -------------------------------------------- 
+		unsigned int	 Pwm_01        : 4  ; //FlgSp1 
+		unsigned int	 Pwm_02        : 4  ; //FlgSp0 
+		unsigned int	 Pwm_03        : 4  ; //FlgSp7 
+		unsigned int	 Pwm_04        : 4  ; //FlgSp6 
+		unsigned int	 Pwm_05        : 4  ; //FlgSp5 
+		unsigned int	 Pwm_06        : 4  ; //FlgSp4 
+		unsigned int	 Pwm_07        : 4  ; //FlgSg7 
+		unsigned int	 Pwm_08        : 4  ; //FlgSg8			               
+		unsigned int   Pwm_09        : 4  ; //FlgSg4 
+		unsigned int	 Pwm_10        : 4  ; //FlgSg5 
+		unsigned int	 Pwm_11        : 4  ; //FlgSg3 
+		unsigned int	 Pwm_12        : 4  ; //FlgSg2 
+    unsigned int	 Pwm_13        : 4  ; //FlgSg1 
+		unsigned int	 Pwm_14        : 4  ; //FlgSg0 
+		unsigned int	 Pwm_15        : 4  ; //FlgSp3 
+		unsigned int	 Pwm_16        : 4  ; //FlgSp2 		
+
+	}BitData;       
+}UnInfCan,*pInfCan;
+
+
+
+//-----文件包含----------------------------------------------
+#include  "user.H"
+#include  "boot.H"
+#include  "RTC.H"
+#endif
\ No newline at end of file
diff --git a/Config.H.bak b/Config.H.bak
new file mode 100644
index 0000000..8f29e50
--- /dev/null
+++ b/Config.H.bak
@@ -0,0 +1,247 @@
+#ifndef _Configfff_H_
+#define _Configfff_H_
+
+
+//-----宏定义-----------------------------------------------------------------
+//开关部分--------------------------------------------------------------
+//支持平台：
+//  ___XC164CM___ 		SSC工作于查询方式
+//  ___XC2765X___ 		SSC工作于查询方式
+#define ___XC886CLM___
+
+#define NumChipSw   2//定义MC33993芯片的数量
+#define DF_SwInNum  1//定义采集芯片的数量
+#define DF_SwOutNum 1//定义输出芯片的数量
+
+#define Tog       2
+#define On        1
+#define Off       0
+
+//#define  N       6    //N为偶数
+
+
+#define   uchar  unsigned char
+#define   ulong  unsigned long
+#define   uint   unsigned int 
+//如果有CAN数据接收，需要定义___CANRX___
+//#define ___CANRX___
+
+//看门狗
+//#define DF_WDT  P1_OUT_P0
+
+//定义
+#define SwIn01	  P3_0
+#define SwIn02	  P3_7
+#define SwIn03	  P2_4
+#define SwIn04	  P2_5
+#define SwIn05	  P3_1
+#define SwIn06	  P3_6
+#define SwIn07	  P2_6
+#define SwIn08	  P2_7
+#define SwOut01	  P3_2
+#define SwOut02	  P3_4
+#define SwOut03	  P4_0
+#define SwOut04	  P0_7
+#define SwOut05	  P0_0
+#define SwOut06	  P0_1
+#define SwOut07	  P1_3
+#define SwOut08	  P1_5
+#define SwOut09	  P0_3
+#define SwOut10	  P4_1
+#define SwOut11	  P3_5
+#define SwOut12	  P3_3
+#define SwOut13	  P1_4
+#define SwOut14	  P1_2
+#define SwOut15	  P0_2
+#define SwOut16	  P1_7
+
+
+//开关采集数据结构，和硬件相关，硬件修改需要响应修改
+typedef union _SwSample
+{
+	struct
+	{
+		ubyte Arr[DF_SwInNum][4];
+	}ArrData;
+	struct
+	{ 
+//-------采集芯片1-------------------------------		
+		unsigned int  S6        : 1;//FlgSg0          
+		unsigned int  S5        : 1;//FlgSg1    
+		unsigned int  S4        : 1;//FlgSg2    
+		unsigned int  S3        : 1;//FlgSg3    
+		unsigned int  S1        : 1;//FlgSg4    
+		unsigned int  S2        : 1;//FlgSg5    
+		unsigned int  S41       : 1;//FlgSg6    
+		unsigned int  S15       : 1;//FlgSg7    
+		unsigned int  S16       : 1;//FlgSg8    
+		unsigned int  S17       : 1;//FlgSg9    
+		unsigned int  S18       : 1;//FlgSg10   
+		unsigned int  S20       : 1;//FlgSg11   
+		unsigned int  S19       : 1;//FlgSg12   
+		unsigned int  S42       : 1;//FlgSg13   
+		unsigned int  S10       : 1;//FlgSp0    
+		unsigned int  S9        : 1;//FlgSp1    
+		unsigned int  S8        : 1;//FlgSp2    
+		unsigned int  S7        : 1;//FlgSp3    
+		unsigned int  S14       : 1;//FlgSp4    
+		unsigned int  S13       : 1;//FlgSp5    
+		unsigned int  S12       : 1;//FlgSp6    
+		unsigned int  S11       : 1;//FlgSp7    
+		unsigned int            : 1;//FlgInt    
+		unsigned int            : 1;//FlgThem	
+		unsigned int            : 8;//	
+			
+	}BitData;
+}UnSwSample,*pUnSwSample;
+
+//LED输出数据结构
+typedef union _SwOut
+{
+	struct
+	{
+		ubyte Arr[DF_SwOutNum][4];	//芯片数量改变需修改
+	}ArrData;
+	struct
+	{ 
+//-------输出芯片1-------------------------------		
+		unsigned int  S21  : 1;//FLGSP0          
+		unsigned int  S22  : 1;//FLGSP1          
+		unsigned int  S23  : 1;//FLGSP2          
+		unsigned int  S24  : 1;//FLGSP3          
+		unsigned int  S34  : 1;//FLGSP4          
+		unsigned int  S33  : 1;//FLGSP5          
+		unsigned int  S32  : 1;//FLGSP6          
+		unsigned int  S31  : 1;//FLGSP7 		
+		unsigned int  S25  : 1;//FLGSG0          
+		unsigned int  S26  : 1;//FLGSG1          
+		unsigned int  S27  : 1;//FLGSG2          
+		unsigned int  S28  : 1;//FLGSG3          
+		unsigned int  S30  : 1;//FLGSG4          
+		unsigned int  S29  : 1;//FLGSG5          
+		unsigned int  S43  : 1;//FLGSG6   
+		unsigned int  S35  : 1;//FLGSG7 
+		unsigned int  S36  : 1;//FLGSG8   
+		unsigned int  S37  : 1;//FLGSG9   
+		unsigned int  S38  : 1;//FLGSG10  
+		unsigned int  S40  : 1;//FLGSG11  
+		unsigned int  S39  : 1;//FLGSG12  
+		unsigned int  S44  : 1;//FLGSG13  
+		unsigned int           : 1;	
+		unsigned int           : 1;	  
+		unsigned int           : 8;
+//-------------------------------------------------			
+	}BitData;
+}UnSwOut,*pUnSwOut;
+
+
+//CAN部分--------------------------------------------------------------
+#define NumTxCan 1
+#define NumRxCan 1//15
+#define NumTxCanMoS 16 //发送消息存放的消息对象起始
+#define NumRxCanMoS 0 //接收消息存放的消息对象起始
+#define ___CANRX___ 
+
+//CAN信息结构
+typedef union _InfCan
+{
+	struct
+	{
+		ubyte Arr[1][8];
+		ubyte ArrRX[2][8];
+	}ArrData;
+	struct
+	{
+//----------发送0-0x10000001 -------------------------------------------
+		unsigned int	 Sta09        : 1  ; //FlgSp1 
+		unsigned int	 Sta10        : 1  ; //FlgSp0 
+		unsigned int	 Sta11        : 1  ; //FlgSp7 
+		unsigned int	 Sta12        : 1  ; //FlgSp6 
+		unsigned int	 Sta13        : 1  ; //FlgSp5 
+		unsigned int	 Sta14        : 1  ; //FlgSp4 
+		unsigned int	 Sta15        : 1  ; //FlgSg7 
+		unsigned int	 Sta16        : 1  ; //FlgSg8		
+	               
+		unsigned int   Sta01        : 1  ; //FlgSg4 
+		unsigned int	 Sta02        : 1  ; //FlgSg5 
+		unsigned int	 Sta03        : 1  ; //FlgSg3 
+		unsigned int	 Sta04        : 1  ; //FlgSg2 
+    unsigned int	 Sta05        : 1  ; //FlgSg1 
+		unsigned int	 Sta06        : 1  ; //FlgSg0 
+		unsigned int	 Sta07        : 1  ; //FlgSp3 
+		unsigned int	 Sta08        : 1  ; //FlgSp2 		
+
+		unsigned int   CanTx3       : 8  ;  ////
+
+		unsigned int   Dia01        : 1  ; //FlgSg4 
+		unsigned int	 Dia02        : 1  ; //FlgSg5 
+		unsigned int	 Dia03        : 1  ; //FlgSg3 
+		unsigned int	 Dia04        : 1  ; //FlgSg2 
+    unsigned int	 Dia05        : 1  ; //FlgSg1 
+		unsigned int	 Dia06        : 1  ; //FlgSg0 
+		unsigned int	 Dia07        : 1  ; //FlgSp3 
+		unsigned int	 Dia08        : 1  ; //FlgSp2 
+	
+		unsigned int   CanTx5       : 8  ;  ////
+		unsigned int   CanTx4       : 8  ;  ////	
+		unsigned int   CanTx7       : 8  ;  ////
+		unsigned int   CanTx6       : 8  ;  ////		
+																						
+//----------接收0x10000002 -------------------------------------------- 
+		unsigned int	 D29        : 1  ; //FlgSp1 
+		unsigned int	 D30        : 1  ; //FlgSp0 
+		unsigned int	 D31        : 1  ; //FlgSp7 
+		unsigned int	 D32        : 1  ; //FlgSp6 
+		unsigned int	 D33        : 1  ; //FlgSp5 
+		unsigned int	 D34        : 1  ; //FlgSp4 
+		unsigned int	 D35        : 1  ; //FlgSg7 
+		unsigned int	 D36        : 1  ; //FlgSg8		
+	               
+		unsigned int   D21        : 1  ; //FlgSg4 
+		unsigned int	 D22        : 1  ; //FlgSg5 
+		unsigned int	 D23        : 1  ; //FlgSg3 
+		unsigned int	 D24        : 1  ; //FlgSg2 
+    unsigned int	 D25        : 1  ; //FlgSg1 
+		unsigned int	 D26        : 1  ; //FlgSg0 
+		unsigned int	 D27        : 1  ; //FlgSp3 
+		unsigned int	 D28        : 1  ; //FlgSp2 		
+
+		unsigned int   CanRx3     : 8  ;  ////
+		unsigned int   CanRx2     : 8  ;  ////	
+		unsigned int   CanRx5     : 8  ;  ////
+		unsigned int   CanRx4     : 8  ;  ////	
+		unsigned int   CanRx7     : 8  ;  ////
+		unsigned int   CanRx6     : 8  ;  ////
+
+//----------接收0x14000003 -------------------------------------------- 
+		unsigned int	 Pwm01        : 4  ; //FlgSp1 
+		unsigned int	 Pwm02        : 4  ; //FlgSp0 
+		unsigned int	 Pwm03        : 4  ; //FlgSp7 
+		unsigned int	 Pwm04        : 4  ; //FlgSp6 
+		unsigned int	 Pwm05        : 4  ; //FlgSp5 
+		unsigned int	 Pwm06        : 4  ; //FlgSp4 
+		unsigned int	 Pwm07        : 4  ; //FlgSg7 
+		unsigned int	 Pwm08        : 4  ; //FlgSg8			               
+		unsigned int   Pwm09        : 4  ; //FlgSg4 
+		unsigned int	 Pwm10        : 4  ; //FlgSg5 
+		unsigned int	 Pwm11        : 4  ; //FlgSg3 
+		unsigned int	 Pwm12        : 4  ; //FlgSg2 
+    unsigned int	 Pwm13        : 4  ; //FlgSg1 
+		unsigned int	 Pwm14        : 4  ; //FlgSg0 
+		unsigned int	 Pwm15        : 4  ; //FlgSp3 
+		unsigned int	 Pwm16        : 4  ; //FlgSp2 		
+
+	}BitData;       
+}UnInfCan,*pInfCan;
+
+
+
+
+
+
+
+
+//-----文件包含----------------------------------------------
+#include  "user.H"
+#include  "boot.H"
+#endif
\ No newline at end of file
diff --git a/ExtDll.iex b/ExtDll.iex
new file mode 100644
index 0000000..b661f48
--- /dev/null
+++ b/ExtDll.iex
@@ -0,0 +1,2 @@
+[EXTDLL]
+Count=0
diff --git a/IO.C b/IO.C
new file mode 100644
index 0000000..dcd5ec9
--- /dev/null
+++ b/IO.C
@@ -0,0 +1,322 @@
+//****************************************************************************
+// @Module        GPIO
+// @Filename      IO.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the IO module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:29
+//
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (IO_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (IO_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void IO_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the IO function 
+//                library. It is assumed that the SFRs used by this library 
+//                are in their reset state. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Init,1)
+
+// USER CODE END
+
+void IO_vInit(void)
+{
+  // USER CODE BEGIN (IO_Init,2)
+
+  // USER CODE END
+
+
+  ///  ***********************************************************************
+  ///  Note : All peripheral related IO configurations are done in the 
+  ///  respective peripheral modules (alternate functions selection)
+  ///  
+  ///  If no pins are selected DAvE assumes that registers are in default 
+  ///  settings
+  ///  ***********************************************************************
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of Port P0:
+  ///  -----------------------------------------------------------------------
+  ///  P0.0:
+  ///  - is used as general input
+  ///  - pull-down device is assigned
+  ///  P0.1:
+  ///  - is used as alternate input for the UART Receive Input
+  ///  - pull-down device is assigned
+  ///  P0.2:
+  ///  - is used as general input
+  ///  - pull-down device is assigned
+  ///  P0.3:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P0.5:
+  ///  - is used as alternate input for the External Interrupt Input 0
+  ///  - pull device is disabled (tristate) 
+  ///  P0.7:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is high level
+  ///  - pull-up device is assigned
+
+
+  SFR_PAGE(_pp1, noSST);         // switch to page 1
+  P0_PUDSEL     =  0xF0;         // load pullup/pulldown select register
+  P0_PUDEN      =  0xCF;         // load pullup/pulldown enable register
+
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P0_DIR        =  0x88;         // load direction register
+  P0_DATA       =  0x80;         // load data output register
+
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of Port P1:
+  ///  -----------------------------------------------------------------------
+  ///  P1.0:
+  ///  - is used as alternate input for the MCAN Node 0 Receiver Input
+  ///  - pull-up device is assigned
+  ///  P1.1:
+  ///  - is used as alternate output for the MCAN Node 0 Transmitter Output
+  ///  - push/pull output is selected
+  ///  - pull-up device is assigned
+  ///  P1.2:
+  ///  - is used as general input
+  ///  - pull-up device is assigned
+  ///  P1.3:
+  ///  - is used as general input
+  ///  - pull-up device is assigned
+  ///  P1.4:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P1.5:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P1.7:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+
+
+  SFR_PAGE(_pp1, noSST);         // switch to page 1
+  P1_PUDSEL     =  0x4F;         // load pullup/pulldown select register
+
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P1_DIR        =  0xB0;         // load direction register
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of Port P2:
+  ///  -----------------------------------------------------------------------
+  ///  P2.4:
+  ///  - is used as general input
+  ///  - input driver is enabled
+  ///  - pull-up device is assigned
+  ///  P2.5:
+  ///  - is used as general input
+  ///  - input driver is enabled
+  ///  - pull-up device is assigned
+  ///  P2.6:
+  ///  - is used as general input
+  ///  - input driver is enabled
+  ///  - pull-up device is assigned
+  ///  P2.7:
+  ///  - is used as general input
+  ///  - input driver is enabled
+  ///  - pull-up device is assigned
+
+  SFR_PAGE(_pp1, noSST);         // switch to page 1
+  P2_PUDEN      =  0xF0;         // load pullup/pulldown enable register
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of Port P3:
+  ///  -----------------------------------------------------------------------
+  ///  P3.0:
+  ///  - is used as general input
+  ///  - pull-up device is assigned
+  ///  P3.1:
+  ///  - is used as general input
+  ///  - pull-up device is assigned
+  ///  P3.2:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is high level
+  ///  - pull-up device is assigned
+  ///  P3.3:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P3.4:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is low level
+  ///  - pull-down device is assigned
+  ///  P3.5:
+  ///  - is used as general purpose output
+  ///  - open drain output is selected
+  ///  - the pin status is high level
+  ///  - pull device is disabled (tristate) 
+  ///  P3.6:
+  ///  - is used as general input
+  ///  - pull-up device is assigned
+  ///  P3.7:
+  ///  - is used as general input
+  ///  - pull-up device is assigned
+
+  SFR_PAGE(_pp3, noSST);         // switch to page 3
+  P3_OD         =  0x20;         // load open-drain register
+
+  SFR_PAGE(_pp1, noSST);         // switch to page 1
+  P3_PUDSEL     =  0xE7;         // load pullup/pulldown select register
+  P3_PUDEN      =  0xDF;         // load pullup/pulldown enable register
+
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P3_DIR        =  0x3C;         // load direction register
+  P3_DATA       =  0x24;         // load data output register
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of Port P4:
+  ///  -----------------------------------------------------------------------
+  ///  P4.0:
+  ///  - is used as general input
+  ///  - pull-down device is assigned
+  ///  P4.1:
+  ///  - is used as general purpose output
+  ///  - push/pull output is selected
+  ///  - the pin status is high level
+  ///  - pull-up device is assigned
+  ///  P4.3:
+  ///  - is used as general purpose output
+  ///  - open drain output is selected
+  ///  - the pin status is high level
+  ///  - pull device is disabled (tristate)  
+
+  SFR_PAGE(_pp3, noSST);         // switch to page 3
+  P4_OD         =  0x08;         // load open-drain register
+
+  SFR_PAGE(_pp1, noSST);         // switch to page 1
+  P4_PUDSEL     =  0x02;         // load pullup/pulldown select register
+  P4_PUDEN      =  0x03;         // load pullup/pulldown enable register
+
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P4_DIR        =  0x0A;         // load direction register
+  P4_DATA       =  0x0A;         // load data output register
+
+
+  // USER CODE BEGIN (IO_Init,3)
+
+  // USER CODE END
+
+} //  End of function IO_vInit
+
+
+
+
+// USER CODE BEGIN (IO_General,10)
+
+// USER CODE END
+
diff --git a/IO.H b/IO.H
new file mode 100644
index 0000000..3605c35
--- /dev/null
+++ b/IO.H
@@ -0,0 +1,248 @@
+//****************************************************************************
+// @Module        GPIO
+// @Filename      IO.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the IO module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:29
+//
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _IO_H_
+#define _IO_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,4)
+
+// USER CODE END
+
+//   Port 0
+
+sbit P0_0       = 0x80;    
+sbit P0_1       = 0x81;    
+sbit P0_2       = 0x82;    
+sbit P0_3       = 0x83;    
+sbit P0_4       = 0x84;    
+sbit P0_5       = 0x85;    
+sbit P0_7       = 0x87;    
+
+//   Port 1
+
+sbit P1_0       = 0x90;    
+sbit P1_1       = 0x91;    
+sbit P1_2       = 0x92;    
+sbit P1_3       = 0x93;    
+sbit P1_4       = 0x94;    
+sbit P1_5       = 0x95;    
+sbit P1_6       = 0x96;    
+sbit P1_7       = 0x97;    
+
+//   Port 2
+
+sbit P2_0       = 0xA0;    
+sbit P2_1       = 0xA1;    
+sbit P2_2       = 0xA2;    
+sbit P2_3       = 0xA3;    
+sbit P2_4       = 0xA4;    
+sbit P2_5       = 0xA5;    
+sbit P2_6       = 0xA6;    
+sbit P2_7       = 0xA7;    
+
+//   Port 3
+
+sbit P3_0       = 0xB0;    
+sbit P3_1       = 0xB1;    
+sbit P3_2       = 0xB2;    
+sbit P3_3       = 0xB3;    
+sbit P3_4       = 0xB4;    
+sbit P3_5       = 0xB5;    
+sbit P3_6       = 0xB6;    
+sbit P3_7       = 0xB7;    
+
+//   Port 4
+
+sbit P4_0       = 0xC8;    
+sbit P4_1       = 0xC9;    
+sbit P4_3       = 0xCB;    
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void IO_vInit(void);
+
+
+// USER CODE BEGIN (IO_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macro         IO_ubReadPin(PinName) 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro returns the status of the chosen portpin.
+//                Note:
+//                'PinName' identifies the pin of a bit-addressable port. The 
+//                default names can be changed in the port configuration 
+//                dialog. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   Status of the chosen portpin
+//
+//----------------------------------------------------------------------------
+// @Parameters    PinName: 
+//                Pin to be read
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+#define IO_ubReadPin(PinName) PinName
+
+//****************************************************************************
+// @Macro         IO_vSetPin(PinName) 
+//
+//----------------------------------------------------------------------------
+// @Description   The chosen portpin is set to '1'.
+//                Note:
+//                'PinName' identifies the pin of a bit-addressable port. The 
+//                default names can be changed in the port configuration 
+//                dialog. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    PinName: 
+//                Pin to be set to '1'
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+#define IO_vSetPin(PinName) PinName = 1
+
+//****************************************************************************
+// @Macro         IO_vResetPin(PinName) 
+//
+//----------------------------------------------------------------------------
+// @Description   The chosen portpin is set to '0'. 
+//                Note: 
+//                'PinName' identifies the pin of a bit-addressable port. The 
+//                default names can be changed in the port configuration 
+//                dialog. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    PinName: 
+//                Pin to be set to '0'
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+#define IO_vResetPin(PinName) PinName = 0
+
+//****************************************************************************
+// @Macro         IO_vTogglePin(PinName) 
+//
+//----------------------------------------------------------------------------
+// @Description   The chosen portpin will be toggled. 
+//                Note:
+//                'PinName' identifies the pin of a bit-addressable port. The 
+//                default names can be changed in the port configuration 
+//                dialog. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    PinName: 
+//                Pin to be toggled
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+#define IO_vTogglePin(PinName) PinName ^= 1
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+// USER CODE BEGIN (IO_Header,9)
+
+// USER CODE END
+
+
+#endif  // ifndef _IO_H_
diff --git a/MAIN.C b/MAIN.C
new file mode 100644
index 0000000..a7d22fd
--- /dev/null
+++ b/MAIN.C
@@ -0,0 +1,261 @@
+//****************************************************************************
+// @Module        Project Settings
+// @Filename      MAIN.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description   This file contains the Project initialization function.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:29
+//
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (MAIN_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+
+// USER CODE BEGIN (MAIN_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void MAIN_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function initializes the microcontroller. It is 
+//                assumed that the SFRs are in their reset state.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Init,1)
+
+// USER CODE END
+
+void MAIN_vInit(void)
+{
+  // USER CODE BEGIN (MAIN_Init,2)
+
+  // USER CODE END
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of the System Clock:
+  ///  -----------------------------------------------------------------------
+  ///  - External Osc is selected (configuration is done in the startup file 
+  ///    'START_XC.A51')
+  ///  - PLL Mode, NDIV =  24
+  ///  - input frequency is 8 MHz
+
+
+  //   FCLK runs at 2 times the frequency of PCLK.
+  SFR_PAGE(_su1, noSST);         // switch to page1
+
+  CMCON         =  0x10;         // load Clock Control Register
+
+  SFR_PAGE(_su0, noSST);         // switch to page0
+
+
+  ///  *********************************************************************************
+  ///  Note : All peripheral related IO configurations are done in the 
+  ///  respective peripheral modules (alternate functions selection)
+  ///  *********************************************************************************
+
+  ///  Initialization of module 'GPIO'
+  IO_vInit();
+
+  ///  Initialization of module 'Timer 2'
+  T2_vInit();
+
+  ///  Initialization of module 'Watch Dog Timer'
+  WDT_vInit();	
+
+  ///  Initialization of module 'MultiCAN Controller '
+  CAN_vInit();
+	
+  ///  Initialization of module 'UART (Serial Interface)'
+  UART_vInit();
+
+  ///  Initialization of  'Shared interrupts'
+  SHINT_vInit();
+
+  //   Interrupt Priority
+
+  IP            =  0x00;         // load Interrupt Priority Register
+  IPH           =  0x00;         // load Interrupt Priority High Register
+  IP1           =  0x00;         // load Interrupt Priority 1 Register
+  IPH1          =  0x00;         // load Interrupt Priority 1 High Register
+
+
+  // USER CODE BEGIN (MAIN_Init,3)
+
+  // USER CODE END
+
+  //// Interrupt structure 2 mode 0 is selected.
+
+  //// Interrupt service routine choice 2 is selected.
+
+  //   globally enable interrupts
+  EA            =  1;           
+
+} //  End of function MAIN_vInit
+
+
+//****************************************************************************
+// @Function      void main(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the main function.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Main,1)
+ubyte rxbuf[25] = {0};
+
+// USER CODE END
+
+void main(void)
+{
+  // USER CODE BEGIN (MAIN_Main,2)
+//  ulong i,j;
+// 	static ubyte tmp[8] = {0};
+//	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+
+  // USER CODE END
+
+  MAIN_vInit();
+
+  // USER CODE BEGIN (MAIN_Main,3)
+	SCU_PAGE        = 0;
+	SP              = 0xC0;    // Initialize Stack Pointer to 0xC0;	
+//	CanTransmit();
+
+//	FlgCan_1 = 1;//复位后延时一段时间再调用CAN发送
+  // USER CODE END
+
+  while(1)
+  {
+
+  // USER CODE BEGIN (MAIN_Main,4)
+//  		for(j=0;j<200;j++){for(i=0;i<133;i++)WDT_vRefresh();}
+//  		tmp[3] = (ubyte)CntCan_1;
+//  		tmp[2] = (ubyte)(CntCan_1>>8);
+
+//		SwSample();
+		CanRXTX();	
+		sbusCanDecode();
+		CanErrorProcess();			
+		WDT_vRefresh();
+//		LedDr();
+		BootMain();
+// 		tmp[1] = (ubyte)CntCan_1;
+//  		tmp[0] = (ubyte)(CntCan_1>>8);
+//  		CAN_vLoadData(0x2, (ulong *)(tmp)); // Add this Line			
+//  		CAN_vTransmit(2);	
+//  		for(j=0;j<200;j++){for(i=0;i<133;i++)WDT_vRefresh();}
+  // USER CODE END
+
+  }
+
+} //  End of function main
+
+
+// USER CODE BEGIN (MAIN_General,10)
+
+// USER CODE END
+
diff --git a/MAIN.H b/MAIN.H
new file mode 100644
index 0000000..507e398
--- /dev/null
+++ b/MAIN.H
@@ -0,0 +1,625 @@
+//****************************************************************************
+// @Module        Project Settings
+// @Filename      MAIN.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description   This is the include header file for all other modules.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:27
+//
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _MAIN_H_
+#define _MAIN_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// Please ensure that SCU_PAGE is switched to Page 1 before using these macros
+#define MAIN_vUnlockProtecReg() PASSWD = 0x9B 
+#define MAIN_vlockProtecReg()   PASSWD = 0xAB
+
+
+// USER CODE BEGIN (MAIN_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,4)
+
+// USER CODE END
+
+#define bool  bit
+#define ulong unsigned long
+#define uword unsigned int
+#define ubyte unsigned char
+
+
+#define KEIL
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+
+// USER CODE BEGIN (MAIN_Header,5)
+
+// USER CODE END
+
+
+//   -------------------------------------------------------------------------
+//   Declaration of SFRs
+//   -------------------------------------------------------------------------
+
+//   Notes: You can avoid the problem that your compiler does not yet support 
+//          the latest derivatives if you use the SFR definitions generated 
+//          by DAvE instead of those that come along with your compiler (in 
+//          the "Register File").
+
+//          PORT SFRs are defined in file 'IO.H'.
+
+//   SFR byte definitions
+sfr ACC        = 0xE0;    
+sfr ADC_CHCTR0 = 0xCA;    
+sfr ADC_CHCTR1 = 0xCB;    
+sfr ADC_CHCTR2 = 0xCC;    
+sfr ADC_CHCTR3 = 0xCD;    
+sfr ADC_CHCTR4 = 0xCE;    
+sfr ADC_CHCTR5 = 0xCF;    
+sfr ADC_CHCTR6 = 0xD2;    
+sfr ADC_CHCTR7 = 0xD3;    
+sfr ADC_CHINCR = 0xCB;    
+sfr ADC_CHINFR = 0xCA;    
+sfr ADC_CHINPR = 0xCD;    
+sfr ADC_CHINSR = 0xCC;    
+sfr ADC_CRCR1  = 0xCA;    
+sfr ADC_CRMR1  = 0xCC;    
+sfr ADC_CRPR1  = 0xCB;    
+sfr ADC_ETRCR  = 0xCF;    
+sfr ADC_EVINCR = 0xCF;    
+sfr ADC_EVINFR = 0xCE;    
+sfr ADC_EVINPR = 0xD3;    
+sfr ADC_EVINSR = 0xD2;    
+sfr ADC_GLOBCTR = 0xCA;    
+sfr ADC_GLOBSTR = 0xCB;    
+sfr ADC_INPCR0 = 0xCE;    
+sfr ADC_LCBR   = 0xCD;    
+sfr ADC_PAGE   = 0xD1;    
+sfr ADC_PRAR   = 0xCC;    
+sfr ADC_Q0R0   = 0xCF;    
+sfr ADC_QBUR0  = 0xD2;    
+sfr ADC_QINR0  = 0xD2;    
+sfr ADC_QMR0   = 0xCD;    
+sfr ADC_QSR0   = 0xCE;    
+sfr ADC_RCR0   = 0xCA;    
+sfr ADC_RCR1   = 0xCB;    
+sfr ADC_RCR2   = 0xCC;    
+sfr ADC_RCR3   = 0xCD;    
+sfr ADC_RESR0H = 0xCB;    
+sfr ADC_RESR0L = 0xCA;    
+sfr ADC_RESR1H = 0xCD;    
+sfr ADC_RESR1L = 0xCC;    
+sfr ADC_RESR2H = 0xCF;    
+sfr ADC_RESR2L = 0xCE;    
+sfr ADC_RESR3H = 0xD3;    
+sfr ADC_RESR3L = 0xD2;    
+sfr ADC_RESRA0H = 0xCB;    
+sfr ADC_RESRA0L = 0xCA;    
+sfr ADC_RESRA1H = 0xCD;    
+sfr ADC_RESRA1L = 0xCC;    
+sfr ADC_RESRA2H = 0xCF;    
+sfr ADC_RESRA2L = 0xCE;    
+sfr ADC_RESRA3H = 0xD3;    
+sfr ADC_RESRA3L = 0xD2;    
+sfr ADC_VFCR   = 0xCE;    
+sfr B          = 0xF0;    
+sfr BCON       = 0xBD;    
+sfr BG         = 0xBE;    
+sfr CAN_ADCON  = 0xD8;    
+sfr CAN_ADH    = 0xDA;    
+sfr CAN_ADL    = 0xD9;    
+sfr CAN_DATA0  = 0xDB;    
+sfr CAN_DATA1  = 0xDC;    
+sfr CAN_DATA2  = 0xDD;    
+sfr CAN_DATA3  = 0xDE;    
+sfr CCU6_CC60RH = 0xFB;    
+sfr CCU6_CC60RL = 0xFA;    
+sfr CCU6_CC60SRH = 0xFB;    
+sfr CCU6_CC60SRL = 0xFA;    
+sfr CCU6_CC61RH = 0xFD;    
+sfr CCU6_CC61RL = 0xFC;    
+sfr CCU6_CC61SRH = 0xFD;    
+sfr CCU6_CC61SRL = 0xFC;    
+sfr CCU6_CC62RH = 0xFF;    
+sfr CCU6_CC62RL = 0xFE;    
+sfr CCU6_CC62SRH = 0xFF;    
+sfr CCU6_CC62SRL = 0xFE;    
+sfr CCU6_CC63RH = 0x9B;    
+sfr CCU6_CC63RL = 0x9A;    
+sfr CCU6_CC63SRH = 0x9B;    
+sfr CCU6_CC63SRL = 0x9A;    
+sfr CCU6_CMPMODIFH = 0xA7;    
+sfr CCU6_CMPMODIFL = 0xA6;    
+sfr CCU6_CMPSTATH = 0xFF;    
+sfr CCU6_CMPSTATL = 0xFE;    
+sfr CCU6_IENH  = 0x9D;    
+sfr CCU6_IENL  = 0x9C;    
+sfr CCU6_INPH  = 0x9F;    
+sfr CCU6_INPL  = 0x9E;    
+sfr CCU6_ISH   = 0x9D;    
+sfr CCU6_ISL   = 0x9C;    
+sfr CCU6_ISRH  = 0xA5;    
+sfr CCU6_ISRL  = 0xA4;    
+sfr CCU6_ISSH  = 0xA5;    
+sfr CCU6_ISSL  = 0xA4;    
+sfr CCU6_MCMCTR = 0xA7;    
+sfr CCU6_MCMOUTH = 0x9B;    
+sfr CCU6_MCMOUTL = 0x9A;    
+sfr CCU6_MCMOUTSH = 0x9F;    
+sfr CCU6_MCMOUTSL = 0x9E;    
+sfr CCU6_MODCTRH = 0xFD;    
+sfr CCU6_MODCTRL = 0xFC;    
+sfr CCU6_PAGE  = 0xA3;    
+sfr CCU6_PISEL0H = 0x9F;    
+sfr CCU6_PISEL0L = 0x9E;    
+sfr CCU6_PISEL2 = 0xA4;    
+sfr CCU6_PSLR  = 0xA6;    
+sfr CCU6_T12DTCH = 0xA5;    
+sfr CCU6_T12DTCL = 0xA4;    
+sfr CCU6_T12H  = 0xFB;    
+sfr CCU6_T12L  = 0xFA;    
+sfr CCU6_T12MSELH = 0x9B;    
+sfr CCU6_T12MSELL = 0x9A;    
+sfr CCU6_T12PRH = 0x9D;    
+sfr CCU6_T12PRL = 0x9C;    
+sfr CCU6_T13H  = 0xFD;    
+sfr CCU6_T13L  = 0xFC;    
+sfr CCU6_T13PRH = 0x9F;    
+sfr CCU6_T13PRL = 0x9E;    
+sfr CCU6_TCTR0H = 0xA7;    
+sfr CCU6_TCTR0L = 0xA6;    
+sfr CCU6_TCTR2H = 0xFB;    
+sfr CCU6_TCTR2L = 0xFA;    
+sfr CCU6_TCTR4H = 0x9D;    
+sfr CCU6_TCTR4L = 0x9C;    
+sfr CCU6_TRPCTRH = 0xFF;    
+sfr CCU6_TRPCTRL = 0xFE;    
+sfr CD_CON     = 0xA1;    
+sfr CD_CORDXH  = 0x9B;    
+sfr CD_CORDXL  = 0x9A;    
+sfr CD_CORDYH  = 0x9D;    
+sfr CD_CORDYL  = 0x9C;    
+sfr CD_CORDZH  = 0x9F;    
+sfr CD_CORDZL  = 0x9E;    
+sfr CD_STATC   = 0xA0;    
+sfr CMCON      = 0xBA;    
+sfr COCON      = 0xBE;    
+sfr DPH        = 0x83;    
+sfr DPL        = 0x82;    
+sfr EO         = 0xA2;    
+sfr EXICON0    = 0xB7;    
+sfr EXICON1    = 0xBA;    
+sfr FDCON      = 0xE9;    
+sfr FDRES      = 0xEB;    
+sfr FDSTEP     = 0xEA;    
+sfr FEAH       = 0xBD;    
+sfr FEAL       = 0xBC;    
+sfr HWBPDR     = 0xF7;    
+sfr HWBPSR     = 0xF6;    
+sfr ID         = 0xB3;    
+sfr IEN0       = 0xA8;    
+sfr IEN1       = 0xE8;    
+sfr IP         = 0xB8;    
+sfr IP1        = 0xF8;    
+sfr IPH        = 0xB9;    
+sfr IPH1       = 0xF9;    
+sfr IRCON0     = 0xB4;    
+sfr IRCON1     = 0xB5;    
+sfr IRCON2     = 0xB6;    
+sfr IRCON3     = 0xB4;    
+sfr IRCON4     = 0xB5;    
+sfr MDU_MD0    = 0xB2;    
+sfr MDU_MD1    = 0xB3;    
+sfr MDU_MD2    = 0xB4;    
+sfr MDU_MD3    = 0xB5;    
+sfr MDU_MD4    = 0xB6;    
+sfr MDU_MD5    = 0xB7;    
+sfr MDU_MDUCON = 0xB1;    
+sfr MDU_MDUSTAT = 0xB0;    
+sfr MDU_MR0    = 0xB2;    
+sfr MDU_MR1    = 0xB3;    
+sfr MDU_MR2    = 0xB4;    
+sfr MDU_MR3    = 0xB5;    
+sfr MDU_MR4    = 0xB6;    
+sfr MDU_MR5    = 0xB7;    
+sfr MISC_CON   = 0xE9;    
+sfr MMBPCR     = 0xF3;    
+sfr MMCR       = 0xF1;    
+sfr MMCR2      = 0xE9;    
+sfr MMDR       = 0xF5;    
+sfr MMICR      = 0xF4;    
+sfr MMSR       = 0xF2;    
+sfr MMWR1      = 0xEB;    
+sfr MMWR2      = 0xEC;    
+sfr MODPISEL   = 0xB3;    
+sfr MODPISEL1  = 0xB7;    
+sfr MODPISEL2  = 0xBA;    
+sfr MODSUSP    = 0xBD;    
+sfr NMICON     = 0xBB;    
+sfr NMISR      = 0xBC;    
+sfr OSC_CON    = 0xB6;    
+sfr P0_ALTSEL0 = 0x80;    
+sfr P0_ALTSEL1 = 0x86;    
+sfr P0_DATA    = 0x80;    
+sfr P0_DIR     = 0x86;    
+sfr P0_OD      = 0x80;    
+sfr P0_PUDEN   = 0x86;    
+sfr P0_PUDSEL  = 0x80;    
+sfr P1_ALTSEL0 = 0x90;    
+sfr P1_ALTSEL1 = 0x91;    
+sfr P1_DATA    = 0x90;    
+sfr P1_DIR     = 0x91;    
+sfr P1_OD      = 0x90;    
+sfr P1_PUDEN   = 0x91;    
+sfr P1_PUDSEL  = 0x90;    
+sfr P2_DATA    = 0xA0;    
+sfr P2_DIR     = 0xA1;    
+sfr P2_PUDEN   = 0xA1;    
+sfr P2_PUDSEL  = 0xA0;    
+sfr P3_ALTSEL0 = 0xB0;    
+sfr P3_ALTSEL1 = 0xB1;    
+sfr P3_DATA    = 0xB0;    
+sfr P3_DIR     = 0xB1;    
+sfr P3_OD      = 0xB0;    
+sfr P3_PUDEN   = 0xB1;    
+sfr P3_PUDSEL  = 0xB0;    
+sfr P4_ALTSEL0 = 0xC8;    
+sfr P4_ALTSEL1 = 0xC9;    
+sfr P4_DATA    = 0xC8;    
+sfr P4_DIR     = 0xC9;    
+sfr P4_OD      = 0xC8;    
+sfr P4_PUDEN   = 0xC9;    
+sfr P4_PUDSEL  = 0xC8;    
+sfr P5_ALTSEL0 = 0x92;    
+sfr P5_ALTSEL1 = 0x93;    
+sfr P5_DATA    = 0x92;    
+sfr P5_DIR     = 0x93;    
+sfr P5_OD      = 0x92;    
+sfr P5_PUDEN   = 0x93;    
+sfr P5_PUDSEL  = 0x92;    
+sfr PASSWD     = 0xBB;    
+sfr PCON       = 0x87;    
+sfr PLL_CON    = 0xB7;    
+sfr PMCON0     = 0xB4;    
+sfr PMCON1     = 0xB5;    
+sfr PMCON2     = 0xBB;    
+sfr PORT_PAGE  = 0xB2;    
+sfr PSW        = 0xD0;    
+sfr SBUF       = 0x99;    
+sfr SCON       = 0x98;    
+sfr SCU_PAGE   = 0xBF;    
+sfr SP         = 0x81;    
+sfr SSC_BRH    = 0xAF;    
+sfr SSC_BRL    = 0xAE;    
+sfr SSC_CONH_O = 0xAB;    
+sfr SSC_CONH_P = 0xAB;    
+sfr SSC_CONL_O = 0xAA;    
+sfr SSC_CONL_P = 0xAA;    
+sfr SSC_PISEL  = 0xA9;    
+sfr SSC_RBL    = 0xAD;    
+sfr SSC_TBL    = 0xAC;    
+sfr SYSCON0    = 0x8F;    
+sfr T21_RC2H   = 0xC3;    
+sfr T21_RC2L   = 0xC2;    
+sfr T21_T2CON  = 0xC0;    
+sfr T21_T2H    = 0xC5;    
+sfr T21_T2L    = 0xC4;    
+sfr T21_T2MOD  = 0xC1;    
+sfr T2_RC2H    = 0xC3;    
+sfr T2_RC2L    = 0xC2;    
+sfr T2_T2CON   = 0xC0;    
+sfr T2_T2H     = 0xC5;    
+sfr T2_T2L     = 0xC4;    
+sfr T2_T2MOD   = 0xC1;    
+sfr TCON       = 0x88;    
+sfr TH0        = 0x8C;    
+sfr TH1        = 0x8D;    
+sfr TL0        = 0x8A;    
+sfr TL1        = 0x8B;    
+sfr TMOD       = 0x89;    
+sfr UART1_BCON = 0xCA;    
+sfr UART1_BG   = 0xCB;    
+sfr UART1_FDCON = 0xCC;    
+sfr UART1_FDRES = 0xCE;    
+sfr UART1_FDSTEP = 0xCD;    
+sfr UART1_SBUF = 0xC9;    
+sfr UART1_SCON = 0xC8;    
+sfr WDTCON     = 0xBB;    //   located in the mapped SFR area
+sfr WDTH       = 0xBF;    //   located in the mapped SFR area
+sfr WDTL       = 0xBE;    //   located in the mapped SFR area
+sfr WDTREL     = 0xBC;    //   located in the mapped SFR area
+sfr WDTWINB    = 0xBD;    //   located in the mapped SFR area
+sfr XADDRH     = 0xB3;    
+
+//   SFR bit definitions
+
+//   CD_STATC
+sbit CD_BSY     = 0xA0;    
+sbit DMAP       = 0xA4;    
+sbit EOC        = 0xA2;    
+sbit ERROR      = 0xA1;    
+sbit INT_EN     = 0xA3;    
+sbit KEEPX      = 0xA5;    
+sbit KEEPY      = 0xA6;    
+sbit KEEPZ      = 0xA7;    
+
+//   IEN0
+sbit EA         = 0xAF;    
+sbit ES         = 0xAC;    
+sbit ET0        = 0xA9;    
+sbit ET1        = 0xAB;    
+sbit ET2        = 0xAD;    
+sbit EX0        = 0xA8;    
+sbit EX1        = 0xAA;    
+
+//   IEN1
+sbit EADC       = 0xE8;    
+sbit ECCIP0     = 0xEC;    
+sbit ECCIP1     = 0xED;    
+sbit ECCIP2     = 0xEE;    
+sbit ECCIP3     = 0xEF;    
+sbit ESSC       = 0xE9;    
+sbit EX2        = 0xEA;    
+sbit EXM        = 0xEB;    
+
+//   IP1
+sbit PADC       = 0xF8;    
+sbit PCCIP0     = 0xFC;    
+sbit PCCIP1     = 0xFD;    
+sbit PCCIP2     = 0xFE;    
+sbit PCCIP3     = 0xFF;    
+sbit PSSC       = 0xF9;    
+sbit PX2        = 0xFA;    
+sbit PXM        = 0xFB;    
+
+//   IP
+sbit PS         = 0xBC;    
+sbit PT0        = 0xB9;    
+sbit PT1        = 0xBB;    
+sbit PT2        = 0xBD;    
+sbit PX0        = 0xB8;    
+sbit PX1        = 0xBA;    
+
+//   MDU_MDUSTAT
+sbit IERR       = 0xB1;    
+sbit IRDY       = 0xB0;    
+sbit MDU_BSY    = 0xB2;    
+
+//   PSW
+sbit AC         = 0xD6;    
+sbit CY         = 0xD7;    
+sbit F0         = 0xD5;    
+sbit F1         = 0xD1;    
+sbit OV         = 0xD2;    
+sbit P          = 0xD0;    
+sbit RS0        = 0xD3;    
+sbit RS1        = 0xD4;    
+
+//   SCON
+sbit RB8        = 0x9A;    
+sbit REN        = 0x9C;    
+sbit RI         = 0x98;    
+sbit SM0        = 0x9F;    
+sbit SM1        = 0x9E;    
+sbit SM2        = 0x9D;    
+sbit TB8        = 0x9B;    
+sbit TI         = 0x99;    
+
+//   T2_T2CON and T21_T2CON
+sbit C_T2       = 0xC1;    
+sbit CP_RL2     = 0xC0;    
+sbit EXEN2      = 0xC3;    
+sbit EXF2       = 0xC6;    
+sbit TF2        = 0xC7;    
+sbit TR2        = 0xC2;    
+
+//   TCON
+sbit IE0        = 0x89;    
+sbit IE1        = 0x8B;    
+sbit IT0        = 0x88;    
+sbit IT1        = 0x8A;    
+sbit TF0        = 0x8D;    
+sbit TF1        = 0x8F;    
+sbit TR0        = 0x8C;    
+sbit TR1        = 0x8E;    
+
+//   UART1_SCON
+sbit RB8_1      = 0xCA;    
+sbit REN_1      = 0xCC;    
+sbit RI_1       = 0xC8;    
+sbit SM0_1      = 0xCF;    
+sbit SM1_1      = 0xCE;    
+sbit SM2_1      = 0xCD;    
+sbit TB8_1      = 0xCB;    
+sbit TI_1       = 0xC9;    
+
+
+//   Definition of the 16-bit SFR
+//   sfr16 data type to access two 8-bit SFRs as a single 16-bit SFR.
+
+sfr16 CAN_ADLH = 0xD9;           // 16-bit Address
+sfr16 CAN_DATA01 = 0xDB;         // 16-bit Address
+sfr16 CAN_DATA23 = 0xDD;         // 16-bit Address
+sfr16 CCU6_CC60RLH = 0xFA;       // 16-bit Address
+sfr16 CCU6_CC60SRLH = 0xFA;      // 16-bit Address
+sfr16 CCU6_CC61RLH = 0xFC;       // 16-bit Address
+sfr16 CCU6_CC61SRLH = 0xFC;      // 16-bit Address
+sfr16 CCU6_CC62RLH = 0xFE;       // 16-bit Address
+sfr16 CCU6_CC62SRLH = 0xFE;      // 16-bit Address
+sfr16 CCU6_CC63RLH = 0x9A;       // 16-bit Address
+sfr16 CCU6_CC63SRLH = 0x9A;      // 16-bit Address
+sfr16 CCU6_T12LH = 0xFA;         // 16-bit Address
+sfr16 CCU6_T12PRLH = 0x9C;       // 16-bit Address
+sfr16 CCU6_T13LH = 0xFC;         // 16-bit Address
+sfr16 CCU6_T13PRLH = 0x9E;       // 16-bit Address
+sfr16 T21_RC2LH = 0xC2;          // 16-bit Address
+sfr16 T21_T2LH = 0xC4;           // 16-bit Address
+sfr16 T2_RC2LH = 0xC2;           // 16-bit Address
+sfr16 T2_T2LH = 0xC4;            // 16-bit Address
+
+//   Definition of the PAGE SFR
+
+//   PORT_PAGE
+#define _pp0 PORT_PAGE=0 // PORT_PAGE postfix
+#define _pp1 PORT_PAGE=1 // PORT_PAGE postfix
+#define _pp2 PORT_PAGE=2 // PORT_PAGE postfix
+#define _pp3 PORT_PAGE=3 // PORT_PAGE postfix
+
+//   ADC_PAGE
+#define _ad0 ADC_PAGE=0 // ADC_PAGE postfix
+#define _ad1 ADC_PAGE=1 // ADC_PAGE postfix
+#define _ad2 ADC_PAGE=2 // ADC_PAGE postfix
+#define _ad3 ADC_PAGE=3 // ADC_PAGE postfix
+#define _ad4 ADC_PAGE=4 // ADC_PAGE postfix
+#define _ad5 ADC_PAGE=5 // ADC_PAGE postfix
+#define _ad6 ADC_PAGE=6 // ADC_PAGE postfix
+
+//   SCU_PAGE
+#define _su0 SCU_PAGE=0 // SCU_PAGE postfix
+#define _su1 SCU_PAGE=1 // SCU_PAGE postfix
+#define _su2 SCU_PAGE=2 // SCU_PAGE postfix
+#define _su3 SCU_PAGE=3 // SCU_PAGE postfix
+
+//   CCU6_PAGE
+#define _cc0 CCU6_PAGE=0 // CCU6_PAGE postfix
+#define _cc1 CCU6_PAGE=1 // CCU6_PAGE postfix
+#define _cc2 CCU6_PAGE=2 // CCU6_PAGE postfix
+#define _cc3 CCU6_PAGE=3 // CCU6_PAGE postfix
+
+#define SST0  0x80        // Save SFR page to ST0
+#define RST0  0xC0        // Restore SFR page from ST0
+#define SST1  0x90        // Save SFR page to ST1
+#define RST1  0xD0        // Restore SFR page from ST1
+#define SST2  0xA0        // Save SFR page to ST2
+#define RST2  0xE0        // Restore SFR page from ST2
+#define SST3  0xB0        // Save SFR page to ST3
+#define RST3  0xF0        // Restore SFR page from ST3
+#define noSST 0x00        // Switch page without saving
+
+#define SFR_PAGE(pg,op) pg+op
+
+//   SYSCON0_RMAP
+//   The access to the mapped SFR area is enabled.
+#define SET_RMAP() SYSCON0 |= 0x01
+
+//   The access to the standard SFR area is enabled.
+#define RESET_RMAP() SYSCON0 &= ~0x01
+
+
+#define _su  SCU_PAGE // SCU_PAGE
+
+#define STR_PAGE(pg,op)  { _push_(op); \
+   pg ; }
+
+#define RST_PAGE(op)  _pop_(op)
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+// USER CODE BEGIN (MAIN_Header,10)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+
+
+#include 
+
+#include "IO.H"
+#include "T2.H"
+#include "WDT.H"
+#include "PS.H"
+#include "CAN.H"
+#include "SHARED_INT.H"
+#include "UART.H"
+
+
+
+
+
+
+// USER CODE BEGIN (MAIN_Header,11)
+#include  "Config.H"
+// USER CODE END
+
+
+#endif  // ifndef _MAIN_H_
diff --git a/PS.C b/PS.C
new file mode 100644
index 0000000..8831cd1
--- /dev/null
+++ b/PS.C
@@ -0,0 +1,296 @@
+//****************************************************************************
+// @Module        Power Saving Modes
+// @Filename      PS.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the PS module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21 08:53:36
+//
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (PS_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (PS_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void PS_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the Power Saving 
+//                function library. It is assumed that the SFRs used by this 
+//                library are in their reset state. 
+//                
+//                This function does not contain any generated C-code, but it 
+//                is possible to insert application specific source lines. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Init,1)
+
+// USER CODE END
+
+void PS_vInit(void)
+{
+  // USER CODE BEGIN (PS_Init,2)
+
+  // USER CODE END
+
+  ///  Slow Down Clock is 48.00 MHz
+  ///  which is 1/4 of the System Clock fSYS
+
+  ///  wake up with reset is selected
+
+
+  SFR_PAGE(_su1, noSST);         // switch to page1 with out saving
+
+  ///  Pin P0.1 (input)
+  ///  - used as wake up pin via RXD_1 from powerdown 
+
+  ///  Pin P0.5 (input)
+  ///  - used as wake up pin via EXINT0 from powerdown 
+
+  PMCON0        =  0x13;         //  wakeup control register
+
+  //   ---------- Modules configuration status for PMCON1 reg.----------
+
+  ///   ADC enabled
+  ///   SSC disabled
+  ///   CCU enabled
+  ///   T2 enabled
+  ///   MDU enabled
+  ///   CAN enabled
+  ///   CDC enabled
+  PMCON1        =  0x02;         //  Power mode control register 1
+
+  SFR_PAGE(_su3, noSST);         // switch to page3 with out saving
+
+  //   ---------- Modules configuration status for PMCON2 reg.----------
+
+  ///   T21 enabled
+  ///   UART1 enabled
+  PMCON2        =  0x00;         //  Power mode control register 2
+
+  SFR_PAGE(_su0, noSST);         // switch to page0 with out saving
+
+  IEN0         |= 0x01;          // interrupt enable  register 0
+  TCON          =  0x01;         // Set TCON.IT0 
+
+  MODPISEL      =  0x01;         // load peripheral input select reg
+
+} //  End of function PS_vInit
+
+
+//****************************************************************************
+// @Function      void PS_vSetPowerDown(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function invokes the software power down mode by 
+//                execution of following steps:
+//                - the external wake-up from software power down remains 
+//                disabled
+//                - bit PD in SFR PMCON0 will be set
+//                  (this will stop all controller functions)
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+void PS_vSetPowerDown(void)
+{
+  //   enter software power down mode
+  STR_PAGE(_su1, _su);           // push current SCU page and switch to page1
+
+  ///  External wake-up enabled
+
+  ///  Wake-up via pin RxD_1 and EXINT0 is selected
+  PMCON0|=0x03;
+
+  MAIN_vUnlockProtecReg();       // open access to protected register
+ 
+  PMCON0 |= 0x04;     //   set   PD
+ 
+  MAIN_vlockProtecReg();         // close access to protected register
+
+  RST_PAGE(_su);                 // restore the old SCU page
+
+} //  End of function PS_vSetPowerDown
+
+
+//****************************************************************************
+// @Function      void PS_vSetSlowDown(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function activates the slow down mode by setting bit 
+//                SD in SFR PMCON0.
+//                Note: DAvE's project settings for the on-chip peripheral 
+//                components are only valid for normal clock operation. 
+//                During slow down mode the behavior of the peripherals can 
+//                differ from these settings due to the reduced clock rate!
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+void PS_vSetSlowDown(void)
+{
+
+  STR_PAGE(_su1, _su);           // push current SCU page and switch to page1
+
+
+  MAIN_vUnlockProtecReg();       // open access to protected register
+
+  PMCON0 |= 0x08;     //   set   SD
+
+  MAIN_vlockProtecReg();         // close access to protected register
+
+  RST_PAGE(_su);                 // restore the old SCU page
+
+} //  End of function PS_vSetSlowDown
+
+
+//****************************************************************************
+// @Function      void PS_vResetSlowDown(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function terminates the slow down mode by clearing bit 
+//                SD in SFR PMCON0.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+void PS_vResetSlowDown(void)
+{
+
+  STR_PAGE(_su1, _su);           // push current SCU page and switch to page1
+
+
+  MAIN_vUnlockProtecReg();       // open access to protected register
+
+  PMCON0 &= ~(ubyte)0x08; //   clear SD
+
+  MAIN_vlockProtecReg();         // close access to protected register
+
+  RST_PAGE(_su);                 // restore the old SCU page
+
+} //  End of function PS_vResetSlowDown
+
+
+// USER CODE BEGIN (PS_General,10)
+
+// USER CODE END
+
diff --git a/PS.H b/PS.H
new file mode 100644
index 0000000..fc8ce79
--- /dev/null
+++ b/PS.H
@@ -0,0 +1,202 @@
+//****************************************************************************
+// @Module        Power Saving Modes
+// @Filename      PS.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the PS module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21 08:53:36
+//
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _PS_H_
+#define _PS_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (PS_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void PS_vInit(void);
+void PS_vSetPowerDown(void);
+void PS_vSetSlowDown(void);
+void PS_vResetSlowDown(void);
+
+// USER CODE BEGIN (PS_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macro         void PS_vSetIdle() 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro enters the idle mode by setting bit IDLE in SFR 
+//                PCON. The instruction will stop the CPU immediately. Thus 
+//                any following code will not be executed before the 
+//                controller has been restarted by an interrupt.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+#define PS_vSetIdle() PCON |= 0x01
+
+
+//****************************************************************************
+// @Macro         PS_vDisableModule(ModuleName) 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro disables a specific peripheral module which is 
+//                passed in a parameter.Switch the page to 1 using the 
+//                statementSFR_PAGE(_su1, SST1);    before calling this 
+//                Disable macro.After that again switch back the page to 0 
+//                with the macro SFR_PAGE(_su1, RST1);.The following 
+//                constants are available for 'ModuleName':
+//                ADC, T2, CCU, SSC, MDU, CAN, CDC, T21, UART1
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    ModuleName: 
+//                Name of the Module
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+#define PS_vDisableModule(Module) PS_vDisableModule_(Module)
+
+#define PS_vDisableModule_(Module) PS_vDisableModule_##Module
+
+#define PS_vDisableModule_ADC                  PMCON1 |= 0x01
+#define PS_vDisableModule_T2                   PMCON1 |= 0x08
+#define PS_vDisableModule_CCU                  PMCON1 |= 0x04
+#define PS_vDisableModule_SSC                  PMCON1 |= 0x02
+#define PS_vDisableModule_MDU                  PMCON1 |= 0x10
+#define PS_vDisableModule_CAN                  PMCON1 |= 0x20
+#define PS_vDisableModule_CDC                  PMCON1 |= 0x40
+#define PS_vDisableModule_T21                  PMCON2 |= 0x01
+#define PS_vDisableModule_UART1                PMCON2 |= 0x02
+
+
+//****************************************************************************
+// @Macro         PS_vEnableModule(ModuleName) 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro enables a specific peripheral module which is 
+//                passed in a parameter. Switch the page to 1 using the 
+//                statement SFR_PAGE(_su1, SST1);    before calling this 
+//                Enable macro.After that again switch back the page to 0 
+//                with the macro SFR_PAGE(_su1, RST1);.The following 
+//                constants are available for 'ModuleName':
+//                ADC, T2, CCU, SSC, MDU, CAN, CDC, T21, UART1
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    ModuleName: 
+//                Name of the Module
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/21
+//
+//****************************************************************************
+
+#define PS_vEnableModule(Module) PS_vEnableModule_(Module)
+
+#define PS_vEnableModule_(Module) PS_vEnableModule_##Module
+
+#define PS_vEnableModule_ADC                  PMCON1 &= ~(ubyte)0x01
+#define PS_vEnableModule_T2                   PMCON1 &= ~(ubyte)0x08
+#define PS_vEnableModule_CCU                  PMCON1 &= ~(ubyte)0x04
+#define PS_vEnableModule_SSC                  PMCON1 &= ~(ubyte)0x02
+#define PS_vEnableModule_MDU                  PMCON1 &= ~(ubyte)0x10
+#define PS_vEnableModule_CAN                  PMCON1 &= ~(ubyte)0x20
+#define PS_vEnableModule_CDC                  PMCON1 &= ~(ubyte)0x40
+#define PS_vEnableModule_T21                  PMCON2 &= ~(ubyte)0x01
+#define PS_vEnableModule_UART1                PMCON2 &= ~(ubyte)0x02
+
+
+// USER CODE BEGIN (PS_Header,9)
+
+// USER CODE END
+
+#endif  // ifndef _PS_H_
diff --git a/RTC.c b/RTC.c
new file mode 100644
index 0000000..534cda7
--- /dev/null
+++ b/RTC.c
@@ -0,0 +1,238 @@
+#include "MAIN.H"
+
+
+unsigned char bySta = 0;
+
+void SDAOut(bit c)
+{
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P4_DIR        =  P4_DIR | 0x08;//修改P4.3为输出
+	P4_3 = c;
+
+}
+
+void SCLOut(bit c)
+{
+	P1_5 = c;
+}
+
+void iic_start(void)
+{
+  SDAOut(1);
+  _nop_();
+  SCLOut(1);
+  somenop;
+  SDAOut(0);
+  somenop;
+  SCLOut(0);
+}
+
+void iic_stop(void)
+{
+  SDAOut(0);
+  _nop_();
+  SCLOut(1);
+  somenop;
+  SDAOut(1);
+}
+
+void iic_ack(bit ackbit)
+{
+  if(ackbit) 
+	SDAOut(0);
+  else 
+	SDAOut(1); 
+  somenop;
+  SCLOut(1);
+  somenop;
+  SCLOut(0);
+  SDAOut(1); 
+  somenop;
+}
+
+bit iic_waitack(void)
+{
+  SDAOut(1);
+  somenop;
+  SCLOut(1);
+	
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P4_DIR        =  P4_DIR & 0xF7;//修改P4.3为输入
+	
+  somenop;
+  if(P4_3)    
+  {   
+		SCLOut(0);
+		iic_stop();
+		return 0;
+  }
+  else  
+  { 
+		SCLOut(0);
+		return 1;
+  }
+}
+
+void iic_sendbyte(unsigned char byt)
+{
+  unsigned char i;
+  for(i=0;i<8;i++)
+  {   
+	  if(byt&0x80) 
+	    SDAOut(1);
+		else 
+		  SDAOut(0);
+		somenop;
+		SCLOut(1);
+		byt <<= 1;
+		somenop;
+	  SCLOut(0);
+  }
+}
+
+
+unsigned char iic_recbyte(void)
+{
+  unsigned char da;
+  unsigned char i;
+	
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P4_DIR        =  P4_DIR & 0xF7;//修改P4.3为输入
+	
+  for(i=0;i<8;i++)
+  {   
+     SCLOut(1);
+     somenop;
+     da <<= 1;
+
+//	P1_IOCR01      =  0x0020;      // load port control register 1
+	  if(P4_3)
+		  da |= 0x01;
+		SCLOut(0);
+		somenop;
+  }
+  return da;
+}
+
+// 十进制转 BCD 码
+unsigned char DecToBcd(unsigned char dec) 
+{
+    return ((dec / 10) << 4) | (dec % 10);
+}
+
+// BCD 码转十进制
+unsigned char BcdToDec(unsigned char bcd) 
+{
+    return ((bcd >> 4) * 10) + (bcd & 0x0F);
+}
+
+
+
+// BM8563 写寄存器函数
+void BM8563_WriteReg(unsigned char reg, unsigned char rdata)
+{
+	iic_start();
+	iic_sendbyte(BM8563_ADDR);  // 发送 BM8563 的 I2C 地址，写操作
+	iic_waitack();
+	iic_sendbyte(reg);  // 发送寄存器地址
+	iic_waitack();	
+	iic_sendbyte(rdata);  // 发送数据
+	iic_waitack();
+	iic_stop();
+}
+
+
+// BM8563 读寄存器函数
+unsigned char BM8563_ReadReg(unsigned char reg)
+{
+	unsigned char rdata;
+	iic_start();
+	iic_sendbyte(BM8563_ADDR);  // 发送 BM8563 的 I2C 地址，写操作
+	iic_waitack();	
+	iic_sendbyte(reg);  // 发送寄存器地址
+	iic_waitack();	
+	iic_start();
+	iic_sendbyte(BM8563_ADDR | 0x01);  // 发送 BM8563 的 I2C 地址，读操作
+	iic_waitack();
+	rdata = iic_recbyte();
+  iic_ack(0); 
+	iic_stop();
+	return rdata;
+}
+
+
+// 初始化 BM8563 的时间
+void BM8563_InitTime()
+{
+	BM8563_WriteReg(BM8563_SEC, 0x00);  // 秒
+	BM8563_WriteReg(BM8563_MIN, 0x00);  // 分
+	BM8563_WriteReg(BM8563_HOUR, 0x00);  // 小时
+	BM8563_WriteReg(BM8563_DAY, 0x01);  // 日
+	BM8563_WriteReg(BM8563_WEEK, 0x01);  // 周
+	BM8563_WriteReg(BM8563_MONTH, 0x01);  // 月
+	BM8563_WriteReg(BM8563_YEAR, DecToBcd(0x25));  // 年，假设为 2025 年
+}
+
+
+// 配置 BM8563 的定时器，实现间隔 4 小时的倒计时唤醒
+void BM8563_Set4HourCountdown()
+{
+	
+//	BM8563_WriteReg(BM8563_CONTROL, 0x01); 
+//	
+//	
+//	bySta = BM8563_ReadReg(BM8563_CONTROL);
+	
+	
+	// 4 小时的秒数，4 * 60 * 60 = 14400 秒
+	unsigned int fourHoursInSeconds = 5;  
+
+	// 选择时钟频率为 1/60 Hz
+	unsigned char timerControl = 0x02;  // 11 for 1/60 Hz
+
+	// 计算所需的计数值
+	unsigned char timerValue = fourHoursInSeconds * 10;  // 因为 1/60 Hz 意味着 1 count per minute
+
+	// 先将定时器控制寄存器设置为 0，停止定时器
+	BM8563_WriteReg(BM8563_CONTROL, 0x00);  
+
+	// 写入定时器计数值
+	BM8563_WriteReg(BM8563_TIMER_VALUE, timerValue);
+
+	// 配置定时器控制寄存器，使能定时器，且定时器到时产生中断
+	BM8563_WriteReg(BM8563_CONTROL, (timerControl | 0x80)); 
+
+	BM8563_WriteReg(BM8563_CSR2, 0x01); 
+	
+}
+
+
+
+// 配置 BM8563 的闹钟，实现间隔 4 小时的唤醒
+void BM8563_Set4HourAlarm() 
+{
+    unsigned char alarmMin =  BcdToDec( BM8563_ReadReg(BM8563_MIN) );
+    unsigned char alarmMinBcd = 0;	
+//------------------------------------------------------------	
+    alarmMin = (alarmMin + 2) % 60;//计算 4 小时后的小时数
+    alarmMinBcd  = DecToBcd(alarmMin);
+
+    BM8563_WriteReg(BM8563_ALARM_MIN,alarmMinBcd&0x7F);// 闹钟分钟设置
+    BM8563_WriteReg(BM8563_ALARM_HOUR, 0x80);       // 无效
+    BM8563_WriteReg(BM8563_ALARM_DAY , 0x80);       // 无效
+    BM8563_WriteReg(BM8563_ALARM_WEEK, 0x80);       // 无效
+    
+    // 配置闹钟控制寄存器，使能闹钟中断
+    BM8563_WriteReg(BM8563_CSR2, 0x02); 
+}
+
+
+
+
+
+
+
+
+
+
+
diff --git a/RTC.h b/RTC.h
new file mode 100644
index 0000000..335c350
--- /dev/null
+++ b/RTC.h
@@ -0,0 +1,64 @@
+#ifndef _RTC_H_
+#define _RTC_H_
+
+//#define _nop_()   udelay(1);
+#define somenop   {_nop_();_nop_();_nop_();_nop_();_nop_();}
+
+
+
+
+extern unsigned char bySta;
+
+
+
+
+// 假设 BM8563 的 I2C 地址
+#define BM8563_ADDR 0xA2  
+
+// 假设 BM8563 寄存器地址
+#define BM8563_CSR2 0x01
+#define BM8563_SEC 0x02
+#define BM8563_MIN 0x03
+#define BM8563_HOUR 0x04
+#define BM8563_DAY 0x05
+#define BM8563_WEEK 0x06
+#define BM8563_MONTH 0x07
+#define BM8563_YEAR 0x08
+#define BM8563_ALARM_MIN 0x09
+#define BM8563_ALARM_HOUR 0x0A
+#define BM8563_ALARM_DAY 0x0B
+#define BM8563_ALARM_WEEK 0x0C
+#define BM8563_CONTROL 0x0E  // 定时器控制寄存器
+#define BM8563_STATUS 0x01
+#define BM8563_TIMER_VALUE 0x0F  // 定时器计数寄存器
+
+
+void BM8563_InitTime();
+void BM8563_Set4HourCountdown();
+unsigned char BM8563_ReadReg(unsigned char reg);
+void BM8563_WriteReg(unsigned char reg, unsigned char rdata);
+void BM8563_Set4HourAlarm(); 
+
+void iic_start(void);
+void iic_stop(void);
+void iic_ack(bit ackbit);
+void iic_sendbyte(unsigned char byt);
+void wrbyte_24c02(unsigned int add,unsigned char dat);
+
+bit iic_waitack(void);
+unsigned char i2c_recbyte(void);
+unsigned char rdbyte_24c02(unsigned int add);
+unsigned char wrEE_CRC_Bak(unsigned char add,unsigned char *eeData,unsigned char len,unsigned char addbak);
+unsigned char rdEE_CRC_Bak(unsigned char add,unsigned char *eeData,unsigned char len,unsigned char addbak);
+
+
+
+
+
+
+
+
+
+
+
+#endif
\ No newline at end of file
diff --git a/SHARED_INT.C b/SHARED_INT.C
new file mode 100644
index 0000000..bd52036
--- /dev/null
+++ b/SHARED_INT.C
@@ -0,0 +1,223 @@
+//****************************************************************************
+// @Module        Shared Interrupt Routines
+// @Filename      SHARED_INT.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description   This file contains the Shared interrupt routines.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:29
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "SHARED_INT.H"
+
+// USER CODE BEGIN (SHARED_INT_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+
+// USER CODE BEGIN (SHARED_INT_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void SHINT_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function initializes the shared interrupts. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SHINT_Init,1)
+
+// USER CODE END
+
+void SHINT_vInit(void)
+{
+  // USER CODE BEGIN (SHINT_Init,2)
+
+  // USER CODE END
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of the Shared  Interrupts:
+  ///  -----------------------------------------------------------------------
+  ///  - Timer 2 Interrupt is Selected
+
+
+  IEN0         |=  0x20;         // load interrupt enable register 0
+
+
+
+  IEN1         |=  0x00;         // load interrupt enable register 1
+
+
+  // USER CODE BEGIN (SHINT_Init,3)
+
+  // USER CODE END
+
+
+} //  End of function SHINT_vInit
+
+
+//****************************************************************************
+// @Function      void SHINT_viXINTR5Isr(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the service routine for the shared interrupt node 
+//                XINTR5. XINTR5 ISR Node is shared by Timer 2, UART 
+//                Fractional Divider(BRG Interrupt),MultiCAN Node 0 and LIN. 
+//                Depending on the selected module interrupt it is called.
+//                T2 - Depending on the selected operating mode it is called 
+//                when TF2 is set by an overflow or underflow of the timer 2 
+//                register or when EXF2 is set by a negative transition on 
+//                T2EX.
+//                UART - It is called after the BRG timer overflows and sets 
+//                the NDOV bit.
+//                CAN -  It is called for the  Service Request Node 0 of the 
+//                MultiCAN module.
+//                Please note that you have to add application specific code 
+//                to this function.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   none
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+//   You have two choices for interrupt type select in Project Settings Page 
+//   under Global Settings Section.
+//   If you select CHOICE 1 then ISR will be generated with push and pop.
+//   If you select CHOICE 2 then ISR will be generated without push and pop.
+//   Default choice is CHOICE 2.
+//   Current selection is CHOICE 2 
+
+// USER CODE BEGIN (SHINT_XINTR5Isr,1)
+
+// USER CODE END
+
+void SHINT_viXINTR5Isr(void) interrupt XINTR5INT
+{
+  // USER CODE BEGIN (SHINT_XINTR5Isr,2)
+
+  // USER CODE END
+
+  SFR_PAGE(_su0, SST0);          // switch to page 0
+
+  //   Timer 2 interrupt handling section...
+
+  if (TF2)
+  {
+    //   a timer 2 overflow has occured
+
+    TF2 = 0;
+
+    // USER CODE BEGIN (SHINT_XINTR5Isr,3)
+RTCProcess();
+    // USER CODE END
+
+  }
+
+  // USER CODE BEGIN (SHINT_XINTR5Isr,7)
+
+  // USER CODE END
+
+  SFR_PAGE(_su0, RST0);          // restore the old SCU page
+} //  End of function SHINT_viXINTR5Isr
+
+
+// USER CODE BEGIN (SHARED_INT_General,10)
+
+// USER CODE END
+
+
diff --git a/SHARED_INT.H b/SHARED_INT.H
new file mode 100644
index 0000000..0d0f103
--- /dev/null
+++ b/SHARED_INT.H
@@ -0,0 +1,122 @@
+//****************************************************************************
+// @Module        Shared Interrupt Routines
+// @Filename      SHARED_INT.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description   This is the include header file for shared interrupts.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:29
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _SHARED_INT_H_
+#define _SHARED_INT_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,4)
+
+// USER CODE END
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void SHINT_vInit(void);
+
+
+// USER CODE BEGIN (SHARED_INT_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SHARED_INT_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+#define  XINTR5INT   5
+
+#define  XINTR8INT   8
+// USER CODE BEGIN (SHARED_INT_Header,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+
+
+
+
+
+#include "MAIN.H"
+
+
+// USER CODE BEGIN (SHARED_INT_Header,10)
+
+// USER CODE END
+
+
+#endif  // ifndef _SHARED_INT_H_
diff --git a/SSC.C b/SSC.C
new file mode 100644
index 0000000..d73aaef
--- /dev/null
+++ b/SSC.C
@@ -0,0 +1,264 @@
+//****************************************************************************
+// @Module        High Speed Synchronous Serial Interface(SSC)
+// @Filename      SSC.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.9
+//
+// @Description:  This file contains functions that use the SSC module.
+//
+//----------------------------------------------------------------------------
+// @Date          2013-11-11 12:29:47
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (SSC_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void SSC_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the SSC function 
+//                library. It is assumed that the SFRs used by this library 
+//                are in their reset state. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2013-11-11
+//
+//****************************************************************************
+
+// USER CODE BEGIN (Init,1)
+
+// USER CODE END
+
+void SSC_vInit(void)
+{
+  // USER CODE BEGIN (Init,2)
+
+  // USER CODE END
+
+  ///  - Port Selection
+  SSC_PISEL     =  0x01;         // load SSC Port Input Select Register to 
+                                 // Port A
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of the used SSC Port Pins:
+  ///  -----------------------------------------------------------------------
+  ///  Pin SCLK (P0.3) is selected for SCLK ouput 
+  ///  Pin MTSR_1 (P0.4) is selected for Master Transmit Output 
+  ///  Pin MRST_1 (P0.5) is selected for Master Receive Input 
+
+  SFR_PAGE(_pp2, noSST);         // switch to page 2 without saving
+  P0_ALTSEL0      |= 0x18;              //  set AltSel0 
+  P0_ALTSEL1      &= ~(ubyte)0x18;      //  set AltSel1
+
+  SFR_PAGE(_pp0, noSST);         // switch to page 0 without saving
+  P0_DIR          |= 0x18;      //  set OutPut Direction
+
+
+  ///  Pin SCLK (P1.2) is Not selected for SCLK ouput 
+  ///  Pin MTSR_0 (P1.3) is Not selected for Master Transmit Output 
+  ///  Pin MRST_0 (P1.4) Not is selected for Master Receive Input 
+
+  SSC_CONH_P &= ~(ubyte)0x80;           //  enable access to control bits
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of the SSC Baud Rate Generator:
+  ///  -----------------------------------------------------------------------
+  ///  - required baud rate = 2000.000 kbaud
+  ///  - real baud rate     = 2000.000 kbaud
+  ///  - deviation          = 0.000 %
+
+  SSC_BRH       =  0x00;         // load SSC baud rate time reload register 
+                                 // high
+  SSC_BRL       =  0x05;         // load SSC baud rate time reload register 
+                                 // low
+
+  ///  -----------------------------------------------------------------------
+  ///  Configuration of the SSC Operation Mode:
+  ///  -----------------------------------------------------------------------
+  ///  - this device is configured as SSC master
+  ///  - transfer data width is 8 bit
+  ///  - transfer/receive MSB first
+  ///  - shift transmit data on the leading clock edge, latch on trailing edge
+  ///  - idle clock line is low, leading clock edge is low-to-high transition
+  ///  - ignore receive error
+  ///  - ignore phase error
+
+
+  SSC_CONH_P    =  0x40;         // load SSC control register
+
+  SSC_CONL_P    =  0x17;         // load SSC control register
+
+  SSC_CONH_P |= 0x80;           //  disable access to control bits
+
+  ///  - SSC interrupt is disabled
+
+  // USER CODE BEGIN (Init,3)
+
+  // USER CODE END
+
+} //  End of function SSC_vInit
+
+
+//****************************************************************************
+// @Function      void SSC_vSendData(ubyte Data) 
+//
+//----------------------------------------------------------------------------
+// @Description   The master device can initiate the first data transfer by 
+//                writing the transmit data into transmit buffer. This value 
+//                is copied into the shift register (which is assumed to be 
+//                empty at this time), and the selected first bit of the 
+//                transmit data is placed onto the MTSR line on the next 
+//                clock from the baud rate generator. 
+//                A slave device immediately outputs the selected first bit 
+//                (MSB or LSB of the transfer data) at pin MRST, when the 
+//                contents of the transmit buffer are copied into the slave's 
+//                shift register. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    Data: 
+//                Data to be send
+//
+//----------------------------------------------------------------------------
+// @Date          2013-11-11
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SendData,1)
+
+// USER CODE END
+
+void SSC_vSendData(ubyte Data)
+{
+  SSC_TBL  = Data;   //  load transmit buffer register
+
+} //  End of function SSC_vSendData
+
+
+//****************************************************************************
+// @Function      ubyte SSC_vGetData(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function returns the contents of the receive buffer. 
+//                When the receive interrupt request flag is set this implies 
+//                that data is available for reading in the receive buffer. 
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   Received data
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2013-11-11
+//
+//****************************************************************************
+
+// USER CODE BEGIN (GetData,1)
+
+// USER CODE END
+
+ubyte SSC_vGetData(void)
+{
+  return(SSC_RBL);     // return receive buffer register
+
+} //  End of function SSC_vGetData
+
+
+
+// USER CODE BEGIN (SSC_General,10)
+
+// USER CODE END
+
diff --git a/SSC.H b/SSC.H
new file mode 100644
index 0000000..6d112f6
--- /dev/null
+++ b/SSC.H
@@ -0,0 +1,107 @@
+//****************************************************************************
+// @Module        High Speed Synchronous Serial Interface(SSC)
+// @Filename      SSC.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.9
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the SSC module.
+//
+//----------------------------------------------------------------------------
+// @Date          2013-11-11 12:29:47
+//
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _SSC_H_
+#define _SSC_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (SSC_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void SSC_vInit(void);
+void SSC_vSendData(ubyte Data);
+ubyte SSC_vGetData(void);
+
+
+// USER CODE BEGIN (SSC_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+
+// USER CODE BEGIN (SSC_Header,9)
+
+// USER CODE END
+
+
+#endif  // ifndef _SSC_H_
diff --git a/START_XC.a51 b/START_XC.a51
new file mode 100644
index 0000000..d914b3b
--- /dev/null
+++ b/START_XC.a51
@@ -0,0 +1,505 @@
+$NOMOD51
+;------------------------------------------------------------------------------
+;  This file is part of the C51 Compiler package
+;  Startup Code for the Infineon XC8xx devices 
+;  Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc.
+;  Version 20100601
+;  -------- Revision ---------
+;  - Previous version 20100405
+;  - Added XC864 with option for LIN_BSL parameters
+;  - Renamed NDIV_XC866 to NDIV_XC86x
+;
+;  *** <<< Use Configuration Wizard in Context Menu >>> ***
+;------------------------------------------------------------------------------
+;  STARTUP.A51:  This code is executed after processor reset.
+;
+;  To translate this file use A51 with the following invocation:
+;
+;     A51 STARTUP.A51
+;
+;  To link the modified STARTUP.OBJ file to your application use the following
+;  Lx51 invocation:
+;
+;     Lx51 your object file list, STARTUP.OBJ  controls
+;
+;------------------------------------------------------------------------------
+;
+; Use off-chip XTAL
+; XC8xx series runs by default from on-chip osciallator.
+; optionally you may use a off-chip XTAL
+;
+XTAL          EQU     1   ; set to 0 On-chip oscillator/ not used for XC82x devices
+;
+; Device = " XC82x "
+XC82x_CHIP    EQU   0     ;applicable to XC83x
+;---------------------------------------------------------------------
+;resulting in fsys = 80MHz for XC866/XC864 and fsys = 96MHz for XC88x unless otherwise mentioned
+;
+; Device = " XC866 "
+XC866_CHIP    EQU   0
+; Device = " XC864 "
+XC864_CHIP    EQU   0
+;
+;  PLL N-Divider
+;  PLL N-Divider must result in fsys = 80MHz
+; <0=>  N=14
+; <1=>  N=15
+; <2=>  N=16 (10 MHz XTAL)
+; <3=>  N=17
+; <4=>  N=18
+; <5=>  N=19
+; <6=>  N=20 (8 MHz XTAL)
+; <7=>  N=21
+; <8=>  N=24
+; <9=>  N=28
+; <10=> N=30
+; <11=> N=32 (5 MHz XTAL)
+; <12=> N=40
+; <13=> N=42
+; <14=> N=45
+; <15=> N=50
+;
+NDIV_XC86x    EQU      2   ; default 2
+;    
+
+;---------------------------------------------------------------------
+; Device = " XC88x "
+XC88x_CHIP    EQU   1
+;
+;  PLL N-Divider for *NON-SAL* device fsys = 96 MHz
+; <0=>  N=10
+; <1=>  N=12 
+; <2=>  N=13
+; <3=>  N=14
+; <4=>  N=15
+; <5=>  N=16 (12 MHz XTAL)
+; <6=>  N=17
+; <7=>  N=18
+; <8=>  N=19
+; <9=>  N=20 (9.6 MHz On-Chip XTAL)
+; <10=> N=24 (8 MHz XTAL)
+; <11=> N=30
+; <12=> N=32 (6 MHz XTAL)
+; <13=> N=36
+; <14=> N=40
+; <15=> N=48 (4 MHz XTAL)
+;
+;  PLL N-Divider for *SAL* device -> fsys = 80 MHz
+; <0=>  N=10 
+; <1=>  N=12
+; <2=>  N=13
+; <3=>  N=14
+; <4=>  N=15
+; <5=>  N=16 (10 MHz On-Chip XTAL)
+; <6=>  N=17
+; <7=>  N=18
+; <8=>  N=19
+; <9=>  N=20 (8 MHz XTAL)
+; <10=> N=24 
+; <11=> N=30
+; <12=> N=32 (5 MHz XTAL)
+; <13=> N=36
+; <14=> N=40 (4 MHz XTAL)
+; <15=> N=48
+;
+
+NDIV_XC88x    EQU       10   ; default 10
+;
+
+;---------------------------------------------------------------------
+; Device = " XC87x "
+XC878_CHIP_16FF    EQU       0
+XC878_CHIP_13FF    EQU       0
+XC874_CHIP_16FF    EQU       0
+XC874_CHIP_13FF    EQU       0
+
+;4 MHz 
+NDIV_XC87x_PLL_CON    EQU       0x18
+NDIV_XC87x_PLL_CON1   EQU       0x20
+NR_XC87x              EQU       0x00
+OD_XC87x              EQU       0x00
+
+;6 MHz 
+;NDIV_XC87x_PLL_CON    EQU       0x18
+;NDIV_XC87x_PLL_CON1   EQU       0x20
+;NR_XC87x              EQU       0x01
+;OD_XC87x              EQU       0x00
+
+;8 MHz default
+;NDIV_XC87x_PLL_CON    EQU       0x18
+;NDIV_XC87x_PLL_CON1   EQU       0x20
+;NR_XC87x              EQU       0x02
+;OD_XC87x              EQU       0x00
+
+;
+
+;
+;------------------------------------------------------------------------------
+;
+;  User-defined  Power-On Initialization of Memory
+;
+;  With the following EQU statements the initialization of memory
+;  at processor reset can be defined:
+;
+; IDATA memory length <0x0-0x100>
+; Note: The absolute start-address of IDATA memory is always 0
+;       The IDATA space overlaps physically the DATA and BIT areas.
+IDATALEN        EQU     0x100
+;
+;  XDATA memory start address <0x0-0xFFFF> 
+;  absolute start-address of XDATA memory
+XDATASTART      EQU     0xF000     
+;
+;  XDATA memory length <0x0-0xFFFF> 
+;  length of XDATA memory in bytes.
+IF (XC82x_CHIP)
+  XDATALEN      EQU     0x100 
+ELSEIF (XC866_CHIP || XC864_CHIP)
+  XDATALEN      EQU     0x200
+ELSEIF (XC88x_CHIP)
+  XDATALEN      EQU     0x600 
+ELSEIF (XC878_CHIP_16FF || XC878_CHIP_13FF)
+  XDATALEN      EQU     0xC00
+ELSEIF (XC874_CHIP_16FF || XC874_CHIP_13FF)
+  XDATALEN      EQU     0xC00
+
+ENDIF
+  
+;
+;  PDATA memory start address <0x0-0xFFFF> 
+;  absolute start-address of PDATA memory
+PDATASTART      EQU     0xF000
+;
+;  PDATA memory length <0x0-0xFF> 
+;  length of PDATA memory in bytes.
+PDATALEN        EQU     0
+;
+; 
+;------------------------------------------------------------------------------
+;
+;  Reentrant Stack Initilization
+;
+;  The following EQU statements define the stack pointer for reentrant
+;  functions and initialized it:
+;
+; Stack Space for reentrant functions in the SMALL model.
+;  Activate reentrant Stack (SMALL model)
+IBPSTACK        EQU     0       ; set to 1 if small reentrant is used.
+;  top of stack <0x0-0xFF> 
+;  set top of stack to highest location+1 
+IBPSTACKTOP     EQU     0xFF +1     ; default 0FFH+1  
+; 
+;
+;  Stack Space for reentrant functions in the LARGE model.      
+;  Activate reentrant Stack (LARGE model)
+XBPSTACK        EQU     0       ; set to 1 if large reentrant is used.
+;  top of stack <0x0-0xFFFF> 
+;  set top of stack to highest location+1.
+XBPSTACKTOP     EQU     0xFFFF +1   ; default 0FFFFH+1 
+; 
+;
+;  Stack Space for reentrant functions in the COMPACT model.    
+;  Activate reentrant Stack (COMPACT model)
+PBPSTACK        EQU     0       ; set to 1 if compact reentrant is used.
+;
+;  top of stack <0x0-0xFF> 
+;  set top of stack to highest location+1.
+PBPSTACKTOP     EQU     0xFF +1     ; default 0FFH+1  
+; 
+; 
+;------------------------------------------------------------------------------
+;
+;  Set Memory Page for Using the Compact Model with 64 KByte xdata RAM
+;
+;  Define the xdata page used for pdata variables. 
+;  PPAGE must conform with the PPAGE set in the linker invocation.
+;
+; Enable pdata memory page initalization
+PPAGEENABLE     EQU     0       ; set to 1 if pdata object are used.
+;
+;  PPAGE number <0x0-0xFF> 
+;  uppermost 256-byte address of the page used for pdata variables.
+PPAGE           EQU     0xF0
+;
+; 
+;------------------------------------------------------------------------------
+;
+;  Parameters for LIN Boostrap Loader (XC864 only)
+;  When these values are not defined, an XC864 device stays in 
+;  LIN-BSL mode and does not start the user application 
+;
+; Enable LIN BSL parameter initialization
+LIN_BSL         EQU     1           ; set to 1 if LIN BSL parameters should be generated in flash table
+;
+;  NAC: No. Activity Count <0x00-0xFF> 
+;  specifies the delay (n * 5ms) before jumping to user mode.
+;  0x01:  0 ms delay. Jump to User Mode immediately
+;  0x02:  5 ms delay before jumping to User Mode
+;  0x03: 10 ms delay before jumping to User Mode
+;  0x04 - 0x0C: 15 - 55 ms delay before jumping to User Mode
+;  0x0D - 0xFF, 0x00: Enter LIN BSL Mode (Invalid NAC)
+LIN_NAC         EQU     0x01
+;
+;  NAD: Node Address for Diagnostic <0x00-0xFF> 
+;  specifies the address of the active slave node.
+LIN_NAD         EQU     0x01
+;
+; 
+;------------------------------------------------------------------------------
+
+;Check the chip selection
+IF ((XC82x_CHIP + XC866_CHIP + XC864_CHIP + XC88x_CHIP + XC878_CHIP_16FF + XC878_CHIP_13FF + XC874_CHIP_16FF + XC874_CHIP_13FF) > 1)
+      __ERROR__  "Please select only one chip!"
+ELSEIF ((XC82x_CHIP + XC866_CHIP + XC864_CHIP + XC88x_CHIP + XC878_CHIP_16FF + XC878_CHIP_13FF + XC874_CHIP_16FF + XC874_CHIP_13FF) == 0)
+      __ERROR__  "Please select a chip!"
+ENDIF
+
+IF (XTAL <> 0)
+    IF (XC866_CHIP <> 0 || XC864_CHIP <> 0)
+       NDIV EQU NDIV_XC86x
+    ELSEIF (XC88x_CHIP <> 0)
+       NDIV EQU NDIV_XC88x
+    ELSEIF (XC878_CHIP_16FF <> 0 || XC878_CHIP_13FF <> 0)
+       ;nothing   
+    ELSEIF (XC874_CHIP_16FF <> 0 || XC874_CHIP_13FF <> 0)
+       ;nothing
+    ELSEIF (XC82x_CHIP <> 0)
+       ;nothing
+    ELSE
+      __WARNING__  "Default NDIV selection is XC866"
+      NDIV EQU NDIV_XC86x  ;Default
+    ENDIF
+ ENDIF                   ;End of XTAL selection
+
+; Standard SFR Symbols 
+ACC     DATA    0E0H
+B       DATA    0F0H
+SP      DATA    81H
+DPL     DATA    82H
+DPH     DATA    83H
+
+; XC8xx specific SFR Symbols used in STARTUP code
+IF (XC82x_CHIP == 0)
+; Take note of different SFR addresses for XC82x. Currently not used.
+        sfr  SCU_PAGE = 0xBF
+        sfr  PLL_CON  = 0xB7
+        sfr  PLL_CON1 = 0xEA;//SCU,RMAP=0,Page=1
+        sfr  CMCON    = 0xBA
+        sfr  OSC_CON  = 0xB6
+        sfr  PASSWD   = 0xBB
+        sfr  XADDRH   = 0xB3
+        sfr  MEX3     = 0x96
+ENDIF
+
+IF(XC874_CHIP_13FF == 1 || XC874_CHIP_16FF == 1)
+        sfr  PORT_PAGE = 0xB2
+        sfr  P3_PUDEN  = 0xB1
+        sfr  P4_PUDEN  = 0xC9
+ENDIF
+
+                NAME    ?C_STARTUP
+
+?C_C51STARTUP   SEGMENT   CODE
+?STACK          SEGMENT   IDATA
+
+                RSEG    ?STACK
+                DS      1
+
+                EXTRN CODE (?C_START)
+                PUBLIC  ?C_STARTUP
+
+                CSEG    AT      0x2000
+?C_STARTUP:     LJMP    STARTUP1
+
+                RSEG    ?C_C51STARTUP
+
+STARTUP1:
+
+IF (XTAL <> 0)       
+                    ; switch to external XTAL
+        IF(XC878_CHIP_16FF <> 0 || XC878_CHIP_13FF <> 0 || XC874_CHIP_16FF <> 0 || XC874_CHIP_13FF <> 0)
+                MOV     SCU_PAGE,#1;
+                MOV     PASSWD, #11000000B     ;Disable Bit-Protection
+                ANL     OSC_CON, #~(0x01 << 2) ;OSCSS = 0
+                ORL     OSC_CON, #(0x01 << 6)  ;Bypass PLL Output ( PLLBYP = 1 )
+                ORL     OSC_CON, #(0x01 << 5)  ;Set PLL Power Down Mode ( PLLPD = 1)
+                ANL     OSC_CON, #~(0x01 << 3) ;XPD = 0, XTAL not powered down
+                          
+                          
+        WAIT_XTAL_STABLE:          ; delay necssary for external clock to stablise
+                MOV     R2,#0x1E   ; wait about 1.5 ms ( varies with oscillator freq )
+        LOOP:
+                MOV     R3,#0x64   
+                DJNZ    R3, $
+                DJNZ    R2, LOOP
+     OSC_WDT:
+                ORL     OSC_CON, #(0x01 << 1)  ;Restart external oscillator watchdog
+                MOV     R0,#0x41               ;Wait for 65 cycles
+                DJNZ    R0, $
+             ;user may want to add an error counter for oscillator detection
+        CHECK_EXTOSCR:
+                MOV     A, OSC_CON
+                JNB     ACC.0, OSC_WDT        
+                ORL     OSC_CON, #(0x01 << 2)  ;Select external oscillator 
+                MOV     PLL_CON,  #NDIV_XC87x_PLL_CON      ; NDIV value 
+                MOV     PLL_CON1, #NDIV_XC87x_PLL_CON1     ; NDIV Value 
+                MOV     A, #NR_XC87x                       ; PDIV Value 
+                ORL     PLL_CON1, A                                     
+                MOV     A, #OD_XC87x                       ; KDIV Value 
+                ORL     CMCON,    A                                     
+                ANL     OSC_CON, #~(0x01 << 5)  ;Change to PLL Normal Mode ( PLLPD = 0) 
+                ORL     OSC_CON, #(0x01 << 7)   ;Restart the PLL watchdog ( PLLRDRES = 1) 
+
+             ;user may want to add an error counter for PLL lock detection
+        PLLNOTRUN:
+                MOV     A, PLL_CON
+                JNB     ACC.1, PLLNOTRUN           ;PLL_Run Status
+
+        PLLNOTLOCKED:
+                MOV     A, PLL_CON
+                JNB     ACC.0, PLLNOTLOCKED        ;PLL_Lock Status
+
+                ANL     OSC_CON, #~(0x01 << 6)     ;Disable bypass PLL output 
+                MOV     PASSWD, #11000011B         ;Enable Bit-Protection
+                MOV     SCU_PAGE,#0
+
+ELSEIF(XC866_CHIP <> 0 || XC864_CHIP <> 0 || XC88x_CHIP <> 0)
+                MOV     SCU_PAGE,#1
+                ORL     PLL_CON, #0x08  ; VCOBYP = 1
+                ORL     PLL_CON, #0x04  ; OSCDISC = 1   _ _ _ NDIV, VCOBYP, OSCDISC, RESLD, LOCK
+                ANL     OSC_CON, #0xF7  ; XPD = 0       power xtal
+                ORL     OSC_CON, #0x04  ; OSCSS = 1     0, 0, 0, OSCPD, XPD, OSCSS, ORDRES, OSCR
+                ;all calculations are based on no wait state
+                MOV     R1,#0
+DelayXTAL0:
+                MOV     R0,#10         ; delay necssary for external clock to stablise (amplitude >= 0.4 * VDDC - refer to product data sheet)
+DelayXTAL:            ; delay time should be adjusted according to different external osciallators
+                DJNZ    R1,$
+                DJNZ    R0,DelayXTAL
+                
+                ; redetection of osc
+OSCR_NOTSET:
+                MOV     R0, #86
+                ORL     OSC_CON, #0x02  ; ORDRES = 1    ;restart oscillator run detection
+                ;assume no wait state, K = 2, 
+                ;Apollo requires to wait for 256 clock cycles -> 2048 vco cycles
+                ;Elektra requires to wait for 342 clock cycles -> 2048 vco cycles
+                ;djnz = 4 cc
+                DJNZ    R0, $
+                MOV     A,OSC_CON
+                JNB     ACC.0, OSCR_NOTSET
+                
+                ;reprogram the NDIV factor to required value
+                ;ORL     PLL_CON, #0x08      ; VCOBYP = 1 to change N-Divider
+                MOV     PASSWD,  #0x98      ; open access to writing protected bit
+                ANL     PLL_CON, #0x0F
+                ORL     PLL_CON, #NDIV*16
+                ANL     PLL_CON, #0xFB      ; OSCDISC = 0, reconnect oscillator to the PLL
+                
+                ;PLL lock detection
+                ORL     PLL_CON, #0x02     ; detect PLL lock
+                MOV     R0, #100           ; LOCK flag should be set within 200us, user need to adapt accordingly
+                                           ; assume a 10MHz XTAL for XC866/XC864 device
+                                           ; device is in prescaler mode, k = 2 therefore fsys = 5MHz
+                                           ; ## 1cclk = 1/(5MHz/3) = 600 ns
+                                           ; DJNZ requires 4 x 600ns = 2.4 us therefore 100 DJNZ -> 240us
+                                           ; for XC88x, the factor 3 (##) is changed to 4 then the calculated value is 
+                                           ; 320 us based on a 10MHz XTAL
+WAIT_LOCK:
+                DJNZ    R0, $
+                MOV     A, PLL_CON
+                JNB     ACC.0, OSCR_NOTSET
+                ; reconnect to PLL
+                ANL     PLL_CON, #0xF7   ; VCOBYP = 0
+                MOV     SCU_PAGE,#0     
+        ENDIF
+ENDIF
+
+IF IDATALEN <> 0
+                MOV     R0,#IDATALEN - 1
+                CLR     A
+IDATALOOP:      MOV     @R0,A
+                DJNZ    R0,IDATALOOP
+ENDIF
+
+IF (XC878_CHIP_16FF <> 0 || XC874_CHIP_16FF <> 0)
+                MOV     MEX3, #0x1F
+ENDIF
+
+IF (XC874_CHIP_13FF <> 0 || XC874_CHIP_16FF <> 0)
+                MOV     PORT_PAGE, #0x01
+                ORL     P3_PUDEN, #0x80
+                ORL     P4_PUDEN, #0xF0
+                MOV     PORT_PAGE, #0x00
+ENDIF
+
+
+
+IF XDATALEN <> 0
+                MOV     DPTR,#XDATASTART
+                MOV     R7,#LOW (XDATALEN)
+  IF (LOW (XDATALEN)) <> 0
+                MOV     R6,#(HIGH (XDATALEN)) +1
+  ELSE
+                MOV     R6,#HIGH (XDATALEN)
+  ENDIF
+                CLR     A
+XDATALOOP:      MOVX    @DPTR,A
+                INC     DPTR
+                DJNZ    R7,XDATALOOP
+                DJNZ    R6,XDATALOOP
+ENDIF
+
+IF PPAGEENABLE <> 0
+                MOV     SCU_PAGE,#3 
+                MOV     XADDRH,#PPAGE
+                MOV     SCU_PAGE,#0 
+ENDIF
+
+IF PDATALEN <> 0
+                MOV     R0,#LOW (PDATASTART)
+                MOV     R7,#LOW (PDATALEN)
+                CLR     A
+PDATALOOP:      MOVX    @R0,A
+                INC     R0
+                DJNZ    R7,PDATALOOP
+ENDIF
+
+IF IBPSTACK <> 0
+EXTRN DATA (?C_IBP)
+
+                MOV     ?C_IBP,#LOW IBPSTACKTOP
+ENDIF
+
+IF XBPSTACK <> 0
+EXTRN DATA (?C_XBP)
+
+                MOV     ?C_XBP,#HIGH XBPSTACKTOP
+                MOV     ?C_XBP+1,#LOW XBPSTACKTOP
+ENDIF
+
+IF PBPSTACK <> 0
+EXTRN DATA (?C_PBP)
+                MOV     ?C_PBP,#LOW PBPSTACKTOP
+ENDIF
+
+                MOV     SP,#?STACK-1
+
+                LJMP    ?C_START
+
+; Overwrite ?C?DPSEL address for XC866 Device
+PUBLIC ?C?DPSEL
+?C?DPSEL DATA 0A2H   ; DPSEL address for Mentor M8051EW
+
+IF XC864_CHIP <> 0
+  ; Optional ROM-table for XC864 LIN-BSL
+  IF LIN_BSL <> 0
+                  CSEG    AT      0FFCH
+                  DB      LIN_NAC
+                  DB      NOT(LIN_NAC)
+                  DB      LIN_NAD
+                  DB      NOT(LIN_NAD)
+  ENDIF
+ENDIF
+
+                END
diff --git a/SwDriver.C b/SwDriver.C
new file mode 100644
index 0000000..2fda42b
--- /dev/null
+++ b/SwDriver.C
@@ -0,0 +1,496 @@
+#include "MAIN.h"
+
+
+
+//*****************************************************************************
+//数据结构
+//*****************************************************************************
+//每个33993的开关命令状态，由于掉电或者干扰导致33993内部复位时，可以用该状态恢复。
+struct StaMc33993CmdSet
+{
+	unsigned char CmdSetting        ;
+	unsigned char CmdInt_Sp         ;
+	unsigned int  CmdInt_Sg         ;
+	unsigned char CmdMetallic_Sp    ;
+	unsigned int  CmdMetallic_Sg    ;
+	unsigned char CmdWetCurr_Sp  	  ;
+	unsigned int  CmdWetCurr_Sg     ;
+	unsigned char CmdTriState_Sp    ;
+	unsigned int  CmdTriState_Sg    ;
+	unsigned char CmdAnalog			    ;
+};
+//33993的开关状态，可以采用字节访问，也可以按位访问//XC886不一样，修改
+union ByteBitAccess
+{
+	struct
+	{
+		ubyte SoMc33993Byte1;
+		ubyte SoMc33993Byte0;
+		ubyte SoMc33993Byte3;
+		ubyte SoMc33993Byte2;
+	}ByteData;
+	struct
+	{
+		unsigned int  FlgSg0    : 1;
+		unsigned int  FlgSg1    : 1;
+		unsigned int  FlgSg2    : 1;
+		unsigned int  FlgSg3    : 1;
+		unsigned int  FlgSg4    : 1;
+		unsigned int  FlgSg5    : 1;
+		unsigned int  FlgSg6    : 1;
+		unsigned int  FlgSg7    : 1;
+		unsigned int  FlgSg8    : 1;
+		unsigned int  FlgSg9    : 1;
+		unsigned int  FlgSg10   : 1;
+		unsigned int  FlgSg11   : 1;
+		unsigned int  FlgSg12   : 1;
+		unsigned int  FlgSg13   : 1;
+		unsigned int  FlgSp0    : 1;
+		unsigned int  FlgSp1    : 1;
+		unsigned int  FlgSp2    : 1;
+		unsigned int  FlgSp3    : 1;
+		unsigned int  FlgSp4    : 1;
+		unsigned int  FlgSp5    : 1;
+		unsigned int  FlgSp6    : 1;
+		unsigned int  FlgSp7    : 1;
+		unsigned int  FlgInt    : 1;
+		unsigned int  FlgThem   : 1;
+		unsigned int            : 8;
+	}BitData;
+};
+//33993的开关状态，可以采用字节访问，也可以按位访问
+union WordByteBitAccess
+{
+	uword StaSg;
+	struct
+	{
+		ubyte StaSgH;
+		ubyte StaSgL;
+	}ByteData;
+	struct
+	{
+		unsigned int 	FlgSg0_FlgSp0         : 1;
+		unsigned int  FlgSg1_FlgSp1         : 1;
+		unsigned int  FlgSg2_FlgSp2         : 1;
+		unsigned int  FlgSg3_FlgSp3         : 1;
+		unsigned int  FlgSg4_FlgSp4         : 1;
+		unsigned int  FlgSg5_FlgSp5         : 1;
+		unsigned int  FlgSg6_FlgSp6         : 1;
+		unsigned int  FlgSg7_FlgSp7         : 1;
+		unsigned int  FlgSg8		            : 1;
+		unsigned int  FlgSg9                : 1;
+		unsigned int  FlgSg10               : 1;
+		unsigned int  FlgSg11               : 1;
+		unsigned int  FlgSg12               : 1;
+		unsigned int  FlgSg13               : 1;
+		unsigned int                        : 1;
+		unsigned int                        : 1;
+	}BitData;
+};
+//*****************************************************************************
+//全局变量
+//*****************************************************************************
+static struct StaMc33993CmdSet PntSta[2] = {0};
+//*****************************************************************************
+//本文件全局函数声明
+//*****************************************************************************
+bit Mc33993StaRcvOneBit(ubyte NumMc,ubyte Sp0ToSg13);
+ubyte Mc33993CmdSendOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13,bit Status);
+void InitMc33993Sec(void);
+void ToggleOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13);
+
+union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL);
+
+
+
+////****************************************************************************
+//// @Function     ubyte Mc33993AnalogChSel(struct StaMc33993CmdSet *PntSta,ubyte NumMc,ubyte Mode,ubyte Channal)
+////
+////----------------------------------------------------------------------------
+//// @Description   模拟通道选择、模式选择
+////
+////----------------------------------------------------------------------------
+//// @Returnvalue   通道切换成功返回1
+////								Mode,高阻，2mA，16mA
+////----------------------------------------------------------------------------
+//// @Parameters    None
+////
+////----------------------------------------------------------------------------
+//// @Date          2008-12-2
+////
+////****************************************************************************
+//ubyte Mc33993AnalogChSel(ubyte NumMc,ubyte Mode,ubyte Channal)
+//{
+//	union WordByteBitAccess  RcvSoMc33993;
+////----------------------------------------------------------------------------
+//	if(NumMc > (NumChipSw-1))NumMc = (NumChipSw-1); //多余NumChipSw片
+//	RcvSoMc33993.ByteData.StaSgL = 0;
+//	RcvSoMc33993.ByteData.StaSgL = (RcvSoMc33993.ByteData.StaSgL | Channal);
+//	switch(Mode)
+//	{
+//    case DF_AN_HIMP:
+//				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;//该两位决定选择哪种模式
+//				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+//				 break;
+//    case DF_AN_2MA:
+//				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;
+//				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 1;
+//				 break;
+//    case DF_AN_16MA:
+//				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 1;
+//				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+//				 break;
+//    default:
+//				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;
+//				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+//	}
+//	Mc33993CmdSend(NumMc,DF_CMDANALOG,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+//
+//	(*(PntSta+NumMc)).CmdAnalog = RcvSoMc33993.ByteData.StaSgL;//保存命令状态
+//
+//	return 1;
+//}
+
+
+//---------------------------------------------------
+
+//*****************************************************************************
+//函数
+//*****************************************************************************
+
+////****************************************************************************
+//// @Function      void SwStaSample(UnSwSample *ptmp,ubyte NumSampleChip)
+////
+////----------------------------------------------------------------------------
+//// @Description   采集33993的开关信号。
+////
+////----------------------------------------------------------------------------
+//// @Returnvalue   None
+////
+////----------------------------------------------------------------------------
+//// @Parameters    ptmp，存放数据结构体指针，NumSampleChip，33993芯片数量
+////
+////----------------------------------------------------------------------------
+//// @Date          2008-12-2
+////
+////****************************************************************************
+void SwStaSample(UnSwSample *ptmp)
+{
+  union ByteBitAccess  *pStaSwIn;
+	uword i,k;
+//----初始化------------------------------------------------------------------------
+  InitMc33993Sec();//一个大循环必须调用一次，这样就算12V掉电或33993复位，马上可以恢复。
+//初始化用作采集的IO
+	for(i=0;i>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP0 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP0 ,Gnd);break;
+				case 1 :if(((((*tmpUn).ArrData.Arr[i][1])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP1 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP1 ,Gnd);break;
+				case 2 :if(((((*tmpUn).ArrData.Arr[i][1])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP2 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP2 ,Gnd);break;
+				case 3 :if(((((*tmpUn).ArrData.Arr[i][1])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP3 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP3 ,Gnd);break;
+				case 4 :if(((((*tmpUn).ArrData.Arr[i][1])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP4 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP4 ,Gnd);break;
+				case 5 :if(((((*tmpUn).ArrData.Arr[i][1])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP5 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP5 ,Gnd);break;
+				case 6 :if(((((*tmpUn).ArrData.Arr[i][1])>>6 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP6 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP6 ,Gnd);break;
+				case 7 :if(((((*tmpUn).ArrData.Arr[i][1])>>7 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP7 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP7 ,Gnd);break;
+				case 8 :if(((((*tmpUn).ArrData.Arr[i][0])>>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG0 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG0 ,Gnd);break;
+				case 9 :if(((((*tmpUn).ArrData.Arr[i][0])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG1 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG1 ,Gnd);break;
+				case 10:if(((((*tmpUn).ArrData.Arr[i][0])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG2 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG2 ,Gnd);break;
+				case 11:if(((((*tmpUn).ArrData.Arr[i][0])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG3 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG3 ,Gnd);break;
+				case 12:if(((((*tmpUn).ArrData.Arr[i][0])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG4 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG4 ,Gnd);break;
+				case 13:if(((((*tmpUn).ArrData.Arr[i][0])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG5 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG5 ,Gnd);break;
+				case 14:if(((((*tmpUn).ArrData.Arr[i][0])>>6 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG6 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG6 ,Gnd);break;
+				case 15:if(((((*tmpUn).ArrData.Arr[i][0])>>7 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG7 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG7 ,Gnd);break;
+				case 16:if(((((*tmpUn).ArrData.Arr[i][3])>>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG8 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG8 ,Gnd);break;
+				case 17:if(((((*tmpUn).ArrData.Arr[i][3])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG9 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG9 ,Gnd);break;
+				case 18:if(((((*tmpUn).ArrData.Arr[i][3])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG10,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG10,Gnd);break;
+				case 19:if(((((*tmpUn).ArrData.Arr[i][3])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG11,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG11,Gnd);break;
+				case 20:if(((((*tmpUn).ArrData.Arr[i][3])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG12,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG12,Gnd);break;
+				case 21:if(((((*tmpUn).ArrData.Arr[i][3])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG13,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG13,Gnd);break;
+				default:;
+			}
+		}
+	}
+}
+
+
+
+//****************************************************************************
+// @Function      void InitMc33993Sec(struct StaMc33993CmdSet *PntSta)
+//
+//----------------------------------------------------------------------------
+// @Description   所有MC33993二次初始化，也就是每次操作33993时都用之前的状态初始化
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    MC33993状态存储结构体指针PntSta
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+void InitMc33993Sec(void)
+{
+  ubyte i;
+  for(i=DF_SwInNum;i>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdInt_Sg)&0x00ff));   //1，关闭中断
+		Mc33993CmdSend(i,DF_CMDMETALLIC_SP,  0,                                                  (*(PntSta+i)).CmdMetallic_Sp);    //0，2mA
+		Mc33993CmdSend(i,DF_CMDMETALLIC_SG,  (ubyte)((((*(PntSta+i)).CmdMetallic_Sg)>>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdMetallic_Sg)&0x00ff));    //0，2mA
+		Mc33993CmdSend(i,DF_CMDANALOG,       0,                                                  (*(PntSta+i)).CmdAnalog);         //0，不选择任何通道
+		Mc33993CmdSend(i,DF_CMDWETCURR_SP,   0,                                                  (*(PntSta+i)).CmdWetCurr_Sp);     //0，湿电流定时器关闭
+		Mc33993CmdSend(i,DF_CMDWETCURR_SG,   (ubyte)((((*(PntSta+i)).CmdWetCurr_Sg) >>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdWetCurr_Sg)&0x00ff));     //0，湿电流定时器关闭
+		Mc33993CmdSend(i,DF_CMDTRISTATE_SP,  0,                                                  (*(PntSta+i)).CmdTriState_Sp);    //0，禁止三态
+		Mc33993CmdSend(i,DF_CMDTRISTATE_SG,  (ubyte)((((*(PntSta+i)).CmdTriState_Sg)>>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdTriState_Sg)&0x00ff));    //0，使能三态
+  }
+}
+
+//****************************************************************************
+// @Function      void InitMc33993(struct StaMc33993CmdSet *PntSta)
+//
+//----------------------------------------------------------------------------
+// @Description   所有MC33993在单片机上电时初始化
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+void InitSW(void)
+{
+  ubyte i;
+  for(i=0;i (NumChipSw-1))NumMc = (NumChipSw-1);
+	switch(CmdBit)
+	{
+//DF_CMDTRISTATE_SP
+		case DF_CMDTRISTATE_SP:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdTriState_Sp;
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdTriState_Sp = RcvSoMc33993.ByteData.StaSgL;
+			break;
+//DF_CMDTRISTATE_SG
+		case DF_CMDTRISTATE_SG:
+		  RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdTriState_Sg;
+			     if(Sp0ToSg13 == DF_FLGSG13) RcvSoMc33993.BitData.FlgSg13       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG12) RcvSoMc33993.BitData.FlgSg12       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG11) RcvSoMc33993.BitData.FlgSg11       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG10) RcvSoMc33993.BitData.FlgSg10       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG9 ) RcvSoMc33993.BitData.FlgSg9        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG8 ) RcvSoMc33993.BitData.FlgSg8        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG7 ) RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG6 ) RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG5 ) RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG4 ) RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG3 ) RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG2 ) RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG1 ) RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG0 ) RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdTriState_Sg = RcvSoMc33993.StaSg;
+			break;
+		default:;
+	}
+	return 1;
+}
+
+//片选产生
+//多余20片需要增加
+void ChangeCsMc33993(ubyte NumMc,bit HorL)
+{
+  switch(NumMc)
+  {
+    case Mc33993_0 :  CS_SwChip_0  = HorL;break;
+    case Mc33993_1 :  CS_SwChip_1  = HorL;break;
+    default:;
+  }
+}
+//****************************************************************************
+// @Function     ubyte Mc33993DataSendRcv(ubyte Data)
+//
+//----------------------------------------------------------------------------
+// @Description   发送数据,返回接收数据
+//                此函数与CPU平台相关,不同CPU需要修改。
+//                此函数适用于XC2765，SSC采用查询方式
+//----------------------------------------------------------------------------
+// @Returnvalue   返回接收的数据
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2011-3-4 10:28:27
+//
+//****************************************************************************
+ubyte Mc33993DataSendRcv(ubyte Data)
+{
+	uword i;
+	SSC_vSendData(Data);	
+	for(i=0;(i<6000)&&(!(IRCON1&0x02));i++);
+  IRCON1 &= 0xFD;
+	for(i=0;(i<6000)&&(!(IRCON1&0x04));i++);
+  IRCON1 &= 0xFB;
+  return((ubyte)(SSC_vGetData()));
+}
+
+//****************************************************************************
+// @Function     union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL)
+//
+//----------------------------------------------------------------------------
+// @Description   发送33993的操作命令,返回开关状态
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   返回接收的3个字节的开关状态
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2011-3-4 10:36:27
+//
+//****************************************************************************
+union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL)
+{
+  union ByteBitAccess  RcvSoMc,*Pnt;
+	union WordByteBitAccess  RcvSoMc33993W;
+//	uword i;
+//----------------------------------------------------------------------------
+	RcvSoMc33993W.ByteData.StaSgH = SetBitH;
+	RcvSoMc33993W.ByteData.StaSgL = SetBitL;
+	switch(CmdBit)//保存命令状态
+	{
+		case DF_CMDSETTING    :(*(PntSta+NumMc)).CmdSetting     = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDINT_SP     :(*(PntSta+NumMc)).CmdInt_Sp      = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDINT_SG     :(*(PntSta+NumMc)).CmdInt_Sg      = RcvSoMc33993W.StaSg;break;
+		case DF_CMDMETALLIC_SP:(*(PntSta+NumMc)).CmdMetallic_Sp = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDMETALLIC_SG:(*(PntSta+NumMc)).CmdMetallic_Sg = RcvSoMc33993W.StaSg;break;
+		case DF_CMDANALOG     :(*(PntSta+NumMc)).CmdAnalog      = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDWETCURR_SP :(*(PntSta+NumMc)).CmdWetCurr_Sp  = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDWETCURR_SG :(*(PntSta+NumMc)).CmdWetCurr_Sg  = RcvSoMc33993W.StaSg;break;
+		case DF_CMDTRISTATE_SP:(*(PntSta+NumMc)).CmdTriState_Sp = RcvSoMc33993W.ByteData.StaSgL;break;
+		case DF_CMDTRISTATE_SG:(*(PntSta+NumMc)).CmdTriState_Sg = RcvSoMc33993W.StaSg;break;
+		default:;
+	}
+	
+	
+	if(NumMc > (NumChipSw-1))NumMc = (NumChipSw-1);
+  ChangeCsMc33993(NumMc,0);
+//----------------------------
+  _nop_();
+	_nop_();
+	_nop_();
+	_nop_();
+	
+//-------------------------------
+
+  RcvSoMc.ByteData.SoMc33993Byte2 = Mc33993DataSendRcv(CmdBit);
+
+  RcvSoMc.ByteData.SoMc33993Byte1 = Mc33993DataSendRcv(SetBitH);
+
+  RcvSoMc.ByteData.SoMc33993Byte0 = Mc33993DataSendRcv(SetBitL);
+
+  ChangeCsMc33993(NumMc,1);
+//----------------------------
+  _nop_();
+	_nop_();
+	_nop_();
+	_nop_();
+//-------------------------------
+  Pnt = &RcvSoMc;
+  return (Pnt);
+}
diff --git a/SwDriver.C.bak b/SwDriver.C.bak
new file mode 100644
index 0000000..d6ac035
--- /dev/null
+++ b/SwDriver.C.bak
@@ -0,0 +1,893 @@
+#include "MAIN.h"
+
+//*****************************************************************************
+//宏定义
+//*****************************************************************************
+//多余20片需要增加
+#define Mc33993_0 			0
+#define Mc33993_1		 		1
+#define Mc33993_2		 		2
+#define Mc33993_3		 		3
+#define Mc33993_4		 		4
+#define Mc33993_5		 		5
+#define Mc33993_6		 		6
+#define Mc33993_7 			7
+#define Mc33993_8 			8
+#define Mc33993_9 			9
+#define Mc33993_10			10
+#define Mc33993_11			11
+#define Mc33993_12			12
+#define Mc33993_13			13
+#define Mc33993_14			14
+#define Mc33993_15			15
+#define Mc33993_16			16
+#define Mc33993_17			17
+#define Mc33993_18			18
+#define Mc33993_19			19
+#define Mc33993_20			20
+
+
+#define D24V		 		0
+#define Gnd		 	   	1
+
+#define TriOff		 	0
+#define TriOn		 	  1
+
+#define WetCur2mA		0
+#define WetCur16mA	1
+
+#define SwToGnd		 	0
+#define SwToPwr		 	1
+
+#define ALLTRI		 	0xff
+#define ALLD24V		 	0x0
+
+#define DF_CMDSWSTATUS 			0x00
+#define DF_CMDSETTING 			0x01
+#define DF_CMDINT_SP 				0x02
+#define DF_CMDINT_SG 				0x03
+#define DF_CMDMETALLIC_SP 	0x04
+#define DF_CMDMETALLIC_SG 	0x05
+#define DF_CMDANALOG 				0x06
+#define DF_CMDWETCURR_SP 		0x07
+#define DF_CMDWETCURR_SG 		0x08
+#define DF_CMDTRISTATE_SP 	0x09
+#define DF_CMDTRISTATE_SG 	0x0A
+#define DF_CMDCALIBRATION 	0x0B
+#define DF_CMDSLEEP				 	0x0C
+#define DF_CMDRESET				 	0x7F
+
+
+#define  DF_FLGTHEM					10
+#define  DF_FLGINT          11
+#define  DF_FLGSP7          12
+#define  DF_FLGSP6          13
+#define  DF_FLGSP5          14
+#define  DF_FLGSP4          15
+#define  DF_FLGSP3          16
+#define  DF_FLGSP2          17
+#define  DF_FLGSP1          18
+#define  DF_FLGSP0          19
+#define  DF_FLGSG13         20
+#define  DF_FLGSG12         21
+#define  DF_FLGSG11         22
+#define  DF_FLGSG10         23
+#define  DF_FLGSG9          24
+#define  DF_FLGSG8          25
+#define  DF_FLGSG7          26
+#define  DF_FLGSG6          27
+#define  DF_FLGSG5          28
+#define  DF_FLGSG4          29
+#define  DF_FLGSG3          30
+#define  DF_FLGSG2          31
+#define  DF_FLGSG1          32
+#define  DF_FLGSG0          33
+
+//Analog
+#define  DF_AN_HIMP          1
+#define  DF_AN_2MA           2
+#define  DF_AN_16MA          3
+
+#define  DF_CH_SG0           1
+#define  DF_CH_SG1           2
+#define  DF_CH_SG2           3
+#define  DF_CH_SG3           4
+#define  DF_CH_SG4           5
+#define  DF_CH_SG5           6
+#define  DF_CH_SG6           7
+#define  DF_CH_SG7           8
+#define  DF_CH_SG8           9
+#define  DF_CH_SG9           10
+#define  DF_CH_SG10          11
+#define  DF_CH_SG11          12
+#define  DF_CH_SG12          13
+#define  DF_CH_SG13          14
+#define  DF_CH_SP0           15
+#define  DF_CH_SP1           16
+#define  DF_CH_SP2           17
+#define  DF_CH_SP3           18
+#define  DF_CH_SP4           19
+#define  DF_CH_SP5           20
+#define  DF_CH_SP6           21
+#define  DF_CH_SP7           22
+
+//*****************************************************************************
+//数据结构
+//*****************************************************************************
+//每个33993的开关命令状态，由于掉电或者干扰导致33993内部复位时，可以用该状态恢复。
+struct StaMc33993CmdSet
+{
+	unsigned char CmdSetting        ;
+	unsigned char CmdInt_Sp         ;
+	unsigned int  CmdInt_Sg         ;
+	unsigned char CmdMetallic_Sp    ;
+	unsigned int  CmdMetallic_Sg    ;
+	unsigned char CmdWetCurr_Sp  	  ;
+	unsigned int  CmdWetCurr_Sg     ;
+	unsigned char CmdTriState_Sp    ;
+	unsigned int  CmdTriState_Sg    ;
+	unsigned char CmdAnalog			    ;
+};
+//33993的开关状态，可以采用字节访问，也可以按位访问//XC886不一样，修改
+union ByteBitAccess
+{
+	struct
+	{
+		ubyte SoMc33993Byte1;
+		ubyte SoMc33993Byte0;
+		ubyte SoMc33993Byte3;
+		ubyte SoMc33993Byte2;
+	}ByteData;
+	struct
+	{
+		unsigned int  FlgSg0    : 1;
+		unsigned int  FlgSg1    : 1;
+		unsigned int  FlgSg2    : 1;
+		unsigned int  FlgSg3    : 1;
+		unsigned int  FlgSg4    : 1;
+		unsigned int  FlgSg5    : 1;
+		unsigned int  FlgSg6    : 1;
+		unsigned int  FlgSg7    : 1;
+		unsigned int  FlgSg8    : 1;
+		unsigned int  FlgSg9    : 1;
+		unsigned int  FlgSg10   : 1;
+		unsigned int  FlgSg11   : 1;
+		unsigned int  FlgSg12   : 1;
+		unsigned int  FlgSg13   : 1;
+		unsigned int  FlgSp0    : 1;
+		unsigned int  FlgSp1    : 1;
+		unsigned int  FlgSp2    : 1;
+		unsigned int  FlgSp3    : 1;
+		unsigned int  FlgSp4    : 1;
+		unsigned int  FlgSp5    : 1;
+		unsigned int  FlgSp6    : 1;
+		unsigned int  FlgSp7    : 1;
+		unsigned int  FlgInt    : 1;
+		unsigned int  FlgThem   : 1;
+		unsigned int            : 8;
+	}BitData;
+};
+//33993的开关状态，可以采用字节访问，也可以按位访问
+union WordByteBitAccess
+{
+	uword StaSg;
+	struct
+	{
+		ubyte StaSgH;
+		ubyte StaSgL;
+	}ByteData;
+	struct
+	{
+		unsigned int 	FlgSg0_FlgSp0         : 1;
+		unsigned int  FlgSg1_FlgSp1         : 1;
+		unsigned int  FlgSg2_FlgSp2         : 1;
+		unsigned int  FlgSg3_FlgSp3         : 1;
+		unsigned int  FlgSg4_FlgSp4         : 1;
+		unsigned int  FlgSg5_FlgSp5         : 1;
+		unsigned int  FlgSg6_FlgSp6         : 1;
+		unsigned int  FlgSg7_FlgSp7         : 1;
+		unsigned int  FlgSg8		            : 1;
+		unsigned int  FlgSg9                : 1;
+		unsigned int  FlgSg10               : 1;
+		unsigned int  FlgSg11               : 1;
+		unsigned int  FlgSg12               : 1;
+		unsigned int  FlgSg13               : 1;
+		unsigned int                        : 1;
+		unsigned int                        : 1;
+	}BitData;
+};
+//*****************************************************************************
+//全局变量
+//*****************************************************************************
+static struct StaMc33993CmdSet PntSta[2] = {0};
+//*****************************************************************************
+//本文件全局函数声明
+//*****************************************************************************
+bit Mc33993StaRcvOneBit(ubyte NumMc,ubyte Sp0ToSg13);
+ubyte Mc33993CmdSendOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13,bit Status);
+void InitMc33993Sec(void);
+void ToggleOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13);
+ubyte Mc33993AnalogChSel(ubyte NumMc,ubyte Mode,ubyte Channal);
+union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL);
+
+
+
+
+
+
+//---------------------------------------------------
+
+//*****************************************************************************
+//函数
+//*****************************************************************************
+void Swtest2(void)
+{
+ 		ulong  i,j;
+	
+	UnSwOut_1.BitData.S21 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S22 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S23 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S24 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S25 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S26 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S27 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S28 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S29 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S30 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S31 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S32 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S33 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S34 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S35 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S36 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S37 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S38 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S39 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S40 = 1;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+
+	UnSwOut_1.BitData.S21 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S22 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S23 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S24 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S25 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S26 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S27 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S28 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S29 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S30 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S31 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S32 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S33 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S34 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S35 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S36 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S37 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S38 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S39 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}	
+	UnSwOut_1.BitData.S40 = 0;LedLight(&UnSwOut_1);	for(j=0;j<200;j++){for(i=0;i<133;i++);}
+
+
+}
+
+//****************************************************************************
+// @Function      void SwStaSample(UnSwSample *ptmp,ubyte NumSampleChip)
+//
+//----------------------------------------------------------------------------
+// @Description   采集33993的开关信号。
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    ptmp，存放数据结构体指针，NumSampleChip，33993芯片数量
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+void SwStaSample(UnSwSample *ptmp)
+{
+  union ByteBitAccess  *pStaSwIn;
+	uword i,k;
+//----初始化------------------------------------------------------------------------
+  InitMc33993Sec();//一个大循环必须调用一次，这样就算12V掉电或33993复位，马上可以恢复。
+//初始化用作采集的IO
+	for(i=0;i>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP0 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP0 ,Gnd);break;
+				case 1 :if(((((*tmpUn).ArrData.Arr[i][1])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP1 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP1 ,Gnd);break;
+				case 2 :if(((((*tmpUn).ArrData.Arr[i][1])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP2 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP2 ,Gnd);break;
+				case 3 :if(((((*tmpUn).ArrData.Arr[i][1])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP3 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP3 ,Gnd);break;
+				case 4 :if(((((*tmpUn).ArrData.Arr[i][1])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP4 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP4 ,Gnd);break;
+				case 5 :if(((((*tmpUn).ArrData.Arr[i][1])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP5 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP5 ,Gnd);break;
+				case 6 :if(((((*tmpUn).ArrData.Arr[i][1])>>6 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP6 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP6 ,Gnd);break;
+				case 7 :if(((((*tmpUn).ArrData.Arr[i][1])>>7 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP7 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SP,DF_FLGSP7 ,Gnd);break;
+				case 8 :if(((((*tmpUn).ArrData.Arr[i][0])>>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG0 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG0 ,Gnd);break;
+				case 9 :if(((((*tmpUn).ArrData.Arr[i][0])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG1 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG1 ,Gnd);break;
+				case 10:if(((((*tmpUn).ArrData.Arr[i][0])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG2 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG2 ,Gnd);break;
+				case 11:if(((((*tmpUn).ArrData.Arr[i][0])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG3 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG3 ,Gnd);break;
+				case 12:if(((((*tmpUn).ArrData.Arr[i][0])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG4 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG4 ,Gnd);break;
+				case 13:if(((((*tmpUn).ArrData.Arr[i][0])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG5 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG5 ,Gnd);break;
+				case 14:if(((((*tmpUn).ArrData.Arr[i][0])>>6 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG6 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG6 ,Gnd);break;
+				case 15:if(((((*tmpUn).ArrData.Arr[i][0])>>7 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG7 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG7 ,Gnd);break;
+				case 16:if(((((*tmpUn).ArrData.Arr[i][3])>>0 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG8 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG8 ,Gnd);break;
+				case 17:if(((((*tmpUn).ArrData.Arr[i][3])>>1 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG9 ,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG9 ,Gnd);break;
+				case 18:if(((((*tmpUn).ArrData.Arr[i][3])>>2 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG10,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG10,Gnd);break;
+				case 19:if(((((*tmpUn).ArrData.Arr[i][3])>>3 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG11,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG11,Gnd);break;
+				case 20:if(((((*tmpUn).ArrData.Arr[i][3])>>4 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG12,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG12,Gnd);break;
+				case 21:if(((((*tmpUn).ArrData.Arr[i][3])>>5 )&0x01) == 1)Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG13,D24V);else Mc33993CmdSendOneBit(i+DF_SwInNum,DF_CMDTRISTATE_SG,DF_FLGSG13,Gnd);break;
+				default:;
+			}
+		}
+	}
+}
+
+
+//****************************************************************************
+// @Function      void ToggleOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13)
+//
+//----------------------------------------------------------------------------
+// @Description   取反给定芯片的给定位，需要提供命令位
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    MC33993状态存储结构体指针PntSta
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+// void ToggleOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13)
+// {
+//   union WordByteBitAccess  RcvSoMc33993;
+// 	bit status;
+
+// 	if(CmdBit == DF_CMDTRISTATE_SG)
+// 	{
+// 		RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdTriState_Sg;
+
+// 		switch(Sp0ToSg13)
+// 		{
+// 			case 	DF_FLGSG13:	status = RcvSoMc33993.BitData.FlgSg13      ;break;
+// 			case 	DF_FLGSG12:	status = RcvSoMc33993.BitData.FlgSg12      ;break;
+// 			case 	DF_FLGSG11:	status = RcvSoMc33993.BitData.FlgSg11      ;break;
+// 			case 	DF_FLGSG10:	status = RcvSoMc33993.BitData.FlgSg10      ;break;
+// 			case 	DF_FLGSG9 :	status = RcvSoMc33993.BitData.FlgSg9       ;break;
+// 			case 	DF_FLGSG8 :	status = RcvSoMc33993.BitData.FlgSg8       ;break;
+// 			case 	DF_FLGSG7 :	status = RcvSoMc33993.BitData.FlgSg7_FlgSp7;break;
+// 			case 	DF_FLGSG6 :	status = RcvSoMc33993.BitData.FlgSg6_FlgSp6;break;
+// 			case 	DF_FLGSG5 :	status = RcvSoMc33993.BitData.FlgSg5_FlgSp5;break;
+// 			case 	DF_FLGSG4 :	status = RcvSoMc33993.BitData.FlgSg4_FlgSp4;break;
+// 			case 	DF_FLGSG3 :	status = RcvSoMc33993.BitData.FlgSg3_FlgSp3;break;
+// 			case 	DF_FLGSG2 :	status = RcvSoMc33993.BitData.FlgSg2_FlgSp2;break;
+// 			case 	DF_FLGSG1 :	status = RcvSoMc33993.BitData.FlgSg1_FlgSp1;break;
+// 			case 	DF_FLGSG0 :	status = RcvSoMc33993.BitData.FlgSg0_FlgSp0;break;
+// 			default:;
+// 		}
+// 		if(status)Mc33993CmdSendOneBit(Mc33993_1,DF_CMDTRISTATE_SG,Sp0ToSg13,D24V);
+// 		else			Mc33993CmdSendOneBit(Mc33993_1,DF_CMDTRISTATE_SG,Sp0ToSg13,Gnd);
+// 	}
+// 	else if(CmdBit == DF_CMDTRISTATE_SP)
+// 	{
+// 		RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdTriState_Sp;
+
+// 		switch(Sp0ToSg13)
+// 		{
+// 			case 	DF_FLGSG7 :	status = RcvSoMc33993.BitData.FlgSg7_FlgSp7;break;
+// 			case 	DF_FLGSG6 :	status = RcvSoMc33993.BitData.FlgSg6_FlgSp6;break;
+// 			case 	DF_FLGSG5 :	status = RcvSoMc33993.BitData.FlgSg5_FlgSp5;break;
+// 			case 	DF_FLGSG4 :	status = RcvSoMc33993.BitData.FlgSg4_FlgSp4;break;
+// 			case 	DF_FLGSG3 :	status = RcvSoMc33993.BitData.FlgSg3_FlgSp3;break;
+// 			case 	DF_FLGSG2 :	status = RcvSoMc33993.BitData.FlgSg2_FlgSp2;break;
+// 			case 	DF_FLGSG1 :	status = RcvSoMc33993.BitData.FlgSg1_FlgSp1;break;
+// 			case 	DF_FLGSG0 :	status = RcvSoMc33993.BitData.FlgSg0_FlgSp0;break;
+// 			default:;
+// 		}
+// 		if(status)Mc33993CmdSendOneBit(Mc33993_1,DF_CMDTRISTATE_SP,Sp0ToSg13,D24V);
+// 		else			Mc33993CmdSendOneBit(Mc33993_1,DF_CMDTRISTATE_SP,Sp0ToSg13,Gnd);
+// 	}
+// }
+
+//****************************************************************************
+// @Function      void InitMc33993Sec(struct StaMc33993CmdSet *PntSta)
+//
+//----------------------------------------------------------------------------
+// @Description   所有MC33993二次初始化，也就是每次操作33993时都用之前的状态初始化
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    MC33993状态存储结构体指针PntSta
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+void InitMc33993Sec(void)
+{
+  ubyte i;
+  for(i=0;i>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdInt_Sg)&0x00ff));   //1，关闭中断
+		Mc33993CmdSend(i,DF_CMDMETALLIC_SP,  0,                                                  (*(PntSta+i)).CmdMetallic_Sp);    //0，2mA
+		Mc33993CmdSend(i,DF_CMDMETALLIC_SG,  (ubyte)((((*(PntSta+i)).CmdMetallic_Sg)>>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdMetallic_Sg)&0x00ff));    //0，2mA
+		Mc33993CmdSend(i,DF_CMDANALOG,       0,                                                  (*(PntSta+i)).CmdAnalog);         //0，不选择任何通道
+		Mc33993CmdSend(i,DF_CMDWETCURR_SP,   0,                                                  (*(PntSta+i)).CmdWetCurr_Sp);     //0，湿电流定时器关闭
+		Mc33993CmdSend(i,DF_CMDWETCURR_SG,   (ubyte)((((*(PntSta+i)).CmdWetCurr_Sg) >>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdWetCurr_Sg)&0x00ff));     //0，湿电流定时器关闭
+		Mc33993CmdSend(i,DF_CMDTRISTATE_SP,  0,                                                  (*(PntSta+i)).CmdTriState_Sp);    //0，禁止三态
+		Mc33993CmdSend(i,DF_CMDTRISTATE_SG,  (ubyte)((((*(PntSta+i)).CmdTriState_Sg)>>8)&0x00ff),(ubyte)(((*(PntSta+i)).CmdTriState_Sg)&0x00ff));    //0，使能三态
+  }
+}
+
+//****************************************************************************
+// @Function      void InitMc33993(struct StaMc33993CmdSet *PntSta)
+//
+//----------------------------------------------------------------------------
+// @Description   所有MC33993在单片机上电时初始化
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+void InitSW(void)
+{
+  ubyte i;
+  for(i=0;i (NumChipSw-1))NumMc = (NumChipSw-1); //多余NumChipSw片
+// 	RcvSoMc33993.ByteData.StaSgL = 0;
+// 	RcvSoMc33993.ByteData.StaSgL = (RcvSoMc33993.ByteData.StaSgL | Channal);
+// 	switch(Mode)
+// 	{
+//     case DF_AN_HIMP:
+// 				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;//该两位决定选择哪种模式
+// 				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+// 				 break;
+//     case DF_AN_2MA:
+// 				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;
+// 				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 1;
+// 				 break;
+//     case DF_AN_16MA:
+// 				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 1;
+// 				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+// 				 break;
+//     default:
+// 				 RcvSoMc33993.BitData.FlgSg6_FlgSp6 = 0;
+// 				 RcvSoMc33993.BitData.FlgSg5_FlgSp5 = 0;
+// 	}
+// 	Mc33993CmdSend(NumMc,DF_CMDANALOG,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+
+// 	(*(PntSta+NumMc)).CmdAnalog = RcvSoMc33993.ByteData.StaSgL;//保存命令状态
+
+// 	return 1;
+// }
+
+//****************************************************************************
+// @Function     bit Mc33993StaRcvOneBit(ubyte NumMc,ubyte Sp0ToSg13)
+//
+//----------------------------------------------------------------------------
+// @Description   读取任意一位的开关状态
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   返回位状态
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+// bit Mc33993StaRcvOneBit(ubyte NumMc,ubyte Sp0ToSg13)
+// {
+// 	union ByteBitAccess  *Pnt;
+// 	bit  BitRcvOneBit;
+// //-----------------------------------------------------------------------------
+// 	if(NumMc > (NumChipSw-1))NumMc = (NumChipSw-1);
+// 	Pnt = Mc33993CmdSend(NumMc,DF_CMDSWSTATUS,0xff,0xff);
+
+// 			 if(Sp0ToSg13 == DF_FLGTHEM)BitRcvOneBit = (*Pnt).BitData.FlgThem;
+// 	else if(Sp0ToSg13 == DF_FLGINT )BitRcvOneBit = (*Pnt).BitData.FlgInt;
+// 	else if(Sp0ToSg13 == DF_FLGSP7 )BitRcvOneBit = (*Pnt).BitData.FlgSp7;
+// 	else if(Sp0ToSg13 == DF_FLGSP6 )BitRcvOneBit = (*Pnt).BitData.FlgSp6;
+// 	else if(Sp0ToSg13 == DF_FLGSP5 )BitRcvOneBit = (*Pnt).BitData.FlgSp5;
+// 	else if(Sp0ToSg13 == DF_FLGSP4 )BitRcvOneBit = (*Pnt).BitData.FlgSp4;
+// 	else if(Sp0ToSg13 == DF_FLGSP3 )BitRcvOneBit = (*Pnt).BitData.FlgSp3;
+// 	else if(Sp0ToSg13 == DF_FLGSP2 )BitRcvOneBit = (*Pnt).BitData.FlgSp2;
+// 	else if(Sp0ToSg13 == DF_FLGSP1 )BitRcvOneBit = (*Pnt).BitData.FlgSp1;
+// 	else if(Sp0ToSg13 == DF_FLGSP0 )BitRcvOneBit = (*Pnt).BitData.FlgSp0;
+// 	else if(Sp0ToSg13 == DF_FLGSG13)BitRcvOneBit = (*Pnt).BitData.FlgSg13;
+// 	else if(Sp0ToSg13 == DF_FLGSG12)BitRcvOneBit = (*Pnt).BitData.FlgSg12;
+// 	else if(Sp0ToSg13 == DF_FLGSG11)BitRcvOneBit = (*Pnt).BitData.FlgSg11;
+// 	else if(Sp0ToSg13 == DF_FLGSG10)BitRcvOneBit = (*Pnt).BitData.FlgSg10;
+// 	else if(Sp0ToSg13 == DF_FLGSG9 )BitRcvOneBit = (*Pnt).BitData.FlgSg9;
+// 	else if(Sp0ToSg13 == DF_FLGSG8 )BitRcvOneBit = (*Pnt).BitData.FlgSg8;
+// 	else if(Sp0ToSg13 == DF_FLGSG7 )BitRcvOneBit = (*Pnt).BitData.FlgSg7;
+// 	else if(Sp0ToSg13 == DF_FLGSG6 )BitRcvOneBit = (*Pnt).BitData.FlgSg6;
+// 	else if(Sp0ToSg13 == DF_FLGSG5 )BitRcvOneBit = (*Pnt).BitData.FlgSg5;
+// 	else if(Sp0ToSg13 == DF_FLGSG4 )BitRcvOneBit = (*Pnt).BitData.FlgSg4;
+// 	else if(Sp0ToSg13 == DF_FLGSG3 )BitRcvOneBit = (*Pnt).BitData.FlgSg3;
+// 	else if(Sp0ToSg13 == DF_FLGSG2 )BitRcvOneBit = (*Pnt).BitData.FlgSg2;
+// 	else if(Sp0ToSg13 == DF_FLGSG1 )BitRcvOneBit = (*Pnt).BitData.FlgSg1;
+// 	else if(Sp0ToSg13 == DF_FLGSG0 )BitRcvOneBit = (*Pnt).BitData.FlgSg0;
+// 	else ;
+// 	return 	BitRcvOneBit;
+// }
+
+//****************************************************************************
+// @Function     ubyte Mc33993CmdSendOneBit(struct StaMc33993CmdSet *PntSta,ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13,bit Status)
+//
+//----------------------------------------------------------------------------
+// @Description   写MC33993任意位，调用Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   成功返回1
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2008-12-2
+//
+//****************************************************************************
+ubyte Mc33993CmdSendOneBit(ubyte NumMc,ubyte CmdBit,ubyte Sp0ToSg13,bit Status)
+{
+	union WordByteBitAccess  RcvSoMc33993;
+//----------------------------------------------------------------------------
+	if(NumMc > (NumChipSw-1))NumMc = (NumChipSw-1);
+	switch(CmdBit)
+	{
+//DF_CMDSETTING
+		case DF_CMDSETTING:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdSetting; //用之前的状态填充RcvSoMc33993低字节,也就是不改变其它位的状态
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;//更新需要改变的位
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+			//(*(PntSta+NumMc)).CmdSetting = RcvSoMc33993.ByteData.StaSgL;//更新后的状态保存
+		  break;
+//DF_CMDINT_SP
+		case DF_CMDINT_SP:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdInt_Sp;
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+			//(*(PntSta+NumMc)).CmdInt_Sp = RcvSoMc33993.ByteData.StaSgL;
+			break;
+//DF_CMDMETALLIC_SP
+		case DF_CMDMETALLIC_SP:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdMetallic_Sp;
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+			//(*(PntSta+NumMc)).CmdMetallic_Sp = RcvSoMc33993.ByteData.StaSgL;
+			break;
+//DF_CMDWETCURR_SP
+		case DF_CMDWETCURR_SP:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdWetCurr_Sp;
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+			//(*(PntSta+NumMc)).CmdWetCurr_Sp = RcvSoMc33993.ByteData.StaSgL;
+			break;
+//DF_CMDTRISTATE_SP
+		case DF_CMDTRISTATE_SP:
+			RcvSoMc33993.ByteData.StaSgL = (*(PntSta+NumMc)).CmdTriState_Sp;
+			     if(Sp0ToSg13 == DF_FLGSP7)RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP6)RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP5)RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP4)RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP3)RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP2)RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP1)RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSP0)RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdTriState_Sp = RcvSoMc33993.ByteData.StaSgL;
+			break;
+//DF_CMDINT_SG
+		case DF_CMDINT_SG:
+		  RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdInt_Sg;
+			     if(Sp0ToSg13 == DF_FLGSG13) RcvSoMc33993.BitData.FlgSg13       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG12) RcvSoMc33993.BitData.FlgSg12       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG11) RcvSoMc33993.BitData.FlgSg11       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG10) RcvSoMc33993.BitData.FlgSg10       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG9 ) RcvSoMc33993.BitData.FlgSg9        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG8 ) RcvSoMc33993.BitData.FlgSg8        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG7 ) RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG6 ) RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG5 ) RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG4 ) RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG3 ) RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG2 ) RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG1 ) RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG0 ) RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdInt_Sg = RcvSoMc33993.StaSg;
+			break;
+//DF_CMDMETALLIC_SG
+		case DF_CMDMETALLIC_SG:
+		  RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdMetallic_Sg;
+			     if(Sp0ToSg13 == DF_FLGSG13) RcvSoMc33993.BitData.FlgSg13       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG12) RcvSoMc33993.BitData.FlgSg12       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG11) RcvSoMc33993.BitData.FlgSg11       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG10) RcvSoMc33993.BitData.FlgSg10       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG9 ) RcvSoMc33993.BitData.FlgSg9        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG8 ) RcvSoMc33993.BitData.FlgSg8        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG7 ) RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG6 ) RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG5 ) RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG4 ) RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG3 ) RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG2 ) RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG1 ) RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG0 ) RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdMetallic_Sg = RcvSoMc33993.StaSg;
+			break;
+//DF_CMDWETCURR_SG
+		case DF_CMDWETCURR_SG:
+		  RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdWetCurr_Sg;
+			     if(Sp0ToSg13 == DF_FLGSG13) RcvSoMc33993.BitData.FlgSg13       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG12) RcvSoMc33993.BitData.FlgSg12       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG11) RcvSoMc33993.BitData.FlgSg11       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG10) RcvSoMc33993.BitData.FlgSg10       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG9 ) RcvSoMc33993.BitData.FlgSg9        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG8 ) RcvSoMc33993.BitData.FlgSg8        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG7 ) RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG6 ) RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG5 ) RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG4 ) RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG3 ) RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG2 ) RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG1 ) RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG0 ) RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdWetCurr_Sg = RcvSoMc33993.StaSg;
+			break;
+//DF_CMDTRISTATE_SG
+		case DF_CMDTRISTATE_SG:
+		  RcvSoMc33993.StaSg = (*(PntSta+NumMc)).CmdTriState_Sg;
+			     if(Sp0ToSg13 == DF_FLGSG13) RcvSoMc33993.BitData.FlgSg13       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG12) RcvSoMc33993.BitData.FlgSg12       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG11) RcvSoMc33993.BitData.FlgSg11       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG10) RcvSoMc33993.BitData.FlgSg10       = Status;
+			else if(Sp0ToSg13 == DF_FLGSG9 ) RcvSoMc33993.BitData.FlgSg9        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG8 ) RcvSoMc33993.BitData.FlgSg8        = Status;
+			else if(Sp0ToSg13 == DF_FLGSG7 ) RcvSoMc33993.BitData.FlgSg7_FlgSp7 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG6 ) RcvSoMc33993.BitData.FlgSg6_FlgSp6 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG5 ) RcvSoMc33993.BitData.FlgSg5_FlgSp5 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG4 ) RcvSoMc33993.BitData.FlgSg4_FlgSp4 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG3 ) RcvSoMc33993.BitData.FlgSg3_FlgSp3 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG2 ) RcvSoMc33993.BitData.FlgSg2_FlgSp2 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG1 ) RcvSoMc33993.BitData.FlgSg1_FlgSp1 = Status;
+			else if(Sp0ToSg13 == DF_FLGSG0 ) RcvSoMc33993.BitData.FlgSg0_FlgSp0 = Status;
+			else ;
+			Mc33993CmdSend(NumMc,CmdBit,RcvSoMc33993.ByteData.StaSgH,RcvSoMc33993.ByteData.StaSgL);
+		  //(*(PntSta+NumMc)).CmdTriState_Sg = RcvSoMc33993.StaSg;
+			break;
+		default:;
+	}
+	return 1;
+}
+
+//片选产生
+//多余20片需要增加
+void ChangeCsMc33993(ubyte NumMc,bit HorL)
+{
+  switch(NumMc)
+  {
+    case Mc33993_0 :  CS_SwChip_0  = HorL;break;
+    case Mc33993_1 :  CS_SwChip_1  = HorL;break;
+    default:;
+  }
+}
+//****************************************************************************
+// @Function     ubyte Mc33993DataSendRcv(ubyte Data)
+//
+//----------------------------------------------------------------------------
+// @Description   发送数据,返回接收数据
+//                此函数与CPU平台相关,不同CPU需要修改。
+//                此函数适用于XC2765，SSC采用查询方式
+//----------------------------------------------------------------------------
+// @Returnvalue   返回接收的数据
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2011-3-4 10:28:27
+//
+//****************************************************************************
+ubyte Mc33993DataSendRcv(ubyte Data)
+{
+	uword i;
+	SSC_vSendData(Data);	
+	for(i=0;(i<6000)&&(!(IRCON1&0x02));i++);
+  IRCON1 &= 0xFD;
+	for(i=0;(i<6000)&&(!(IRCON1&0x04));i++);
+  IRCON1 &= 0xFB;
+  return((ubyte)(SSC_vGetData()));
+}
+
+//****************************************************************************
+// @Function     union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL)
+//
+//----------------------------------------------------------------------------
+// @Description   发送33993的操作命令,返回开关状态
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   返回接收的3个字节的开关状态
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2011-3-4 10:36:27
+//
+//****************************************************************************
+union ByteBitAccess *Mc33993CmdSend(ubyte NumMc,ubyte CmdBit,ubyte SetBitH,ubyte SetBitL)
+{
+  union ByteBitAccess  RcvSoMc33993,*Pnt;
+	union WordByteBitAccess  RcvSoMc33993W;
+//	uword i;
+//----------------------------------------------------------------------------
+	RcvSoMc33993W.ByteData.StaSgH = SetBitH;
+	RcvSoMc33993W.ByteData.StaSgL = SetBitL;
+	switch(CmdBit)//保存命令状态
+	{
+		case DF_CMDSETTING    :(*(PntSta+NumMc)).CmdSetting     = RcvSoMc33993W.StaSg;break;
+		case DF_CMDINT_SP     :(*(PntSta+NumMc)).CmdInt_Sp      = RcvSoMc33993W.StaSg;break;
+		case DF_CMDINT_SG     :(*(PntSta+NumMc)).CmdInt_Sg      = RcvSoMc33993W.StaSg;break;
+		case DF_CMDMETALLIC_SP:(*(PntSta+NumMc)).CmdMetallic_Sp = RcvSoMc33993W.StaSg;break;
+		case DF_CMDMETALLIC_SG:(*(PntSta+NumMc)).CmdMetallic_Sg = RcvSoMc33993W.StaSg;break;
+		case DF_CMDANALOG     :(*(PntSta+NumMc)).CmdAnalog      = RcvSoMc33993W.StaSg;break;
+		case DF_CMDWETCURR_SP :(*(PntSta+NumMc)).CmdWetCurr_Sp  = RcvSoMc33993W.StaSg;break;
+		case DF_CMDWETCURR_SG :(*(PntSta+NumMc)).CmdWetCurr_Sg  = RcvSoMc33993W.StaSg;break;
+		case DF_CMDTRISTATE_SP:(*(PntSta+NumMc)).CmdTriState_Sp = RcvSoMc33993W.StaSg;break;
+		case DF_CMDTRISTATE_SG:(*(PntSta+NumMc)).CmdTriState_Sg = RcvSoMc33993W.StaSg;break;
+		default:;
+	}
+	
+	
+	if(NumMc > (NumChipSw-1))NumMc = (NumChipSw-1);
+  ChangeCsMc33993(NumMc,0);
+//----------------------------
+  _nop_();
+	_nop_();
+	_nop_();
+	_nop_();
+	
+//-------------------------------
+
+  RcvSoMc33993.ByteData.SoMc33993Byte2 = Mc33993DataSendRcv(CmdBit);
+
+  RcvSoMc33993.ByteData.SoMc33993Byte1 = Mc33993DataSendRcv(SetBitH);
+
+  RcvSoMc33993.ByteData.SoMc33993Byte0 = Mc33993DataSendRcv(SetBitL);
+
+  ChangeCsMc33993(NumMc,1);
+//----------------------------
+  _nop_();
+	_nop_();
+	_nop_();
+	_nop_();
+//-------------------------------
+  Pnt = &RcvSoMc33993;
+  return (Pnt);
+}
diff --git a/SwDriver.H b/SwDriver.H
new file mode 100644
index 0000000..91e78e1
--- /dev/null
+++ b/SwDriver.H
@@ -0,0 +1,122 @@
+#ifndef _MC33993_H_
+#define _MC33993_H_
+
+//*****************************************************************************
+//宏定义
+//*****************************************************************************
+//多余20片需要增加
+#define Mc33993_0 			0
+#define Mc33993_1		 		1
+#define Mc33993_2		 		2
+#define Mc33993_3		 		3
+#define Mc33993_4		 		4
+#define Mc33993_5		 		5
+#define Mc33993_6		 		6
+#define Mc33993_7 			7
+#define Mc33993_8 			8
+#define Mc33993_9 			9
+#define Mc33993_10			10
+#define Mc33993_11			11
+#define Mc33993_12			12
+#define Mc33993_13			13
+#define Mc33993_14			14
+#define Mc33993_15			15
+#define Mc33993_16			16
+#define Mc33993_17			17
+#define Mc33993_18			18
+#define Mc33993_19			19
+#define Mc33993_20			20
+
+
+#define D24V		 		0
+#define Gnd		 	   	1
+
+#define TriOff		 	0
+#define TriOn		 	  1
+
+#define WetCur2mA		0
+#define WetCur16mA	1
+
+#define SwToGnd		 	0
+#define SwToPwr		 	1
+
+#define ALLTRI		 	0xff
+#define ALLD24V		 	0x0
+
+#define DF_CMDSWSTATUS 			0x00
+#define DF_CMDSETTING 			0x01
+#define DF_CMDINT_SP 				0x02
+#define DF_CMDINT_SG 				0x03
+#define DF_CMDMETALLIC_SP 	0x04
+#define DF_CMDMETALLIC_SG 	0x05
+#define DF_CMDANALOG 				0x06
+#define DF_CMDWETCURR_SP 		0x07
+#define DF_CMDWETCURR_SG 		0x08
+#define DF_CMDTRISTATE_SP 	0x09
+#define DF_CMDTRISTATE_SG 	0x0A
+#define DF_CMDCALIBRATION 	0x0B
+#define DF_CMDSLEEP				 	0x0C
+#define DF_CMDRESET				 	0x7F
+
+
+#define  DF_FLGTHEM					10
+#define  DF_FLGINT          11
+#define  DF_FLGSP7          12
+#define  DF_FLGSP6          13
+#define  DF_FLGSP5          14
+#define  DF_FLGSP4          15
+#define  DF_FLGSP3          16
+#define  DF_FLGSP2          17
+#define  DF_FLGSP1          18
+#define  DF_FLGSP0          19
+#define  DF_FLGSG13         20
+#define  DF_FLGSG12         21
+#define  DF_FLGSG11         22
+#define  DF_FLGSG10         23
+#define  DF_FLGSG9          24
+#define  DF_FLGSG8          25
+#define  DF_FLGSG7          26
+#define  DF_FLGSG6          27
+#define  DF_FLGSG5          28
+#define  DF_FLGSG4          29
+#define  DF_FLGSG3          30
+#define  DF_FLGSG2          31
+#define  DF_FLGSG1          32
+#define  DF_FLGSG0          33
+
+//Analog
+#define  DF_AN_HIMP          1
+#define  DF_AN_2MA           2
+#define  DF_AN_16MA          3
+
+#define  DF_CH_SG0           1
+#define  DF_CH_SG1           2
+#define  DF_CH_SG2           3
+#define  DF_CH_SG3           4
+#define  DF_CH_SG4           5
+#define  DF_CH_SG5           6
+#define  DF_CH_SG6           7
+#define  DF_CH_SG7           8
+#define  DF_CH_SG8           9
+#define  DF_CH_SG9           10
+#define  DF_CH_SG10          11
+#define  DF_CH_SG11          12
+#define  DF_CH_SG12          13
+#define  DF_CH_SG13          14
+#define  DF_CH_SP0           15
+#define  DF_CH_SP1           16
+#define  DF_CH_SP2           17
+#define  DF_CH_SP3           18
+#define  DF_CH_SP4           19
+#define  DF_CH_SP5           20
+#define  DF_CH_SP6           21
+#define  DF_CH_SP7           22 
+//*****************************************************************************
+//外部引用全局函数声明
+//*****************************************************************************
+void SwStaSample(UnSwSample *ptmp);
+void InitSW(void);
+void LedLight(UnSwOut *tmpUn);
+//void Swtest2(void);
+//ubyte Mc33993AnalogChSel(ubyte NumMc,ubyte Mode,ubyte Channal);
+#endif
\ No newline at end of file
diff --git a/T2.C b/T2.C
new file mode 100644
index 0000000..07d74b4
--- /dev/null
+++ b/T2.C
@@ -0,0 +1,172 @@
+//****************************************************************************
+// @Module        Timer 2
+// @Filename      T2.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the T2 module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:31
+//
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (T2_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (T2_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void T2_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the Timer 2 function 
+//                library. It is assumed that the SFRs used by this library 
+//                are in their reset state. 
+//                
+//                The following SFRs and SFR fields will be initialized:
+//                T2_RC2H/RC2L     - reload/capture timer 2 register
+//                T2_T2H/T2L     -  timer 2 register
+//                ET2           - timer 2 interrupt enable
+//                T2_T2MOD         - timer 2 mode register
+//                CP/RL2        - Capture/Reload select
+//                EXEN2         - External enable control
+//                TR2           - Timer2 run control
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Init,1)
+
+// USER CODE END
+
+void T2_vInit(void)
+{
+  // USER CODE BEGIN (T2_Init,2)
+
+  // USER CODE END
+
+  //   -----------------------------------------------------------------------
+  //   Operating Mode
+  //   -----------------------------------------------------------------------
+
+  ///  16-bit timer function with automatic reload when timer 2 overflows
+  ///  the timer 2 resolution is .5 us
+  ///  the timer 2 overflow is 1000.000 us
+  ///  timer 2 interrupt: enabled
+  ///  timer 2 will be started
+
+  //   -----------------------------------------------------------------------
+  //   Register Initialization
+  //   -----------------------------------------------------------------------
+
+  T2_T2LH       =  0xF830;       // load timer 2 reload/capture register low 
+                                 // & high bytes
+
+  T2_RC2LH      =  0xF830;       // load timer 2 reload/capture register low 
+                                 // & high bytes
+  T2_T2MOD      =  0x00;         // load timer 2 mode register
+
+  ///  timer 2 Interrupt enable bit is set in SHINT_vInit() function
+
+  // USER CODE BEGIN (T2_Init,3)
+
+  // USER CODE END
+
+  TR2 = 1; //   start timer
+
+} //  End of function T2_vInit
+
+
+// USER CODE BEGIN (T2_General,10)
+
+// USER CODE END
+
diff --git a/T2.H b/T2.H
new file mode 100644
index 0000000..a55512d
--- /dev/null
+++ b/T2.H
@@ -0,0 +1,104 @@
+//****************************************************************************
+// @Module        Timer 2
+// @Filename      T2.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the T2 module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:31
+//
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _T2_H_
+#define _T2_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,4)
+
+// USER CODE END
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (T2_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void T2_vInit(void);
+
+// USER CODE BEGIN (T2_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+
+//   Shared interrupt vector definitions are defined in SHARED_INT.H
+
+// USER CODE BEGIN (T2_Header,9)
+
+// USER CODE END
+
+#endif  // ifndef _T2_H_
diff --git a/UART.C b/UART.C
new file mode 100644
index 0000000..9d28748
--- /dev/null
+++ b/UART.C
@@ -0,0 +1,350 @@
+//****************************************************************************
+// @Module        UART (Serial Interface)
+// @Filename      UART.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the UART module.
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12 19:56:03
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (UART_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (UART_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void UART_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the UART function 
+//                library. It is assumed that the SFRs used by this library 
+//                are in their reset state. 
+//                
+//                The following SFR fields will be initialized:
+//                - register SCON
+//                - bits SMOD and ES
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Init,1)
+
+// USER CODE END
+
+void UART_vInit(void)
+{
+  // USER CODE BEGIN (UART_Init,2)
+
+  // USER CODE END
+
+  ///  -----------------------------------------------------------------------
+  ///  UART settings
+  ///  -----------------------------------------------------------------------
+  ///  Pin TXD_1 (P0.2) is selected for transmission
+  ///  Pin RXD_1 (P0.1) is selected for reception
+  ///  Receiver enabled
+  ///  Mode 1: 8-bit data, 1 start bit, 1 stop bit, variable baud rate
+  ///  BRG is selected for baudrate generation
+
+  SFR_PAGE(_pp2, noSST);         // switch to page 2 without saving
+  P0_ALTSEL0   &= ~(ubyte)0x04;  // configure alternate function register 0
+  P0_ALTSEL1   |=  (ubyte)0x04;  // configure alternate function register 1
+  SFR_PAGE(_pp0, noSST);         // switch to page 0 without saving
+  P0_DIR       |=  (ubyte)0x04;  // set output direction
+
+
+  MODPISEL     |=  (ubyte)0x01;  // configure peripheral input select register
+  BCON          =  0x00;         // reset baudrate timer/reload register
+  SCON          =  0x50;         // load serial channel control register
+
+  ///  -----------------------------------------------------------------------
+  ///  Baudrate generator settings
+  ///  -----------------------------------------------------------------------
+  ///  input clock = fPCLK
+  ///  Fractional divider is disabled
+  ///  baudrate = 100.0000 kbaud
+
+  BG            =  0x0E;         // load baudrate timer/reload register
+  BCON         |=  0x01;         // load baud rate control register
+
+
+  // USER CODE BEGIN (UART_Init,3)
+
+  // USER CODE END
+
+  ///  UART interrupt enabled
+  ES = 1;
+
+} //  End of function UART_vInit
+
+
+//****************************************************************************
+// @Function      void UART_viIsr(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the service routine for the UART interrupt. It is 
+//                called after each transmission (flag TI set) or reception 
+//                (flag RI set) of a data unit.
+//                Please note that you have to add application specific code 
+//                to this function.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12
+//
+//****************************************************************************
+
+//   You have two choices for interrupt type select in Project Settings Page 
+//   under Global Settings Section.
+//   If you select CHOICE 1 then ISR will be generated with push and pop.
+//   If you select CHOICE 2 then ISR will be generated without push and pop.
+//   Default choice is CHOICE 2.
+//   Current selection is CHOICE 2 
+
+// USER CODE BEGIN (UART_Isr,1)
+uint16_t char_data[25] = {0};
+// USER CODE END
+
+void UART_viIsr(void) interrupt UARTINT
+{
+
+    // USER CODE BEGIN (UART_Isr,2)
+//	static uint8_t i = 0;
+	static uint8_t cnt_sbus = 0;
+	static uint8_t state = 0;
+	static uint8_t receive = 0;
+	static uint8_t sbus_buff[25];
+	SBusData *tmp_sbus_data;
+    // USER CODE END
+  SFR_PAGE(_su0, SST0);          // switch to page 0
+  if (TI)
+  {
+    // USER CODE BEGIN (UART_Isr,3)
+
+       TI = 0;
+
+    // USER CODE END
+  }
+  if (RI)
+  {
+    // USER CODE BEGIN (UART_Isr,4)
+       RI = 0;
+		
+      char_data[0] = (ubyte)SBUF;		
+//		UART_vSendData8(char_data[0]);
+		
+			switch(state)
+			{				
+				case 0:
+					if(0x0f == char_data[0])
+					{
+						receive = 0;
+						cnt_sbus = 0;
+						sbus_buff[cnt_sbus] = char_data[0];
+						cnt_sbus++;
+						state = 1;
+					}
+					else
+					{
+						state = 0;
+					}
+					break;
+				case 1:
+					if(cnt_sbus >= 24)
+					{
+						if(0x0 == char_data[0])
+						{
+							cnt_sbus = 0;
+							receive = 0;
+							sbus_buff[cnt_sbus] = char_data[0];
+							state = 0;
+							tmp_sbus_data = parseSBusData(sbus_buff);
+						}
+					}
+					else if( (0x0f == char_data[0]) && (10 != cnt_sbus) )//当为第10个字节为0x0F是正常的，所以不用清0
+					{
+						receive = 0;
+						cnt_sbus = 0;
+						sbus_buff[cnt_sbus] = char_data[0];
+						cnt_sbus++;
+						state = 1;
+					}
+					else
+					{
+						sbus_buff[cnt_sbus] = char_data[0];
+						cnt_sbus ++;
+						state = 1;
+					}
+					break;
+				default:break;
+			}
+		
+    // USER CODE END
+  }
+
+    // USER CODE BEGIN (UART_Isr,5)
+
+    // USER CODE END
+  SFR_PAGE(_su0, RST0);          // restore the old page
+} //  End of function UART_viIsr
+
+
+//****************************************************************************
+// @Function      ubyte UART_ubGetData8(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function returns the last received 8-bit data unit. 
+//                Interrupt flag RI will be cleared.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   received data unit
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12
+//
+//****************************************************************************
+
+//ubyte UART_ubGetData8(void)
+//{
+//  //   Clear the receiver interrupt flag
+//  RI = 0;
+
+//  //   Return the received data byte
+//  return(SBUF);
+
+//} //  End of function UART_ubGetData8
+
+
+//****************************************************************************
+// @Function      void UART_vSendData8(ubyte ubData) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function transmits an 8-bit data unit. At first 
+//                interrupt flag TI is cleared, then buffer SBUF is written.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    ubData: 
+//                data to be transmitted
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12
+//
+//****************************************************************************
+
+//void UART_vSendData8(ubyte ubData)
+//{
+//  //   Clear the transmitter interrupt flag
+//  TI = 0;
+
+//  //   Write the transmit data byte, this initiates the transmission.
+//  SBUF = ubData;
+//} //  End of function UART_vSendData8
+
+
+// USER CODE BEGIN (UART_General,10)
+
+// USER CODE END
+
diff --git a/UART.H b/UART.H
new file mode 100644
index 0000000..22efa1c
--- /dev/null
+++ b/UART.H
@@ -0,0 +1,127 @@
+//****************************************************************************
+// @Module        UART (Serial Interface)
+// @Filename      UART.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the UART module.
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12 19:56:03
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _UART_H_
+#define _UART_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void UART_vInit(void);
+ubyte UART_ubGetData8(void);
+void UART_vSendData8(ubyte ubData);
+
+// USER CODE BEGIN (UART_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macro         UART_vRxEnable() 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro releases the receive function of the UART by 
+//                setting bit REN.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/12/12
+//
+//****************************************************************************
+
+#define UART_vRxEnable() REN = 1
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+#define UARTINT  4
+
+// USER CODE BEGIN (UART_Header,9)
+
+// USER CODE END
+
+#endif  // ifndef _UART_H_
diff --git a/UART1.C b/UART1.C
new file mode 100644
index 0000000..416fc49
--- /dev/null
+++ b/UART1.C
@@ -0,0 +1,261 @@
+//****************************************************************************
+// @Module        UART1 (Serial Interface)
+// @Filename      UART1.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the UART1 module.
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31 19:17:02
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (UART1_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void UART1_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the UART1 function 
+//                library. It is assumed that the SFRs used by this library 
+//                are in their reset state. 
+//                
+//                The following SFR fields will be initialized:
+//                - register SCON
+//                - bits SMOD and EX2
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Init,1)
+
+// USER CODE END
+
+void UART1_vInit(void)
+{
+  // USER CODE BEGIN (UART1_Init,2)
+
+  // USER CODE END
+
+  ///  -----------------------------------------------------------------------
+  ///  UART1 settings
+  ///  -----------------------------------------------------------------------
+  ///  Pin TXD1_1 (P3.1) is selected for transmission
+  ///  Pin RXD1_1 (P3.2) is selected for reception
+  ///  Receiver enabled
+  ///  UART1 interrupt is enabled
+  ///  Ignore Normal divider overflow interrupt
+  ///  Mode 1: 8-bit data, 1 start bit, 1 stop bit, variable baud rate
+  ///  Receiver interrupt flag RI_1 will only be activated if a valid stop 
+  ///  bit was received
+  ///  BRG is selected for baudrate generation
+
+  SFR_PAGE(_pp2, noSST);         // switch to page 2 without saving
+  P3_ALTSEL0   |=  (ubyte)0x02;  // configure alternate function register 0
+  P3_ALTSEL1   |=  (ubyte)0x02;  // configure alternate function register 1
+  SFR_PAGE(_pp0, noSST);         // switch to page 0 without saving
+  P3_DIR       |=  (ubyte)0x02;  // set output direction
+
+
+  SFR_PAGE(_su3, noSST);         // switch to page 3 without saving
+  MODPISEL1    |=  (ubyte)0x08;  // configure peripheral input select register
+  SFR_PAGE(_su0, noSST);         // switch to page 0 without saving
+
+  SET_RMAP();                   
+
+  UART1_BCON    =  0x00;         // reset baudrate timer/reload register
+  UART1_SCON    =  0x50;         // load serial channel control register
+
+  ///  -----------------------------------------------------------------------
+  ///  Baudrate generator settings
+  ///  -----------------------------------------------------------------------
+  ///  input clock = fPCLK
+  ///  Fractional divider is disabled
+  ///  baudrate = 9.6154 kbaud
+
+  UART1_BG      =  0x9B;         // load baudrate timer/reload register
+  UART1_BCON   |=  0x01;         // load baud rate control register
+
+
+  RESET_RMAP();                 
+
+
+  // USER CODE BEGIN (UART1_Init,3)
+
+  // USER CODE END
+
+} //  End of function UART1_vInit
+
+
+//****************************************************************************
+// @Function      ubyte UART1_ubGetData8(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function returns the last received 8-bit data unit. 
+//                Interrupt flag RI_1 will be cleared.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   received data unit
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31
+//
+//****************************************************************************
+
+ubyte UART1_ubGetData8(void)
+{
+
+  ubyte ubData;
+
+  _push_(SYSCON0);               // push the current RMAP
+  SET_RMAP();                   
+
+  //   Clear the receiver interrupt flag
+  UART1_SCON   &= ~(ubyte)0x01; 
+
+
+  //   Read the received data bits 0..7
+  ubData = (ubyte)UART1_SBUF;
+
+
+  _pop_(SYSCON0);                // restore the old RMAP
+
+  //   Return the received data byte
+  return(ubData);
+
+} //  End of function UART1_ubGetData8
+//****************************************************************************
+// @Function      void UART1_vSendData8(ubyte ubData) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function transmits an 8-bit data unit. At first 
+//                interrupt flag TI_1 is cleared, then buffer SBUF is written.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    ubData: 
+//                data to be transmitted
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31
+//
+//****************************************************************************
+
+void UART1_vSendData8(ubyte ubData)
+{
+
+  _push_(SYSCON0);               // push the current RMAP
+  SET_RMAP();                   
+
+  //   Clear the transmitter interrupt flag
+  UART1_SCON   &= ~(ubyte)0x02; 
+
+  //   Write the transmit data byte, this initiates the transmission.
+  UART1_SBUF = ubData;
+
+  _pop_(SYSCON0);                // restore the old RMAP
+
+} //  End of function UART1_vSendData8
+
+
+// USER CODE BEGIN (UART1_General,10)
+
+// USER CODE END
+
diff --git a/UART1.H b/UART1.H
new file mode 100644
index 0000000..7fa5c4f
--- /dev/null
+++ b/UART1.H
@@ -0,0 +1,153 @@
+//****************************************************************************
+// @Module        UART1 (Serial Interface)
+// @Filename      UART1.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the UART1 module.
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31 19:17:02
+//
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _UART1_H_
+#define _UART1_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (UART1_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void UART1_vInit(void);
+ubyte UART1_ubGetData8(void);
+void UART1_vSendData8(ubyte ubData);
+
+// USER CODE BEGIN (UART1_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macro         UART1_vRxEnable() 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro releases the receive function of the UART1 by 
+//                setting bit REN_1.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31
+//
+//****************************************************************************
+
+//   RMAP should be set before calling this macro.
+
+#define UART1_vRxEnable() REN_1 = 1
+
+
+//****************************************************************************
+// @Macro         UART1_vRxDisable() 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro disables the receive function of the UART1 by 
+//                clearing bit REN_1.
+//                Note: Any data that is currently being received is received 
+//                to completion, including the setting of interrupt flag RI_1.
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2024/10/31
+//
+//****************************************************************************
+
+//   RMAP should be set before calling this macro.
+
+#define UART1_vRxDisable() REN_1 = 0
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+
+// USER CODE BEGIN (UART1_Header,9)
+
+// USER CODE END
+
+#endif  // ifndef _UART1_H_
diff --git a/User.c b/User.c
new file mode 100644
index 0000000..54885d5
--- /dev/null
+++ b/User.c
@@ -0,0 +1,508 @@
+#include "MAIN.H"
+//can信息
+UnInfCan    UnInfCan_1   = {0};
+UnSwSample  UnSwSample_1 = {0};
+UnSwOut	    UnSwOut_1    = {0};
+UnRemoteControlOutput       UnRemoteControlOutput_1 = {0,0,0,0,0,0,0,0};//遥控器数据发送
+UnRemoteControlOutput       UnRemoteControlOutput_2 = {0,0,0,0,0,0,0,0};//遥控器数据发送 
+
+SBusData    sbus_data;
+
+//CAN发送周期
+uword             CntCan_1    = 0;
+bit               FlgCan_1    = 0;
+
+//第一次采集到有效数据指示
+bit FlgOneTime = 0;
+ubyte uart2RxFlag = 0;
+uword RgCanPerid = 50;
+
+ubyte           can_error_cnt = 0;
+ubyte           can_error_flg = 0;	
+
+//PWM 20181227
+ubyte PwmH[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+//-----------------------------------------------------------------------
+//RTC定时器
+//-----------------------------------------------------------------------
+void RTCProcess(void)
+{
+//************************************************************************
+//////CAN发送周期
+	if(FlgCan_1){CntCan_1++;if(CntCan_1 >= RgCanPerid){FlgCan_1=0; CntCan_1=0;}}else{CntCan_1=0;}
+
+//************************************************************************
+}
+
+// SBus 数据解析函数
+SBusData* parseSBusData(const uint8_t *input_data)
+{
+    // 解析16个通道的数据，每个通道为11位
+    sbus_data.channels[0]  = (input_data[1]      | input_data[2] << 8) & 0x07FF;
+    sbus_data.channels[1]  = (input_data[2] >> 3 | input_data[3] << 5) & 0x07FF;
+    sbus_data.channels[2]  = (input_data[3] >> 6 | input_data[4] << 2 | input_data[5] << 10) & 0x07FF;
+    sbus_data.channels[3]  = (input_data[5] >> 1 | input_data[6] << 7) & 0x07FF;
+    sbus_data.channels[4]  = (input_data[6] >> 4 | input_data[7] << 4) & 0x07FF;
+    sbus_data.channels[5]  = (input_data[7] >> 7 | input_data[8] << 1 | input_data[9] << 9) & 0x07FF;
+
+    sbus_data.channels[6]  = (input_data[9] >> 2 | input_data[10] << 6) & 0x07FF;
+    sbus_data.channels[7]  = (input_data[10] >> 5 | input_data[11] << 3) & 0x07FF;
+    sbus_data.channels[8]  = (input_data[12]     | input_data[13] << 8) & 0x07FF;
+    sbus_data.channels[9]  = (input_data[13] >> 3 | input_data[14] << 5) & 0x07FF;
+    sbus_data.channels[10] = (input_data[14] >> 6 | input_data[15] << 2 | input_data[15] << 10) & 0x07FF;
+    sbus_data.channels[11] = (input_data[16] >> 1 | input_data[17] << 7) & 0x07FF;
+    sbus_data.channels[12] = (input_data[17] >> 4 | input_data[18] << 4) & 0x07FF;
+    sbus_data.channels[13] = (input_data[18] >> 7 | input_data[19] << 1 | input_data[20] << 9) & 0x07FF;
+    sbus_data.channels[14] = (input_data[20] >> 2 | input_data[21] << 6) & 0x07FF;
+    sbus_data.channels[15] = (input_data[21] >> 5 | input_data[22] << 3) & 0x07FF;
+
+    // 解析标志字节
+    sbus_data.flags = input_data[23];
+		uart2RxFlag = 1;
+		
+//    for(ubyte i=0;i<8;i++)
+//    {
+//      printf( "%d ",i);
+//      printf( "%04x\r\n",sbus_data.channels[i]);
+//    }
+//   printf("%d\r\n",sbus_data.channels[0]);
+    return  &sbus_data;
+}
+
+//can错误处理
+void CanErrorProcess(void)
+{
+	ubyte ubNSRL;
+	ubyte ubNSRH;
+	ubyte ubResetLEC = 0x3F;
+//-------------------------------------------
+	EA            =  0;
+
+	CAN_pushAMRegs();              // push the CAN Access Mediator Registers
+	SFR_PAGE(_su0, SST0);          // switch to page 0
+
+	CAN_vWriteCANAddress(CAN_NSR0);
+	CAN_vReadEN();
+	ubNSRL = CAN_DATA0;
+	ubNSRH = CAN_DATA1;
+	if (ubNSRL & 0x20)      // if ALERT
+	{
+		CAN_vInit();
+	}
+	if (ubNSRL & 0x07)  // if LEC
+	{
+		ubResetLEC = 0x38;
+	}
+	//// Reset LEC, TXOK, RXOK, ALERT, EWRN, BOFF, LLE, LOE (if set)
+	CAN_vWriteCANAddress(CAN_NSR0); // Addressing CAN_NSR0
+	CAN_DATA0   =  ~(ubNSRL & ubResetLEC);       // load CAN_NSR0 status register[7-0]
+	CAN_DATA1   =  ~(ubNSRH);       // load CAN_NSR0 status register[15-8]
+	CAN_vWriteEN(D0_VALID+D1_VALID);  // Data0 and Data1 are Valid for
+
+	SFR_PAGE(_su0, RST0);          // restore the old SCU page
+	CAN_popAMRegs();               // restore the CAN Access Mediator Registers
+
+	EA            =  1;
+}
+
+
+void CanTransmit(ubyte index,ubyte *buf)
+{
+  ubyte CanTransmitbuf[8] = {0,0,0,0,0,0,0,0};
+//-----------------	--------
+	CanTransmitbuf[2] = buf[0];
+	CanTransmitbuf[3] = buf[1];	
+	CanTransmitbuf[0] = buf[2];	
+	CanTransmitbuf[1] = buf[3];	
+	CanTransmitbuf[6] = buf[4];	
+	CanTransmitbuf[7] = buf[5];	
+	CanTransmitbuf[4] = buf[6];	
+	CanTransmitbuf[5] = buf[7];	
+
+	CAN_waitTransmit(index);//发送前等待上一帧发送完毕，这样不会丢帧
+	CAN_vLoadData(index, (ulong *)CanTransmitbuf);// 装载数据
+	CAN_vTransmit(index);
+}
+
+typedef enum {
+    STT_INIT_LIGHT,    // 必须保留的初始状态
+    STT_STABLE,        // 稳定态
+    STT_BLINK_CHECK,   // 闪烁检测
+    STT_BLINKING       // 闪烁保持
+} BlinkState;
+
+typedef struct {
+    BlinkState current_state;
+    uint8_t last_input;
+    uint16_t unified_timer;  // 统一计时器[7](@ref)
+    uint8_t trans_count;     // 保留必要的事件计数器
+    uint8_t stable_type;     
+} BlinkDetector;
+
+BlinkDetector blink_detector = {0};
+
+/* LED状态检测核心状态机（统一计时器优化版）
+ * 参数：
+ *   ctx          - 状态机上下文指针（需保证非空）
+ *   current_input- 当前输入电平（0:灭 1:亮）
+ *   output       - 输出状态指针（0:无效 1:稳定亮 2:稳定灭 3:闪烁）
+ * 设计原则：
+ *   1. 单一定时器复用机制[8](@ref)
+ *   2. 防御性清零策略[1](@ref)
+ *   3. 状态迁移原子操作[9](@ref)
+ */
+void detectLedState(BlinkDetector* ctx, uint8_t current_input, uint8_t* output) 
+{
+    *output = 0;
+
+    switch(ctx->current_state) 
+    {
+        /* 关键初始状态：确保首次正确捕获输入 */
+        case STT_INIT_LIGHT: 
+        {
+            ctx->last_input = current_input;       // 强制记录初始值
+            ctx->stable_type = current_input ? 1 : 2;
+            ctx->current_state = STT_STABLE;       // 立即进入稳定态
+            ctx->unified_timer = 0;                // 初始化计时器
+				  	*output = 0;
+            break;
+        }
+
+        case STT_STABLE: 
+        {
+						if(current_input != ctx->last_input) 
+						{
+								ctx->current_state = STT_BLINK_CHECK;
+								ctx->trans_count = 1;
+								ctx->unified_timer = 0;
+								ctx->last_input = current_input;
+						  	ctx->stable_type = current_input ? 1 : 2; // 同步状态类型[4](@ref)
+						} 
+						else if(ctx->unified_timer >= STABLE_CONFIRM_TIME) 
+						{
+								*output = ctx->stable_type; 
+								ctx->unified_timer = 0;
+								ctx->stable_type = current_input ? 1 : 2; // 二次确认[10](@ref)
+						}
+						else 
+						{
+								ctx->unified_timer++;
+								*output = ctx->stable_type; 
+						}			
+            break;
+        }
+        /* 闪烁检测态：在时间窗口内统计电平跳变次数 */
+        case STT_BLINK_CHECK: 
+        {
+            if(ctx->unified_timer >= BLINK_WINDOW)    // 达到检测窗口时长[8](@ref)
+            {
+                if(ctx->trans_count >= MIN_BLINKS)    // 满足最小闪烁次数
+                {                                  
+                    ctx->current_state = STT_BLINKING;// 进入闪烁保持态
+                    ctx->unified_timer = 0;           // 重置超时计时器
+                } 
+                else                                  // 未达闪烁阈值
+                {
+                    ctx->current_state = STT_STABLE;  // 返回稳定态
+                    ctx->unified_timer = 0;           // 跨状态复用计时器
+                }
+            }
+            else                                      // 窗口期内检测
+            {                                       
+                ctx->unified_timer++;                // 窗口期计时累计
+								if(current_input != ctx->last_input) 
+								{
+										ctx->trans_count++;                   // 跳变次数累计
+										ctx->last_input = current_input;      // 更新最新输入值
+								}
+            }
+            break;
+        }
+
+        /* 闪烁保持态：监测闪烁活动持续性 */
+				case STT_BLINKING: 
+				{
+						// 新增输入变化检测
+						if(current_input != ctx->last_input) 
+						{
+								ctx->unified_timer = 0;       // 重置超时计时器
+								ctx->last_input = current_input;
+								*output = 3;                 // 持续输出闪烁状态							
+						}
+						else if(ctx->unified_timer >= BLINK_TIMEOUT) 
+						{
+								ctx->current_state = STT_STABLE;
+								ctx->stable_type = current_input ? 1 : 2; // 根据最终状态更新类型[4](@ref)
+								ctx->unified_timer = 0;
+						}
+						else 
+						{
+								ctx->unified_timer ++;        // 仅当输入稳定时累计计时
+								*output = 3;                 // 持续输出闪烁状态
+						}
+						break;
+				}
+				
+				default:break;
+    }
+}
+
+//SBUS和CAN的数据转换
+void sbusCanDecode(void)
+{ 
+	float SBUS2CANdecodeTemp = 0.0;	
+
+//----------------------------------------------
+	if(uart2RxFlag == 1)
+	{		
+		uart2RxFlag = 0;
+		
+		//转弯
+		SBUS2CANdecodeTemp = (float)(sbus_data.channels[0]);
+		SBUS2CANdecodeTemp = (DF_ZeroValue - SBUS2CANdecodeTemp)*23;//需要变换一下符号，因为加油是正
+		DF_Curvature = (int16_t)SBUS2CANdecodeTemp;//曲率	
+		if( (DF_Curvature > (-50)) && (DF_Curvature < 50) ) //增加回0的死区，解决会中问题。
+		{
+			DF_Curvature = 0;
+		}				
+		
+		//转速
+		SBUS2CANdecodeTemp = (float)(sbus_data.channels[1]);
+		SBUS2CANdecodeTemp = (DF_ZeroValue - SBUS2CANdecodeTemp)*2.3;//需要变换一下符号，因为加油是正
+		DF_Speed = (int16_t)SBUS2CANdecodeTemp;//转速
+		if( (DF_Speed > (-50)) && (DF_Speed < 50) ) //增加回0的死区，解决会中问题。
+		{
+			DF_Speed = 0;
+		}		
+		
+    //备用	
+		SBUS2CANdecodeTemp = (float)(sbus_data.channels[7]);
+		SBUS2CANdecodeTemp = (DF_ZeroValue - SBUS2CANdecodeTemp);//需要变换一下符号，因为加油是正
+		DF_Reserve = (int16_t)SBUS2CANdecodeTemp;//转速
+		if( (DF_Reserve > (-50)) && (DF_Reserve < 50) ) //增加回0的死区，解决会中问题。
+		{
+			DF_Reserve = 0;
+		}
+
+		
+		//SwA
+		if(sbus_data.channels[1] >= 1700)//按下
+		{
+			DF_SwA = 1;
+		}
+		else
+		{
+			DF_SwA = 0;
+		}
+		
+		//SwB
+		if(sbus_data.channels[6] >= 1700)//第三档
+		{
+			DF_SwB = 2;
+		}
+		else if(sbus_data.channels[6] <= 250)//第二档
+		{
+			DF_SwB = 0;
+		}
+		else//第一档
+		{
+			DF_SwB = 1;
+		}	
+		
+		//SwC
+		if(sbus_data.channels[4] >= 1700)//第三档
+		{
+			DF_SwC = 2;
+		}
+		else if(sbus_data.channels[4] <= 250)//第二档
+		{
+			DF_SwC = 0;
+		}
+		else//第一档
+		{
+			DF_SwC = 1;
+		}		
+		
+		//SwD
+		if(sbus_data.channels[5] >= 1700)//按下
+		{
+			DF_SwD = 1;
+		}
+		else
+		{
+			DF_SwD = 0;
+		}		
+
+		if(0 == sbus_data.flags)//23通道数据 为0标志手柄连接正常
+		{
+			DF_RCHSta = 1;//手柄在线			
+		}
+		else
+		{
+			DF_RCHSta = 0;//手柄离线		
+		}
+		
+		SBUS2CANdecodeTemp = (float)(sbus_data.channels[2]);
+		UnRemoteControlOutput_2.bit_data.speed = (int16_t)SBUS2CANdecodeTemp;//保留轴		
+		
+		SBUS2CANdecodeTemp = (float)(sbus_data.channels[3]);
+		UnRemoteControlOutput_2.bit_data.curvature = (int16_t)SBUS2CANdecodeTemp;//保留轴	
+				
+  }
+	
+	UnRemoteControlOutput_2.bit_data.switch_a = P1_2;//
+	UnRemoteControlOutput_2.bit_data.switch_d = P1_3;//		
+}
+
+
+//CAN发送接收
+void CanRXTX(void)
+{
+	stCAN_SWObj StrCanRx = {0};
+	uword tmp = 0;
+	ubyte i = 0,j = 0;
+	ubyte sbus_temp[2] = {0,0};
+	
+	static ubyte match_freq_sta = 0;
+	static uword match_freq_cnt = 0;	
+  static uword match_freq_time = 0;		
+//------------------------------------
+	if(CAN_ubNewData(DF_SwRx))
+	{
+		CAN_vGetMsgObj(DF_SwRx, &StrCanRx);
+
+		UnInfCan_1.ArrData.ArrRX[0][3] = StrCanRx.ulDATAL.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[0][2] = StrCanRx.ulDATAL.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[0][1] = StrCanRx.ulDATAL.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[0][0] = StrCanRx.ulDATAL.ubDB[3];
+		UnInfCan_1.ArrData.ArrRX[0][7] = StrCanRx.ulDATAH.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[0][6] = StrCanRx.ulDATAH.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[0][5] = StrCanRx.ulDATAH.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[0][4] = StrCanRx.ulDATAH.ubDB[3];
+
+		CAN_vReleaseObj(DF_SwRx);
+	}
+
+	if(CAN_ubNewData(DF_SwRxPwm))
+	{
+//		CAN_vGetMsgObj(DF_SwRxPwm, &StrCanRx);
+
+//		UnInfCan_1.ArrData.ArrRX[1][2] = StrCanRx.ulDATAL.ubDB[0];
+//		UnInfCan_1.ArrData.ArrRX[1][3] = StrCanRx.ulDATAL.ubDB[1];
+//		UnInfCan_1.ArrData.ArrRX[1][0] = StrCanRx.ulDATAL.ubDB[2];
+//		UnInfCan_1.ArrData.ArrRX[1][1] = StrCanRx.ulDATAL.ubDB[3];
+//		UnInfCan_1.ArrData.ArrRX[1][6] = StrCanRx.ulDATAH.ubDB[0];
+//		UnInfCan_1.ArrData.ArrRX[1][7] = StrCanRx.ulDATAH.ubDB[1];
+//		UnInfCan_1.ArrData.ArrRX[1][4] = StrCanRx.ulDATAH.ubDB[2];
+//		UnInfCan_1.ArrData.ArrRX[1][5] = StrCanRx.ulDATAH.ubDB[3];
+
+//		CAN_vReleaseObj(DF_SwRxPwm);
+////		//接收的数据保存到PWM数据结构中20181227
+////		PwmH[0 ] = (ubyte)UnInfCan_1.BitData.Pwm_01;
+////		PwmH[1 ] = (ubyte)UnInfCan_1.BitData.Pwm_02;
+////		PwmH[2 ] = (ubyte)UnInfCan_1.BitData.Pwm_03;
+////		PwmH[3 ] = (ubyte)UnInfCan_1.BitData.Pwm_04;
+////		PwmH[4 ] = (ubyte)UnInfCan_1.BitData.Pwm_05;
+////		PwmH[5 ] = (ubyte)UnInfCan_1.BitData.Pwm_06;
+////		PwmH[6 ] = (ubyte)UnInfCan_1.BitData.Pwm_07;
+////		PwmH[7 ] = (ubyte)UnInfCan_1.BitData.Pwm_08;
+////		PwmH[8 ] = (ubyte)UnInfCan_1.BitData.Pwm_09;
+////		PwmH[9 ] = (ubyte)UnInfCan_1.BitData.Pwm_10;
+////		PwmH[10] = (ubyte)UnInfCan_1.BitData.Pwm_11;
+////		PwmH[11] = (ubyte)UnInfCan_1.BitData.Pwm_12;
+////		PwmH[12] = (ubyte)UnInfCan_1.BitData.Pwm_13;
+////		PwmH[13] = (ubyte)UnInfCan_1.BitData.Pwm_14;
+////		PwmH[14] = (ubyte)UnInfCan_1.BitData.Pwm_15;
+////		PwmH[15] = (ubyte)UnInfCan_1.BitData.Pwm_16;
+
+	}
+	
+//50ms发送一帧
+	if(!FlgCan_1)
+	{
+		FlgCan_1 = 1;
+		
+		sbus_temp[0] = P1_3;
+		
+//		sbus_temp[1] = 3;
+    detectLedState(&blink_detector, sbus_temp[0], &sbus_temp[1]);		
+//	  UnRemoteControlOutput_2.bit_data.enable = blink_detector.current_state;//
+//	  UnRemoteControlOutput_2.bit_data.reserve1	= sbus_temp[1];	
+		
+
+		if( (MATCH_CMD == UnInfCan_1.ArrData.ArrRX[0][0]) || (CHANGE_CMD == UnInfCan_1.ArrData.ArrRX[0][0]) )//对频或者切换
+		{
+			if(MATCH_CMD == UnInfCan_1.ArrData.ArrRX[0][0])//对频
+			{
+				match_freq_time = MATCH_TIME;
+			}
+			else
+			{
+				match_freq_time = CHANGE_TIME;
+			}
+			
+			switch(match_freq_sta)
+			{
+				case 0:				
+					if(match_freq_cnt >= match_freq_time)//时间根据命令确定
+					{
+		      	SwOut01 = 0;//取消对频						
+						match_freq_sta = 1;
+						match_freq_cnt = 0;						
+					}
+					else
+					{
+					  SwOut01 = 1;//对频指令
+						match_freq_sta = 0;	
+						match_freq_cnt ++;
+					}
+				break;
+					
+				case 1:
+					if(match_freq_cnt >= MATCH_WAIT_TIME)//
+					{
+		      	SwOut01 = 0;//取消对频						
+						match_freq_sta = 0;
+						match_freq_cnt = 0;
+						UnInfCan_1.ArrData.ArrRX[0][0] = 0;
+					}
+					else
+					{
+					  SwOut01 = 0;//对频指令
+						match_freq_sta = 1;	
+						match_freq_cnt ++;
+					}
+				break;									
+				default:;				
+			}
+		}
+		
+    CanTransmit(DF_SwTx,(ubyte *)&UnRemoteControlOutput_1.arr[0]);
+    CanTransmit(DF_SwTx1,(ubyte *)&UnRemoteControlOutput_2.arr[0]);	
+	}
+	
+	if( (0x40 == can_error_cnt) || (0x80 == can_error_cnt) )//20250625判断是否出现总线错误
+	{
+		 can_error_flg = can_error_cnt;
+		 CAN_vInit();
+		 can_error_cnt = 0;
+	}			
+	
+	
+	
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/User.c.bak b/User.c.bak
new file mode 100644
index 0000000..22b39dd
--- /dev/null
+++ b/User.c.bak
@@ -0,0 +1,330 @@
+#include "MAIN.H"
+//can信息
+UnInfCan    UnInfCan_1   = {0};
+UnSwSample  UnSwSample_1 = {0};
+UnSwOut	    UnSwOut_1    = {0};
+
+//CAN发送周期
+uword             CntCan_1    = 0;
+bit               FlgCan_1    = 0;
+//第一次采集到有效数据指示
+bit FlgOneTime = 0;
+
+uword RgCanPerid = 1000;
+
+//PWM 20181227
+ubyte PwmH[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+//-----------------------------------------------------------------------
+//RTC定时器
+//-----------------------------------------------------------------------
+void RTCProcess(void)
+{
+//************************************************************************
+//////CAN发送周期
+	if(FlgCan_1){CntCan_1++;if(CntCan_1 >= RgCanPerid){FlgCan_1=0; CntCan_1=0;}}else{CntCan_1=0;}
+
+//************************************************************************
+}
+
+//输出PWM	20181227
+/*
+ubyte *pStt,	状态机变量
+bit Cmd,			状态机输入，1，根据PwmH的值来决定输出，0，输出0
+bit Out,			状态机输出
+ubyte *pCnt,	定时计数器
+ubyte *pPwmH	状态机参数，PWM的高电平时间
+*/ 
+bit funcPwmOut(ubyte *pStt,bit Cmd,ubyte *pCnt,ubyte *pPwmH)
+{
+ubyte PwmL = 0; 
+bit Out = 0;
+//------------------------------------------------------------------------------------------------
+	if((*pPwmH) > dfPwmH)(*pPwmH) = dfPwmH;	 //限制最大值
+	PwmL = dfPwmH - (*pPwmH);//计算PWM低电平
+
+	if((1 == Cmd) )
+	{
+		if(0 == (*pPwmH))	 //高电平为0，表示PWM无效，由Cmd来控制，Cmd为1输出1，Cmd为0，输出0
+		{
+			Out = 1;
+			(*pStt) = 0;	
+		}
+		else
+		{
+			switch((*pStt))
+			{
+				case 0:
+					(*pCnt) = 0;
+					(*pStt) = 1;
+					Out = 1;
+				break;
+				case 1:
+					if((*pCnt) >= (*pPwmH))
+					{
+						(*pCnt) = 0;
+						(*pStt) = 2;
+						Out = 0;
+					}
+					else
+					{
+					 	(*pCnt)++;
+						(*pStt) = 1;
+						Out = 1;
+					}
+				break;
+				case 2:
+					if((*pCnt) >= PwmL)
+					{
+						(*pCnt) = 0;
+						(*pStt) = 1;
+						Out = 1;
+					}
+					else
+					{
+					 	(*pCnt)++;
+						(*pStt) = 2;
+						Out = 0;
+					}
+				break;
+		//-----------------------------------------------------
+				default:;
+			}//switch
+		}//else
+	}//if
+	else 
+	{
+		Out = 0;		
+		(*pStt) = 0;
+	}
+	return Out;
+}
+
+
+//根据接收的CAN缓冲区数据驱动相应ＬＥＤ指示灯。
+void LedDr(void)
+{
+static ubyte RgSTT[16] = {0};
+static ubyte CntTime[16] = {0};
+//------------------------------------------------------------------------------------------------
+
+	dfOut_01 = funcPwmOut(&RgSTT[0 ],dfCmd_01,&CntTime[0 ],&PwmH[0 ]);	
+	dfOut_02 = funcPwmOut(&RgSTT[1 ],dfCmd_02,&CntTime[1 ],&PwmH[1 ]);	
+	dfOut_03 = funcPwmOut(&RgSTT[2 ],dfCmd_03,&CntTime[2 ],&PwmH[2 ]);	
+	dfOut_04 = funcPwmOut(&RgSTT[3 ],dfCmd_04,&CntTime[3 ],&PwmH[3 ]);	
+	dfOut_05 = funcPwmOut(&RgSTT[4 ],dfCmd_05,&CntTime[4 ],&PwmH[4 ]);	
+	dfOut_06 = funcPwmOut(&RgSTT[5 ],dfCmd_06,&CntTime[5 ],&PwmH[5 ]);	
+	dfOut_07 = funcPwmOut(&RgSTT[6 ],dfCmd_07,&CntTime[6 ],&PwmH[6 ]);	
+	dfOut_08 = funcPwmOut(&RgSTT[7 ],dfCmd_08,&CntTime[7 ],&PwmH[7 ]);	
+	dfOut_09 = funcPwmOut(&RgSTT[8 ],dfCmd_09,&CntTime[8 ],&PwmH[8 ]);	
+	dfOut_10 = funcPwmOut(&RgSTT[9 ],dfCmd_10,&CntTime[9 ],&PwmH[9 ]);	
+	dfOut_11 = funcPwmOut(&RgSTT[10],dfCmd_11,&CntTime[10],&PwmH[10]);	
+	dfOut_12 = funcPwmOut(&RgSTT[11],dfCmd_12,&CntTime[11],&PwmH[11]);	
+	dfOut_13 = funcPwmOut(&RgSTT[12],dfCmd_13,&CntTime[12],&PwmH[12]);	
+	dfOut_14 = funcPwmOut(&RgSTT[13],dfCmd_14,&CntTime[13],&PwmH[13]);	
+	dfOut_15 = funcPwmOut(&RgSTT[14],dfCmd_15,&CntTime[14],&PwmH[14]);	
+	dfOut_16 = funcPwmOut(&RgSTT[15],dfCmd_16,&CntTime[15],&PwmH[15]);	
+
+}
+
+
+//can错误处理
+void CanErrorProcess(void)
+{
+	ubyte ubNSRL;
+	ubyte ubNSRH;
+	ubyte ubResetLEC = 0x3F;
+//-------------------------------------------
+	EA            =  0;
+
+	CAN_pushAMRegs();              // push the CAN Access Mediator Registers
+	SFR_PAGE(_su0, SST0);          // switch to page 0
+
+	CAN_vWriteCANAddress(CAN_NSR0);
+	CAN_vReadEN();
+	ubNSRL = CAN_DATA0;
+	ubNSRH = CAN_DATA1;
+	if (ubNSRL & 0x20)      // if ALERT
+	{
+		CAN_vInit();
+	}
+	if (ubNSRL & 0x07)  // if LEC
+	{
+		ubResetLEC = 0x38;
+	}
+	//// Reset LEC, TXOK, RXOK, ALERT, EWRN, BOFF, LLE, LOE (if set)
+	CAN_vWriteCANAddress(CAN_NSR0); // Addressing CAN_NSR0
+	CAN_DATA0   =  ~(ubNSRL & ubResetLEC);       // load CAN_NSR0 status register[7-0]
+	CAN_DATA1   =  ~(ubNSRH);       // load CAN_NSR0 status register[15-8]
+	CAN_vWriteEN(D0_VALID+D1_VALID);  // Data0 and Data1 are Valid for
+
+	SFR_PAGE(_su0, RST0);          // restore the old SCU page
+	CAN_popAMRegs();               // restore the CAN Access Mediator Registers
+
+	EA            =  1;
+}
+
+
+////效验算法
+//void Password(void)
+//{
+//	ubyte i;
+////---------------------------------
+//	for(i=0;i<5;i++)
+//	{
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][3];//CAN 第0个字节
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][2];//CAN 第1个字节
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][1];//CAN 第2个字节
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][0];//CAN 第3个字节
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][7];//CAN 第4个字节
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][6];//CAN 第5个字节
+//		UnInfCan_1.ArrData.Arr[0][4] ^= UnInfCan_1.ArrData.Arr[0][5];//CAN 第6个字节
+//	}
+//}
+
+
+void CanTransmit(void)
+{
+//	ulong i;
+//-----------------	--------
+	CAN_waitTransmit(DF_SwTx);//发送前等待上一帧发送完毕，这样不会丢帧
+//	Password();
+
+	CAN_vLoadData(DF_SwTx, (ulong *)(&UnInfCan_1.ArrData.Arr[0][0])); // 装载数据
+	CAN_vTransmit(DF_SwTx);
+}
+
+
+//CAN发送一帧
+void CanTX(void)
+{
+//-----------------------------------
+	if(1 == SwOut09)UnInfCan_1.ArrData.Arr[0][3] |= (~0x01);else UnInfCan_1.ArrData.Arr[0][3] &= 0x01;		//KGF1		//20200303修改为与接收到的数据一致，反馈与接收到时数据为一致
+	if(1 == SwOut10)UnInfCan_1.ArrData.Arr[0][3] |= (~0x02);else UnInfCan_1.ArrData.Arr[0][3] &= 0x02;		//KGF2		
+	if(1 == SwOut04)UnInfCan_1.ArrData.Arr[0][3] |= (~0x04);else UnInfCan_1.ArrData.Arr[0][3] &= 0x04;		//KGF3
+	if(1 == SwOut03)UnInfCan_1.ArrData.Arr[0][3] |= (~0x08);else UnInfCan_1.ArrData.Arr[0][3] &= 0x08;		//KGF4
+	if(1 == SwOut06)UnInfCan_1.ArrData.Arr[0][3] |= (~0x10);else UnInfCan_1.ArrData.Arr[0][3] &= 0x10;		//KGF5
+	if(1 == SwOut05)UnInfCan_1.ArrData.Arr[0][3] |= (~0x20);else UnInfCan_1.ArrData.Arr[0][3] &= 0x20;		//KGF6
+	if(1 == SwOut15)UnInfCan_1.ArrData.Arr[0][3] |= (~0x40);else UnInfCan_1.ArrData.Arr[0][3] &= 0x40;		//KGF7
+	if(1 == SwOut16)UnInfCan_1.ArrData.Arr[0][3] |= (~0x80);else UnInfCan_1.ArrData.Arr[0][3] &= 0x80;		//KGF8
+	if(1 == SwOut13)UnInfCan_1.ArrData.Arr[0][2] |= (~0x01);else UnInfCan_1.ArrData.Arr[0][2] &= 0x01;		//KGF9
+	if(1 == SwOut14)UnInfCan_1.ArrData.Arr[0][2] |= (~0x02);else UnInfCan_1.ArrData.Arr[0][2] &= 0x02;		//KGF10
+	if(1 == SwOut08)UnInfCan_1.ArrData.Arr[0][2] |= (~0x04);else UnInfCan_1.ArrData.Arr[0][2] &= 0x04;		//KGF11
+	if(1 == SwOut07)UnInfCan_1.ArrData.Arr[0][2] |= (~0x08);else UnInfCan_1.ArrData.Arr[0][2] &= 0x08;		//KGF12
+	if(1 == SwOut02)UnInfCan_1.ArrData.Arr[0][2] |= (~0x10);else UnInfCan_1.ArrData.Arr[0][2] &= 0x10;		//KGF13
+	if(1 == SwOut01)UnInfCan_1.ArrData.Arr[0][2] |= (~0x20);else UnInfCan_1.ArrData.Arr[0][2] &= 0x20;		//KGF14
+	if(1 == SwOut11)UnInfCan_1.ArrData.Arr[0][2] |= (~0x40);else UnInfCan_1.ArrData.Arr[0][2] &= 0x40;		//KGF15
+	if(1 == SwOut12)UnInfCan_1.ArrData.Arr[0][2] |= (~0x80);else UnInfCan_1.ArrData.Arr[0][2] &= 0x80;		//KGF16
+
+	if(1 == SwIn01 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x01);else UnInfCan_1.ArrData.Arr[0][1] |= 0x01;		//Dia01  20200225修改为0数据变为1,1数据变为0，这样大CPU方便处理
+	if(1 == SwIn02 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x02);else UnInfCan_1.ArrData.Arr[0][1] |= 0x02;		//Dia02
+	if(1 == SwIn03 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x04);else UnInfCan_1.ArrData.Arr[0][1] |= 0x04;		//Dia03
+	if(1 == SwIn04 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x08);else UnInfCan_1.ArrData.Arr[0][1] |= 0x08;		//Dia04
+	if(1 == SwIn05 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x10);else UnInfCan_1.ArrData.Arr[0][1] |= 0x10;		//Dia05
+	if(1 == SwIn06 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x20);else UnInfCan_1.ArrData.Arr[0][1] |= 0x20;		//Dia06
+	if(1 == SwIn07 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x40);else UnInfCan_1.ArrData.Arr[0][1] |= 0x40;		//Dia07	  
+	if(1 == SwIn08 )UnInfCan_1.ArrData.Arr[0][1] &= (~0x80);else UnInfCan_1.ArrData.Arr[0][1] |= 0x80;		//Dia08			
+                               
+	UnInfCan_1.ArrData.Arr[0][0] = 0;
+	UnInfCan_1.ArrData.Arr[0][7] = 0;
+	UnInfCan_1.ArrData.Arr[0][6] = 0;
+	UnInfCan_1.ArrData.Arr[0][5] = (ubyte)(RgCanPerid>>8);
+	UnInfCan_1.ArrData.Arr[0][4] = (ubyte)(RgCanPerid);
+
+	CanTransmit();
+}
+
+//CAN发送接收
+void CanRXTX(void)
+{
+	stCAN_SWObj StrCanRx = {0};
+	uword tmp = 0;
+	ubyte i = 0,j = 0;
+//------------------------------------
+	if(CAN_ubNewData(DF_SwRx))
+	{
+		CAN_vGetMsgObj(DF_SwRx, &StrCanRx);
+
+		UnInfCan_1.ArrData.ArrRX[0][3] = StrCanRx.ulDATAL.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[0][2] = StrCanRx.ulDATAL.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[0][1] = StrCanRx.ulDATAL.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[0][0] = StrCanRx.ulDATAL.ubDB[3];
+		UnInfCan_1.ArrData.ArrRX[0][7] = StrCanRx.ulDATAH.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[0][6] = StrCanRx.ulDATAH.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[0][5] = StrCanRx.ulDATAH.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[0][4] = StrCanRx.ulDATAH.ubDB[3];
+
+		CAN_vReleaseObj(DF_SwRx);
+
+		//CAN发送周期	50-5000ms
+		tmp = (uword)UnInfCan_1.ArrData.ArrRX[0][6];
+		tmp = (tmp << 8);
+		tmp |= ((uword)UnInfCan_1.ArrData.ArrRX[0][7]);
+		if(tmp >= 50)RgCanPerid = tmp;
+		if(tmp >= 5000)RgCanPerid = 5000;
+
+//		UnInfCan_1.ArrData.Arr[0][3] = UnInfCan_1.ArrData.ArrRX[0][0];
+//		UnInfCan_1.ArrData.Arr[0][2] = UnInfCan_1.ArrData.ArrRX[0][1];
+//		UnInfCan_1.ArrData.Arr[0][1] = UnInfCan_1.ArrData.ArrRX[0][2]; 20200225注释不更新诊断数据
+//		UnInfCan_1.ArrData.Arr[0][0] = UnInfCan_1.ArrData.ArrRX[0][3];
+//		UnInfCan_1.ArrData.Arr[0][7] = UnInfCan_1.ArrData.ArrRX[0][4];
+//		UnInfCan_1.ArrData.Arr[0][6] = UnInfCan_1.ArrData.ArrRX[0][5];
+//		UnInfCan_1.ArrData.Arr[0][5] = (ubyte)(RgCanPerid>>8);
+//		UnInfCan_1.ArrData.Arr[0][4] = (ubyte)(RgCanPerid);
+//		CanTransmit();	 20200730不发送干扰数据运行
+	}
+
+	if(CAN_ubNewData(DF_SwRxPwm))
+	{
+		CAN_vGetMsgObj(DF_SwRxPwm, &StrCanRx);
+
+		UnInfCan_1.ArrData.ArrRX[1][2] = StrCanRx.ulDATAL.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[1][3] = StrCanRx.ulDATAL.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[1][0] = StrCanRx.ulDATAL.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[1][1] = StrCanRx.ulDATAL.ubDB[3];
+		UnInfCan_1.ArrData.ArrRX[1][6] = StrCanRx.ulDATAH.ubDB[0];
+		UnInfCan_1.ArrData.ArrRX[1][7] = StrCanRx.ulDATAH.ubDB[1];
+		UnInfCan_1.ArrData.ArrRX[1][4] = StrCanRx.ulDATAH.ubDB[2];
+		UnInfCan_1.ArrData.ArrRX[1][5] = StrCanRx.ulDATAH.ubDB[3];
+
+		CAN_vReleaseObj(DF_SwRxPwm);
+		//接收的数据保存到PWM数据结构中20181227
+		PwmH[0 ] = (ubyte)UnInfCan_1.BitData.Pwm_01;
+		PwmH[1 ] = (ubyte)UnInfCan_1.BitData.Pwm_02;
+		PwmH[2 ] = (ubyte)UnInfCan_1.BitData.Pwm_03;
+		PwmH[3 ] = (ubyte)UnInfCan_1.BitData.Pwm_04;
+		PwmH[4 ] = (ubyte)UnInfCan_1.BitData.Pwm_05;
+		PwmH[5 ] = (ubyte)UnInfCan_1.BitData.Pwm_06;
+		PwmH[6 ] = (ubyte)UnInfCan_1.BitData.Pwm_07;
+		PwmH[7 ] = (ubyte)UnInfCan_1.BitData.Pwm_08;
+		PwmH[8 ] = (ubyte)UnInfCan_1.BitData.Pwm_09;
+		PwmH[9 ] = (ubyte)UnInfCan_1.BitData.Pwm_10;
+		PwmH[10] = (ubyte)UnInfCan_1.BitData.Pwm_11;
+		PwmH[11] = (ubyte)UnInfCan_1.BitData.Pwm_12;
+		PwmH[12] = (ubyte)UnInfCan_1.BitData.Pwm_13;
+		PwmH[13] = (ubyte)UnInfCan_1.BitData.Pwm_14;
+		PwmH[14] = (ubyte)UnInfCan_1.BitData.Pwm_15;
+		PwmH[15] = (ubyte)UnInfCan_1.BitData.Pwm_16;
+
+
+//		UnInfCan_1.ArrData.Arr[0][3] = UnInfCan_1.ArrData.ArrRX[1][0];
+//		UnInfCan_1.ArrData.Arr[0][2] = UnInfCan_1.ArrData.ArrRX[1][1];
+//		UnInfCan_1.ArrData.Arr[0][1] = UnInfCan_1.ArrData.ArrRX[1][2];	20200225注释不更新诊断数据
+//		UnInfCan_1.ArrData.Arr[0][0] = UnInfCan_1.ArrData.ArrRX[1][3];
+//		UnInfCan_1.ArrData.Arr[0][7] = UnInfCan_1.ArrData.ArrRX[1][4];
+//		UnInfCan_1.ArrData.Arr[0][6] = UnInfCan_1.ArrData.ArrRX[1][5];
+//		UnInfCan_1.ArrData.Arr[0][5] = UnInfCan_1.ArrData.ArrRX[1][6];
+//		UnInfCan_1.ArrData.Arr[0][4] = UnInfCan_1.ArrData.ArrRX[1][7];
+//		CanTransmit();
+
+	}
+		//接收一帧，调用一次点灯程序。
+		LedDr();
+
+//100ms发送一帧
+	if(!FlgCan_1)
+	{
+		FlgCan_1 = 1;
+		CanTX();
+	}
+
+}
diff --git a/WDT.C b/WDT.C
new file mode 100644
index 0000000..9fcbc73
--- /dev/null
+++ b/WDT.C
@@ -0,0 +1,204 @@
+//****************************************************************************
+// @Module        Watch Dog Timer
+// @Filename      WDT.C
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains functions that use the WDT module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:32
+//
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,1)
+
+// USER CODE END
+
+
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+#include "MAIN.H"
+
+// USER CODE BEGIN (WDT_General,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @External Prototypes
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Local Functions
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_General,9)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Function      void WDT_vInit(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This is the initialization function of the 'Watch Dog 
+//                Timer' function library. It is assumed that the SFRs used 
+//                by this library are in their reset state. 
+//                
+//                The watchdog timer is used.
+//                The following SFR fields will be initialized:
+//                WDTREL - WDT reload value
+//                WDTIN  - WDT input frequency selection
+//                Then the watchdog timer will be refreshed.
+//                Note: The user has to take care that RMAP bit in SYSCON0 is 
+//                to be set while using the registers of Watch dog timer.
+//                Registers are WDTCON,WDTWINB,WDTREL,WDTH,WDTL
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Init,1)
+
+// USER CODE END
+
+void WDT_vInit(void)
+{
+  // USER CODE BEGIN (WDT_Init,2)
+
+  // USER CODE END
+
+  ///  the watchdog timer is used and it is enabled in INIT function,user has 
+  ///  to take care of WDT refresh
+  ///  the RMAP bit of SYSCON0 is set
+  ///  the input frequency is fSYS/128
+  ///  the watchdog timer reload value is 0xDB
+  ///  the watchdog timeout period is 50 ms
+
+  SFR_PAGE(_su1, noSST);         // switch to page1 without saving
+
+  MAIN_vUnlockProtecReg();       // open access to protected register
+
+  SET_RMAP(); 
+  WDTCON |= 0x04;     //   set   WDTEN
+  WDTREL = 0xDB;      //Watch dog timer reload register
+  WDTCON |= 0x03;                // set WDTRS,set WDTIN
+  RESET_RMAP(); 
+
+  MAIN_vlockProtecReg();         // close access to protected register
+  SFR_PAGE(_su0, noSST);         // switch to page0 with out saving
+
+  // USER CODE BEGIN (WDT_Init,3)
+
+  // USER CODE END
+
+
+
+} //  End of function WDT_vInit
+
+
+//****************************************************************************
+// @Function      void WDT_vDisable(void) 
+//
+//----------------------------------------------------------------------------
+// @Description   This function disables the WDT.
+//                pls refer to the Note on WDT_vInit function Description
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+void WDT_vDisable(void)
+{
+  SFR_PAGE(_su1, noSST);         // switch to page1 without saving
+
+  MAIN_vUnlockProtecReg();       // open access to protected register
+  SFR_PAGE(_su0, noSST);         // switch to page0 with out saving
+
+  SET_RMAP();
+  WDTCON &= ~(ubyte)0x04; //   clear WDTEN
+  RESET_RMAP();
+  SFR_PAGE(_su1, noSST);         // switch to page1 without saving
+
+  MAIN_vlockProtecReg();         // close access to protected register
+  SFR_PAGE(_su0, noSST);         // switch to page0 with out saving
+} //  End of function WDT_vDisable
+
+
+// USER CODE BEGIN (WDT_General,10)
+
+// USER CODE END
+
diff --git a/WDT.H b/WDT.H
new file mode 100644
index 0000000..8baf9f5
--- /dev/null
+++ b/WDT.H
@@ -0,0 +1,130 @@
+//****************************************************************************
+// @Module        Watch Dog Timer
+// @Filename      WDT.H
+// @Project       CL2.0.dav
+//----------------------------------------------------------------------------
+// @Controller    Infineon XC886CLM-8FF
+//
+// @Compiler      Keil
+//
+// @Codegenerator 1.3
+//
+// @Description:  This file contains all function prototypes and macros for 
+//                the WDT module.
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18 20:45:32
+//
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,1)
+
+// USER CODE END
+
+
+
+#ifndef _WDT_H_
+#define _WDT_H_
+
+//****************************************************************************
+// @Project Includes
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,2)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macros
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,3)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Defines
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,4)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Typedefs
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,5)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Imported Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,6)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Global Variables
+//****************************************************************************
+
+// USER CODE BEGIN (WDT_Header,7)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Prototypes Of Global Functions
+//****************************************************************************
+
+void WDT_vInit(void);
+void WDT_vDisable(void);
+
+// USER CODE BEGIN (WDT_Header,8)
+
+// USER CODE END
+
+
+//****************************************************************************
+// @Macro         WDT_vRefresh() 
+//
+//----------------------------------------------------------------------------
+// @Description   This macro refreshes the watchdog timer to the reload 
+//                value. The interrupts are disabled during execution of the 
+//                instructions that set bit WDTRS. 
+//                Note: The user has to take care that this macro is called 
+//                before expiry of the watchdog timer.
+//                pls refer to the Note on WDT_vInit function Description
+//
+//----------------------------------------------------------------------------
+// @Returnvalue   None
+//
+//----------------------------------------------------------------------------
+// @Parameters    None
+//
+//----------------------------------------------------------------------------
+// @Date          2025/1/18
+//
+//****************************************************************************
+
+#define WDT_vRefresh()  { EA = 0; SET_RMAP(); WDTCON |= 0x02; \
+   RESET_RMAP(); EA = 1; }
+
+
+//****************************************************************************
+// @Interrupt Vectors
+//****************************************************************************
+
+
+// USER CODE BEGIN (WDT_Header,9)
+
+// USER CODE END
+
+#endif  // ifndef _WDT_H_
diff --git a/XC88x_FLADDR.H b/XC88x_FLADDR.H
new file mode 100644
index 0000000..8bd905e
--- /dev/null
+++ b/XC88x_FLADDR.H
@@ -0,0 +1,876 @@
+//***************************************************************************
+//*     BootROM entries for XC88x-AA and AB Step                            *
+//*     Updated  : 2006-03-14                                               *
+//*     Copyright: (c) 2006 Infineon Technologies AG                        *
+//***************************************************************************
+
+#ifndef  __XC88x_FLADDR_H__
+#define  __XC88x_FLADDR_H__
+
+// User Configuration //
+#define XC88xAA           1    // Must be set to '1/0' (for AA step)
+#define XC88xAB           0    // Must be set to '1/0' (set to '1' for AB step)
+#define XC88xAC           0    // Must be set to '1/0' (Set to '1' for AC step)
+
+#define USE_BANK          3    // Register Bank used during Program / Erase
+                               // Default = 3
+#define WORDLINE_BUFFER_ADDRESS  0x80  // Starting address of the Buffer in the IRAM
+                                       // This Buffer will be used to store data
+                                       // before it is being programmed to flash
+#define USE_64BYTE_BUFFER 0	   // If PFlash will be programmed, set this to '1'
+                               // Programming PFLash will need 64Byte WordLine Buffer
+                               // Else, default buffer size is set to 32byte.
+#define USE_PFLERASE      1    // Set to '1' if PFlErase() routine is to be used.
+                               // Set to '0' if not used, to save some code space.
+#define USE_DLFERASE      1    // Set to '1' if DFlErase() routine is to be used.
+                               // Set to '0' if not used, to save some code space.
+
+// End of user configuration
+
+
+//+----------------------------------------------+
+//|   ROM entries taken from manual              |
+//|   and AppNote aboute programming the FLASH   |
+//|   used in XC88x_FLHANDLER.ASM                |
+//+----------------------------------------------+
+
+//====================================================================================
+#if (XC88xAA || XC88xAB || XC88xAC)             // Use the FSM to program / erase flash
+#define FLASH_ERASE_BROM_ENTRY          0xDFF9  // Erase Flash Bank
+#define FLASH_PROGRAM_BROM_ENTRY        0xDFF6  // Program Flash Bank.
+#define FLASH_ERASE_ABORT_BROM_ENTRY    0xDFF3  // Abort the on going erase process
+#define FLASH_READ_STATUS_BROM_ENTRY    0xDFF0  // Read Flash Status
+#endif
+#if (XC88xAA)
+#define FLASH_PROTECT_BROM_ENTRY        0xDB06
+#endif
+#if (XC88xAB || XC88xAC)
+#define FLASH_PROTECT_BROM_ENTRY        0xDFD8
+#endif
+//====================================================================================
+
+//+-----------------------------------------+
+//|   General definitions of used sources   |
+//+-----------------------------------------+
+// used buffer address in IRAM for Wordline erase/program 
+#if (XC88xAA || XC88xAB || XC88xAC)  
+#define MAGIC_MEMORY                  0x36  // reserve magic memory from D:0x36 .. D:0x3E
+#if (USE_64BYTE_BUFFER == 1)
+#define BYTES_PER_WORDLINE            64    //
+#else
+#define BYTES_PER_WORDLINE            32    //
+#endif
+#define RESERVED_BYTES                0x08
+#define PFLASH0                       0     // PFlash 0
+#define PFLASH1                       1     // PFlash 1
+#define PFLASH2	                      2     // PFlash 2
+#define DFLASH0                       3     // DFlash 0
+#define DFLASH1                       4     // DFlash 1
+
+#endif
+//+------------------------------------------------+
+//|   End of general definitions of used sources   |
+//+------------------------------------------------+
+
+
+
+//************************************************************************************************
+//*   Definitions of Bank-, Sector- and Wordlineaddresses
+//* 
+//************************************************************************************************
+// Sectors of PFlash0 for erasing -- transferred in  PFlErase() first parameter
+
+// Sector.07/Sector.06/Sector.05/Sector.04/Sector.03/Sector.02/ Sector.01/ Sector.00 /
+// ---------/---------/---------/---------/---------/Pfl0Sec02/ Pfl0Sec01/ Pfl0Sec00 /
+// ---------/---------/---------/---------/---------/-256B-4WL/-256B--4WL/-7.5k-120WL/
+// ---------/---------/---------/---------/---------/-0x1F00--/--0x1E00--/--0x0000----/
+#define PFL0_SEC0   0x0001
+#define PFL0_SEC1   0x0002
+#define PFL0_SEC2   0x0004
+
+// Sectors of PFlash1 for erasing -- transferred in  PFlErase() Second parameter
+
+// Sector.07/Sector.06/Sector.05/Sector.04/Sector.03/Sector.02/ Sector.01/ Sector.00  /
+// ---------/---------/---------/---------/---------/Pfl1Sec02/ Pfl1Sec01/ Pfl1Sec00  /
+// ---------/---------/---------/---------/---------/-256B-4WL/-256B--4WL/-7.5k-120WL/
+// ---------/---------/---------/---------/---------/-0x3F00--/--0x3E00--/--0x2000----/
+#define PFL1_SEC0   0x0001
+#define PFL1_SEC1   0x0002
+#define PFL1_SEC2   0x0004
+
+// Sectors of PFlash2 for erasing -- transferred in  PFlErase() Third parameter
+
+// Sector.07/Sector.06/Sector.05/Sector.04/Sector.03/Sector.02/ Sector.01/ Sector.00  /
+// ---------/---------/---------/---------/---------/Pfl2Sec02/ Pfl2Sec01/ Pfl2Sec00  /
+// ---------/---------/---------/---------/---------/-256B-4WL/-256B--4WL/-7.5k-120WL/
+// ---------/---------/---------/---------/---------/-0x5F00--/--0x5E00--/--0x4000----/
+#define PFL2_SEC0   0x0001
+#define PFL2_SEC1   0x0002
+#define PFL2_SEC2   0x0004
+
+// Sectors of DFlash 0 for erasing -- transfered in DFlErase() First parameter
+// DFlash 0 address is also mirrorred to 0x7xxx
+
+// Sector.15/Sector.14/Sector.13/Sector.12/Sector.11/Sector.10/Sector.09/Sector.08/
+// ---------/---------/---------/---------/---------/---------/Dfl0Sec09/Dfl0Sec08/
+// ---------/---------/---------/---------/---------/---------/-128-4WL-/-128-4WL-/
+// ---------/---------/---------/---------/---------/---------/--0xAF80-/--0xAF00-/
+ 
+// Sector.07/Sector.06/Sector.05/Sector.04/Sector.03/Sector.02/Sector.01/Sector.00/
+// Dfl0Sec07/Dfl0Sec06/Dfl0Sec05/Dfl0Sec04/Dfl0Sec03/Dfl0Sec02/Dfl0Sec01/Dfl0Sec00/
+// -128-4WL-/-128-4WL-/-256-8WL-/-256-8WL-/-512-16WL/-512-16WL/-1k--32WL/-1k--32WL/
+// --0xAE80-/--0xAE00-/--0xAD00-/--0xAC00-/-0xAA00--/-0xA800--/--0xA400-/--0xA000-/
+
+#define DFL0_SEC0   0x0001
+#define DFL0_SEC1   0x0002
+#define DFL0_SEC2   0x0004
+#define DFL0_SEC3   0x0008
+#define DFL0_SEC4   0x0010
+#define DFL0_SEC5   0x0020
+#define DFL0_SEC6   0x0040
+#define DFL0_SEC7   0x0080
+#define DFL0_SEC8   0x0100
+#define DFL0_SEC9   0x0200
+#define DFL0_SECALL 0x3FF
+
+// Sectors of DFlash 1 for erasing -- transfered in DFlErase() Second parameter
+// DFlash 1 address is also mirrorred to 0x6xxx
+
+// Sector.15/Sector.14/Sector.13/Sector.12/Sector.11/Sector.10/Sector.09/Sector.08/
+// ---------/---------/---------/---------/---------/---------/Dfl1Sec09/Dfl1Sec08/
+// ---------/---------/---------/---------/---------/---------/-128-4WL-/-128-4WL-/
+// ---------/---------/---------/---------/---------/---------/--0xAF80-/--0xAF00-/
+ 
+// Sector.07/Sector.06/Sector.05/Sector.04/Sector.03/Sector.02/Sector.01/Sector.00/
+// Dfl1Sec07/Dfl1Sec06/Dfl1Sec05/Dfl1Sec04/Dfl1Sec03/Dfl1Sec02/Dfl1Sec01/Dfl1Sec00/
+// -128-4WL-/-128-4WL-/-256-8WL-/-256-8WL-/-512-16WL/-512-16WL/-1k--32WL/-1k--32WL/
+// --0xAE80-/--0xAE00-/--0xAD00-/--0xAC00-/-0xAA00--/-0xA800--/--0xA400-/--0xA000-/
+
+#define DFL1_SEC0   0x0001
+#define DFL1_SEC1   0x0002
+#define DFL1_SEC2   0x0004
+#define DFL1_SEC3   0x0008
+#define DFL1_SEC4   0x0010
+#define DFL1_SEC5   0x0020
+#define DFL1_SEC6   0x0040
+#define DFL1_SEC7   0x0080
+#define DFL1_SEC8   0x0100
+#define DFL1_SEC9   0x0200
+#define DFL1_SECALL 0x3FF
+
+//###################################################################################
+// WordLine startaddresses for Sectors in PFlas 0, each WL with 64bytes
+
+// Sector 0 -- 7.5 kbytes -- 120 Wordlines
+#define PFL0_SEC0_WL00  0x0000
+#define PFL0_SEC0_WL01  0x0040
+#define PFL0_SEC0_WL02  0x0080
+#define PFL0_SEC0_WL03  0x00C0
+#define PFL0_SEC0_WL04  0x0100
+#define PFL0_SEC0_WL05  0x0140
+#define PFL0_SEC0_WL06  0x0180
+#define PFL0_SEC0_WL07  0x01C0
+#define PFL0_SEC0_WL08  0x0200
+#define PFL0_SEC0_WL09  0x0240
+#define PFL0_SEC0_WL10  0x0280
+#define PFL0_SEC0_WL11  0x02C0
+#define PFL0_SEC0_WL12  0x0300
+#define PFL0_SEC0_WL13  0x0340
+#define PFL0_SEC0_WL14  0x0380
+#define PFL0_SEC0_WL15  0x03C0
+#define PFL0_SEC0_WL16  0x0400
+#define PFL0_SEC0_WL17  0x0440
+#define PFL0_SEC0_WL18  0x0480
+#define PFL0_SEC0_WL19  0x04C0
+#define PFL0_SEC0_WL20  0x0500
+#define PFL0_SEC0_WL21  0x0540
+#define PFL0_SEC0_WL22  0x0580
+#define PFL0_SEC0_WL23  0x05C0
+#define PFL0_SEC0_WL24  0x0600
+#define PFL0_SEC0_WL25  0x0640
+#define PFL0_SEC0_WL26  0x0680
+#define PFL0_SEC0_WL27  0x06C0
+#define PFL0_SEC0_WL28  0x0700
+#define PFL0_SEC0_WL29  0x0740
+#define PFL0_SEC0_WL30  0x0780
+#define PFL0_SEC0_WL31  0x07C0
+#define PFL0_SEC0_WL32  0x0800
+#define PFL0_SEC0_WL33  0x0840
+#define PFL0_SEC0_WL34  0x0880
+#define PFL0_SEC0_WL35  0x08C0
+#define PFL0_SEC0_WL36  0x0900
+#define PFL0_SEC0_WL37  0x0940
+#define PFL0_SEC0_WL38  0x0980
+#define PFL0_SEC0_WL39  0x09C0
+#define PFL0_SEC0_WL40  0x0A00
+#define PFL0_SEC0_WL41  0x0A40
+#define PFL0_SEC0_WL42  0x0A80
+#define PFL0_SEC0_WL43  0x0AC0
+#define PFL0_SEC0_WL44  0x0B00
+#define PFL0_SEC0_WL45  0x0B40
+#define PFL0_SEC0_WL46  0x0B80
+#define PFL0_SEC0_WL47  0x0BC0
+#define PFL0_SEC0_WL48  0x0C00
+#define PFL0_SEC0_WL49  0x0C40
+#define PFL0_SEC0_WL50  0x0C80
+#define PFL0_SEC0_WL51  0x0CC0
+#define PFL0_SEC0_WL52  0x0D00
+#define PFL0_SEC0_WL53  0x0D40
+#define PFL0_SEC0_WL54  0x0D80
+#define PFL0_SEC0_WL55  0x0DC0
+#define PFL0_SEC0_WL56  0x0E00
+#define PFL0_SEC0_WL57  0x0E40
+#define PFL0_SEC0_WL58  0x0E80
+#define PFL0_SEC0_WL59  0x0EC0
+#define PFL0_SEC0_WL60  0x0F00
+#define PFL0_SEC0_WL61  0x0F40
+#define PFL0_SEC0_WL62  0x0F80
+#define PFL0_SEC0_WL63  0x0FC0
+#define PFL0_SEC0_WL64  0x1000
+#define PFL0_SEC0_WL65  0x1040
+#define PFL0_SEC0_WL66  0x1080
+#define PFL0_SEC0_WL67  0x10C0
+#define PFL0_SEC0_WL68  0x1100
+#define PFL0_SEC0_WL69  0x1140
+#define PFL0_SEC0_WL70  0x1180
+#define PFL0_SEC0_WL71  0x11C0
+#define PFL0_SEC0_WL72  0x1200
+#define PFL0_SEC0_WL73  0x1240
+#define PFL0_SEC0_WL74  0x1280
+#define PFL0_SEC0_WL75  0x12C0
+#define PFL0_SEC0_WL76  0x1300
+#define PFL0_SEC0_WL77  0x1340
+#define PFL0_SEC0_WL78  0x1380
+#define PFL0_SEC0_WL79  0x13C0
+#define PFL0_SEC0_WL80  0x1400
+#define PFL0_SEC0_WL81  0x1440
+#define PFL0_SEC0_WL82  0x1480
+#define PFL0_SEC0_WL83  0x14C0
+#define PFL0_SEC0_WL84  0x1500
+#define PFL0_SEC0_WL85  0x1540
+#define PFL0_SEC0_WL86  0x1580
+#define PFL0_SEC0_WL87  0x15C0
+#define PFL0_SEC0_WL88  0x1600
+#define PFL0_SEC0_WL89  0x1640
+#define PFL0_SEC0_WL90  0x1680
+#define PFL0_SEC0_WL91  0x16C0
+#define PFL0_SEC0_WL92  0x1700
+#define PFL0_SEC0_WL93  0x1740
+#define PFL0_SEC0_WL94  0x1780
+#define PFL0_SEC0_WL95  0x17C0
+#define PFL0_SEC0_WL96  0x1800
+#define PFL0_SEC0_WL97  0x1840
+#define PFL0_SEC0_WL98  0x1880
+#define PFL0_SEC0_WL99  0x18C0
+#define PFL0_SEC0_WL100 0x1900
+#define PFL0_SEC0_WL101 0x1940
+#define PFL0_SEC0_WL102 0x1980
+#define PFL0_SEC0_WL103 0x19C0
+#define PFL0_SEC0_WL104 0x1A00
+#define PFL0_SEC0_WL105 0x1A40
+#define PFL0_SEC0_WL106 0x1A80
+#define PFL0_SEC0_WL107 0x1AC0
+#define PFL0_SEC0_WL108 0x1B00
+#define PFL0_SEC0_WL109 0x1B40
+#define PFL0_SEC0_WL110 0x1B80
+#define PFL0_SEC0_WL111 0x1BC0
+#define PFL0_SEC0_WL112 0x1C00
+#define PFL0_SEC0_WL113 0x1C40
+#define PFL0_SEC0_WL114 0x1C80
+#define PFL0_SEC0_WL115 0x1CC0
+#define PFL0_SEC0_WL116 0x1D00
+#define PFL0_SEC0_WL117 0x1D40
+#define PFL0_SEC0_WL118 0x1D80
+#define PFL0_SEC0_WL119 0x1DC0
+
+// Sector 1 -- 256 bytes -- 4 Wordlines
+#define PFL0_SEC1_WL120 0x1E00
+#define PFL0_SEC1_WL121 0x1E40
+#define PFL0_SEC1_WL122 0x1E80
+#define PFL0_SEC1_WL123 0x1EC0
+
+// Sector 2 -- 256 bytes -- 4 Wordlines
+#define PFL0_SEC2_WL124 0x1F00
+#define PFL0_SEC2_WL125 0x1F40
+#define PFL0_SEC2_WL126 0x1F80
+#define PFL0_SEC2_WL127 0x1FC0
+
+//###################################################################################
+// WordLine startaddresses for Sectors in PFlash 1, each _WL with 64bytes
+
+// Sector 0 -- 7.5 kbytes -- 120 Wordlines
+#define PFL1_SEC0_WL00  0x2000
+#define PFL1_SEC0_WL01  0x2040
+#define PFL1_SEC0_WL02  0x2080
+#define PFL1_SEC0_WL03  0x20C0
+#define PFL1_SEC0_WL04  0x2100
+#define PFL1_SEC0_WL05  0x2140
+#define PFL1_SEC0_WL06  0x2180
+#define PFL1_SEC0_WL07  0x21C0
+#define PFL1_SEC0_WL08  0x2200
+#define PFL1_SEC0_WL09  0x2240
+#define PFL1_SEC0_WL10  0x2280
+#define PFL1_SEC0_WL11  0x22C0
+#define PFL1_SEC0_WL12  0x2300
+#define PFL1_SEC0_WL13  0x2340
+#define PFL1_SEC0_WL14  0x2380
+#define PFL1_SEC0_WL15  0x23C0
+#define PFL1_SEC0_WL16  0x2400
+#define PFL1_SEC0_WL17  0x2440
+#define PFL1_SEC0_WL18  0x2480
+#define PFL1_SEC0_WL19  0x24C0
+#define PFL1_SEC0_WL20  0x2500
+#define PFL1_SEC0_WL21  0x2540
+#define PFL1_SEC0_WL22  0x2580
+#define PFL1_SEC0_WL23  0x25C0
+#define PFL1_SEC0_WL24  0x2600
+#define PFL1_SEC0_WL25  0x2640
+#define PFL1_SEC0_WL26  0x2680
+#define PFL1_SEC0_WL27  0x26C0
+#define PFL1_SEC0_WL28  0x2700
+#define PFL1_SEC0_WL29  0x2740
+#define PFL1_SEC0_WL30  0x2780
+#define PFL1_SEC0_WL31  0x27C0
+#define PFL1_SEC0_WL32  0x2800
+#define PFL1_SEC0_WL33  0x2840
+#define PFL1_SEC0_WL34  0x2880
+#define PFL1_SEC0_WL35  0x28C0
+#define PFL1_SEC0_WL36  0x2900
+#define PFL1_SEC0_WL37  0x2940
+#define PFL1_SEC0_WL38  0x2980
+#define PFL1_SEC0_WL39  0x29C0
+#define PFL1_SEC0_WL40  0x2A00
+#define PFL1_SEC0_WL41  0x2A40
+#define PFL1_SEC0_WL42  0x2A80
+#define PFL1_SEC0_WL43  0x2AC0
+#define PFL1_SEC0_WL44  0x2B00
+#define PFL1_SEC0_WL45  0x2B40
+#define PFL1_SEC0_WL46  0x2B80
+#define PFL1_SEC0_WL47  0x2BC0
+#define PFL1_SEC0_WL48  0x2C00
+#define PFL1_SEC0_WL49  0x2C40
+#define PFL1_SEC0_WL50  0x2C80
+#define PFL1_SEC0_WL51  0x2CC0
+#define PFL1_SEC0_WL52  0x2D00
+#define PFL1_SEC0_WL53  0x2D40
+#define PFL1_SEC0_WL54  0x2D80
+#define PFL1_SEC0_WL55  0x2DC0
+#define PFL1_SEC0_WL56  0x2E00
+#define PFL1_SEC0_WL57  0x2E40
+#define PFL1_SEC0_WL58  0x2E80
+#define PFL1_SEC0_WL59  0x2EC0
+#define PFL1_SEC0_WL60  0x2F00
+#define PFL1_SEC0_WL61  0x2F40
+#define PFL1_SEC0_WL62  0x2F80
+#define PFL1_SEC0_WL63  0x2FC0
+#define PFL1_SEC0_WL64  0x3000
+#define PFL1_SEC0_WL65  0x3040
+#define PFL1_SEC0_WL66  0x3080
+#define PFL1_SEC0_WL67  0x30C0
+#define PFL1_SEC0_WL68  0x3100
+#define PFL1_SEC0_WL69  0x3140
+#define PFL1_SEC0_WL70  0x3180
+#define PFL1_SEC0_WL71  0x31C0
+#define PFL1_SEC0_WL72  0x3200
+#define PFL1_SEC0_WL73  0x3240
+#define PFL1_SEC0_WL74  0x3280
+#define PFL1_SEC0_WL75  0x32C0
+#define PFL1_SEC0_WL76  0x3300
+#define PFL1_SEC0_WL77  0x3340
+#define PFL1_SEC0_WL78  0x3380
+#define PFL1_SEC0_WL79  0x33C0
+#define PFL1_SEC0_WL80  0x3400
+#define PFL1_SEC0_WL81  0x3440
+#define PFL1_SEC0_WL82  0x3480
+#define PFL1_SEC0_WL83  0x34C0
+#define PFL1_SEC0_WL84  0x3500
+#define PFL1_SEC0_WL85  0x3540
+#define PFL1_SEC0_WL86  0x3580
+#define PFL1_SEC0_WL87  0x35C0
+#define PFL1_SEC0_WL88  0x3600
+#define PFL1_SEC0_WL89  0x3640
+#define PFL1_SEC0_WL90  0x3680
+#define PFL1_SEC0_WL91  0x36C0
+#define PFL1_SEC0_WL92  0x3700
+#define PFL1_SEC0_WL93  0x3740
+#define PFL1_SEC0_WL94  0x3780
+#define PFL1_SEC0_WL95  0x37C0
+#define PFL1_SEC0_WL96  0x3800
+#define PFL1_SEC0_WL97  0x3840
+#define PFL1_SEC0_WL98  0x3880
+#define PFL1_SEC0_WL99  0x38C0
+#define PFL1_SEC0_WL100 0x3900
+#define PFL1_SEC0_WL101 0x3940
+#define PFL1_SEC0_WL102 0x3980
+#define PFL1_SEC0_WL103 0x39C0
+#define PFL1_SEC0_WL104 0x3A00
+#define PFL1_SEC0_WL105 0x3A40
+#define PFL1_SEC0_WL106 0x3A80
+#define PFL1_SEC0_WL107 0x3AC0
+#define PFL1_SEC0_WL108 0x3B00
+#define PFL1_SEC0_WL109 0x3B40
+#define PFL1_SEC0_WL110 0x3B80
+#define PFL1_SEC0_WL111 0x3BC0
+#define PFL1_SEC0_WL112 0x3C00
+#define PFL1_SEC0_WL113 0x3C40
+#define PFL1_SEC0_WL114 0x3C80
+#define PFL1_SEC0_WL115 0x3CC0
+#define PFL1_SEC0_WL116 0x3D00
+#define PFL1_SEC0_WL117 0x3D40
+#define PFL1_SEC0_WL118 0x3D80
+#define PFL1_SEC0_WL119 0x3DC0
+
+// Sector 1 -- 256 bytes -- 4 Wordlines
+#define PFL1_SEC1_WL120 0x3E00
+#define PFL1_SEC1_WL121 0x3E40
+#define PFL1_SEC1_WL122 0x3E80
+#define PFL1_SEC1_WL123 0x3EC0
+
+// Sector 2 -- 256 bytes -- 4 Wordlines
+#define PFL1_SEC2_WL124 0x3F00
+#define PFL1_SEC2_WL125 0x3F40
+#define PFL1_SEC2_WL126 0x3F80
+#define PFL1_SEC2_WL127 0x3FC0
+
+//###################################################################################
+// WordLine startaddresses for Sectors in PFlash 2, each WL with 64bytes
+
+// Sector 0 -- 7.5 kbytes -- 120 Wordlines
+#define PFL2_SEC0_WL00  0x4000
+#define PFL2_SEC0_WL01  0x4040
+#define PFL2_SEC0_WL02  0x4080
+#define PFL2_SEC0_WL03  0x40C0
+#define PFL2_SEC0_WL04  0x4100
+#define PFL2_SEC0_WL05  0x4140
+#define PFL2_SEC0_WL06  0x4180
+#define PFL2_SEC0_WL07  0x41C0
+#define PFL2_SEC0_WL08  0x4200
+#define PFL2_SEC0_WL09  0x4240
+#define PFL2_SEC0_WL10  0x4280
+#define PFL2_SEC0_WL11  0x42C0
+#define PFL2_SEC0_WL12  0x4300
+#define PFL2_SEC0_WL13  0x4340
+#define PFL2_SEC0_WL14  0x4380
+#define PFL2_SEC0_WL15  0x43C0
+#define PFL2_SEC0_WL16  0x4400
+#define PFL2_SEC0_WL17  0x4440
+#define PFL2_SEC0_WL18  0x4480
+#define PFL2_SEC0_WL19  0x44C0
+#define PFL2_SEC0_WL20  0x4500
+#define PFL2_SEC0_WL21  0x4540
+#define PFL2_SEC0_WL22  0x4580
+#define PFL2_SEC0_WL23  0x45C0
+#define PFL2_SEC0_WL24  0x4600
+#define PFL2_SEC0_WL25  0x4640
+#define PFL2_SEC0_WL26  0x4680
+#define PFL2_SEC0_WL27  0x46C0
+#define PFL2_SEC0_WL28  0x4700
+#define PFL2_SEC0_WL29  0x4740
+#define PFL2_SEC0_WL30  0x4780
+#define PFL2_SEC0_WL31  0x47C0
+#define PFL2_SEC0_WL32  0x4800
+#define PFL2_SEC0_WL33  0x4840
+#define PFL2_SEC0_WL34  0x4880
+#define PFL2_SEC0_WL35  0x48C0
+#define PFL2_SEC0_WL36  0x4900
+#define PFL2_SEC0_WL37  0x4940
+#define PFL2_SEC0_WL38  0x4980
+#define PFL2_SEC0_WL39  0x49C0
+#define PFL2_SEC0_WL40  0x4A00
+#define PFL2_SEC0_WL41  0x4A40
+#define PFL2_SEC0_WL42  0x4A80
+#define PFL2_SEC0_WL43  0x4AC0
+#define PFL2_SEC0_WL44  0x4B00
+#define PFL2_SEC0_WL45  0x4B40
+#define PFL2_SEC0_WL46  0x4B80
+#define PFL2_SEC0_WL47  0x4BC0
+#define PFL2_SEC0_WL48  0x4C00
+#define PFL2_SEC0_WL49  0x4C40
+#define PFL2_SEC0_WL50  0x4C80
+#define PFL2_SEC0_WL51  0x4CC0
+#define PFL2_SEC0_WL52  0x4D00
+#define PFL2_SEC0_WL53  0x4D40
+#define PFL2_SEC0_WL54  0x4D80
+#define PFL2_SEC0_WL55  0x4DC0
+#define PFL2_SEC0_WL56  0x4E00
+#define PFL2_SEC0_WL57  0x4E40
+#define PFL2_SEC0_WL58  0x4E80
+#define PFL2_SEC0_WL59  0x4EC0
+#define PFL2_SEC0_WL60  0x4F00
+#define PFL2_SEC0_WL61  0x4F40
+#define PFL2_SEC0_WL62  0x4F80
+#define PFL2_SEC0_WL63  0x4FC0
+#define PFL2_SEC0_WL64  0x5000
+#define PFL2_SEC0_WL65  0x5040
+#define PFL2_SEC0_WL66  0x5080
+#define PFL2_SEC0_WL67  0x50C0
+#define PFL2_SEC0_WL68  0x5100
+#define PFL2_SEC0_WL69  0x5140
+#define PFL2_SEC0_WL70  0x5180
+#define PFL2_SEC0_WL71  0x51C0
+#define PFL2_SEC0_WL72  0x5200
+#define PFL2_SEC0_WL73  0x5240
+#define PFL2_SEC0_WL74  0x5280
+#define PFL2_SEC0_WL75  0x52C0
+#define PFL2_SEC0_WL76  0x5300
+#define PFL2_SEC0_WL77  0x5340
+#define PFL2_SEC0_WL78  0x5380
+#define PFL2_SEC0_WL79  0x53C0
+#define PFL2_SEC0_WL80  0x5400
+#define PFL2_SEC0_WL81  0x5440
+#define PFL2_SEC0_WL82  0x5480
+#define PFL2_SEC0_WL83  0x54C0
+#define PFL2_SEC0_WL84  0x5500
+#define PFL2_SEC0_WL85  0x5540
+#define PFL2_SEC0_WL86  0x5580
+#define PFL2_SEC0_WL87  0x55C0
+#define PFL2_SEC0_WL88  0x5600
+#define PFL2_SEC0_WL89  0x5640
+#define PFL2_SEC0_WL90  0x5680
+#define PFL2_SEC0_WL91  0x56C0
+#define PFL2_SEC0_WL92  0x5700
+#define PFL2_SEC0_WL93  0x5740
+#define PFL2_SEC0_WL94  0x5780
+#define PFL2_SEC0_WL95  0x57C0
+#define PFL2_SEC0_WL96  0x5800
+#define PFL2_SEC0_WL97  0x5840
+#define PFL2_SEC0_WL98  0x5880
+#define PFL2_SEC0_WL99  0x58C0
+#define PFL2_SEC0_WL100 0x5900
+#define PFL2_SEC0_WL101 0x5940
+#define PFL2_SEC0_WL102 0x5980
+#define PFL2_SEC0_WL103 0x59C0
+#define PFL2_SEC0_WL104 0x5A00
+#define PFL2_SEC0_WL105 0x5A40
+#define PFL2_SEC0_WL106 0x5A80
+#define PFL2_SEC0_WL107 0x5AC0
+#define PFL2_SEC0_WL108 0x5B00
+#define PFL2_SEC0_WL109 0x5B40
+#define PFL2_SEC0_WL110 0x5B80
+#define PFL2_SEC0_WL111 0x5BC0
+#define PFL2_SEC0_WL112 0x5C00
+#define PFL2_SEC0_WL113 0x5C40
+#define PFL2_SEC0_WL114 0x5C80
+#define PFL2_SEC0_WL115 0x5CC0
+#define PFL2_SEC0_WL116 0x5D00
+#define PFL2_SEC0_WL117 0x5D40
+#define PFL2_SEC0_WL118 0x5D80
+#define PFL2_SEC0_WL119 0x5DC0
+
+// Sector 1 -- 256 bytes -- 4 Wordlines
+#define PFL2_SEC1_WL120 0x5E00
+#define PFL2_SEC1_WL121 0x5E40
+#define PFL2_SEC1_WL122 0x5E80
+#define PFL2_SEC1_WL123 0x5EC0
+
+// Sector 2 -- 256 bytes -- 4 Wordlines
+#define PFL2_SEC2_WL124 0x5F00
+#define PFL2_SEC2_WL125 0x5F40
+#define PFL2_SEC2_WL126 0x5F80
+#define PFL2_SEC2_WL127 0x5FC0
+
+//###################################################################################
+// WordLine startaddresses for sectors in DFlash 0, each WL with 32bytes
+// DFlash 0 address is also mirrorred to 0x7xxx
+
+// Sector 0 -- 1024 bytes -- 32 Wordlines
+#define DFL0_SEC0_WL00  0xA000
+#define DFL0_SEC0_WL01  0xA020
+#define DFL0_SEC0_WL02  0xA040
+#define DFL0_SEC0_WL03  0xA060
+#define DFL0_SEC0_WL04  0xA080
+#define DFL0_SEC0_WL05  0xA0A0
+#define DFL0_SEC0_WL06  0xA0C0
+#define DFL0_SEC0_WL07  0xA0E0
+#define DFL0_SEC0_WL08  0xA100
+#define DFL0_SEC0_WL09  0xA120
+#define DFL0_SEC0_WL10  0xA140
+#define DFL0_SEC0_WL11  0xA160
+#define DFL0_SEC0_WL12  0xA180
+#define DFL0_SEC0_WL13  0xA1A0
+#define DFL0_SEC0_WL14  0xA1C0
+#define DFL0_SEC0_WL15  0xA1E0
+#define DFL0_SEC0_WL16  0xA200
+#define DFL0_SEC0_WL17  0xA220
+#define DFL0_SEC0_WL18  0xA240
+#define DFL0_SEC0_WL19  0xA260
+#define DFL0_SEC0_WL20  0xA280
+#define DFL0_SEC0_WL21  0xA2A0
+#define DFL0_SEC0_WL22  0xA2C0
+#define DFL0_SEC0_WL23  0xA2E0
+#define DFL0_SEC0_WL24  0xA300
+#define DFL0_SEC0_WL25  0xA320
+#define DFL0_SEC0_WL26  0xA340
+#define DFL0_SEC0_WL27  0xA360
+#define DFL0_SEC0_WL28  0xA380
+#define DFL0_SEC0_WL29  0xA3A0
+#define DFL0_SEC0_WL30  0xA3C0
+#define DFL0_SEC0_WL31  0xA3E0
+
+// Sector 1 -- 1024 bytes -- 32 Wordlines
+#define DFL0_SEC1_WL32  0xA400
+#define DFL0_SEC1_WL33  0xA420
+#define DFL0_SEC1_WL34  0xA440
+#define DFL0_SEC1_WL35  0xA460
+#define DFL0_SEC1_WL36  0xA480
+#define DFL0_SEC1_WL37  0xA4A0
+#define DFL0_SEC1_WL38  0xA4C0
+#define DFL0_SEC1_WL39  0xA4E0
+#define DFL0_SEC1_WL40  0xA500
+#define DFL0_SEC1_WL41  0xA520
+#define DFL0_SEC1_WL42  0xA540
+#define DFL0_SEC1_WL43  0xA560
+#define DFL0_SEC1_WL44  0xA580
+#define DFL0_SEC1_WL45  0xA5A0
+#define DFL0_SEC1_WL46  0xA5C0
+#define DFL0_SEC1_WL47  0xA5E0
+#define DFL0_SEC1_WL48  0xA600
+#define DFL0_SEC1_WL49  0xA620
+#define DFL0_SEC1_WL50  0xA640
+#define DFL0_SEC1_WL51  0xA660
+#define DFL0_SEC1_WL52  0xA680
+#define DFL0_SEC1_WL53  0xA6A0
+#define DFL0_SEC1_WL54  0xA6C0
+#define DFL0_SEC1_WL55  0xA6E0
+#define DFL0_SEC1_WL56  0xA700
+#define DFL0_SEC1_WL57  0xA720
+#define DFL0_SEC1_WL58  0xA740
+#define DFL0_SEC1_WL59  0xA760
+#define DFL0_SEC1_WL60  0xA780
+#define DFL0_SEC1_WL61  0xA7A0
+#define DFL0_SEC1_WL62  0xA7C0
+#define DFL0_SEC1_WL63  0xA7E0
+
+// Sector 2 -- 512 bytes -- 16 Wordlines
+#define DFL0_SEC2_WL64  0xA800
+#define DFL0_SEC2_WL65  0xA820
+#define DFL0_SEC2_WL66  0xA840
+#define DFL0_SEC2_WL67  0xA860
+#define DFL0_SEC2_WL68  0xA880
+#define DFL0_SEC2_WL69  0xA8A0
+#define DFL0_SEC2_WL70  0xA8C0
+#define DFL0_SEC2_WL71  0xA8E0
+#define DFL0_SEC2_WL72  0xA900
+#define DFL0_SEC2_WL73  0xA920
+#define DFL0_SEC2_WL74  0xA940
+#define DFL0_SEC2_WL75  0xA960
+#define DFL0_SEC2_WL76  0xA980
+#define DFL0_SEC2_WL77  0xA9A0
+#define DFL0_SEC2_WL78  0xA9C0
+#define DFL0_SEC2_WL79  0xA9E0
+
+// Sector 3 -- 512 bytes -- 16 Wordlines
+#define DFL0_SEC3_WL80  0xAA00
+#define DFL0_SEC3_WL81  0xAA20
+#define DFL0_SEC3_WL82  0xAA40
+#define DFL0_SEC3_WL83  0xAA60
+#define DFL0_SEC3_WL84  0xAA80
+#define DFL0_SEC3_WL85  0xAAA0
+#define DFL0_SEC3_WL86  0xAAC0
+#define DFL0_SEC3_WL87  0xAAE0
+#define DFL0_SEC3_WL88  0xAB00
+#define DFL0_SEC3_WL89  0xAB20
+#define DFL0_SEC3_WL90  0xAB40
+#define DFL0_SEC3_WL91  0xAB60
+#define DFL0_SEC3_WL92  0xAB80
+#define DFL0_SEC3_WL93  0xABA0
+#define DFL0_SEC3_WL94  0xABC0
+#define DFL0_SEC3_WL95  0xABE0
+
+// Sector 4 -- 256 bytes -- 8 Wordlines
+#define DFL0_SEC4_WL96  0xAC00
+#define DFL0_SEC4_WL97  0xAC20
+#define DFL0_SEC4_WL98  0xAC40
+#define DFL0_SEC4_WL99  0xAC60
+#define DFL0_SEC4_WL100 0xAC80
+#define DFL0_SEC4_WL101 0xACA0
+#define DFL0_SEC4_WL102 0xACC0
+#define DFL0_SEC4_WL103 0xACE0
+
+// Sector 5 -- 256 bytes -- 8 Wordlines
+#define DFL0_SEC5_WL104 0xAD00
+#define DFL0_SEC5_WL105 0xAD20
+#define DFL0_SEC5_WL106 0xAD40
+#define DFL0_SEC5_WL107 0xAD60
+#define DFL0_SEC5_WL108 0xAD80
+#define DFL0_SEC5_WL109 0xADA0
+#define DFL0_SEC5_WL110 0xADC0
+#define DFL0_SEC5_WL111 0xADE0
+
+// Sector 6 -- 128 bytes -- 4 Wordlines
+#define DFL0_SEC6_WL112 0xAE00
+#define DFL0_SEC6_WL113 0xAE20
+#define DFL0_SEC6_WL114 0xAE40
+#define DFL0_SEC6_WL115 0xAE60
+
+// Sector 7 -- 128 bytes -- 4 Wordlines
+#define DFL0_SEC7_WL116 0xAE80
+#define DFL0_SEC7_WL117 0xAEA0
+#define DFL0_SEC7_WL118 0xAEC0
+#define DFL0_SEC7_WL119 0xAEE0
+
+// Sector 8 -- 128 bytes -- 4 Wordlines
+#define DFL0_SEC8_WL120 0xAF00
+#define DFL0_SEC8_WL121 0xAF20
+#define DFL0_SEC8_WL122 0xAF40
+#define DFL0_SEC8_WL123 0xAF60
+
+// Sector 9 -- 128 bytes -- 4 Wordlines
+#define DFL0_SEC9_WL124 0xAF80
+#define DFL0_SEC9_WL125 0xAFA0
+#define DFL0_SEC9_WL126 0xAFC0
+#define DFL0_SEC9_WL127 0xAFE0
+
+//###################################################################################
+// WordLine startaddresses for sectors in DFlash 1, each WL with 32bytes
+// DFlash 0 address is also mirrorred to 0x6xxx
+
+// Sector 0 -- 1024 bytes -- 32 Wordlines
+#define DFL1_SEC0_WL00  0xA000
+#define DFL1_SEC0_WL01  0xA020
+#define DFL1_SEC0_WL02  0xA040
+#define DFL1_SEC0_WL03  0xA060
+#define DFL1_SEC0_WL04  0xA080
+#define DFL1_SEC0_WL05  0xA0A0
+#define DFL1_SEC0_WL06  0xA0C0
+#define DFL1_SEC0_WL07  0xA0E0
+#define DFL1_SEC0_WL08  0xA100
+#define DFL1_SEC0_WL09  0xA120
+#define DFL1_SEC0_WL10  0xA140
+#define DFL1_SEC0_WL11  0xA160
+#define DFL1_SEC0_WL12  0xA180
+#define DFL1_SEC0_WL13  0xA1A0
+#define DFL1_SEC0_WL14  0xA1C0
+#define DFL1_SEC0_WL15  0xA1E0
+#define DFL1_SEC0_WL16  0xA200
+#define DFL1_SEC0_WL17  0xA220
+#define DFL1_SEC0_WL18  0xA240
+#define DFL1_SEC0_WL19  0xA260
+#define DFL1_SEC0_WL20  0xA280
+#define DFL1_SEC0_WL21  0xA2A0
+#define DFL1_SEC0_WL22  0xA2C0
+#define DFL1_SEC0_WL23  0xA2E0
+#define DFL1_SEC0_WL24  0xA300
+#define DFL1_SEC0_WL25  0xA320
+#define DFL1_SEC0_WL26  0xA340
+#define DFL1_SEC0_WL27  0xA360
+#define DFL1_SEC0_WL28  0xA380
+#define DFL1_SEC0_WL29  0xA3A0
+#define DFL1_SEC0_WL30  0xA3C0
+#define DFL1_SEC0_WL31  0xA3E0
+
+// Sector 1 -- 1024 bytes -- 32 Wordlines
+#define DFL1_SEC1_WL32  0xA400
+#define DFL1_SEC1_WL33  0xA420
+#define DFL1_SEC1_WL34  0xA440
+#define DFL1_SEC1_WL35  0xA460
+#define DFL1_SEC1_WL36  0xA480
+#define DFL1_SEC1_WL37  0xA4A0
+#define DFL1_SEC1_WL38  0xA4C0
+#define DFL1_SEC1_WL39  0xA4E0
+#define DFL1_SEC1_WL40  0xA500
+#define DFL1_SEC1_WL41  0xA520
+#define DFL1_SEC1_WL42  0xA540
+#define DFL1_SEC1_WL43  0xA560
+#define DFL1_SEC1_WL44  0xA580
+#define DFL1_SEC1_WL45  0xA5A0
+#define DFL1_SEC1_WL46  0xA5C0
+#define DFL1_SEC1_WL47  0xA5E0
+#define DFL1_SEC1_WL48  0xA600
+#define DFL1_SEC1_WL49  0xA620
+#define DFL1_SEC1_WL50  0xA640
+#define DFL1_SEC1_WL51  0xA660
+#define DFL1_SEC1_WL52  0xA680
+#define DFL1_SEC1_WL53  0xA6A0
+#define DFL1_SEC1_WL54  0xA6C0
+#define DFL1_SEC1_WL55  0xA6E0
+#define DFL1_SEC1_WL56  0xA700
+#define DFL1_SEC1_WL57  0xA720
+#define DFL1_SEC1_WL58  0xA740
+#define DFL1_SEC1_WL59  0xA760
+#define DFL1_SEC1_WL60  0xA780
+#define DFL1_SEC1_WL61  0xA7A0
+#define DFL1_SEC1_WL62  0xA7C0
+#define DFL1_SEC1_WL63  0xA7E0
+
+// Sector 2 -- 512 bytes -- 16 Wordlines
+#define DFL1_SEC2_WL64  0xA800
+#define DFL1_SEC2_WL65  0xA820
+#define DFL1_SEC2_WL66  0xA840
+#define DFL1_SEC2_WL67  0xA860
+#define DFL1_SEC2_WL68  0xA880
+#define DFL1_SEC2_WL69  0xA8A0
+#define DFL1_SEC2_WL70  0xA8C0
+#define DFL1_SEC2_WL71  0xA8E0
+#define DFL1_SEC2_WL72  0xA900
+#define DFL1_SEC2_WL73  0xA920
+#define DFL1_SEC2_WL74  0xA940
+#define DFL1_SEC2_WL75  0xA960
+#define DFL1_SEC2_WL76  0xA980
+#define DFL1_SEC2_WL77  0xA9A0
+#define DFL1_SEC2_WL78  0xA9C0
+#define DFL1_SEC2_WL79  0xA9E0
+
+// Sector 3 -- 512 bytes -- 16 Wordlines
+#define DFL1_SEC3_WL80  0xAA00
+#define DFL1_SEC3_WL81  0xAA20
+#define DFL1_SEC3_WL82  0xAA40
+#define DFL1_SEC3_WL83  0xAA60
+#define DFL1_SEC3_WL84  0xAA80
+#define DFL1_SEC3_WL85  0xAAA0
+#define DFL1_SEC3_WL86  0xAAC0
+#define DFL1_SEC3_WL87  0xAAE0
+#define DFL1_SEC3_WL88  0xAB00
+#define DFL1_SEC3_WL89  0xAB20
+#define DFL1_SEC3_WL90  0xAB40
+#define DFL1_SEC3_WL91  0xAB60
+#define DFL1_SEC3_WL92  0xAB80
+#define DFL1_SEC3_WL93  0xABA0
+#define DFL1_SEC3_WL94  0xABC0
+#define DFL1_SEC3_WL95  0xABE0
+
+// Sector 4 -- 256 bytes -- 8 Wordlines
+#define DFL1_SEC4_WL96  0xAC00
+#define DFL1_SEC4_WL97  0xAC20
+#define DFL1_SEC4_WL98  0xAC40
+#define DFL1_SEC4_WL99  0xAC60
+#define DFL1_SEC4_WL100 0xAC80
+#define DFL1_SEC4_WL101 0xACA0
+#define DFL1_SEC4_WL102 0xACC0
+#define DFL1_SEC4_WL103 0xACE0
+
+// Sector 5 -- 256 bytes -- 8 Wordlines
+#define DFL1_SEC5_WL104 0xAD00
+#define DFL1_SEC5_WL105 0xAD20
+#define DFL1_SEC5_WL106 0xAD40
+#define DFL1_SEC5_WL107 0xAD60
+#define DFL1_SEC5_WL108 0xAD80
+#define DFL1_SEC5_WL109 0xADA0
+#define DFL1_SEC5_WL110 0xADC0
+#define DFL1_SEC5_WL111 0xADE0
+
+// Sector 6 -- 128 bytes -- 4 Wordlines
+#define DFL1_SEC6_WL112 0xAE00
+#define DFL1_SEC6_WL113 0xAE20
+#define DFL1_SEC6_WL114 0xAE40
+#define DFL1_SEC6_WL115 0xAE60
+
+// Sector 7 -- 128 bytes -- 4 Wordlines
+#define DFL1_SEC7_WL116 0xAE80
+#define DFL1_SEC7_WL117 0xAEA0
+#define DFL1_SEC7_WL118 0xAEC0
+#define DFL1_SEC7_WL119 0xAEE0
+
+// Sector 8 -- 128 bytes -- 4 Wordlines
+#define DFL1_SEC8_WL120 0xAF00
+#define DFL1_SEC8_WL121 0xAF20
+#define DFL1_SEC8_WL122 0xAF40
+#define DFL1_SEC8_WL123 0xAF60
+
+// Sector 9 -- 128 bytes -- 4 Wordlines
+#define DFL1_SEC9_WL124 0xAF80
+#define DFL1_SEC9_WL125 0xAFA0
+#define DFL1_SEC9_WL126 0xAFC0
+#define DFL1_SEC9_WL127 0xAFE0
+
+#endif  // #ifndef  __XC88x_FLADDR_H__
diff --git a/XC88x_FLHANDLER.ASM b/XC88x_FLHANDLER.ASM
new file mode 100644
index 0000000..6c49a6b
--- /dev/null
+++ b/XC88x_FLHANDLER.ASM
@@ -0,0 +1,166 @@
+;************************************************************************************
+;*  FILE        : XC88x_FLHANDLER.ASM                                               *
+;*  DESCRIPTION : Flash handler routine for XC88x AA and AB                                *
+;*  COPYRIGHT   : (c) 2006 Infineon Technologies AG                                 *
+;*  UPDATED     : 14/03/2006                                                        *
+;************************************************************************************
+$ NOMOD51
+$ DEBUG
+#include "XC88x_FLADDR.H"  
+
+FLASH_ERASE        CODE  FLASH_ERASE_BROM_ENTRY
+FLASH_PROG         CODE  FLASH_PROGRAM_BROM_ENTRY
+FLASH_ERASE_ABORT  CODE  FLASH_ERASE_ABORT_BROM_ENTRY
+FLASH_READ_STATUS  CODE  FLASH_READ_STATUS_BROM_ENTRY
+FLASH_PROTECT      CODE  FLASH_PROTECT_BROM_ENTRY
+     
+DSEG AT  MAGIC_MEMORY
+DS   RESERVED_BYTES                        ; Reserved for FLASH Handler in Boot ROM
+
+
+
+
+;------------------------------------------------------------------------------------------
+; Function Name   : bit DFlErase (unsigned int DFlash0Sector, unsigned int DFlash1Sector)
+; Description     : Erase DFlash Sectors (Bank3 and Bank4)
+; Input Parameter : DFlash0Sector => Bit0 = Erase Sector0
+;                                    Bit1 = Erase Sector1
+;                                    Bit2 = Erase Sector2
+;                                    Bit3 = Erase Sector3
+;                                    Bit4 = Erase Sector4
+;                                    Bit5 = Erase Sector5
+;                                    Bit6 = Erase Sector6
+;                                    Bit7 = Erase Sector7
+;                                    Bit8 = Erase Sector8
+;                                    Bit9 = Erase Sector9
+;                   DFlash1Sector => Bit0 = Erase Sector0
+;                                    Bit1 = Erase Sector1
+;                                    Bit2 = Erase Sector2
+;                                    Bit3 = Erase Sector3
+;                                    Bit4 = Erase Sector4
+;                                    Bit5 = Erase Sector5
+;                                    Bit6 = Erase Sector6
+;                                    Bit7 = Erase Sector7
+;                                    Bit8 = Erase Sector8
+;                                    Bit9 = Erase Sector9
+;                                                   
+;                   e.g: DFlash0Sector = 0x202
+;                        DFlash1Sector = 0x380
+;                         ==> Will erase Bank3 Sector 1
+;                                  erase Bank3 Sector 9
+;                                  erase Bank4 Sector 7
+;                                  erase Bank4 Sector 8
+;                                  erase Bank4 Sector 9
+; Return Value    : Bit => 1 = Successfull
+;                          0 = Fail
+; Required Stack Size = 12
+;------------------------------------------------------------------------------------------
+#if USE_DLFERASE
+?PR?_DFlErase?XC88x_FLHANDLER SEGMENT CODE    
+RSEG ?PR?_DFlErase?XC88x_FLHANDLER
+PUBLIC _DFlErase
+_DFlErase:
+  USING  USE_BANK
+  MOV  AR1,R6  ; BANK3
+  MOV  AR0,R7  ; BANK3
+
+  MOV  AR4,R4 ; BANK4
+  MOV  AR3,R5 ; BANK4
+
+  CLR    A
+  MOV    AR5, A ; BANK0
+  MOV    AR6, A ; BANK1
+  MOV    AR7, A ; BANK2
+
+  PUSH   PSW
+	PUSH   ACC
+	PUSH   B
+#if (USE_BANK == 0)
+  ANL    PSW, #0xE7      ; Set to Bank0
+#elseif (USE_BANK == 1)
+  SETB   PSW.3
+  CLR    PSW.4
+#elif (USE_BANK == 2)
+  CLR    PSW.3
+  SETB   PSW.4
+#elif (USE_BANK == 3)
+  ORL    PSW, #0x18
+#endif 
+
+  LCALL  FLASH_ERASE
+  JC     _derase_fail
+	POP    B
+	POP    ACC
+  POP    PSW
+  SETB   C
+  RET
+_derase_fail:
+	POP    B
+	POP    ACC
+  POP    PSW
+  CLR    C
+RET
+#endif
+
+;------------------------------------------------------------------------------------------
+; Function Name:   bit FlProg(unsigned char idata *WlBuf)
+; Description:     Program the 32byte data in the WlBuf to the EEPROM
+;                  When calling this function, user should already programmed
+;                  the DPTR with the EEPROM address (aligned to 32byte boundary)
+; Input Parameter: *WlBuf  ==> The pointer to the starting location of the buffer
+;                              in the IDATA memory.
+; Return Value:    Bit => 1 = Successfull
+;                         0 = Fail
+; Required Stack Size = 12
+;------------------------------------------------------------------------------------------
+?PR?_FlProg?XC88x_FLHANDLER SEGMENT CODE    
+RSEG ?PR?_FlProg?XC88x_FLHANDLER
+PUBLIC _FlProg
+_FlProg:
+using USE_BANK
+  MOV   AR0,R7          ; move C51 parameter registers to AR0
+                       ; this is the pointer to the WLBuf
+											 
+;	MOV		A,#0x6F			
+;	MOV		DPH,A
+;	MOV		A,#0x0		; the DPL will = DPL+0x20 after one successful program	
+;	MOV		DPL,A											 
+											 
+  PUSH   PSW
+	PUSH   ACC
+	PUSH   B
+#if (USE_BANK == 0)
+  ANL    PSW, #0xE7      ; Set to Bank0
+#elif (USE_BANK == 1)
+  SETB   PSW.3
+  CLR    PSW.4
+#elif (USE_BANK == 2)
+  CLR    PSW.3
+  SETB   PSW.4
+#elif (USE_BANK == 3)
+  ORL    PSW, #0x18
+#endif
+	
+  LCALL  FLASH_PROG     ; LCALL FLASH_PROG
+  JC     _prog_fail
+	POP    B
+	POP    ACC
+  POP    PSW
+  SETB   C
+  RET
+_prog_fail:
+	POP    B
+	POP    ACC
+  POP    PSW
+  CLR    C
+RET
+
+
+
+
+
+
+
+END
+        
+;;#endif    ;;#if (XC88xAA)
diff --git a/XC8Memory.c b/XC8Memory.c
new file mode 100644
index 0000000..deab615
--- /dev/null
+++ b/XC8Memory.c
@@ -0,0 +1,134 @@
+//****************************************************************************
+// File Name     XC8Memory.c
+//----------------------------------------------------------------------------
+// Derivatives   Infineon XC88x AA and AB
+//
+// Description   Sets of function to handle the memory in the XC88x AA.
+//               In particular, the Flash handling is taken care of here.
+//
+//----------------------------------------------------------------------------
+// Date          14.03.2006 10:48:38
+// Copyright     (c) 2006 Infineon Technologies
+//****************************************************************************
+
+#include "XC8Memory.h"
+
+/*
+// **************************************************************************
+// Function Name:    void LoadXD2WLBuf (unsigned char xdata *address)
+// Description:      Load  32byte of data from the XDATA to the WLBuf
+//                   WLBuf is a buffer that is located in the IDATA-space
+// Input Parameter:  *address ==>  pointer to the address
+//                                 in the XDATA memory
+// Output Parameter: none
+
+// NOTE: Execution time and code can saved, 
+//       if you have the possibility to write directly in
+//       the buffer
+// **************************************************************************
+void LoadXD2WLBuf(unsigned char xdata *address)
+{
+// Loads Wordline Buffer with 32bytes from given address in XDATA
+unsigned char i;
+ for (i=0; i  pointer to the address
+//            in the CODE memory
+// Output Parameter: none
+
+// NOTE: Execution time and code can saved, 
+//       if you have the possibility to write directly in
+//       the buffer
+// ***********************************************************************
+void LoadConst2WLBuf(unsigned char code *address)
+{
+// Loads Wordline Buffer with 32bytes from given address in CODE
+unsigned char i;
+ for (i=0; i pointer to the location in the FLASH.
+//                                       The address must be aligned to a 32byte boundary
+// Output Parameter: 1 = Success
+//                   0 = Fail
+// Note:             used Stack Size = 12
+// **************************************************************************************
+bit ProgWL(unsigned char code *AdrBnkXSecYWLZ)
+{
+unsigned int i;
+ i = AdrBnkXSecYWLZ;
+ MEM_DPH = i>>8;
+ MEM_DPL = i;
+ return (FlProg(&WLBuf[0]));
+}
+
+// *************************************************************************************
+// Function Name:    void LoadConst2XD (unsigned char xdata *dstaddress, 
+//                   unsigned char code *srcaddress, unsigned int length)
+// Description:      Copy the data from the CODE memory to XDATA memory
+// Input Parameter:  *srcaddress ==> pointer to the location in the FLASH/EEPROM.
+//                   lenght      ==> The number of byte to be copied
+// Output Parameter: *dstaddress ==> pointer to the location in the XDATA memory.
+//                                   The data will be copied to this location
+
+// NOTE: Execution time and code can saved, 
+//       if you have the possibility to write directly in
+//       the buffer
+// *************************************************************************************
+void LoadConst2XD(unsigned char xdata *dstaddress, unsigned char code *srcaddress, unsigned char length)
+{
+// Loads number of constants to XDATA at given addresses
+unsigned char i;
+ for (i=0; i pointer to the location in the XDATA memory.
+//                                   No byte alignment is necessary
+//                   lenght      ==> The number of byte to be copied
+// Output Parameter: *dstaddress ==> pointer to the location in the XDATA memory.
+//                                   The data will be copied to this location
+//
+// NOTE: Execution time and code can saved, 
+//       if you have the possibility to write directly in
+//       the buffer
+// *************************************************************************************
+void LoadXD2XD(unsigned char xdata *dstaddress, unsigned char xdata *srcaddress, unsigned int length)
+{
+// Copies number of bytes in XDATA to XDATA at given addresses
+unsigned int i;
+ for (i=0; i pointer to the location in the CODE memory.
+//                                No byte alignment is necessary
+// Return Value:  Data Byte
+// *************************************************************************************
+unsigned char ReadConst(unsigned char code *address)
+{
+ return (*address);
+}
+
+*/
\ No newline at end of file
diff --git a/XC8Memory.h b/XC8Memory.h
new file mode 100644
index 0000000..0b13e87
--- /dev/null
+++ b/XC8Memory.h
@@ -0,0 +1,72 @@
+//****************************************************************************
+// File Name     XC8Memory.h
+//----------------------------------------------------------------------------
+// Derivatives   Infineon XC88x AA and AB
+//
+// Description   Sets of function to handle the memory in the XC88x AA.
+//               In particular, the Flash handling is taken care of here.
+//
+//----------------------------------------------------------------------------
+// Date          14.03.2006 10:48:38
+// Copyright     (c) 2006 Infineon Technologies
+//****************************************************************************
+
+// Header for XC8Memory.c
+// Memory handling of XC88x AA derivatives
+
+#ifndef _XC8MEMORY_H_
+#define _XC8MEMORY_H_
+
+#include "XC88x_FLADDR.H"
+
+
+//+------------------------------------------------+
+//|   Global variables needed
+//+------------------------------------------------+
+// Buffer for the 32byte data before being written to eEPROM
+extern unsigned char idata WLBuf[BYTES_PER_WORDLINE];
+
+// Function to program the WLBuf to Flash Memory
+bit ProgWL(unsigned char code *AdrBnkXSecYWLZ);
+// Function to load the data from XDATA memory to WLBuf
+void LoadXD2WLBuf(unsigned char xdata *address);
+// Function to load the data from CODE memory to WLBuf
+// This is used to copy data from one Flash location to another.
+void LoadConst2WLBuf(unsigned char code *address);
+// Function to load the data from CODE memory to XDATA memory
+void LoadConst2XD(unsigned char xdata *dstaddress, unsigned char code *srcaddress, unsigned char length);
+// Function to read a byte from CODE memory
+unsigned char ReadConst(unsigned char code *address);
+
+// All of the description of the functions below is done in XC88x_FLHANDER.ASM
+// Erase Flash Sectors
+// Required Stack Size = 12
+extern bit PFlErase (unsigned char Bank0Sector, unsigned char Bank1Sector, unsigned char Bank2Sector);
+extern bit DFlErase (unsigned int DFlash0Sector, unsigned int DFlash1Sector);
+
+// Program Flash
+// Required Stack Size = 12
+extern bit FlProg(unsigned char idata *SrcBuf);
+
+// Check if Flash is ready to read
+// Bank = Bank Number to be checked
+// Required Stack Size = 6
+extern bit FlReady(unsigned char Bank);
+
+// Abort the existing erase process
+// Required Stack Size = 6
+extern bit FlEraseAbort(void);
+
+// Program / Remove Password.
+// Detail is available in FLHANDLER.asm
+extern bit FlProtect(unsigned char Password);
+
+extern unsigned char _FlReadByte(void);
+extern void FlExecute(unsigned char AddrH, unsigned char AddrL);
+
+sfr MEM_DPH    = 0x83;    
+sfr MEM_DPL    = 0x82;
+sfr MEM_NMICON = 0xBB;
+sfr MEM_NMISR  = 0xBC;
+
+#endif  // _XC8MEMORY_H_
diff --git a/boot.H b/boot.H
new file mode 100644
index 0000000..b11c0cf
--- /dev/null
+++ b/boot.H
@@ -0,0 +1,79 @@
+#ifndef _BOOT_H_
+#define _BOOT_H_
+#include "XC88x_FLADDR.H"
+
+#define ArrXram ((ubyte volatile xdata *)0xf000)
+#define DF_XramLenth 0x600
+#define ArrBootCode ((ubyte volatile code *)0x7000)
+#define DF_BootCodeLenth 0x600
+
+
+
+#define ACKNOWLEDGE      0x55
+#define BLOCK_ERROR      0xFF
+#define TIMEOUT_ERROR    0xF0
+#define PROTECTION_ERROR 0xFD
+
+#define RX_MSGOBJ        5
+#define TX_MSGOBJ        9		  // Define the Message Object for Transmit (No FIFO// is supported for Transmit)
+
+
+//---外部要使用变量声明---------------------------------------------------------------------
+void BootMain(void);
+void CAN_waitTransmit(ubyte RgMsgobj);
+
+
+
+//+------------------------------------------------+
+//|   Global variables needed
+//+------------------------------------------------+
+// Buffer for the 32byte data before being written to eEPROM
+extern unsigned char idata WLBuf[BYTES_PER_WORDLINE];
+
+// Function to program the WLBuf to Flash Memory
+bit ProgWL(unsigned char code *AdrBnkXSecYWLZ);
+// Function to load the data from XDATA memory to WLBuf
+void LoadXD2WLBuf(unsigned char xdata *address);
+// Function to load the data from CODE memory to WLBuf
+// This is used to copy data from one Flash location to another.
+void LoadConst2WLBuf(unsigned char code *address);
+// Function to load the data from CODE memory to XDATA memory
+void LoadConst2XD(unsigned char xdata *dstaddress, unsigned char code *srcaddress, unsigned char length);
+// Function to read a byte from CODE memory
+unsigned char ReadConst(unsigned char code *address);
+
+// All of the description of the functions below is done in XC88x_FLHANDER.ASM
+// Erase Flash Sectors
+// Required Stack Size = 12
+extern bit PFlErase (unsigned char Bank0Sector, unsigned char Bank1Sector, unsigned char Bank2Sector);
+extern bit DFlErase (unsigned int DFlash0Sector, unsigned int DFlash1Sector);
+
+// Program Flash
+// Required Stack Size = 12
+extern bit FlProg(unsigned char idata *SrcBuf);
+
+// Check if Flash is ready to read
+// Bank = Bank Number to be checked
+// Required Stack Size = 6
+extern bit FlReady(unsigned char Bank);
+
+// Abort the existing erase process
+// Required Stack Size = 6
+extern bit FlEraseAbort(void);
+
+// Program / Remove Password.
+// Detail is available in FLHANDLER.asm
+extern bit FlProtect(unsigned char Password);
+
+extern unsigned char _FlReadByte(void);
+extern void FlExecute(unsigned char AddrH, unsigned char AddrL);
+
+sfr MEM_DPH    = 0x83;    
+sfr MEM_DPL    = 0x82;
+sfr MEM_NMICON = 0xBB;
+sfr MEM_NMISR  = 0xBC;
+
+
+
+
+#endif
\ No newline at end of file
diff --git a/boot.c b/boot.c
new file mode 100644
index 0000000..cd672db
--- /dev/null
+++ b/boot.c
@@ -0,0 +1,129 @@
+#include "MAIN.H" 
+
+	ubyte idata WLBuf[32] _at_ 0x80;
+// This function will generate a Watchdog Reset
+// The reset will be generated in about 21 us
+void CAN_setWDTReset(void)
+{
+  SFR_PAGE(_su1, noSST);         // switch to page1 without saving
+  MAIN_vUnlockProtecReg();       // open access to protected register
+
+  SET_RMAP(); 
+  WDTCON |= 0x04;     //   set   WDTEN
+  WDTREL = 0xFF;      //Watch dog timer reload register
+  WDTCON |= 0x03;                // set WDTRS,set WDTIN
+  RESET_RMAP(); 
+
+  MAIN_vlockProtecReg();         // close access to protected register
+  SFR_PAGE(_su0, noSST);         // switch to page0 with out saving
+	
+   while(1);
+}
+
+
+void CAN_waitTransmit(ubyte RgMsgobj)
+{
+	ulong i;
+	for(i=0;(i<6000)&&(!CAN_ubRequestMsgObj(RgMsgobj));i++)WDT_vRefresh();
+}
+
+
+// CAN Acknowledge Frame consist of 2 data bytes.
+// The first data byte is the Acknowledge Code
+// The second data byte is the valid data depending on the Acknowledge Code
+// TX_MSGOBJ is set to one Message object only.
+void CAN_sendAck(ubyte Ack0,ubyte Ack1)
+{
+	ubyte Arrtmp[8] = {0};
+//--------------------------------------------
+	Arrtmp[3] = Ack0;
+	Arrtmp[2] = Ack1;
+
+	CAN_vLoadData(TX_MSGOBJ, (ulong *)(Arrtmp)); // Add this Line			
+	CAN_vTransmit(TX_MSGOBJ);
+	CAN_waitTransmit(TX_MSGOBJ);
+}
+
+
+
+
+// Flash_Wait does not take care of the timeout.
+// In case programming / erasing fail, it will automatically reset the chip.
+// (to be implemented)
+void Flash_Wait(void)
+{
+	ubyte ubCount0, ubCount1, ubCount2;
+
+	SYSCON0  = SYSCON0 & 0xFE;
+	SCU_PAGE = 0;                 // Mandatory
+	for (ubCount2=0; ubCount2 < 50; ubCount2++) 
+		{
+			for (ubCount1=0; ubCount1 < 255; ubCount1++) 
+			{
+				for (ubCount0=0; ubCount0 < 255; ubCount0++) 
+				{
+					if (NMISR & 0x4) 
+					{
+						NMISR &= ~0x04;
+						return;
+					}
+				}
+			}
+		}
+	CAN_setWDTReset();
+}
+
+
+
+void BootMain(void)
+{
+	stCAN_SWObj  StrBootRx;
+	ubyte  ulCANData[8];
+	ubyte i;
+
+//------------------------------------	
+	if(CAN_ubNewData(RX_MSGOBJ))
+	{
+		CAN_vGetMsgObj(RX_MSGOBJ, &StrBootRx);	
+		ulCANData[3] = StrBootRx.ulDATAL.ubDB[0];
+		ulCANData[2] = StrBootRx.ulDATAL.ubDB[1];
+		ulCANData[1] = StrBootRx.ulDATAL.ubDB[2];
+		ulCANData[0] = StrBootRx.ulDATAL.ubDB[3];
+		ulCANData[7] = StrBootRx.ulDATAH.ubDB[0];
+		ulCANData[6] = StrBootRx.ulDATAH.ubDB[1];
+		ulCANData[5] = StrBootRx.ulDATAH.ubDB[2];
+		ulCANData[4] = StrBootRx.ulDATAH.ubDB[3];
+		CAN_vReleaseObj(RX_MSGOBJ);
+		
+		EA = 0;
+		TR2 = 0;
+		WDT_vDisable();//清除WDT，否则在boot程序中会产生复位	
+//------------------------------------------------------------				
+		if((ulCANData[0] == 0xaa) && (ulCANData[1] == 0xaa))//重启
+		{
+			CAN_sendAck(ACKNOWLEDGE, 0x01);
+			CAN_setWDTReset();
+		}	
+//------------------------------------------------------------	
+		else if((ulCANData[0] == 0x33) && (ulCANData[1] == 0x33))//编程11
+		{
+			SCU_PAGE = 0;	
+	    NMISR    = 0;	
+      DFlErase(0x0, 0x0300);//擦除bank1 sector 8，9
+      Flash_Wait();  // In case fail, the chip will generate WDT Reset			
+			
+			for(i=0;i<32;i++)
+			{
+				WLBuf[i] = 0;
+			}			
+			WLBuf[0] = 0x11;//编程标识,0x6F00
+			DPH = 0x6F;
+			DPL = 0;	
+			FlProg(&WLBuf[0]);
+      Flash_Wait();  // In case fail, the chip will generate WDT Reset					
+			CAN_sendAck(ACKNOWLEDGE, 0x04);
+		}	
+//------------------------------------------------------------			
+		else ;
+	}		
+}
\ No newline at end of file
diff --git a/temperature.C b/temperature.C
new file mode 100644
index 0000000..ae52a7e
--- /dev/null
+++ b/temperature.C
@@ -0,0 +1,189 @@
+#include "temperature.H"
+#include 
+#include 
+
+UnSwSample  UnSwSample_1 = {0};
+#define Measure_Period 11000
+
+////////////////////////////////////////////////////////////////////
+// 计算字节序列的校验和
+unsigned char CRC8MY(unsigned char *serial, unsigned char length) 
+{
+    unsigned char result = 0x00;
+    unsigned char pDataBuf;
+    unsigned char i;
+    while (length--) {
+        pDataBuf = *serial++;
+        for (i = 0; i < 8; i++) {
+            if ((result ^ pDataBuf) & 0x01) {
+                result ^= 0x18;
+                result >>= 1;
+                result |= 0x80;
+            }
+            else {
+                result >>= 1;
+            }
+            pDataBuf >>= 1;
+        }
+    }
+			
+    return result;   //返回校验和
+}
+
+
+//非精确延时10*X us，固定误差10us
+//@12.000MHz 12T模式
+void Delay_us(uword x)
+{
+	for (; x > 0; x--)
+	{
+		_nop_();
+		_nop_();
+	}
+	
+}
+
+////////////////////////////////////////////////////////////////////
+// 主机发送 复位脉冲（ 大于 480 us 低电平） ，并检查 存在 脉冲
+unsigned char ow_resetpresence(void)
+{
+	unsigned char presence; int count=0;
+
+	SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P3_DIR        =  P3_DIR | 0x20;      // load direction register	 P3.5切换为输出
+	
+	DQ = 0;                        // 主机拉低 DQ 总线
+	Delay_us(240);                 // 拉低 DQ 总线 持续 480us
+	DQ = 1;                        // 主机释放总线，由上拉电阻拉高
+	
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P3_DIR        =  P3_DIR & 0xDF;// load direction register	
+	
+	Delay_us(40);                                // 等待 80us 后检查 presence
+	presence = DQ;                               // 检查存在 脉冲
+	while( presence && (count< 17) )
+	{
+		Delay_us(2);
+		presence = DQ;
+		count++;
+	}
+		Delay_us(200);                             // 时序末尾 等待
+		return(presence);
+}                                              // presence =0 时， M6 01 存在 , presence =1 时， M601 不存在
+
+////////////////////////////////////////////////////////////////////
+//// READ_BIT – 从 M601 读取 一位数
+unsigned char read_bit(void) 
+{
+	unsigned char res;
+
+	SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P3_DIR        =  P3_DIR | 0x20;      // load direction register	 切换为输出状态	
+	
+  DQ = 0;                        // 主机拉低 DQ 总线
+  Delay_us(2);                   // 拉低 DQ 总线 持续 3us
+  DQ = 1;                        // 主机释放 DQ 总线，由上拉电阻拉高
+  Delay_us(5);                   // 等待 10us 确保总线上数据稳定
+	
+  SFR_PAGE(_pp0, noSST);         // switch to page 0
+  P3_DIR        =  P3_DIR & 0xDF;// load direction register	
+	
+  res = DQ;                     
+  Delay_us(28);                        // 时序末尾 等待
+  return(res);                           // 返回读取 数值
+}
+
+////////////////////////////////////////////////////////////////////
+//// WRITE_BIT – 主机 写一位数据 到 M601
+void write_bit(char bitval) 
+{
+	SFR_PAGE(_pp0, noSST);                // switch to page 0
+  P3_DIR  =  P3_DIR | 0x20;             // load direction register	 切换为输出状态
+	
+	DQ = 0;                              	// 主机拉低 DQ 总线
+  Delay_us(2);                          // 拉低 DQ 总线 持续 5us
+	if(bitval == 1) DQ =1;                // 如果 写 1，此时拉高 DQ 总线
+  Delay_us(25);                         // 如果 写 0，则持续拉低 DQ 总线 60 us
+  DQ = 1;                               // 释放 DQ 总线
+  Delay_us(5);                          // （写 0）恢复 时间 10us
+}
+
+/////////////////////////////////////////////////////////////////////
+//// READ_BYTE - 从 M601 读取 一字节 数据
+unsigned char read_byte(void) 
+{
+	unsigned char i, j;
+	unsigned char value = 0;
+	for (i = 0;i < 8;i++) {
+		j = read_bit();
+		value = (value) | (j<> i;
+		temp &= 0x01;                                  // 低位 先行
+		write_bit(temp);
+	}
+}
+
+
+//读取测温数据
+void Single_point_Read_Temperature(void)
+{
+	unsigned char get[9];
+  unsigned char tpmsb, tplsb, i;
+	int signedInt_f_tem;
+	short s_tem;
+	short wtem;
+	float f_tem;
+  UnSwSample_1.bit_data.reserve = 0;
+	if (ow_resetpresence())
+	{
+			
+		 // 建议保留该判断！可以有效排查硬件连接是否出现问题！
+		 //	printf("\nPresence Error\n");
+		UnSwSample_1.bit_data.reserve = 0x01;
+	}
+	write_byte(0xCC); //Skip ROM ，或使用 匹配 ROM 序列号 （见后文）
+	write_byte(0x44); // 转换 温度
+	Delay_us(Measure_Period / 2);
+	// 温度 转换时间， 应根据配置寄存器的重复性设置选择 4ms ，5.5ms 或 10.5m
+	if (ow_resetpresence())
+	{
+		// 建议保留该判断！可以有效排查硬件连接是否出现问题！
+		//	printf("\nPresence Error\n");
+		UnSwSample_1.bit_data.reserve = 0x02;		
+	}
+	write_byte(0xCC); // Skip ROM ，或使用 匹配 ROM 序列号 （见后文）
+	write_byte(0xBE); // 读取 Scratch Pad 中数值
+	for (i = 0; i < 9; i++) get[i]=read_byte();
+	if(get[8] != CRC8MY(get,8))
+	{
+		// 建议保留该判断！可以有效排查软件时序是否出现问题！
+		// printf("\nCRC Error\n");
+	   UnSwSample_1.bit_data.reserve = 0x03;
+	}
+	else
+	{
+		tpmsb = get[1]; // 温度高字节
+		tplsb = get[0]; // 温度 低字节
+		wtem= (tpmsb << 8 | tplsb);
+		s_tem =(short) wtem;
+		f_tem=(s_tem * 1.0)/256 + 40.0;			       
+		// 将浮点数转换为有符号整型
+		 signedInt_f_tem = (int)f_tem;
+		// 温度 有符号整型转成无符号整形	
+		 UnSwSample_1.bit_data.temperature = (unsigned int)signedInt_f_tem;			
+	 //	printf( "\nTemp= %f degrees C\n", f_tem); // 打印摄氏温度
+	}
+}
+
+
diff --git a/temperature.h b/temperature.h
new file mode 100644
index 0000000..7e1ca90
--- /dev/null
+++ b/temperature.h
@@ -0,0 +1,89 @@
+#ifndef _TEMPERATURE_H_
+#define _TEMPERATURE_H_
+
+#include "MAIN.H"
+
+
+#define DQ       P3_5
+
+
+//20250116 增加温度采集字节
+typedef struct _StrSwSample       
+{
+    unsigned int emergency_stop_switch : 1;  // 通道1，急停开关
+    unsigned int High_voltage_switch   : 1;  // 通道2，高压开关
+    unsigned int CH03                  : 1;  // 通道3
+    unsigned int CH04                  : 1;  // 通道4
+    unsigned int CH05                  : 1;  // 通道5
+    unsigned int CH06                  : 1;  // 通道6
+    unsigned int CH07                  : 1;  // 通道7
+    unsigned int CH08                  : 1;  // 通道8
+    unsigned int CH09                  : 1;  // 通道9
+    unsigned int CH10                  : 1;  // 通道10
+    unsigned int CH11                  : 1;  // 通道11
+    unsigned int CH12                  : 1;  // 通道12
+    unsigned int CH13                  : 1;  // 通道13
+    unsigned int CH14                  : 1;  // 通道14
+    unsigned int CH15                  : 1;  // 通道15
+    unsigned int CH16                  : 1;  // 通道16
+    unsigned int CH17                  : 1;  // 通道17
+    unsigned int CH18                  : 1;  // 通道18
+    unsigned int CH19                  : 1;  // 通道19
+    unsigned int CH20                  : 1;  // 通道20
+    unsigned int CH21                  : 1;  // 通道21
+    unsigned int CH22                  : 1;  // 通道22
+    unsigned int CH23                  : 1;  // 通道23
+    unsigned int CH24                  : 1;  // 通道24
+    unsigned int CH25                  : 1;  // 通道25
+    unsigned int CH26                  : 1;  // 通道26
+    unsigned int CH27                  : 1;  // 通道27
+    unsigned int CH28                  : 1;  // 通道28
+    unsigned int CH29                  : 1;  // 通道29
+    unsigned int CH30                  : 1;  // 通道30
+    unsigned int CH31                  : 1;  // 通道31
+    unsigned int CH32                  : 1;  // 通道32
+    unsigned int CH33                  : 1;  // 通道33
+    unsigned int CH34                  : 1;  // 通道34
+    unsigned int CH35                  : 1;  // 通道35
+    unsigned int CH36                  : 1;  // 通道36
+    unsigned int CH37                  : 1;  // 通道37
+    unsigned int CH38                  : 1;  // 通道38
+    unsigned int CH39                  : 1;  // 通道39
+    unsigned int CH40                  : 1;  // 通道40
+    unsigned int CH41                  : 1;  // 通道41
+    unsigned int CH42                  : 1;  // 通道42
+    unsigned int CH43                  : 1;  // 通道43
+    unsigned int CH44                  : 1;  // 通道44
+    unsigned int reserve               : 4;
+	  uword temperature;                 // 温度
+		
+} StrSwSample;
+
+typedef union _UnSwSample
+{
+    StrSwSample bit_data;              // 使用定义的结构体变量名
+    unsigned char arr[sizeof(StrSwSample)];  // 通过结构体类型确定大小
+} UnSwSample;
+
+
+void Single_point_Read_Temperature(void);  //声明函数
+
+
+
+
+
+
+
+
+	
+
+
+
+
+
+extern UnSwSample  UnSwSample_1 ;
+
+
+
+
+#endif // _TEMPERATURE_H_
diff --git a/user.H b/user.H
new file mode 100644
index 0000000..4cf5f6f
--- /dev/null
+++ b/user.H
@@ -0,0 +1,164 @@
+#ifndef _user_H_
+#define _user_H_
+
+
+#define SAMPLE_INTERVAL      50    // 50ms采样周期
+#define BLINK_TIMEOUT        (1000 / SAMPLE_INTERVAL)  // 1秒稳定确认
+#define BLINK_WINDOW         (1000 / SAMPLE_INTERVAL)  // 1秒闪烁检测窗口
+#define STABLE_CONFIRM_TIME  (1000 / SAMPLE_INTERVAL)  // 1秒闪烁检测窗口
+#define MIN_BLINKS           2
+
+#define MATCH_TIME           (2000 / SAMPLE_INTERVAL)//对频时间
+#define MATCH_WAIT_TIME      (1000 / SAMPLE_INTERVAL)//对频完，等待时间
+
+#define CHANGE_TIME          (200 / SAMPLE_INTERVAL)//对频时间
+
+#define MATCH_CMD           0xDB//对频命令
+#define CHANGE_CMD          0xBD//切换命令
+
+
+#define   uint32_t   ulong
+#define   uint16_t   uword
+#define   uint8_t    ubyte
+				  
+#define   int16_t    signed int
+				  
+				  
+#define   DF_SwTx           6
+#define   DF_SwRx           7
+#define   DF_SwRxPwm        8
+#define   DF_SwTx1          10
+
+
+#define   dfCmd_01   UnInfCan_1.BitData.D21      //KGF1  
+#define   dfCmd_02   UnInfCan_1.BitData.D22      //KGF2	
+#define   dfCmd_03   UnInfCan_1.BitData.D23      //KGF3  
+#define   dfCmd_04   UnInfCan_1.BitData.D24      //KGF4  
+#define   dfCmd_05   UnInfCan_1.BitData.D25      //KGF5  
+#define   dfCmd_06   UnInfCan_1.BitData.D26      //KGF6  
+#define   dfCmd_07   UnInfCan_1.BitData.D27      //KGF7  
+#define   dfCmd_08   UnInfCan_1.BitData.D28      //KGF8  
+#define   dfCmd_09   UnInfCan_1.BitData.D29      //KGF9  
+#define   dfCmd_10   UnInfCan_1.BitData.D30      //KGF10 
+#define   dfCmd_11   UnInfCan_1.BitData.D31      //KGF11 
+#define   dfCmd_12   UnInfCan_1.BitData.D32      //KGF12 
+#define   dfCmd_13   UnInfCan_1.BitData.D33      //KGF13 
+#define   dfCmd_14   UnInfCan_1.BitData.D34      //KGF14 
+#define   dfCmd_15   UnInfCan_1.BitData.D35      //KGF15 
+#define   dfCmd_16   UnInfCan_1.BitData.D36      //KGF16 
+
+#define   dfOut_01   SwOut09                     //KGF1  
+#define   dfOut_02   SwOut10                     //KGF2	
+#define   dfOut_03   SwOut04                     //KGF3  
+#define   dfOut_04   SwOut03                     //KGF4  
+#define   dfOut_05   SwOut06                     //KGF5  
+#define   dfOut_06   SwOut05                     //KGF6  
+#define   dfOut_07   SwOut15                     //KGF7  
+#define   dfOut_08   SwOut16                     //KGF8  
+#define   dfOut_09   SwOut13                     //KGF9  
+#define   dfOut_10   SwOut14                     //KGF10 
+#define   dfOut_11   SwOut08                     //KGF11 
+#define   dfOut_12   SwOut07                     //KGF12 
+#define   dfOut_13   SwOut02                     //KGF13 
+#define   dfOut_14   SwOut01                     //KGF14 
+#define   dfOut_15   SwOut11                     //KGF15 
+#define   dfOut_16   SwOut12                     //KGF16 
+
+#define   dfPwmH		 10	 //PWMμ???μ???ê±??￡?10￡?10ms×óóò￡???ì?Dèòa2aê?20181227
+
+
+
+
+
+
+#define  DF_ZeroValue        1000//?ù?Yò￡???÷￡???0ê±êy?Y?a1022
+
+#define  DF_Speed            UnRemoteControlOutput_1.bit_data.speed//?ù?è
+#define  DF_Curvature        UnRemoteControlOutput_1.bit_data.curvature//×aí?
+#define  DF_Reserve          UnRemoteControlOutput_1.bit_data.reserve1//±￡á?
+#define  DF_SwA              UnRemoteControlOutput_1.bit_data.switch_a//DF_SwA
+#define  DF_SwB              UnRemoteControlOutput_1.bit_data.switch_b//DF_SwB
+#define  DF_SwC              UnRemoteControlOutput_1.bit_data.switch_c//DF_SwC
+#define  DF_SwD              UnRemoteControlOutput_1.bit_data.switch_d//DF_SwD
+#define  DF_RCHSta           UnRemoteControlOutput_1.bit_data.enable//ê?±úê1?ü×′ì?
+
+//#define  DF_RCHEmSwSta       UnRCH_1.BitData.RCHBit07//?±í￡?a1?×′ì?ê1?ü×′ì?
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// ?¨ò?2￠3?ê??ˉ SBus ?a???á11ì?
+typedef struct {
+    uint16_t channels[16];  // ′?′￠16??í¨μàμ??a???á1?
+    uint8_t flags;          // ±ê??×??ú
+} SBusData;
+
+
+
+
+
+
+// ?óê?ò￡???÷ê?è?
+typedef struct _StrRemoteControlOutput
+{
+	//-----·￠?íêy?Y0x12000023----------------------------------------------
+	  signed   int speed      : 16;  // ?ú?ê
+    signed   int curvature  : 16;  // ?ù?è
+	
+	
+    unsigned int reserve1   : 16;  // ò￡???á
+
+    unsigned int switch_a   : 1;   // SwA
+    unsigned int switch_b   : 2;   // SwB  ?±í￡?a1? 1êí·?  0/2ê??±í￡
+    unsigned int switch_c   : 2;   // SwC  ?￡ê??a1? 1×??ˉ  0/2ê?ê??ˉ
+    unsigned int switch_d   : 1;   // SwD  é?μ??a1? ?è?ì°′?ù3¤°′
+    unsigned int reserve2   : 1;   // ±￡á?
+    unsigned int reserve3   : 1;   // ±￡á?
+                            
+    unsigned int enable     : 8;   // ê1?ü
+} StrRemoteControlInput;
+
+typedef union _UnRemoteControlInput
+{
+    StrRemoteControlInput bit_data;             // ê1ó??¨ò?μ??á11ì?±?á???
+    uint8_t arr[sizeof(StrRemoteControlInput)]; // í¨1y?á11ì?ààDíè·?¨′óD?
+} UnRemoteControlOutput;
+
+
+
+
+
+
+
+//---ía2?òaê1ó?±?á?éù?÷---------------------------------------------------------------------
+extern  UnSwOut	 UnSwOut_1;
+extern  UnInfCan UnInfCan_1;
+extern  uword    CntCan_1;
+extern  bit      FlgCan_1;
+
+extern  ubyte    rxbuf[25];
+extern  ubyte    uart2RxFlag;
+extern  ubyte    can_error_cnt;
+
+
+void CanRXTX(void);
+void SwSample(void);
+void LedDr(void);
+void RTCProcess(void);
+void CanErrorProcess(void);
+void CanTransmit(ubyte index,ubyte *buf);
+SBusData* parseSBusData(const uint8_t *input_data);
+void sbusCanDecode(void);
+
+#endif
\ No newline at end of file
diff --git a/user.H.bak b/user.H.bak
new file mode 100644
index 0000000..6a13b4d
--- /dev/null
+++ b/user.H.bak
@@ -0,0 +1,57 @@
+#ifndef _user_H_
+#define _user_H_
+
+#define DF_SwTx        6
+#define DF_SwRx        7
+
+#define   dfCmd01   UnInfCan_1.BitData.D21      //KGF1  
+#define   dfCmd02   UnInfCan_1.BitData.D22      //KGF2	
+#define   dfCmd03   UnInfCan_1.BitData.D23      //KGF3  
+#define   dfCmd04   UnInfCan_1.BitData.D24      //KGF4  
+#define   dfCmd05   UnInfCan_1.BitData.D25      //KGF5  
+#define   dfCmd06   UnInfCan_1.BitData.D26      //KGF6  
+#define   dfCmd07   UnInfCan_1.BitData.D27      //KGF7  
+#define   dfCmd08   UnInfCan_1.BitData.D28      //KGF8  
+#define   dfCmd09   UnInfCan_1.BitData.D29      //KGF9  
+#define   dfCmd10   UnInfCan_1.BitData.D30      //KGF10 
+#define   dfCmd11   UnInfCan_1.BitData.D31      //KGF11 
+#define   dfCmd12   UnInfCan_1.BitData.D32      //KGF12 
+#define   dfCmd13   UnInfCan_1.BitData.D33      //KGF13 
+#define   dfCmd14   UnInfCan_1.BitData.D34      //KGF14 
+#define   dfCmd15   UnInfCan_1.BitData.D35      //KGF15 
+#define   dfCmd16   UnInfCan_1.BitData.D36      //KGF16 
+
+#define   dfOut01   SwOut09                     //KGF1  
+#define   dfOut02   SwOut10                     //KGF2	
+#define   dfOut03   SwOut04                     //KGF3  
+#define   dfOut04   SwOut03                     //KGF4  
+#define   dfOut05   SwOut06                     //KGF5  
+#define   dfOut06   SwOut05                     //KGF6  
+#define   dfOut07   SwOut15                     //KGF7  
+#define   dfOut08   SwOut16                     //KGF8  
+#define   dfOut09   SwOut13                     //KGF9  
+#define   dfOut10   SwOut14                     //KGF10 
+#define   dfOut11   SwOut08                     //KGF11 
+#define   dfOut12   SwOut07                     //KGF12 
+#define   dfOut13   SwOut02                     //KGF13 
+#define   dfOut14   SwOut01                     //KGF14 
+#define   dfOut15   SwOut11                     //KGF15 
+#define   dfOut16   SwOut12                     //KGF16 
+
+
+
+
+//---外部要使用变量声明---------------------------------------------------------------------
+extern  UnSwOut	 UnSwOut_1;
+extern  UnInfCan UnInfCan_1;
+extern  uword    CntCan_1;
+extern  bit      FlgCan_1;
+
+void CanRXTX(void);
+void SwSample(void);
+void LedDr(void);
+void RTCProcess(void);
+void CanErrorProcess(void);
+void CanTransmit(void);
+
+#endif
\ No newline at end of file