#include <stdint.h>
#include <stdbool.h>
#include <regs_base.h>

Data Structures
struct	sdrv_adc

struct	sdrv_adc_rc_cfg

struct	sdrv_adc_rcht_entry_cfg

struct	sdrv_adc_rc_entry_cfg

struct	sdrv_adc_ana_param_cfg

struct	sdrv_adc_fifo_cfg

struct	sdrv_adc_sync_cfg

Functions
void	sdrv_adc_init (sdrv_adc_t *sdrv_adcX, unsigned int clk_div)

void	sdrv_adc_set_dc_offset (sdrv_adc_t *sdrv_adcX, int16_t offset)

int16_t	sdrv_adc_get_dc_offset (sdrv_adc_t *sdrv_adcX)

void	sdrv_adc_set_slave_mode (sdrv_adc_t *sdrv_adcX)

void	sdrv_adc_clr_slave_mode (sdrv_adc_t *sdrv_adcX)

uint32_t	sdrv_adc_read_int_status (sdrv_adc_t *sdrv_adcX)

void	sdrv_adc_clear_int_status (sdrv_adc_t *sdrv_adcX, uint32_t int_bits)

void	sdrv_adc_int_status_en_cfg (sdrv_adc_t *sdrv_adcX, uint32_t int_bits, bool enable)

void	sdrv_adc_int_status_sig_en_cfg (sdrv_adc_t *sdrv_adcX, uint32_t int_bits, bool enable)

void	sdrv_adc_rc_cfg (sdrv_adc_t sdrv_adcX, unsigned int rc_nbr, sdrv_adc_rc_cfg_t rc_cfg)

void	sdrv_adc_rc_start_tmr (sdrv_adc_t *sdrv_adcX, unsigned int rc_nbr)

void	sdrv_adc_rc_start_timers (sdrv_adc_t *sdrv_adcX, sdrv_adc_rc_start_flag_t rc_flags)

void	sdrv_adc_rc_stop_tmr (sdrv_adc_t *sdrv_adcX, unsigned int rc_nbr)

void	sdrv_adc_rc_soft_trg (sdrv_adc_t *sdrv_adcX, unsigned int rc_nbr)

void	sdrv_adc_rcht_ready (sdrv_adc_t *sdrv_adcX, uint8_t ready_len)

void	sdrv_adc_rcht_clr_ready (sdrv_adc_t *sdrv_adcX)

void	sdrv_adc_rcht_entry_cfg (sdrv_adc_t *sdrv_adcX, unsigned int entry_nbr, sdrv_adc_rcht_entry_cfg_t entry_cfg)

void	sdrv_adc_rc_entry_cfg (sdrv_adc_t *sdrv_adcX, unsigned int rc_nbr, unsigned int entry_nbr, sdrv_adc_rc_entry_cfg_t entry_cfg)

void	sdrv_adc_ana_param_cfg (sdrv_adc_t *sdrv_adcX, unsigned int param_nbr, sdrv_adc_ana_param_cfg_t aparam_cfg)

void	sdrv_adc_fifo_cfg (sdrv_adc_t sdrv_adcX, sdrv_adc_fifo_cfg_t fifo_cfg)

void	sdrv_adc_fifo_rc_cfg (sdrv_adc_t *sdrv_adcX, sdrv_adc_fifo_rc_cfg_t rc_cfg)

uint32_t	sdrv_adc_fifo_status (sdrv_adc_t *sdrv_adcX)

uint32_t	sdrv_adc_read_fifo (sdrv_adc_t *sdrv_adcX)

uintptr_t	sdrv_adc_fifo_addr (sdrv_adc_t *sdrv_adcX)

void	sdrv_adc_dma_enable (sdrv_adc_t *sdrv_adcX, sdrv_adc_dma_src_cfg_t req_src)

void	sdrv_adc_dma_disable (sdrv_adc_t *sdrv_adcX)

void	sdrv_adc_sync_cfg (sdrv_adc_t sdrv_adcX, sdrv_adc_sync_cfg_t sync_cfg, uint8_t slot_cid, unsigned int len)

void	sdrv_adc_sync_start (sdrv_adc_t *sdrv_adcX)

void	sdrv_adc_Async_start (sdrv_adc_t *sdrv_adcX)

void	sdrv_adc_sync_slot_reset (sdrv_adc_t *sdrv_adcX)

void	sdrv_adc_stop (sdrv_adc_t *sdrv_adcX, bool rc_tmr_stop)

void	sdrv_adc_power_ctrl (sdrv_adc_t *sdrv_adcX, bool down)

Detailed Description

Copyright: Copyright (c) 2021 Semidrive Semiconductor. All rights reserved.

Macro Definition Documentation

◆ ADC_CH_POLAR_NEG

#define ADC_CH_POLAR_NEG 0u

◆ ADC_CH_POLAR_POS

#define ADC_CH_POLAR_POS 1u

◆ ADC_CH_SEL_TAISHAN

#define ADC_CH_SEL_TAISHAN	(	ch,
		polar,
		mux
	)	((((mux) & 0x7u) << 6) \| (((polar) & 0x1u) << 3) \| ((ch) & 0x7u))

◆ ADC_DCH_SEL_TAISHAN

#define ADC_DCH_SEL_TAISHAN	(	ch_p,
		ch_n,
		mux
	)	((((mux) & 0x7u) << 6) \| (((ch_p) & 0x7u) << 3) \| ((ch_n) & 0x7u))

◆ SADC_ANA_PARAM_CCN_MSK

#define SADC_ANA_PARAM_CCN_MSK (0xFu << SADC_ANA_PARAM_CCN_POS)

◆ SADC_ANA_PARAM_CCN_POS

#define SADC_ANA_PARAM_CCN_POS (12)

◆ SADC_ANA_PARAM_CCP_MSK

#define SADC_ANA_PARAM_CCP_MSK (0xFu << SADC_ANA_PARAM_CCP_POS)

◆ SADC_ANA_PARAM_CCP_POS

#define SADC_ANA_PARAM_CCP_POS (8)

◆ SADC_ANA_PARAM_CCT_MSK

#define SADC_ANA_PARAM_CCT_MSK (0x1Fu << SADC_ANA_PARAM_CCT_POS)

◆ SADC_ANA_PARAM_CCT_POS

#define SADC_ANA_PARAM_CCT_POS (16)

◆ SADC_ANA_PARAM_DIFF_SEL

#define SADC_ANA_PARAM_DIFF_SEL (1u << 5)

◆ SADC_ANA_PARAM_REF_SEL

#define SADC_ANA_PARAM_REF_SEL (1u << 4)

◆ SADC_ANA_PARAM_SAMCTRL_MSK

#define SADC_ANA_PARAM_SAMCTRL_MSK (0x7u << SADC_ANA_PARAM_SAMCTRL_POS)

◆ SADC_ANA_PARAM_SAMCTRL_POS

#define SADC_ANA_PARAM_SAMCTRL_POS (0)

◆ SADC_ANA_REF_PART1_PD

#define SADC_ANA_REF_PART1_PD (1U << 0)

◆ SADC_ANA_REF_PART1_PDBISA

#define SADC_ANA_REF_PART1_PDBISA (1U << 1)

◆ SADC_CLK_CTRL_DIV_BYPASS

#define SADC_CLK_CTRL_DIV_BYPASS (1u << 0)

◆ SADC_CLK_CTRL_REFH_MSK

#define SADC_CLK_CTRL_REFH_MSK (0xFu << SADC_CLK_CTRL_REFH_POS)

◆ SADC_CLK_CTRL_REFH_POS

#define SADC_CLK_CTRL_REFH_POS (8)

◆ SADC_CLK_CTRL_REFL_MSK

#define SADC_CLK_CTRL_REFL_MSK (0xFu << SADC_CLK_CTRL_REFL_POS)

◆ SADC_CLK_CTRL_REFL_POS

#define SADC_CLK_CTRL_REFL_POS (12)

◆ SADC_DCOC_EN

#define SADC_DCOC_EN (1u << 4)

◆ SADC_DCOC_OVWR

#define SADC_DCOC_OVWR (1u << 8)

◆ SADC_DCOC_START

#define SADC_DCOC_START (1u << 3)

◆ SADC_DCOC_TIMES_MSK

#define SADC_DCOC_TIMES_MSK (0x7u << SADC_DCOC_TIMES_POS)

◆ SADC_DCOC_TIMES_POS

#define SADC_DCOC_TIMES_POS (0)

◆ SADC_DCOC_VALUE_DONE

#define SADC_DCOC_VALUE_DONE (1u << 31)

◆ SADC_DCOC_VALUE_MSK

#define SADC_DCOC_VALUE_MSK (0xFFFu << SADC_DCOC_VALUE_POS)

◆ SADC_DCOC_VALUE_POS

#define SADC_DCOC_VALUE_POS (16)

◆ SADC_DCOC_VALUE_SIGN

#define SADC_DCOC_VALUE_SIGN (1u << 28)

◆ SADC_DMA_CH0EN_F0RC0

#define SADC_DMA_CH0EN_F0RC0 (1u << 11)

◆ SADC_DMA_CH0EN_F1RC1

#define SADC_DMA_CH0EN_F1RC1 (1u << 10)

◆ SADC_DMA_CH0EN_F2RC2

#define SADC_DMA_CH0EN_F2RC2 (1u << 9)

◆ SADC_DMA_CH0EN_F3RC3

#define SADC_DMA_CH0EN_F3RC3 (1u << 8)

◆ SADC_DMA_CH0EN_RCHT

#define SADC_DMA_CH0EN_RCHT (1u << 12)

◆ SADC_DMA_CH1EN_F0RC0

#define SADC_DMA_CH1EN_F0RC0 (1u << 19)

◆ SADC_DMA_CH1EN_F1RC1

#define SADC_DMA_CH1EN_F1RC1 (1u << 18)

◆ SADC_DMA_CH1EN_F2RC2

#define SADC_DMA_CH1EN_F2RC2 (1u << 17)

◆ SADC_DMA_CH1EN_F3RC3

#define SADC_DMA_CH1EN_F3RC3 (1u << 16)

◆ SADC_DMA_CH1EN_RCHT

#define SADC_DMA_CH1EN_RCHT (1u << 20)

◆ SADC_DMA_MODE_FIFO0

#define SADC_DMA_MODE_FIFO0 (1u << 3)

◆ SADC_DMA_MODE_FIFO1

#define SADC_DMA_MODE_FIFO1 (1u << 2)

◆ SADC_DMA_MODE_FIFO2

#define SADC_DMA_MODE_FIFO2 (1u << 1)

◆ SADC_DMA_MODE_FIFO3

#define SADC_DMA_MODE_FIFO3 (1u << 0)

◆ SADC_DMA_MODE_RCHT

#define SADC_DMA_MODE_RCHT (1u << 4)

◆ SADC_FIFO_CFG_BYPASS

#define SADC_FIFO_CFG_BYPASS (1u << 4)

◆ SADC_FIFO_CFG_PACK16_AMSEL

#define SADC_FIFO_CFG_PACK16_AMSEL (1u << 8)

◆ SADC_FIFO_CFG_PACK_M_16

#define SADC_FIFO_CFG_PACK_M_16 (0u)

◆ SADC_FIFO_CFG_PACK_M_32

#define SADC_FIFO_CFG_PACK_M_32 (1u)

◆ SADC_FIFO_CFG_PACK_M_64

#define SADC_FIFO_CFG_PACK_M_64 (2u)

◆ SADC_FIFO_CFG_PACK_M_MSK

#define SADC_FIFO_CFG_PACK_M_MSK (0x3u << SADC_FIFO_CFG_PACK_M_POS)

◆ SADC_FIFO_CFG_PACK_M_POS

#define SADC_FIFO_CFG_PACK_M_POS (0)

◆ SADC_HTC_DONE_LEN_MSK

#define SADC_HTC_DONE_LEN_MSK (0xFu << SADC_HTC_DONE_LEN_POS)

◆ SADC_HTC_DONE_LEN_POS

#define SADC_HTC_DONE_LEN_POS (0)

◆ SADC_HTC_READY

#define SADC_HTC_READY (1u << 31)

◆ SADC_HTC_READY_LEN_MSK

#define SADC_HTC_READY_LEN_MSK (0xFFu << SADC_HTC_READY_LEN_POS)

◆ SADC_HTC_READY_LEN_POS

#define SADC_HTC_READY_LEN_POS (8)

◆ SADC_INIT_DONE

#define SADC_INIT_DONE (1u << 24)

◆ SADC_INIT_START

#define SADC_INIT_START (1u << 20)

◆ SADC_INIT_VALUE_MSK

#define SADC_INIT_VALUE_MSK (0xFFFFFu << SADC_INIT_VALUE_POS)

◆ SADC_INIT_VALUE_POS

#define SADC_INIT_VALUE_POS (0)

◆ SADC_INT_STAT_END_COV_RC0

#define SADC_INT_STAT_END_COV_RC0 (1u << 3)

◆ SADC_INT_STAT_END_COV_RC1

#define SADC_INT_STAT_END_COV_RC1 (1u << 2)

◆ SADC_INT_STAT_END_COV_RC2

#define SADC_INT_STAT_END_COV_RC2 (1u << 1)

◆ SADC_INT_STAT_END_COV_RC3

#define SADC_INT_STAT_END_COV_RC3 (1u << 0)

◆ SADC_INT_STAT_END_COV_RCHT

#define SADC_INT_STAT_END_COV_RCHT (1u << 4)

◆ SADC_INT_STAT_MNT_CONT

#define SADC_INT_STAT_MNT_CONT (1u << 24)

◆ SADC_INT_STAT_MNT_SINGLE0

#define SADC_INT_STAT_MNT_SINGLE0 (1u << 16)

◆ SADC_INT_STAT_MNT_SINGLE1

#define SADC_INT_STAT_MNT_SINGLE1 (1u << 17)

◆ SADC_INT_STAT_MNT_SINGLE2

#define SADC_INT_STAT_MNT_SINGLE2 (1u << 18)

◆ SADC_INT_STAT_MNT_SINGLE3

#define SADC_INT_STAT_MNT_SINGLE3 (1u << 19)

◆ SADC_INT_STAT_MNT_SINGLE4

#define SADC_INT_STAT_MNT_SINGLE4 (1u << 20)

◆ SADC_INT_STAT_MNT_SINGLE5

#define SADC_INT_STAT_MNT_SINGLE5 (1u << 21)

◆ SADC_INT_STAT_MNT_SINGLE6

#define SADC_INT_STAT_MNT_SINGLE6 (1u << 22)

◆ SADC_INT_STAT_MNT_SINGLE7

#define SADC_INT_STAT_MNT_SINGLE7 (1u << 23)

◆ SADC_INT_STAT_SUB_FIFO0

#define SADC_INT_STAT_SUB_FIFO0 (1u << 8)

◆ SADC_INT_STAT_SUB_FIFO1

#define SADC_INT_STAT_SUB_FIFO1 (1u << 9)

◆ SADC_INT_STAT_SUB_FIFO2

#define SADC_INT_STAT_SUB_FIFO2 (1u << 10)

◆ SADC_INT_STAT_SUB_FIFO3

#define SADC_INT_STAT_SUB_FIFO3 (1u << 11)

◆ SADC_INT_STAT_TS_OVF

#define SADC_INT_STAT_TS_OVF (1u << 12)

◆ SADC_MNT_THRES_HIGH_MSK

#define SADC_MNT_THRES_HIGH_MSK (0xFFFu << SADC_MNT_THRES_HIGH_POS)

◆ SADC_MNT_THRES_HIGH_POS

#define SADC_MNT_THRES_HIGH_POS (0)

◆ SADC_MNT_THRES_LOW_MSK

#define SADC_MNT_THRES_LOW_MSK (0xFFFu << SADC_MNT_THRES_LOW_POS)

◆ SADC_MNT_THRES_LOW_POS

#define SADC_MNT_THRES_LOW_POS (16)

◆ SADC_MNT_THRES_MODE_BETWEEN

#define SADC_MNT_THRES_MODE_BETWEEN (0x2u << SADC_MNT_THRES_MODE_POS)

◆ SADC_MNT_THRES_MODE_CLOSE

#define SADC_MNT_THRES_MODE_CLOSE (0x3u << SADC_MNT_THRES_MODE_POS)

◆ SADC_MNT_THRES_MODE_HIGHER

#define SADC_MNT_THRES_MODE_HIGHER (0x0u << SADC_MNT_THRES_MODE_POS)

◆ SADC_MNT_THRES_MODE_LOWER

#define SADC_MNT_THRES_MODE_LOWER (0x1u << SADC_MNT_THRES_MODE_POS)

◆ SADC_MNT_THRES_MODE_MSK

#define SADC_MNT_THRES_MODE_MSK (0x3u << SADC_MNT_THRES_MODE_POS)

◆ SADC_MNT_THRES_MODE_POS

#define SADC_MNT_THRES_MODE_POS (28)

◆ SADC_RC_ENTRY_AMSEL_MSK

#define SADC_RC_ENTRY_AMSEL_MSK (0x1FFu << SADC_RC_ENTRY_AMSEL_POS)

◆ SADC_RC_ENTRY_AMSEL_POS

#define SADC_RC_ENTRY_AMSEL_POS (0)

◆ SADC_RC_ENTRY_CSEL_MSK

#define SADC_RC_ENTRY_CSEL_MSK (0xFu << SADC_RC_ENTRY_CSEL_POS)

◆ SADC_RC_ENTRY_CSEL_POS

#define SADC_RC_ENTRY_CSEL_POS (12)

◆ SADC_RC_ENTRY_RPT_CNT_MSK

#define SADC_RC_ENTRY_RPT_CNT_MSK (0xFu << SADC_RC_ENTRY_RPT_CNT_POS)

◆ SADC_RC_ENTRY_RPT_CNT_POS

#define SADC_RC_ENTRY_RPT_CNT_POS (24)

◆ SADC_RC_ENTRY_RPT_MODE

#define SADC_RC_ENTRY_RPT_MODE (1u << 16)

◆ SADC_RC_OVWR_CUR_EN

#define SADC_RC_OVWR_CUR_EN (1u << 16)

◆ SADC_RC_Q_CUR_MSK

#define SADC_RC_Q_CUR_MSK (0xFu << SADC_RC_Q_CUR_POS)

◆ SADC_RC_Q_CUR_POS

#define SADC_RC_Q_CUR_POS (0)

◆ SADC_RC_Q_END_MSK

#define SADC_RC_Q_END_MSK (0xFu << SADC_RC_Q_END_POS)

◆ SADC_RC_Q_END_POS

#define SADC_RC_Q_END_POS (8)

◆ SADC_RC_Q_START_MSK

#define SADC_RC_Q_START_MSK (0xFu << SADC_RC_Q_START_POS)

◆ SADC_RC_Q_START_POS

#define SADC_RC_Q_START_POS (4)

◆ SADC_RC_SOFT_TRG

#define SADC_RC_SOFT_TRG (1u << 15)

◆ SADC_RC_TIMER_COMPARE_MSK

#define SADC_RC_TIMER_COMPARE_MSK (0xFFFFu << SADC_RC_TIMER_COMPARE_POS)

◆ SADC_RC_TIMER_COMPARE_POS

#define SADC_RC_TIMER_COMPARE_POS (0)

◆ SADC_RC_TIMER_TERMINAL_MSK

#define SADC_RC_TIMER_TERMINAL_MSK (0xFFFFu << SADC_RC_TIMER_TERMINAL_POS)

◆ SADC_RC_TIMER_TERMINAL_POS

#define SADC_RC_TIMER_TERMINAL_POS (16)

◆ SADC_RC_TMR_SLAVE

#define SADC_RC_TMR_SLAVE (1u << 13)

◆ SADC_RC_TRG_EN

#define SADC_RC_TRG_EN (1u << 17)

◆ SADC_RC_TRG_MODE_SW

#define SADC_RC_TRG_MODE_SW (1u << 14)

◆ SADC_RC_TRG_START

#define SADC_RC_TRG_START (1u << 12)

◆ SADC_RCHT_ENTRY_AMSEL_MSK

#define SADC_RCHT_ENTRY_AMSEL_MSK (0x1FFu << SADC_RCHT_ENTRY_AMSEL_POS)

◆ SADC_RCHT_ENTRY_AMSEL_POS

#define SADC_RCHT_ENTRY_AMSEL_POS (0)

◆ SADC_RCHT_ENTRY_CSEL_MSK

#define SADC_RCHT_ENTRY_CSEL_MSK (0xFu << SADC_RCHT_ENTRY_CSEL_POS)

◆ SADC_RCHT_ENTRY_CSEL_POS

#define SADC_RCHT_ENTRY_CSEL_POS (12)

◆ SADC_RCHT_ENTRY_RPT_CNT_MSK

#define SADC_RCHT_ENTRY_RPT_CNT_MSK (0x7u << SADC_RCHT_ENTRY_RPT_CNT_POS)

◆ SADC_RCHT_ENTRY_RPT_CNT_POS

#define SADC_RCHT_ENTRY_RPT_CNT_POS (24)

◆ SADC_RCHT_ENTRY_RPT_MODE

#define SADC_RCHT_ENTRY_RPT_MODE (1u << 16)

◆ SADC_SCH_CFG_ASYNC_STALL

#define SADC_SCH_CFG_ASYNC_STALL (1u << 12)

◆ SADC_SCH_CFG_MODE_MASTER

#define SADC_SCH_CFG_MODE_MASTER (1u << 9)

◆ SADC_SCH_CFG_MODE_SYNC

#define SADC_SCH_CFG_MODE_SYNC (1u << 10)

◆ SADC_SCH_CFG_ROT_EN

#define SADC_SCH_CFG_ROT_EN (1u << 11)

◆ SADC_SCH_CFG_RST_DONE

#define SADC_SCH_CFG_RST_DONE (1u << 28)

◆ SADC_SCH_CFG_SLOT_CONST

#define SADC_SCH_CFG_SLOT_CONST (1u << 8)

◆ SADC_SCH_CFG_SLOT_HALT

#define SADC_SCH_CFG_SLOT_HALT (1u << 24)

◆ SADC_SCH_CFG_SLOT_ITVL_MSK

#define SADC_SCH_CFG_SLOT_ITVL_MSK (0xFFu << SADC_SCH_CFG_SLOT_ITVL_POS)

◆ SADC_SCH_CFG_SLOT_ITVL_POS

#define SADC_SCH_CFG_SLOT_ITVL_POS (0)

◆ SADC_SCH_CFG_SLOT_RST

#define SADC_SCH_CFG_SLOT_RST (1u << 25)

◆ SADC_SCH_CFG_SLV_DLY_MSK

#define SADC_SCH_CFG_SLV_DLY_MSK (0xFFu << SADC_SCH_CFG_SLV_DLY_POS)

◆ SADC_SCH_CFG_SLV_DLY_POS

#define SADC_SCH_CFG_SLV_DLY_POS (16)

◆ SADC_SCH_CFG_TS_RST

#define SADC_SCH_CFG_TS_RST (1u << 31)

◆ SADC_SCH_CFG_TS_VLD

#define SADC_SCH_CFG_TS_VLD (1u << 30)

◆ SADC_SCH_CID_CNT

#define SADC_SCH_CID_CNT (SDRV_ADC_CID_PART_CNT * SADC_SCH_CID_CNT_PER_REG)

◆ SADC_SCH_CID_CNT_PER_REG

#define SADC_SCH_CID_CNT_PER_REG (32 / SADC_SCH_CID_WIDTH_BIT)

◆ SADC_SCH_CID_MSK

#define SADC_SCH_CID_MSK (0x7u)

◆ SADC_SCH_CID_MV_NEXT

#define SADC_SCH_CID_MV_NEXT (7u)

◆ SADC_SCH_CID_WIDTH_BIT

#define SADC_SCH_CID_WIDTH_BIT (4)

◆ SADC_SOFT_RST_ANA

#define SADC_SOFT_RST_ANA (1u << 1)

◆ SADC_SOFT_RST_DIG

#define SADC_SOFT_RST_DIG (1u << 0)

◆ SADC_SOFT_RST_RC0TMR

#define SADC_SOFT_RST_RC0TMR (1u << 2)

◆ SADC_SOFT_RST_RC1TMR

#define SADC_SOFT_RST_RC1TMR (1u << 3)

◆ SADC_SOFT_RST_RC2TMR

#define SADC_SOFT_RST_RC2TMR (1u << 4)

◆ SADC_SOFT_RST_RC3TMR

#define SADC_SOFT_RST_RC3TMR (1u << 5)

◆ SADC_SOFT_RST_RC_POS

#define SADC_SOFT_RST_RC_POS (2)

◆ SADC_SUB_FIFO_EMPTY

#define SADC_SUB_FIFO_EMPTY (1u << 24)

◆ SADC_SUB_FIFO_FULL

#define SADC_SUB_FIFO_FULL (1u << 25)

◆ SADC_SUB_FIFO_RC_EN_MSK

#define SADC_SUB_FIFO_RC_EN_MSK (0x1Fu << SADC_SUB_FIFO_RC_EN_POS)

◆ SADC_SUB_FIFO_RC_EN_POS

#define SADC_SUB_FIFO_RC_EN_POS (16)

◆ SADC_SUB_FIFO_SADDR_MSK

#define SADC_SUB_FIFO_SADDR_MSK (0x7Fu << SADC_SUB_FIFO_SADDR_POS)

◆ SADC_SUB_FIFO_SADDR_POS

#define SADC_SUB_FIFO_SADDR_POS (0)

◆ SADC_SUB_FIFO_THRES_MSK

#define SADC_SUB_FIFO_THRES_MSK (0x7Fu << SADC_SUB_FIFO_THRES_POS)

◆ SADC_SUB_FIFO_THRES_POS

#define SADC_SUB_FIFO_THRES_POS (8)

◆ sdrv_adc1

#define sdrv_adc1 ((sdrv_adc_t *)APB_ADC1_BASE)

◆ sdrv_adc2

#define sdrv_adc2 ((sdrv_adc_t *)APB_ADC2_BASE)

◆ sdrv_adc3

#define sdrv_adc3 ((sdrv_adc_t *)APB_ADC3_BASE)

◆ SDRV_ADC_ANA_PARAM_CNT

#define SDRV_ADC_ANA_PARAM_CNT (16u)

◆ SDRV_ADC_CID_PART_CNT

#define SDRV_ADC_CID_PART_CNT (8u)

◆ SDRV_ADC_CLK_DIV_MAX

#define SDRV_ADC_CLK_DIV_MAX 32 /* max clock division ratio */

◆ SDRV_ADC_CLK_DIV_MIN

#define SDRV_ADC_CLK_DIV_MIN 5 /* recommended min clock division ratio */

◆ SDRV_ADC_FIFO_INPUT_ALL

#define SDRV_ADC_FIFO_INPUT_ALL (0x1Fu)

◆ SDRV_ADC_FIFO_INPUT_RC0

#define SDRV_ADC_FIFO_INPUT_RC0 (1u << 3)

◆ SDRV_ADC_FIFO_INPUT_RC1

#define SDRV_ADC_FIFO_INPUT_RC1 (1u << 2)

◆ SDRV_ADC_FIFO_INPUT_RC2

#define SDRV_ADC_FIFO_INPUT_RC2 (1u << 1)

◆ SDRV_ADC_FIFO_INPUT_RC3

#define SDRV_ADC_FIFO_INPUT_RC3 (1u << 0)

Descriptor for configuring FIFO data source.

◆ SDRV_ADC_FIFO_INPUT_RCHT

#define SDRV_ADC_FIFO_INPUT_RCHT (1u << 4)

◆ SDRV_ADC_FIFO_MODE_PACK16

#define SDRV_ADC_FIFO_MODE_PACK16 (0u)

◆ SDRV_ADC_FIFO_MODE_PACK32

#define SDRV_ADC_FIFO_MODE_PACK32 (1u)

◆ SDRV_ADC_FIFO_MODE_PACK64

#define SDRV_ADC_FIFO_MODE_PACK64 (2u)

◆ SDRV_ADC_INPUT_DIFF

#define SDRV_ADC_INPUT_DIFF 1

◆ SDRV_ADC_INPUT_SINGLE

#define SDRV_ADC_INPUT_SINGLE 0

◆ SDRV_ADC_MNT_SINGLE_CNT

#define SDRV_ADC_MNT_SINGLE_CNT (8u)

◆ SDRV_ADC_POLL_TMO

#define SDRV_ADC_POLL_TMO (1000 * 1000u)

◆ SDRV_ADC_RC_CNT

#define SDRV_ADC_RC_CNT (4u)

◆ SDRV_ADC_RC_ENTRY_CNT

#define SDRV_ADC_RC_ENTRY_CNT (16u)

◆ SDRV_ADC_RC_REPM_HW_TRG

#define SDRV_ADC_RC_REPM_HW_TRG 0

◆ SDRV_ADC_RC_REPM_SW_TRG

#define SDRV_ADC_RC_REPM_SW_TRG 1

◆ SDRV_ADC_RC_TMR_MODE_MASTER

#define SDRV_ADC_RC_TMR_MODE_MASTER 0

◆ SDRV_ADC_RC_TMR_MODE_SLAVE

#define SDRV_ADC_RC_TMR_MODE_SLAVE 1

◆ SDRV_ADC_RC_TRG_MODE_HW

#define SDRV_ADC_RC_TRG_MODE_HW 0

◆ SDRV_ADC_RC_TRG_MODE_SW

#define SDRV_ADC_RC_TRG_MODE_SW 1

◆ SDRV_ADC_RCHT_ENTRY_CNT

#define SDRV_ADC_RCHT_ENTRY_CNT (32u)

◆ SDRV_ADC_RCHT_REPEAT_1

#define SDRV_ADC_RCHT_REPEAT_1 0

◆ SDRV_ADC_RCHT_REPEAT_16

#define SDRV_ADC_RCHT_REPEAT_16 4

◆ SDRV_ADC_RCHT_REPEAT_2

#define SDRV_ADC_RCHT_REPEAT_2 1

◆ SDRV_ADC_RCHT_REPEAT_4

#define SDRV_ADC_RCHT_REPEAT_4 2

◆ SDRV_ADC_RCHT_REPEAT_8

#define SDRV_ADC_RCHT_REPEAT_8 3

◆ SDRV_ADC_REF_VREFP1

#define SDRV_ADC_REF_VREFP1 0

◆ SDRV_ADC_REF_VREFP2

#define SDRV_ADC_REF_VREFP2 1

◆ SDRV_ADC_SAMPLE_TIME_10D5

#define SDRV_ADC_SAMPLE_TIME_10D5 3

◆ SDRV_ADC_SAMPLE_TIME_130D5

#define SDRV_ADC_SAMPLE_TIME_130D5 7

◆ SDRV_ADC_SAMPLE_TIME_18D5

#define SDRV_ADC_SAMPLE_TIME_18D5 4

◆ SDRV_ADC_SAMPLE_TIME_2D5

#define SDRV_ADC_SAMPLE_TIME_2D5 0

◆ SDRV_ADC_SAMPLE_TIME_34D5

#define SDRV_ADC_SAMPLE_TIME_34D5 5

◆ SDRV_ADC_SAMPLE_TIME_4D5

#define SDRV_ADC_SAMPLE_TIME_4D5 1

◆ SDRV_ADC_SAMPLE_TIME_66D5

#define SDRV_ADC_SAMPLE_TIME_66D5 6

◆ SDRV_ADC_SAMPLE_TIME_6D5

#define SDRV_ADC_SAMPLE_TIME_6D5 2

◆ SDRV_ADC_START_ALL

#define SDRV_ADC_START_ALL ((1u << SDRV_ADC_RC_CNT) - 1)

◆ SDRV_ADC_START_RC0

#define SDRV_ADC_START_RC0 (1u << 0)

Descriptor for starting multiple RC timer at the same time.

◆ SDRV_ADC_START_RC1

#define SDRV_ADC_START_RC1 (1u << 1)

◆ SDRV_ADC_START_RC2

#define SDRV_ADC_START_RC2 (1u << 2)

◆ SDRV_ADC_START_RC3

#define SDRV_ADC_START_RC3 (1u << 3)

◆ SDRV_ADC_SUB_FIFO_CNT

#define SDRV_ADC_SUB_FIFO_CNT (4u)

Typedef Documentation

◆ sdrv_adc_ana_param_cfg_t

typedef struct sdrv_adc_ana_param_cfg sdrv_adc_ana_param_cfg_t

Analog Param configuration info.

◆ sdrv_adc_dma_src_cfg_t

typedef enum sdrv_adc_dma_src_cfg sdrv_adc_dma_src_cfg_t

Describe which source to trigger DMA request.

◆ sdrv_adc_fifo_cfg_t

typedef struct sdrv_adc_fifo_cfg sdrv_adc_fifo_cfg_t

FIFO configuration info.

◆ sdrv_adc_fifo_rc_cfg_t

typedef unsigned int sdrv_adc_fifo_rc_cfg_t

◆ sdrv_adc_rc_cfg_t

typedef struct sdrv_adc_rc_cfg sdrv_adc_rc_cfg_t

RC(Request Channel) configuration info.

◆ sdrv_adc_rc_entry_cfg_t

typedef struct sdrv_adc_rc_entry_cfg sdrv_adc_rc_entry_cfg_t

RC(Request Channel) entry configuration info.

◆ sdrv_adc_rc_start_flag_t

typedef unsigned int sdrv_adc_rc_start_flag_t

◆ sdrv_adc_rcht_entry_cfg_t

typedef struct sdrv_adc_rcht_entry_cfg sdrv_adc_rcht_entry_cfg_t

RCHT(Request Channel Hardware Trigger) entry configuration info.

◆ sdrv_adc_sync_cfg_t

typedef struct sdrv_adc_sync_cfg sdrv_adc_sync_cfg_t

Sync mode configuration info.

◆ sdrv_adc_sync_cid_t

typedef enum sdrv_adc_sync_cid sdrv_adc_sync_cid_t

Descriptor for configuring slot CID in sync mode.

◆ sdrv_adc_t

typedef volatile struct sdrv_adc sdrv_adc_t

Registers of ADC Controller.

Enumeration Type Documentation

◆ sdrv_adc_dma_src_cfg

enum sdrv_adc_dma_src_cfg

Describe which source to trigger DMA request.

Enumerator
SDRV_ADC_DMA_SRC_FIFO	fifo threshold
SDRV_ADC_DMA_SRC_RC0	RC0 conversion done
SDRV_ADC_DMA_SRC_RC1	RC1 conversion done
SDRV_ADC_DMA_SRC_RC2	RC2 conversion done
SDRV_ADC_DMA_SRC_RC3	RC3 conversion done
SDRV_ADC_DMA_SRC_RCHT	RCHT conversion done

◆ sdrv_adc_sync_cid

enum sdrv_adc_sync_cid

Descriptor for configuring slot CID in sync mode.

Enumerator
SDRV_ADC_SYNC_CID_RC0
SDRV_ADC_SYNC_CID_RC1
SDRV_ADC_SYNC_CID_RC2
SDRV_ADC_SYNC_CID_RC3
SDRV_ADC_SYNC_CID_RCHT
SDRV_ADC_SYNC_CID_MERGE
SDRV_ADC_SYNC_CID_IDLE

Function Documentation

◆ sdrv_adc_ana_param_cfg()

void sdrv_adc_ana_param_cfg	(	sdrv_adc_t *	sdrv_adcX,
		unsigned int	param_nbr,
		sdrv_adc_ana_param_cfg_t	aparam_cfg
	)

Configure one of the analog parameter array.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	param_nbr	parameter number [0, 15]
[in]	aparam_cfg	analog parameter configuration info

◆ sdrv_adc_Async_start()

void sdrv_adc_Async_start ( sdrv_adc_t * sdrv_adcX )

Put ADC in Async mode and start working.

Parameters

[in] sdrv_adcX ADC controller

◆ sdrv_adc_clear_int_status()

void sdrv_adc_clear_int_status	(	sdrv_adc_t *	sdrv_adcX,
		uint32_t	int_bits
	)

Clear ADC normal interrupt status.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	int_bits	interrupt bits to be cleared

◆ sdrv_adc_clr_slave_mode()

void sdrv_adc_clr_slave_mode ( sdrv_adc_t * sdrv_adcX )

Set ADC controller to Master mode.

Call this if it's set ot Slave mode and Slave mode isn't needed any more.

Parameters

[in] sdrv_adcX ADC controller

◆ sdrv_adc_dma_disable()

void sdrv_adc_dma_disable ( sdrv_adc_t * sdrv_adcX )

Disable DMA request of the ADC controller.

Parameters

[in] sdrv_adcX ADC controller

◆ sdrv_adc_dma_enable()

void sdrv_adc_dma_enable	(	sdrv_adc_t *	sdrv_adcX,
		sdrv_adc_dma_src_cfg_t	req_src
	)

Configure the source to trigger DMA request and enable it.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	req_src	DMA request source

◆ sdrv_adc_fifo_addr()

uintptr_t sdrv_adc_fifo_addr ( sdrv_adc_t * sdrv_adcX )

Return FIFO address of the ADC controller.

Parameters

[in] sdrv_adcX ADC controller

◆ sdrv_adc_fifo_cfg()

void sdrv_adc_fifo_cfg	(	sdrv_adc_t *	sdrv_adcX,
		sdrv_adc_fifo_cfg_t *	fifo_cfg
	)

Configure FIFO working mode.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	fifo_cfg	fifo configuration parameter

◆ sdrv_adc_fifo_rc_cfg()

void sdrv_adc_fifo_rc_cfg	(	sdrv_adc_t *	sdrv_adcX,
		sdrv_adc_fifo_rc_cfg_t	rc_cfg
	)

Configure which RC or RCHT could insert its data into FIFO.

After initialization, FIFO receives data from all RC and RCHT. Call this only if data from some RC or RCHT isn't needed.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	rc_cfg	could be any or combine of SDRV_ADC_FIFO_INPUT_RC*

◆ sdrv_adc_fifo_status()

uint32_t sdrv_adc_fifo_status ( sdrv_adc_t * sdrv_adcX )

Get ADC FIFO status.

Parameters

[in] sdrv_adcX ADC controller

◆ sdrv_adc_get_dc_offset()

int16_t sdrv_adc_get_dc_offset ( sdrv_adc_t * sdrv_adcX )

Get current data calibration offset value of ADC controller.

Parameters

[in]	sdrv_adcX	ADC controller
[out]	current	dc_offset value

◆ sdrv_adc_init()

void sdrv_adc_init	(	sdrv_adc_t *	sdrv_adcX,
		unsigned int	clk_div
	)

ADC controller init.

This function initializes the ADC controller device. Excluding clock divison ratio, the controller is initialized for common usage. If user need special configuration, call other functions after initialization.

Note: Call this function when switching between sync mode and Async mode.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	clk_div	clock division ratio for analog part

◆ sdrv_adc_int_status_en_cfg()

void sdrv_adc_int_status_en_cfg	(	sdrv_adc_t *	sdrv_adcX,
		uint32_t	int_bits,
		bool	enable
	)

Enable or disable ADC controller to record normal interrupt status.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	int_bits	interrupt bits
[in]	enable	set int_bits or clear int_bits

◆ sdrv_adc_int_status_sig_en_cfg()

void sdrv_adc_int_status_sig_en_cfg	(	sdrv_adc_t *	sdrv_adcX,
		uint32_t	int_bits,
		bool	enable
	)

Enable or disable ADC controller to trigger normal interrupt.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	int_bits	interrupt bits
[in]	enable	set int_bits or clear int_bits

◆ sdrv_adc_power_ctrl()

void sdrv_adc_power_ctrl	(	sdrv_adc_t *	sdrv_adcX,
		bool	down
	)

ADC analog reference configuration.

This function control BIAS and SAR analog part power down or power on.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	down	true for power down, false for power on

◆ sdrv_adc_rc_cfg()

void sdrv_adc_rc_cfg	(	sdrv_adc_t *	sdrv_adcX,
		unsigned int	rc_nbr,
		sdrv_adc_rc_cfg_t *	rc_cfg
	)

RC(Request Channel) configuration.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	int_bits	rc number [0, 3]
[in]	rc_cfg	RC configuration parameter

◆ sdrv_adc_rc_entry_cfg()

void sdrv_adc_rc_entry_cfg	(	sdrv_adc_t *	sdrv_adcX,
		unsigned int	rc_nbr,
		unsigned int	entry_nbr,
		sdrv_adc_rc_entry_cfg_t	entry_cfg
	)

Configure RC(Request Channel) entry.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	rc_nbr	RC number [0, 3]
[in]	entry_nbr	entry number [0, 15]
[in]	entry_cfg	entry configuration parameter, including channel info

◆ sdrv_adc_rc_soft_trg()

void sdrv_adc_rc_soft_trg	(	sdrv_adc_t *	sdrv_adcX,
		unsigned int	rc_nbr
	)

Trigger ADC conversion once if the RC is in software trigger mode.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	int_bits	rc number [0, 3]

◆ sdrv_adc_rc_start_timers()

void sdrv_adc_rc_start_timers	(	sdrv_adc_t *	sdrv_adcX,
		sdrv_adc_rc_start_flag_t	rc_flags
	)

Start multiple RC timer at the same time to trigger ADC conversion.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	rc_flags	flag of one or multiple rc number

◆ sdrv_adc_rc_start_tmr()

void sdrv_adc_rc_start_tmr	(	sdrv_adc_t *	sdrv_adcX,
		unsigned int	rc_nbr
	)

Start RC timer to trigger ADC conversion.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	int_bits	rc number [0, 3]

◆ sdrv_adc_rc_stop_tmr()

void sdrv_adc_rc_stop_tmr	(	sdrv_adc_t *	sdrv_adcX,
		unsigned int	rc_nbr
	)

Stop RC timer.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	int_bits	rc number [0, 3]

◆ sdrv_adc_rcht_clr_ready()

void sdrv_adc_rcht_clr_ready ( sdrv_adc_t * sdrv_adcX )

Clear RCHT(Request Channel Hardware Trigger) ready.

Parameters

[in] sdrv_adcX ADC controller

◆ sdrv_adc_rcht_entry_cfg()

void sdrv_adc_rcht_entry_cfg	(	sdrv_adc_t *	sdrv_adcX,
		unsigned int	entry_nbr,
		sdrv_adc_rcht_entry_cfg_t	entry_cfg
	)

Configure RCHT(Request Channel Hardware Trigger) entry.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	entry_nbr	entry number [0, 31]
[in]	entry_cfg	entry configuration parameter, including channel info

◆ sdrv_adc_rcht_ready()

void sdrv_adc_rcht_ready	(	sdrv_adc_t *	sdrv_adcX,
		uint8_t	ready_len
	)

Set RCHT(Request Channel Hardware Trigger) ready.

If RCHT is ready, RCHT receives signals from cross trigger.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	ready_len	htc ready length in sync mode. The recommended value is (sync slot_interval - 5). It's invalid in Async mode.

◆ sdrv_adc_read_fifo()

uint32_t sdrv_adc_read_fifo ( sdrv_adc_t * sdrv_adcX )

Read ADC FIFO data.

In pack16 mode, reading once returns 2 conversion data. In pack64 mode, must call this twice to get 1 conversion data.

Parameters

[in] sdrv_adcX ADC controller

◆ sdrv_adc_read_int_status()

uint32_t sdrv_adc_read_int_status ( sdrv_adc_t * sdrv_adcX )

Read ADC normal interrupt status.

Parameters

[in]	sdrv_adcX	ADC controller
[out]	normal	interrupt status

◆ sdrv_adc_set_dc_offset()

void sdrv_adc_set_dc_offset	(	sdrv_adc_t *	sdrv_adcX,
		int16_t	offset
	)

Set data calibration offset value of ADC controller.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	offset	dc_offset value

◆ sdrv_adc_set_slave_mode()

void sdrv_adc_set_slave_mode ( sdrv_adc_t * sdrv_adcX )

Set ADC controller to Slave mode.

After initialization, ADC controller is in Master mode. Call this if user needs Slave mode.

Parameters

[in] sdrv_adcX ADC controller

◆ sdrv_adc_stop()

void sdrv_adc_stop	(	sdrv_adc_t *	sdrv_adcX,
		bool	rc_tmr_stop
	)

Stop ADC from working.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	rc_tmr_stop	stop RC timer from running or not

◆ sdrv_adc_sync_cfg()

void sdrv_adc_sync_cfg	(	sdrv_adc_t *	sdrv_adcX,
		sdrv_adc_sync_cfg_t	sync_cfg,
		uint8_t *	slot_cid,
		unsigned int	len
	)

Configure slot CIDs and interval if it's in sync mode.

Parameters

[in]	sdrv_adcX	ADC controller
[in]	sync_cfg	slot interval and interval mode parameter
[in]	slot_cid	slot CID buffer, could be SDRV_ADC_SYNC_CID_*
[in]	len	slot CID buffer length [1, 64]

◆ sdrv_adc_sync_slot_reset()

void sdrv_adc_sync_slot_reset ( sdrv_adc_t * sdrv_adcX )

Reset slot CID pointer to 0 in sync mode.

Parameters

[in] sdrv_adcX ADC controller

◆ sdrv_adc_sync_start()

void sdrv_adc_sync_start ( sdrv_adc_t * sdrv_adcX )

Put ADC in sync mode and start working.

Call sdrv_adc_sync_cfg before this.

Parameters

[in] sdrv_adcX ADC controller

Data Structures

Functions

Detailed Description

Macro Definition Documentation

◆ ADC_CH_POLAR_NEG

◆ ADC_CH_POLAR_POS

◆ ADC_CH_SEL_TAISHAN

◆ ADC_DCH_SEL_TAISHAN

◆ SADC_ANA_PARAM_CCN_MSK

◆ SADC_ANA_PARAM_CCN_POS

◆ SADC_ANA_PARAM_CCP_MSK

◆ SADC_ANA_PARAM_CCP_POS

◆ SADC_ANA_PARAM_CCT_MSK

◆ SADC_ANA_PARAM_CCT_POS

◆ SADC_ANA_PARAM_DIFF_SEL

◆ SADC_ANA_PARAM_REF_SEL

◆ SADC_ANA_PARAM_SAMCTRL_MSK

◆ SADC_ANA_PARAM_SAMCTRL_POS

◆ SADC_ANA_REF_PART1_PD

◆ SADC_ANA_REF_PART1_PDBISA

◆ SADC_CLK_CTRL_DIV_BYPASS

◆ SADC_CLK_CTRL_REFH_MSK

◆ SADC_CLK_CTRL_REFH_POS

◆ SADC_CLK_CTRL_REFL_MSK

◆ SADC_CLK_CTRL_REFL_POS

◆ SADC_DCOC_EN

◆ SADC_DCOC_OVWR

◆ SADC_DCOC_START

◆ SADC_DCOC_TIMES_MSK

◆ SADC_DCOC_TIMES_POS

◆ SADC_DCOC_VALUE_DONE

◆ SADC_DCOC_VALUE_MSK

◆ SADC_DCOC_VALUE_POS

◆ SADC_DCOC_VALUE_SIGN

◆ SADC_DMA_CH0EN_F0RC0

◆ SADC_DMA_CH0EN_F1RC1

◆ SADC_DMA_CH0EN_F2RC2

◆ SADC_DMA_CH0EN_F3RC3

◆ SADC_DMA_CH0EN_RCHT

◆ SADC_DMA_CH1EN_F0RC0

◆ SADC_DMA_CH1EN_F1RC1

◆ SADC_DMA_CH1EN_F2RC2

◆ SADC_DMA_CH1EN_F3RC3

◆ SADC_DMA_CH1EN_RCHT

◆ SADC_DMA_MODE_FIFO0

◆ SADC_DMA_MODE_FIFO1

◆ SADC_DMA_MODE_FIFO2

◆ SADC_DMA_MODE_FIFO3

◆ SADC_DMA_MODE_RCHT

◆ SADC_FIFO_CFG_BYPASS

◆ SADC_FIFO_CFG_PACK16_AMSEL

◆ SADC_FIFO_CFG_PACK_M_16

◆ SADC_FIFO_CFG_PACK_M_32

◆ SADC_FIFO_CFG_PACK_M_64

◆ SADC_FIFO_CFG_PACK_M_MSK

◆ SADC_FIFO_CFG_PACK_M_POS

◆ SADC_HTC_DONE_LEN_MSK

◆ SADC_HTC_DONE_LEN_POS

◆ SADC_HTC_READY

◆ SADC_HTC_READY_LEN_MSK

◆ SADC_HTC_READY_LEN_POS

◆ SADC_INIT_DONE

◆ SADC_INIT_START

◆ SADC_INIT_VALUE_MSK

◆ SADC_INIT_VALUE_POS

◆ SADC_INT_STAT_END_COV_RC0

◆ SADC_INT_STAT_END_COV_RC1

◆ SADC_INT_STAT_END_COV_RC2

◆ SADC_INT_STAT_END_COV_RC3

◆ SADC_INT_STAT_END_COV_RCHT

◆ SADC_INT_STAT_MNT_CONT

◆ SADC_INT_STAT_MNT_SINGLE0

◆ SADC_INT_STAT_MNT_SINGLE1

◆ SADC_INT_STAT_MNT_SINGLE2

◆ SADC_INT_STAT_MNT_SINGLE3

◆ SADC_INT_STAT_MNT_SINGLE4

◆ SADC_INT_STAT_MNT_SINGLE5

◆ SADC_INT_STAT_MNT_SINGLE6

◆ SADC_INT_STAT_MNT_SINGLE7

◆ SADC_INT_STAT_SUB_FIFO0