267 lines
12 KiB
C
267 lines
12 KiB
C
/** ************************************************************************************************
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* SEMIDRIVE Copyright Statement
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* Copyright (c) SEMIDRIVE. All rights reserved
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*
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* This software and all rights therein are owned by SEMIDRIVE, and are
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* protected by copyright law and other relevant laws, regulations and
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* protection. Without SEMIDRIVE's prior written consent and/or related rights,
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* please do not use this software or any potion thereof in any form or by any
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* means. You may not reproduce, modify or distribute this software except in
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* compliance with the License. Unless required by applicable law or agreed to
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* in writing, software distributed under the License is distributed on
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* an 'AS IS' basis, WITHOUT WARRANTIES OF ANY KIND, either express or implied.
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*
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**************************************************************************************************/
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/** ************************************************************************************************
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* \file firewall_hw.h
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* \brief This file contains macros and interfaces for firewall hardware.
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*
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* <table>
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* <tr><th>Date <th>Version
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* <tr><td>2023/11/29 <td>1.0.0
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* </table>
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**************************************************************************************************/
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#ifndef _FIREWALL_HW_H_
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#define _FIREWALL_HW_H_
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/***************************************************************************************************
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* Include header files
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**************************************************************************************************/
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#include "regs_base.h"
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#include "core_id.h"
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/***************************************************************************************************
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* Global Macro definition
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**************************************************************************************************/
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/** \brief The id of the core SF master. */
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#define FIREWALL_MASTER_ID_CORE_SF (0U)
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/** \brief The id of the core SP0 master. */
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#define FIREWALL_MASTER_ID_CORE_SP0 (1U)
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/** \brief The id of the core SP1 master. */
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#define FIREWALL_MASTER_ID_CORE_SP1 (2U)
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/** \brief The id of the core SX0 master. */
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#define FIREWALL_MASTER_ID_CORE_SX0 (3U)
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/** \brief The id of the core SX1 master. */
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#define FIREWALL_MASTER_ID_CORE_SX1 (4U)
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/** \brief The id of the core DMA_SF master. */
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#define FIREWALL_MASTER_ID_DMA_SF (5U)
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/** \brief The id of the core GAMA master. */
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#define FIREWALL_MASTER_ID_GAMA (6U)
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/** \brief The id of the core ENET and FLEXRAY master. */
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#define FIREWALL_MASTER_ID_ENET_FLEXRAY (7U)
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/** \brief The id of the core DMA_AP master. */
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#define FIREWALL_MASTER_ID_DMA_AP (8U)
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/** \brief The id of the core USB master. */
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#define FIREWALL_MASTER_ID_USB (9U)
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/** \brief The id of the core SEHC master. */
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#define FIREWALL_MASTER_ID_SEHC (10U)
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/** \brief The id of the core SEIP master. */
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#define FIREWALL_MASTER_ID_SEIP (11U)
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/** \brief The id of the core CSI master. */
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#define FIREWALL_MASTER_ID_CSI (12U)
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/** \brief The id of the core DC master. */
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#define FIREWALL_MASTER_ID_DC (13U)
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/** \brief The id of the core G2D master. */
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#define FIREWALL_MASTER_ID_G2D (14U)
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/** \brief The id of the core XSPISLV master. */
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#define FIREWALL_MASTER_ID_PTB_XSPISLV (15U)
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/** \brief The maximum number of masters. */
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#define FIREWALL_MASTER_MAXNUM (16U)
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/** \brief The id of the SF domain. */
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#define FIREWALL_DOMAIN_ID_SF (0x7U)
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/** \brief The id of the SP0 domain. */
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#define FIREWALL_DOMAIN_ID_SP0 (0x2U)
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/** \brief The id of the SP1 domain. */
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#define FIREWALL_DOMAIN_ID_SP1 (0x3U)
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/** \brief The id of the SX0 domain. */
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#define FIREWALL_DOMAIN_ID_SX0 (0x4U)
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/** \brief The id of the SX1 domain. */
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#define FIREWALL_DOMAIN_ID_SX1 (0x5U)
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/** \brief The id of the UNLOCK domain. */
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#define FIREWALL_DOMAIN_ID_UNLOCK (0x0U)
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/** \brief The id of the LOCK domain. */
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#define FIREWALL_DOMAIN_ID_LOCK (0x1U)
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/** \brief The id of the DMA domain. */
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#define FIREWALL_DOMAIN_ID_DMA (0x6U)
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/** \brief The maximum number of domains. */
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#define FIREWALL_DOMAIN_MAXNUM (0x8U)
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#define FIREWALL_MAIN_MASTER_ID FIREWALL_MASTER_ID_CORE_SF
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#define FIREWALL_MANAGER_DOMAIN_ID FIREWALL_DOMAIN_ID_SF
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/** \brief The maximum number of apbmux. */
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#define FIREWALL_PPC_APBMUX_MAXNUM (7U)
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/** \brief The maximum number of memory ports. */
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#define FIREWALL_MPC_MEMPORT_MAXNUM (23U)
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/** \brief The maximum number of regions for the ROM memory port. */
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#define FIREWALL_MPC_ROM_MAXREGION (1U)
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/** \brief The maximum number of regions for the RAM memory port. */
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#define FIREWALL_MPC_RAM_MAXREGION (8U)
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/** \brief The maximum number of regions for the DRAM memory port. */
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#define FIREWALL_MPC_DRAM_MAXREGION (16U)
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/** \brief The maximum number of regions for the XSPI memory port. */
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#define FIREWALL_MPC_XSPI_MAXREGION (16U)
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/** \brief The maximum number of regions for the MB memory port. */
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#define FIREWALL_MPC_MB_MAXREGION (8U)
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/** \brief The maximum number of regions for the VIC memory port. */
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#define FIREWALL_MPC_VIC_MAXREGION (1U)
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/** \brief The maximum number of regions for the CR5 memory port. */
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#define FIREWALL_MPC_CR5_MAXREGION (8U)
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/** \brief The maximum number of regions for the SEIP memory port. */
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#define FIREWALL_MPC_SEIP_MAXREGION (8U)
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/** \brief The maximum number of regions for the GAMA memory port. */
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#define FIREWALL_MPC_GAMA_MAXREGION (8U)
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/** \brief The id of the MPC reserved port. */
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#define FIREWALL_MPC_RESERVED_PORTID (16U)
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/** \brief The offset address of the ROM mpc register. */
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#define FIREWALL_MPC_ROMC_ADDR_OFFSET ((uint16_t)0x800U)
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/** \brief The offset address of the RAM1C mpc register. */
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#define FIREWALL_MPC_RAM1C_ADDR_OFFSET ((uint16_t)0xC00U)
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/** \brief The offset address of the RAM2C mpc register. */
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#define FIREWALL_MPC_RAM2C_ADDR_OFFSET ((uint16_t)0x1000U)
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/** \brief The offset address of the RAM3C mpc register. */
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#define FIREWALL_MPC_RAM3C_ADDR_OFFSET ((uint16_t)0x1400U)
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/** \brief The offset address of the RAM4C mpc register. */
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#define FIREWALL_MPC_RAM4C_ADDR_OFFSET ((uint16_t)0x1800U)
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/** \brief The offset address of the SDRAMC mpc register. */
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#define FIREWALL_MPC_SDRAMC_ADDR_OFFSET ((uint16_t)0x1C00U)
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/** \brief The offset address of the XSPI1A mpc register. */
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#define FIREWALL_MPC_XSPI1A_ADDR_OFFSET ((uint16_t)0x2000U)
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/** \brief The offset address of the XSPI1B mpc register. */
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#define FIREWALL_MPC_XSPI1B_ADDR_OFFSET ((uint16_t)0x2400U)
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/** \brief The offset address of the XSPI2A mpc register. */
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#define FIREWALL_MPC_XSPI2A_ADDR_OFFSET ((uint16_t)0x2800U)
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/** \brief The offset address of the XSPI2B mpc register. */
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#define FIREWALL_MPC_XSPI2B_ADDR_OFFSET ((uint16_t)0x2C00U)
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/** \brief The offset address of the MB mpc register. */
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#define FIREWALL_MPC_MB_ADDR_OFFSET ((uint16_t)0x3000U)
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/** \brief The offset address of the VIC1 mpc register. */
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#define FIREWALL_MPC_VIC1_ADDR_OFFSET ((uint16_t)0x3400U)
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/** \brief The offset address of the VIC2A mpc register. */
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#define FIREWALL_MPC_VIC2A_ADDR_OFFSET ((uint16_t)0x3800U)
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/** \brief The offset address of the VIC2B mpc register. */
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#define FIREWALL_MPC_VIC2B_ADDR_OFFSET ((uint16_t)0x3C00U)
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/** \brief The offset address of the VIC3A mpc register. */
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#define FIREWALL_MPC_VIC3A_ADDR_OFFSET ((uint16_t)0x4000U)
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/** \brief The offset address of the VIC3B mpc register. */
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#define FIREWALL_MPC_VIC3B_ADDR_OFFSET ((uint16_t)0x4400U)
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/** \brief The offset address of the CR5SF mpc register. */
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#define FIREWALL_MPC_CR5SF_ADDR_OFFSET ((uint16_t)0x4C00U)
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/** \brief The offset address of the CR5SP0 mpc register. */
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#define FIREWALL_MPC_CR5SP0_ADDR_OFFSET ((uint16_t)0x5000U)
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/** \brief The offset address of the CR5SP1 mpc register. */
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#define FIREWALL_MPC_CR5SP1_ADDR_OFFSET ((uint16_t)0x5400U)
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/** \brief The offset address of the CR5SX0 mpc register. */
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#define FIREWALL_MPC_CR5SX0_ADDR_OFFSET ((uint16_t)0x5800U)
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/** \brief The offset address of the CR5SX1 mpc register. */
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#define FIREWALL_MPC_CR5SX1_ADDR_OFFSET ((uint16_t)0x5C00U)
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/** \brief The offset address of the SEIP mpc register. */
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#define FIREWALL_MPC_SEIP_ADDR_OFFSET ((uint16_t)0x6000U)
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/** \brief The offset address of the GAMA mpc register. */
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#define FIREWALL_MPC_GAMA_ADDR_OFFSET ((uint16_t)0x6400U)
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/** \brief The maximum number of peripherals in apbmux1. */
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#define FIREWALL_PPC_APBMUX1_IP_MAXNUM (16U)
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/** \brief The maximum number of peripherals in apbmux2. */
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#define FIREWALL_PPC_APBMUX2_IP_MAXNUM (64U)
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/** \brief The maximum number of peripherals in apbmux3. */
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#define FIREWALL_PPC_APBMUX3_IP_MAXNUM (64U)
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/** \brief The maximum number of peripherals in apbmux4. */
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#define FIREWALL_PPC_APBMUX4_IP_MAXNUM (64U)
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/** \brief The maximum number of peripherals in apbmux5. */
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#define FIREWALL_PPC_APBMUX5_IP_MAXNUM (32U)
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/** \brief The maximum number of peripherals in apbmux6. */
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#define FIREWALL_PPC_APBMUX6_IP_MAXNUM (32U)
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/** \brief The maximum number of peripherals in apbmux7. */
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#define FIREWALL_PPC_APBMUX7_IP_MAXNUM (16U)
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/** \brief The maximum number of peripherals. */
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#define FIREWALL_PPC_IP_MAXNUM (288U)
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/** \brief The offset address of the apbmux1 ppc register. */
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#define FIREWALL_PPC_APBMUX_OFFSET ((uint32_t)0x8000U)
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/** \brief The base address of GPIO_SF controller. */
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#ifdef APB_GPIO_SF_BASE
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#define FIREWALL_APB_GPIO_SF_BASE APB_GPIO_SF_BASE
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#endif /* #ifdef APB_GPIO_SF_BASE */
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/** \brief The base address of GPIO_AP controller. */
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#ifdef APB_GPIO_AP_BASE
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#define FIREWALL_APB_GPIO_AP_BASE APB_GPIO_AP_BASE
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#endif /* #ifdef APB_GPIO_AP_BASE */
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/** \brief The maximum number of cores. */
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#define FIREWALL_GPIO_CORE_MAXNUM (5U)
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/** \brief The maximum number of gpio pin channels. */
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#define FIREWALL_GPIO_CHANNEL_MAXNUM (214U)
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/** \brief The maximum number of sf gpio pin channels. */
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#define FIREWALL_GPIO_SF_MAXNUM (0x87U)
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/** \brief The maximum number of ap gpio pin channels. */
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#define FIREWALL_GPIO_AP_MAXNUM (0x4FU)
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/** \brief The id of SF domain in gpio module. */
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#ifdef CORE_SF
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#define FIREWALL_GPIO_DGSEL_CORE0 CORE_SF
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#endif /* #ifdef CORE_SF */
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/** \brief The id of SP0 domain in gpio module. */
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#ifdef CORE_SP0
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#define FIREWALL_GPIO_DGSEL_CORE1 CORE_SP0
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#endif /* #ifdef CORE_SP0 */
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/** \brief The id of SP1 domain in gpio module. */
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#ifdef CORE_SP1
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#define FIREWALL_GPIO_DGSEL_CORE2 CORE_SP1
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#endif /* #ifdef CORE_SP1 */
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/** \brief The id of SX0 domain in gpio module. */
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#ifdef CORE_SX0
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#define FIREWALL_GPIO_DGSEL_CORE3 CORE_SX0
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#endif /* #ifdef CORE_SX0 */
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/** \brief The id of SX1 domain in gpio module. */
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#ifdef CORE_SX1
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#define FIREWALL_GPIO_DGSEL_CORE4 CORE_SX1
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#endif /* #ifdef CORE_SX1 */
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/***************************************************************************************************
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* Global Function Declarations
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**************************************************************************************************/
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/**
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* @brief Get the maximum number of memory regions in the specified memory port.
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*
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* This function return the maximum number of regions for the port.
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*
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* @param[in] base_offset the offset address of the port.
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*
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* @return The maximum number of regions for the port.
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*/
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uint8_t mpc_get_region_maxnum(uint16_t base_offset);
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/**
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* @brief Get the maximum number of peripherals for the apbmux.
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*
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* This function get the maximum number of peripherals in the specified apbmux.
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*
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* @param[in] ppc_apbmux_id the id of the apbmux.
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*
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* @return The maximum number of peripherals for the apbmux.
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*/
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uint16_t sdrv_firewall_ppc_get_apbmux_ip_maxnum(uint8_t ppc_apbmux_id);
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/**
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* @brief Get the base address of the gpio controller.
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*
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* @param[in] channel_id The id of the pin channel.
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* @param[in] gpio_Base The base address of the gpio controller.
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*
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* @return The result of this function.
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* @details - return FIREWALL_E_OK : Get the specified gpio base address success.
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* - return FIREWALL_E_GPIO_CHANNEL_ID : The id of the pin channel is unvalid.
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*/
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bool sdrv_firewall_gpio_get_base_addr(uint16_t *channel_id,
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uint32_t *gpio_Base);
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#endif /* _FIREWALL_HW_H_ */
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/* End of file */
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