/** ************************************************************************************************ * SEMIDRIVE Copyright Statement * Copyright (c) SEMIDRIVE. All rights reserved * * This software and all rights therein are owned by SEMIDRIVE, and are * protected by copyright law and other relevant laws, regulations and * protection. Without SEMIDRIVE's prior written consent and/or related rights, * please do not use this software or any potion thereof in any form or by any * means. You may not reproduce, modify or distribute this software except in * compliance with the License. Unless required by applicable law or agreed to * in writing, software distributed under the License is distributed on * an 'AS IS' basis, WITHOUT WARRANTIES OF ANY KIND, either express or implied. * **************************************************************************************************/ /** ************************************************************************************************ * \file firewall_hw.h * \brief This file contains macros and interfaces for firewall hardware. * * *
Date Version *
2023/11/29 1.0.0 *
**************************************************************************************************/ #ifndef _FIREWALL_HW_H_ #define _FIREWALL_HW_H_ /*************************************************************************************************** * Include header files **************************************************************************************************/ #include "regs_base.h" #include "core_id.h" /*************************************************************************************************** * Global Macro definition **************************************************************************************************/ /** \brief The id of the core SF master. */ #define FIREWALL_MASTER_ID_CORE_SF (0U) /** \brief The id of the core SP0 master. */ #define FIREWALL_MASTER_ID_CORE_SP0 (1U) /** \brief The id of the core SP1 master. */ #define FIREWALL_MASTER_ID_CORE_SP1 (2U) /** \brief The id of the core SX0 master. */ #define FIREWALL_MASTER_ID_CORE_SX0 (3U) /** \brief The id of the core SX1 master. */ #define FIREWALL_MASTER_ID_CORE_SX1 (4U) /** \brief The id of the core DMA_SF master. */ #define FIREWALL_MASTER_ID_DMA_SF (5U) /** \brief The id of the core GAMA master. */ #define FIREWALL_MASTER_ID_GAMA (6U) /** \brief The id of the core ENET and FLEXRAY master. */ #define FIREWALL_MASTER_ID_ENET_FLEXRAY (7U) /** \brief The id of the core DMA_AP master. */ #define FIREWALL_MASTER_ID_DMA_AP (8U) /** \brief The id of the core USB master. */ #define FIREWALL_MASTER_ID_USB (9U) /** \brief The id of the core SEHC master. */ #define FIREWALL_MASTER_ID_SEHC (10U) /** \brief The id of the core SEIP master. */ #define FIREWALL_MASTER_ID_SEIP (11U) /** \brief The id of the core CSI master. */ #define FIREWALL_MASTER_ID_CSI (12U) /** \brief The id of the core DC master. */ #define FIREWALL_MASTER_ID_DC (13U) /** \brief The id of the core G2D master. */ #define FIREWALL_MASTER_ID_G2D (14U) /** \brief The id of the core XSPISLV master. */ #define FIREWALL_MASTER_ID_PTB_XSPISLV (15U) /** \brief The maximum number of masters. */ #define FIREWALL_MASTER_MAXNUM (16U) /** \brief The id of the SF domain. */ #define FIREWALL_DOMAIN_ID_SF (0x7U) /** \brief The id of the SP0 domain. */ #define FIREWALL_DOMAIN_ID_SP0 (0x2U) /** \brief The id of the SP1 domain. */ #define FIREWALL_DOMAIN_ID_SP1 (0x3U) /** \brief The id of the SX0 domain. */ #define FIREWALL_DOMAIN_ID_SX0 (0x4U) /** \brief The id of the SX1 domain. */ #define FIREWALL_DOMAIN_ID_SX1 (0x5U) /** \brief The id of the UNLOCK domain. */ #define FIREWALL_DOMAIN_ID_UNLOCK (0x0U) /** \brief The id of the LOCK domain. */ #define FIREWALL_DOMAIN_ID_LOCK (0x1U) /** \brief The id of the DMA domain. */ #define FIREWALL_DOMAIN_ID_DMA (0x6U) /** \brief The maximum number of domains. */ #define FIREWALL_DOMAIN_MAXNUM (0x8U) #define FIREWALL_MAIN_MASTER_ID FIREWALL_MASTER_ID_CORE_SF #define FIREWALL_MANAGER_DOMAIN_ID FIREWALL_DOMAIN_ID_SF /** \brief The maximum number of apbmux. */ #define FIREWALL_PPC_APBMUX_MAXNUM (7U) /** \brief The maximum number of memory ports. */ #define FIREWALL_MPC_MEMPORT_MAXNUM (23U) /** \brief The maximum number of regions for the ROM memory port. */ #define FIREWALL_MPC_ROM_MAXREGION (1U) /** \brief The maximum number of regions for the RAM memory port. */ #define FIREWALL_MPC_RAM_MAXREGION (8U) /** \brief The maximum number of regions for the DRAM memory port. */ #define FIREWALL_MPC_DRAM_MAXREGION (16U) /** \brief The maximum number of regions for the XSPI memory port. */ #define FIREWALL_MPC_XSPI_MAXREGION (16U) /** \brief The maximum number of regions for the MB memory port. */ #define FIREWALL_MPC_MB_MAXREGION (8U) /** \brief The maximum number of regions for the VIC memory port. */ #define FIREWALL_MPC_VIC_MAXREGION (1U) /** \brief The maximum number of regions for the CR5 memory port. */ #define FIREWALL_MPC_CR5_MAXREGION (8U) /** \brief The maximum number of regions for the SEIP memory port. */ #define FIREWALL_MPC_SEIP_MAXREGION (8U) /** \brief The maximum number of regions for the GAMA memory port. */ #define FIREWALL_MPC_GAMA_MAXREGION (8U) /** \brief The id of the MPC reserved port. */ #define FIREWALL_MPC_RESERVED_PORTID (16U) /** \brief The offset address of the ROM mpc register. */ #define FIREWALL_MPC_ROMC_ADDR_OFFSET ((uint16_t)0x800U) /** \brief The offset address of the RAM1C mpc register. */ #define FIREWALL_MPC_RAM1C_ADDR_OFFSET ((uint16_t)0xC00U) /** \brief The offset address of the RAM2C mpc register. */ #define FIREWALL_MPC_RAM2C_ADDR_OFFSET ((uint16_t)0x1000U) /** \brief The offset address of the RAM3C mpc register. */ #define FIREWALL_MPC_RAM3C_ADDR_OFFSET ((uint16_t)0x1400U) /** \brief The offset address of the RAM4C mpc register. */ #define FIREWALL_MPC_RAM4C_ADDR_OFFSET ((uint16_t)0x1800U) /** \brief The offset address of the SDRAMC mpc register. */ #define FIREWALL_MPC_SDRAMC_ADDR_OFFSET ((uint16_t)0x1C00U) /** \brief The offset address of the XSPI1A mpc register. */ #define FIREWALL_MPC_XSPI1A_ADDR_OFFSET ((uint16_t)0x2000U) /** \brief The offset address of the XSPI1B mpc register. */ #define FIREWALL_MPC_XSPI1B_ADDR_OFFSET ((uint16_t)0x2400U) /** \brief The offset address of the XSPI2A mpc register. */ #define FIREWALL_MPC_XSPI2A_ADDR_OFFSET ((uint16_t)0x2800U) /** \brief The offset address of the XSPI2B mpc register. */ #define FIREWALL_MPC_XSPI2B_ADDR_OFFSET ((uint16_t)0x2C00U) /** \brief The offset address of the MB mpc register. */ #define FIREWALL_MPC_MB_ADDR_OFFSET ((uint16_t)0x3000U) /** \brief The offset address of the VIC1 mpc register. */ #define FIREWALL_MPC_VIC1_ADDR_OFFSET ((uint16_t)0x3400U) /** \brief The offset address of the VIC2A mpc register. */ #define FIREWALL_MPC_VIC2A_ADDR_OFFSET ((uint16_t)0x3800U) /** \brief The offset address of the VIC2B mpc register. */ #define FIREWALL_MPC_VIC2B_ADDR_OFFSET ((uint16_t)0x3C00U) /** \brief The offset address of the VIC3A mpc register. */ #define FIREWALL_MPC_VIC3A_ADDR_OFFSET ((uint16_t)0x4000U) /** \brief The offset address of the VIC3B mpc register. */ #define FIREWALL_MPC_VIC3B_ADDR_OFFSET ((uint16_t)0x4400U) /** \brief The offset address of the CR5SF mpc register. */ #define FIREWALL_MPC_CR5SF_ADDR_OFFSET ((uint16_t)0x4C00U) /** \brief The offset address of the CR5SP0 mpc register. */ #define FIREWALL_MPC_CR5SP0_ADDR_OFFSET ((uint16_t)0x5000U) /** \brief The offset address of the CR5SP1 mpc register. */ #define FIREWALL_MPC_CR5SP1_ADDR_OFFSET ((uint16_t)0x5400U) /** \brief The offset address of the CR5SX0 mpc register. */ #define FIREWALL_MPC_CR5SX0_ADDR_OFFSET ((uint16_t)0x5800U) /** \brief The offset address of the CR5SX1 mpc register. */ #define FIREWALL_MPC_CR5SX1_ADDR_OFFSET ((uint16_t)0x5C00U) /** \brief The offset address of the SEIP mpc register. */ #define FIREWALL_MPC_SEIP_ADDR_OFFSET ((uint16_t)0x6000U) /** \brief The offset address of the GAMA mpc register. */ #define FIREWALL_MPC_GAMA_ADDR_OFFSET ((uint16_t)0x6400U) /** \brief The maximum number of peripherals in apbmux1. */ #define FIREWALL_PPC_APBMUX1_IP_MAXNUM (16U) /** \brief The maximum number of peripherals in apbmux2. */ #define FIREWALL_PPC_APBMUX2_IP_MAXNUM (64U) /** \brief The maximum number of peripherals in apbmux3. */ #define FIREWALL_PPC_APBMUX3_IP_MAXNUM (64U) /** \brief The maximum number of peripherals in apbmux4. */ #define FIREWALL_PPC_APBMUX4_IP_MAXNUM (64U) /** \brief The maximum number of peripherals in apbmux5. */ #define FIREWALL_PPC_APBMUX5_IP_MAXNUM (32U) /** \brief The maximum number of peripherals in apbmux6. */ #define FIREWALL_PPC_APBMUX6_IP_MAXNUM (32U) /** \brief The maximum number of peripherals in apbmux7. */ #define FIREWALL_PPC_APBMUX7_IP_MAXNUM (16U) /** \brief The maximum number of peripherals. */ #define FIREWALL_PPC_IP_MAXNUM (288U) /** \brief The offset address of the apbmux1 ppc register. */ #define FIREWALL_PPC_APBMUX_OFFSET ((uint32_t)0x8000U) /** \brief The base address of GPIO_SF controller. */ #ifdef APB_GPIO_SF_BASE #define FIREWALL_APB_GPIO_SF_BASE APB_GPIO_SF_BASE #endif /* #ifdef APB_GPIO_SF_BASE */ /** \brief The base address of GPIO_AP controller. */ #ifdef APB_GPIO_AP_BASE #define FIREWALL_APB_GPIO_AP_BASE APB_GPIO_AP_BASE #endif /* #ifdef APB_GPIO_AP_BASE */ /** \brief The maximum number of cores. */ #define FIREWALL_GPIO_CORE_MAXNUM (5U) /** \brief The maximum number of gpio pin channels. */ #define FIREWALL_GPIO_CHANNEL_MAXNUM (214U) /** \brief The maximum number of sf gpio pin channels. */ #define FIREWALL_GPIO_SF_MAXNUM (0x87U) /** \brief The maximum number of ap gpio pin channels. */ #define FIREWALL_GPIO_AP_MAXNUM (0x4FU) /** \brief The id of SF domain in gpio module. */ #ifdef CORE_SF #define FIREWALL_GPIO_DGSEL_CORE0 CORE_SF #endif /* #ifdef CORE_SF */ /** \brief The id of SP0 domain in gpio module. */ #ifdef CORE_SP0 #define FIREWALL_GPIO_DGSEL_CORE1 CORE_SP0 #endif /* #ifdef CORE_SP0 */ /** \brief The id of SP1 domain in gpio module. */ #ifdef CORE_SP1 #define FIREWALL_GPIO_DGSEL_CORE2 CORE_SP1 #endif /* #ifdef CORE_SP1 */ /** \brief The id of SX0 domain in gpio module. */ #ifdef CORE_SX0 #define FIREWALL_GPIO_DGSEL_CORE3 CORE_SX0 #endif /* #ifdef CORE_SX0 */ /** \brief The id of SX1 domain in gpio module. */ #ifdef CORE_SX1 #define FIREWALL_GPIO_DGSEL_CORE4 CORE_SX1 #endif /* #ifdef CORE_SX1 */ /*************************************************************************************************** * Global Function Declarations **************************************************************************************************/ /** * @brief Get the maximum number of memory regions in the specified memory port. * * This function return the maximum number of regions for the port. * * @param[in] base_offset the offset address of the port. * * @return The maximum number of regions for the port. */ uint8_t mpc_get_region_maxnum(uint16_t base_offset); /** * @brief Get the maximum number of peripherals for the apbmux. * * This function get the maximum number of peripherals in the specified apbmux. * * @param[in] ppc_apbmux_id the id of the apbmux. * * @return The maximum number of peripherals for the apbmux. */ uint16_t sdrv_firewall_ppc_get_apbmux_ip_maxnum(uint8_t ppc_apbmux_id); /** * @brief Get the base address of the gpio controller. * * @param[in] channel_id The id of the pin channel. * @param[in] gpio_Base The base address of the gpio controller. * * @return The result of this function. * @details - return FIREWALL_E_OK : Get the specified gpio base address success. * - return FIREWALL_E_GPIO_CHANNEL_ID : The id of the pin channel is unvalid. */ bool sdrv_firewall_gpio_get_base_addr(uint16_t *channel_id, uint32_t *gpio_Base); #endif /* _FIREWALL_HW_H_ */ /* End of file */