lvds_reg.h File Reference

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Detailed Description

Copyright

Copyright (c) 2022 Semidrive Semiconductor. All rights reserved.

Macro Definition Documentation

CH0_ATEST_SEL_MASK

#define CH0_ATEST_SEL_MASK   0x7 << CH0_ATEST_SEL_SHIFT

CH0_ATEST_SEL_SHIFT

#define CH0_ATEST_SEL_SHIFT   16

CH0_BPP_MASK

#define CH0_BPP_MASK   0x3 << CH0_BPP_SHIFT

CH0_BPP_SHIFT

#define CH0_BPP_SHIFT   1

CH0_CMP_MASK_MASK

#define CH0_CMP_MASK_MASK   0xFFFF << CH0_CMP_MASK_SHFIT

CH0_CMP_MASK_SHFIT

#define CH0_CMP_MASK_SHFIT   24

CH0_COM_EN_MASK

#define CH0_COM_EN_MASK   0x1 << CH0_COM_EN_SHIFT

CH0_COM_EN_SHIFT

#define CH0_COM_EN_SHIFT   3

CH0_DATA_CLK_DELAY_MASK

#define CH0_DATA_CLK_DELAY_MASK   0x3 << CH0_DATA_CLK_DELAY_SHIFT

CH0_DATA_CLK_DELAY_SHIFT

#define CH0_DATA_CLK_DELAY_SHIFT   1

CH0_DATA_CLK_PT_SL_MASK

#define CH0_DATA_CLK_PT_SL_MASK   0x7F << CH0_DATA_CLK_PT_SL_SHIFT

CH0_DATA_CLK_PT_SL_SHIFT

#define CH0_DATA_CLK_PT_SL_SHIFT   4

CH0_DTEST_OUT_MASK

#define CH0_DTEST_OUT_MASK   0x1 << CH0_DTEST_OUT_SHIFT

CH0_DTEST_OUT_SHIFT

#define CH0_DTEST_OUT_SHIFT   23

CH0_DTEST_SEL_MASK

#define CH0_DTEST_SEL_MASK   0x3 << CH0_DTEST_SEL_SHIFT

CH0_DTEST_SEL_SHIFT

#define CH0_DTEST_SEL_SHIFT   14

CH0_DUALMODE_MASK

#define CH0_DUALMODE_MASK   0x1 << CH0_DUALMODE_SHIFT

CH0_DUALMODE_SHIFT

#define CH0_DUALMODE_SHIFT   0

CH0_DUALODD_MASK

#define CH0_DUALODD_MASK   0x1 << CH0_DUALODD_SHIFT

CH0_DUALODD_SHIFT

#define CH0_DUALODD_SHIFT   22

CH0_EN_MASK

#define CH0_EN_MASK   (unsigned int)0x1 << CH0_EN_SHIFT

CH0_EN_SHIFT

#define CH0_EN_SHIFT   31

CH0_ERR_CLK_MASK

#define CH0_ERR_CLK_MASK   0x1 << CH0_ERR_CLK_SHIFT

CH0_ERR_CLK_SHIFT

#define CH0_ERR_CLK_SHIFT   0

CH0_FORMAT_MASK

#define CH0_FORMAT_MASK   0x1 << CH0_FORMAT_SHIFT

CH0_FORMAT_SHIFT

#define CH0_FORMAT_SHIFT   3

CH0_FRAME_MASK_MASK

#define CH0_FRAME_MASK_MASK   0x3 << CH0_FRAME_MASK_SHIFT

CH0_FRAME_MASK_SHIFT

#define CH0_FRAME_MASK_SHIFT   5

CH0_LANE_UPDATE_MASK

#define CH0_LANE_UPDATE_MASK   0x7FFF << CH0_LANE_UPDATE_SHIFT

CH0_LANE_UPDATE_SHIFT

#define CH0_LANE_UPDATE_SHIFT   7

CH0_MUX_MASK

#define CH0_MUX_MASK   0x3 << CH0_MUX_SHIFT

CH0_MUX_SHIFT

#define CH0_MUX_SHIFT   23

CH0_RTERM_EN_MASK

#define CH0_RTERM_EN_MASK   0x1 << CH0_RTERM_EN_SHIFT

CH0_RTERM_EN_SHIFT

#define CH0_RTERM_EN_SHIFT   1

CH0_RTERM_MASK

#define CH0_RTERM_MASK   0xF << CH0_RTERM_SHIFT

CH0_RTERM_SHIFT

#define CH0_RTERM_SHIFT   1

CH0_RXD_N_MASK

#define CH0_RXD_N_MASK   0x1 << CH0_RXD_N_SHIFT

CH0_RXD_N_SHIFT

#define CH0_RXD_N_SHIFT   26

CH0_RXD_P_MASK

#define CH0_RXD_P_MASK   0x1 << CH0_RXD_P_SHIFT

CH0_RXD_P_SHIFT

#define CH0_RXD_P_SHIFT   25

CH0_RXDA_MASK

#define CH0_RXDA_MASK   0x1 << CH0_RXDA_SHIFT

CH0_RXDA_SHIFT

#define CH0_RXDA_SHIFT   24

CH0_RXEN_MASK

#define CH0_RXEN_MASK   0x1 << CH0_RXEN_SHIFT

CH0_RXEN_SHIFT

#define CH0_RXEN_SHIFT   6

CH0_SOFT_RESET_MASK

#define CH0_SOFT_RESET_MASK   0x1 << CH0_SOFT_RESET_SHIFT

CH0_SOFT_RESET_SHIFT

#define CH0_SOFT_RESET_SHIFT   0

CH0_SUBLVDS_MASK

#define CH0_SUBLVDS_MASK   0x1 << CH0_SUBLVDS_SHIFT

CH0_SUBLVDS_SHIFT

#define CH0_SUBLVDS_SHIFT   2

CH0_TEST_IEN_N_MASK

#define CH0_TEST_IEN_N_MASK   0x1 << CH0_TEST_IEN_N_SHIFT

CH0_TEST_IEN_N_SHIFT

#define CH0_TEST_IEN_N_SHIFT   4

CH0_TEST_IEN_P_MASK

#define CH0_TEST_IEN_P_MASK   0x1 << CH0_TEST_IEN_P_SHIFT

CH0_TEST_IEN_P_SHIFT

#define CH0_TEST_IEN_P_SHIFT   5

CH0_TEST_OEN_N_MASK

#define CH0_TEST_OEN_N_MASK   0x1 << CH0_TEST_OEN_N_SHIFT

CH0_TEST_OEN_N_SHIFT

#define CH0_TEST_OEN_N_SHIFT   6

CH0_TEST_OEN_P_MASK

#define CH0_TEST_OEN_P_MASK   0x1 << CH0_TEST_OEN_P_SHIFT

CH0_TEST_OEN_P_SHIFT

#define CH0_TEST_OEN_P_SHIFT   7

CH0_TEST_PULLDN_MASK

#define CH0_TEST_PULLDN_MASK   0x1 << CH0_TEST_PULLDN_SHIFT

CH0_TEST_PULLDN_SHIFT

#define CH0_TEST_PULLDN_SHIFT   8

CH0_TEST_RXCM_EN_MASK

#define CH0_TEST_RXCM_EN_MASK   0x1 << CH0_TEST_RXCM_EN_SHIFT

CH0_TEST_RXCM_EN_SHIFT

#define CH0_TEST_RXCM_EN_SHIFT   9

CH0_TEST_RXEN_MASK

#define CH0_TEST_RXEN_MASK   0x1 << CH0_TEST_RXEN_SHIFT

CH0_TEST_RXEN_SHIFT

#define CH0_TEST_RXEN_SHIFT   10

CH0_TEST_SCHMITT_EN_MASK

#define CH0_TEST_SCHMITT_EN_MASK   0x1 << CH0_TEST_SCHMITT_EN_SHIFT

CH0_TEST_SCHMITT_EN_SHIFT

#define CH0_TEST_SCHMITT_EN_SHIFT   11

CH0_TEST_TXD_N_MASK

#define CH0_TEST_TXD_N_MASK   0x1 << CH0_TEST_TXD_N_SHIFT

CH0_TEST_TXD_N_SHIFT

#define CH0_TEST_TXD_N_SHIFT   12

CH0_TEST_TXD_P_MASK

#define CH0_TEST_TXD_P_MASK   0x1 << CH0_TEST_TXD_P_SHIFT

CH0_TEST_TXD_P_SHIFT

#define CH0_TEST_TXD_P_SHIFT   13

CH0_TRIM_SEL_MASK

#define CH0_TRIM_SEL_MASK   0x1 << CH0_TRIM_SEL_SHIFT

CH0_TRIM_SEL_SHIFT

#define CH0_TRIM_SEL_SHIFT   0

CH0_TXEN_MASK

#define CH0_TXEN_MASK   0x1 << CH0_TXEN_SHIFT

CH0_TXEN_SHIFT

#define CH0_TXEN_SHIFT   7

CH0_TXSWING_MASK

#define CH0_TXSWING_MASK   0x1 << CH0_TXSWING_SHIFT

CH0_TXSWING_SHIFT

#define CH0_TXSWING_SHIFT   3

CH0_TXVCOM_MASK

#define CH0_TXVCOM_MASK   0x1 << CH0_TXVCOM_SHIFT

CH0_TXVCOM_SHIFT

#define CH0_TXVCOM_SHIFT   8

CH0_VSYNC_POL_MASK

#define CH0_VSYNC_POL_MASK   0x1 << CH0_VSYNC_POL_SHIFT

CH0_VSYNC_POL_SHIFT

#define CH0_VSYNC_POL_SHIFT   4

CRC_SRC_MASK

#define CRC_SRC_MASK   0x1 << CRC_SRC_SHIFT

CRC_SRC_SHIFT

#define CRC_SRC_SHIFT   4

DC1_MUX_CTRL

#define DC1_MUX_CTRL   (0x2000)

DSP_CLK_MASK

#define DSP_CLK_MASK   0x1 << DSP_CLK_SHIFT

DSP_CLK_SHIFT

#define DSP_CLK_SHIFT   0

LVDS_BASE

#define LVDS_BASE   0xF34C0000

LVDS_CH0_CTRL

#define LVDS_CH0_CTRL   (0x1000)

LVDS_CH0_PAD_COM_SET

#define LVDS_CH0_PAD_COM_SET   (0x1100)

LVDS_CH0_PAD_SET_

#define LVDS_CH0_PAD_SET_

(

i

)

(0x1010 + 0x4 * i)

LVDS_CH0_RX_CTRL

#define LVDS_CH0_RX_CTRL   (0x1200)

LVDS_SOFT_RESET

#define LVDS_SOFT_RESET   (0x1008)

LVDS_TEST_CFG

#define LVDS_TEST_CFG   (0x100c)

LVDS_TEST_CLK_MASK

#define LVDS_TEST_CLK_MASK   0x7F << LVDS_TEST_CLK_SHIFT

LVDS_TEST_CLK_SHIFT

#define LVDS_TEST_CLK_SHIFT   8

LVDS_TEST_DATA_MASK

#define LVDS_TEST_DATA_MASK   0x7F << LVDS_TEST_DATA_MASK

LVDS_TEST_DATA_SHIFT

#define LVDS_TEST_DATA_SHIFT   0

LVDS_TEST_EN_MASK

#define LVDS_TEST_EN_MASK   0x1 << LVDS_TEST_EN_SHIFT

LVDS_TEST_EN_SHIFT

#define LVDS_TEST_EN_SHIFT   7

PARAL_FB_CLK_POL_MASK

#define PARAL_FB_CLK_POL_MASK   0x1 << PARAL_FB_CLK_POL_SHIFT

PARAL_FB_CLK_POL_SHIFT

#define PARAL_FB_CLK_POL_SHIFT   5

PARAL_OUT_BPP_MASK

#define PARAL_OUT_BPP_MASK   0x3 << PARAL_OUT_BPP_SHIFT

PARAL_OUT_BPP_SHIFT

#define PARAL_OUT_BPP_SHIFT   16

PARAL_OUT_CLK_POL_MASK

#define PARAL_OUT_CLK_POL_MASK   0x1 << PARAL_OUT_CLK_POL_SHIFT

PARAL_OUT_CLK_POL_SHIFT

#define PARAL_OUT_CLK_POL_SHIFT   6

PARAL_OUT_EN_MASK

#define PARAL_OUT_EN_MASK   0x1 << PARAL_OUT_EN_SHIFT

PARAL_OUT_EN_SHIFT

#define PARAL_OUT_EN_SHIFT   8

PARAL_TO_CSI_EN_MASK

#define PARAL_TO_CSI_EN_MASK   0x1 << PARAL_TO_CSI_EN_SHIFT

PARAL_TO_CSI_EN_SHIFT

#define PARAL_TO_CSI_EN_SHIFT   10

PARAL_TO_LVDS_EN_MASK

#define PARAL_TO_LVDS_EN_MASK   0x1 << PARAL_TO_LVDS_EN_SHIFT

PARAL_TO_LVDS_EN_SHIFT

#define PARAL_TO_LVDS_EN_SHIFT   9