SemiDrive SSDK Appication Program Interface PTG3.0
Data Fields
sdrv_dma_channel_config_t

#include <sdrv_dma.h>

Data Fields

sdrv_dma_tinstance
 
sdrv_dma_channel_id_e channel_id
 
sdrv_dma_xfer_mode_e xfer_mode
 
sdrv_dma_xfer_type_e xfer_type
 
paddr_t src_addr
 
sdrv_dma_bus_width_e src_width
 
sdrv_dma_addr_inc_e src_inc
 
uint32_t src_burst_len
 
paddr_t dst_addr
 
sdrv_dma_bus_width_e dst_width
 
sdrv_dma_addr_inc_e dst_inc
 
uint32_t dst_burst_len
 
uint32_t xfer_bytes
 
int mux_id
 
sdrv_dma_port_sel_e src_port_sel
 
sdrv_dma_port_sel_e dst_port_sel
 
uint32_t src_cache
 
uint32_t dst_cache
 
uint32_t interrupt_type
 
sdrv_dma_buffer_mode_e buffer_mode
 
sdrv_dma_loop_mode_e loop_mode
 
sdrv_dma_switch_event_ctrl_e switch_event_ctrl
 
sdrv_dma_trigger_mode_e trig_mode
 
paddr_t linklist_addr
 
sdrv_dma_linklist_type_e linklist_mad_type
 
sdrv_dma_mad_crc_mode_e mad_crc_mode
 
sdrv_dma_data_crc_mode_e data_crc_mode
 

Field Documentation

◆ buffer_mode

Handshake request mode

◆ channel_id

Transfer mode

◆ data_crc_mode

sdrv_dma_data_crc_mode_e data_crc_mode

Data CRC sel

◆ data_crc_sel

◆ dst_addr

paddr_t dst_addr

Target port bus width

◆ dst_burst_len

uint32_t dst_burst_len

Number of bytes to transfer.

◆ dst_cache

uint32_t dst_cache

DMA interrupt type

◆ dst_inc

Target port burst length

◆ dst_port_sel

sdrv_dma_port_sel_e dst_port_sel

DMA source cache enable

◆ dst_width

Increase target address after each transaction?

◆ instance

sdrv_dma_t* instance

< DMA controller ID of this channel

◆ interrupt_type

uint32_t interrupt_type

Buffer mode

◆ linklist_addr

paddr_t linklist_addr

Linklist MAD type

◆ linklist_mad_type

sdrv_dma_linklist_type_e linklist_mad_type

MAD CRC type

◆ loop_mode

Switch event control

◆ mad_crc_mode

Data CRC mode

◆ mux_id

int mux_id

DMA source port select

◆ src_addr

paddr_t src_addr

Source port bus width

◆ src_burst_len

uint32_t src_burst_len

Target buffer address

◆ src_cache

uint32_t src_cache

DMA target cache enable

◆ src_inc

Source port burst length

◆ src_port_sel

sdrv_dma_port_sel_e src_port_sel

DMA target port select

◆ src_width

Increase source address after each transaction?

◆ switch_event_ctrl

sdrv_dma_switch_event_ctrl_e switch_event_ctrl

Transfer trigger mode

◆ trig_mode

Link address - next MAD address

◆ xfer_bytes

uint32_t xfer_bytes

DMA Mux ID

◆ xfer_mode

Transfer type - source and target buffer types

◆ xfer_type

Source buffer address


The documentation for this struct was generated from the following file: