#include <sdrv_acmp.h>

Data Fields
sdrv_acmp_csel_t	csel_idx

uint8_t	amux_setup

uint8_t	prop_delay: 5

uint8_t	rbw: 4

uint8_t	fbw: 4

bool	sample_en

bool	mask_en

bool	pol_adj

bool	sync_en

sdrv_acmp_reg_sel_t	refsel

sdrv_acmp_sd_sel_t	sdsel

sdrv_acmp_hcfg_t	hcfg

uint8_t	dain

Field Documentation

◆ amux_setup

uint8_t amux_setup

Analog mux setup time, preparation time required for a comparison. The first period of (prop_delay + amux_setup) time in a comparison, the comparison result is not reliable.

◆ csel_idx

sdrv_acmp_csel_t csel_idx

Index of compare select controller

◆ dain

uint8_t dain

Reference voltage adjustment.

◆ fbw

uint8_t fbw

Falling edge filter, unit: cycle number of clock, set 0 means bypass filter

◆ hcfg

sdrv_acmp_hcfg_t hcfg

Set hysteresis window

◆ mask_en

bool mask_en

If sample_en is not enabled, mask_en refers to converting the above digital sampling clock into an enable signal, which will be output only when the sampling clock is high

◆ pol_adj

bool pol_adj

Analog output polar adjust

◆ prop_delay

uint8_t prop_delay

Propagation delay, in cycles of clock

◆ rbw

uint8_t rbw

Rising edge filter, unit: cycle number of clock, set 0 means bypass filter

◆ refsel

sdrv_acmp_reg_sel_t refsel

select reference voltage source

◆ sample_en

bool sample_en

The result of analog comparison is sampled by an additional digital clock and then output. sample_en is usually set to 0, when set to 1, mask and sync will not work.

◆ sdsel

sdrv_acmp_sd_sel_t sdsel

Single-ended or differential comparison mode

◆ sync_en

bool sync_en

Whether the output result is synchronized with the internal clock of acmp

The documentation for this struct was generated from the following file:

Z:/01-Code/06-SSDK-DEV-Firewall/ssdk/drivers/include/sdrv_acmp.h

Data Fields