SemiDrive SSDK Appication Program Interface PTG3.0
Data Structures | Typedefs | Functions
sdrv_rstgen.h File Reference
#include <types.h>
#include <sdrv_common.h>

Go to the source code of this file.

Data Structures

struct  sdrv_rstgen
 
struct  sdrv_rstgen_sig
 
struct  sdrv_rstgen_general_reg
 
struct  sdrv_rstgen_glb_ctl
 
struct  sdrv_recovery_btm
 
struct  sdrv_recovery_etimer
 
struct  sdrv_recovery_epwm
 
struct  sdrv_recovery_module
 

Typedefs

typedef void(* sdrv_rstgen_sig_handler) (uint32_t rstgen_sig_id)
 

Functions

status_t sdrv_rstgen_assert (sdrv_rstgen_sig_t *rst_sig)
 
status_t sdrv_rstgen_deassert (sdrv_rstgen_sig_t *rst_sig)
 
status_t sdrv_rstgen_reset (sdrv_rstgen_sig_t *rst_sig)
 
status_t sdrv_rstgen_global_reset (sdrv_rstgen_glb_t *rst_glb_ctl)
 
status_t sdrv_rstgen_status (sdrv_rstgen_sig_t *rst_sig)
 
uint32_t sdrv_rstgen_global_status (sdrv_rstgen_glb_t *rst_glb_ctl)
 
status_t sdrv_rstgen_global_status_clear (sdrv_rstgen_glb_t *rst_glb_ctl)
 
uint32_t sdrv_rstgen_current_global_status (sdrv_rstgen_glb_t *rst_glb_ctl)
 
uint32_t sdrv_rstgen_read_general (sdrv_rstgen_general_reg_t *rst_gen_reg)
 
status_t sdrv_rstgen_write_general (sdrv_rstgen_general_reg_t *rst_gen_reg, uint32_t val)
 
status_t sdrv_rstgen_write_general_bit (sdrv_rstgen_general_reg_t *rst_gen_reg, uint8_t start, uint8_t width, uint32_t val)
 
status_t sdrv_rstgen_lowpower_set (sdrv_rstgen_sig_t *rst_sig, enum reset_lowpower_mode mode, uint32_t val)
 
status_t sdrv_rstgen_wdt_reset_enable (reset_wdt_id_e wdt, bool enable)
 
status_t sdrv_rstgen_wdt_core_reset_enable (reset_wdt_id_e wdt, reset_core_id_e core, bool enable)
 
status_t sdrv_recovery_module (sdrv_recovery_module_t *recovery_module)
 

Detailed Description

Copyright
Copyright (c) 2022 Semidrive Semiconductor. All rights reserved.

Macro Definition Documentation

◆ SDRV_RSTGEN_CORE

#define SDRV_RSTGEN_CORE   1

◆ SDRV_RSTGEN_DEBUG

#define SDRV_RSTGEN_DEBUG   6

◆ SDRV_RSTGEN_GENERAL_REG_NUM

#define SDRV_RSTGEN_GENERAL_REG_NUM   8

◆ SDRV_RSTGEN_INDEX

#define SDRV_RSTGEN_INDEX (   id)    ((uint32_t)(((uint32_t)(id)) & BIT_MASK(SDRV_RSTGEN_TYPE_SHIFT)))

◆ SDRV_RSTGEN_IST

#define SDRV_RSTGEN_IST   5

◆ SDRV_RSTGEN_LATENT

#define SDRV_RSTGEN_LATENT   2

◆ SDRV_RSTGEN_MISSION

#define SDRV_RSTGEN_MISSION   3

◆ SDRV_RSTGEN_MODULE

#define SDRV_RSTGEN_MODULE   4

◆ SDRV_RSTGEN_SIG_ID

#define SDRV_RSTGEN_SIG_ID (   type,
  idx 
)     ((uint32_t)((((uint32_t)(type)) << ((uint32_t)SDRV_RSTGEN_TYPE_SHIFT)) | ((uint32_t)(idx))))

◆ SDRV_RSTGEN_TYPE

#define SDRV_RSTGEN_TYPE (   id)    ((uint32_t)(((uint32_t)(id)) >> ((uint32_t)SDRV_RSTGEN_TYPE_SHIFT)))

◆ SDRV_RSTGEN_TYPE_SHIFT

#define SDRV_RSTGEN_TYPE_SHIFT   24

Typedef Documentation

◆ reset_core_id_e

typedef enum reset_core_id reset_core_id_e

◆ reset_wdt_id_e

typedef enum reset_wdt_id reset_wdt_id_e

◆ sdrv_recovery_btm_t

typedef struct sdrv_recovery_btm sdrv_recovery_btm_t

semidrive recovery device.

◆ sdrv_recovery_epwm_t

typedef struct sdrv_recovery_epwm sdrv_recovery_epwm_t

◆ sdrv_recovery_etimer_t

typedef struct sdrv_recovery_etimer sdrv_recovery_etimer_t

◆ sdrv_recovery_module_t

typedef struct sdrv_recovery_module sdrv_recovery_module_t

◆ sdrv_rstgen_general_reg_t

typedef struct sdrv_rstgen_general_reg sdrv_rstgen_general_reg_t

SDRV rstgen general register.

◆ sdrv_rstgen_glb_t

typedef struct sdrv_rstgen_glb_ctl sdrv_rstgen_glb_t

SDRV rstgen global reset controller.

◆ sdrv_rstgen_sig_handler

typedef void(* sdrv_rstgen_sig_handler) (uint32_t rstgen_sig_id)

semidrive reset sig handler.

call pre handler before reset/assert signal, and call post handler after reset/deassert signal, if necessary.

◆ sdrv_rstgen_sig_t

typedef struct sdrv_rstgen_sig sdrv_rstgen_sig_t

SDRV rstgen signal.

◆ sdrv_rstgen_t

typedef struct sdrv_rstgen sdrv_rstgen_t

SDRV rstgen controller.

Enumeration Type Documentation

◆ reset_core_id

enum reset_core_id
Enumerator
RESET_CORE_SF 
RESET_CORE_SP0 
RESET_CORE_SP1 
RESET_CORE_SX0 
RESET_CORE_SX1 

◆ reset_lowpower_mode

enum reset_lowpower_mode
Enumerator
RESET_LP_HIB 
RESET_LP_SLEEP 

◆ reset_wdt_id

enum reset_wdt_id
Enumerator
RESET_WDT1 
RESET_WDT2 
RESET_WDT3 
RESET_WDT4 
RESET_WDT5 
RESET_WDT6 

◆ sdrv_reset_error

enum sdrv_reset_error

RESET status error code.

Enumerator
SDRV_RESET_STATUS_SIGNAL_ASSERT 
SDRV_RESET_STATUS_LOCK 
SDRV_RESET_STATUS_TIMEOUT 
SDRV_RESET_STATUS_WRONG_SIGNAL 

Function Documentation

◆ sdrv_recovery_module()

status_t sdrv_recovery_module ( sdrv_recovery_module_t *  recovery_module)

sdrv recovery latent module.

Some latent modules (btm/etimer/epwm etc.) will be not reset when core is reset, so these modules should be recovery when core restart.

Parameters
[in]recovery_modulerecovery latent module list
Returns
0 if success, or a negative error code.

◆ sdrv_rstgen_assert()

status_t sdrv_rstgen_assert ( sdrv_rstgen_sig_t *  rst_sig)

Assert a reset signal.

The reset singal will stay asserted until reset_deassert() is called.

Parameters
[in]rst_sigReset signal.
Returns
0 if OK, or a negative error code.

◆ sdrv_rstgen_current_global_status()

uint32_t sdrv_rstgen_current_global_status ( sdrv_rstgen_glb_t *  rst_glb_ctl)

Check current global reset status.

Global reset status only for the last time. If multiple reset source comes neatly the same time, only the first one will be recorded.

Parameters
[in]rst_glb_ctlGlobal reset controller.
Returns
SF and AP domain current global reset status. bit[31:25] for rstgen AP: bit[31] rstgen ap software global reset bit[30] reserved bit[29] efusec security violation bit[28] system panic(vdc function irq) bit[27] sem1/sem2 error bit[26] reserved bit[25] PT sensor interrupt bit[24:0] for rstgen SF: bit[24] wdt6 int reset request bit[23] wdt6 int reset request bit[22] wdt4 int reset request bit[21] wdt4 int reset request bit[20] wdt2 int reset request bit[19] reserved bit[18] wdt5 int reset request bit[17] wdt5 int reset request bit[16] wdt3 int reset request bit[15] wdt3 int reset request bit[14] wdt1 int reset request bit[13] reserved bit[12] ist done fail bit[11] rstgen sf software global reset bit[10] reserved bit[9] wdt2 int reset request (Only for E3104/E3106/E3205/E3206) bit[8] wdt1 int reset request (Only for E3104/E3106/E3205/E3206) bit[7] ist done fail (Only for E3104/E3106/E3205/E3206) bit[6] rstgen sf software global reset (Only for E3104/E3106/E3205/E3206) bit[5] rstgen ap cold reset request bit[4] efusec security violation bit[3] system panic(vdc function irq) bit[2] sem1/sem2 error bit[1] reserved bit[0] PT sensor interrupt Especially, bit[31:10] are invalid for E3104/E3106/E3205/E3206.

◆ sdrv_rstgen_deassert()

status_t sdrv_rstgen_deassert ( sdrv_rstgen_sig_t *  rst_sig)

Deassert a reset signal.

Release a reset signal.

Parameters
[in]rst_sigReset signal.
Returns
0 if OK, or a negative error code.

◆ sdrv_rstgen_global_reset()

status_t sdrv_rstgen_global_reset ( sdrv_rstgen_glb_t *  rst_glb_ctl)

Global reset.

Global reset SF/AP domain

Parameters
[in]rst_glb_ctlGlobal reset controller.
Returns
0 if OK, or a negative error code.

◆ sdrv_rstgen_global_status()

uint32_t sdrv_rstgen_global_status ( sdrv_rstgen_glb_t *  rst_glb_ctl)

Check global reset status.

Global reset status for all the time, including each global reset status before clear or power off. If multiple reset source comes neatly the same time, only the first one will be recorded.

Parameters
[in]rst_glb_ctlGlobal reset controller.
Returns
SF and AP domain global reset status. bit[31:25] for rstgen AP: bit[31] rstgen ap software global reset bit[30] reserved bit[29] efusec security violation bit[28] system panic(vdc function irq) bit[27] sem1/sem2 error bit[26] reserved bit[25] PT sensor interrupt bit[24:0] for rstgen SF: bit[24] wdt6 int reset request bit[23] wdt6 int reset request bit[22] wdt4 int reset request bit[21] wdt4 int reset request bit[20] wdt2 int reset request bit[19] reserved bit[18] wdt5 int reset request bit[17] wdt5 int reset request bit[16] wdt3 int reset request bit[15] wdt3 int reset request bit[14] wdt1 int reset request bit[13] reserved bit[12] ist done fail bit[11] rstgen sf software global reset bit[10] reserved bit[9] wdt2 int reset request (Only for E3104/E3106/E3205/E3206) bit[8] wdt1 int reset request (Only for E3104/E3106/E3205/E3206) bit[7] ist done fail (Only for E3104/E3106/E3205/E3206) bit[6] rstgen sf software global reset (Only for E3104/E3106/E3205/E3206) bit[5] rstgen ap cold reset request bit[4] efusec security violation bit[3] system panic(vdc function irq) bit[2] sem1/sem2 error bit[1] reserved bit[0] PT sensor interrupt Especially, bit[31:10] are invalid for E3104/E3106/E3205/E3206.

◆ sdrv_rstgen_global_status_clear()

status_t sdrv_rstgen_global_status_clear ( sdrv_rstgen_glb_t *  rst_glb_ctl)

clear global reset status.

Clear global reset status, otherwise the status will keep until power off.

Parameters
[in]rst_glb_ctlGlobal reset controller.

◆ sdrv_rstgen_lowpower_set()

status_t sdrv_rstgen_lowpower_set ( sdrv_rstgen_sig_t *  rst_sig,
enum reset_lowpower_mode  mode,
uint32_t  val 
)

Config reset signal assert/deassert in lowpower mode.

Parameters
[in]rst_sigReset signal.
[in]modelowpower mode
[in]val0:assert, 1:deassert
Returns
0 if OK, or a negative error code.

◆ sdrv_rstgen_read_general()

uint32_t sdrv_rstgen_read_general ( sdrv_rstgen_general_reg_t *  rst_gen_reg)

Read reset general reg.

The data saved in general regs will be not lost until SOC power down.

Parameters
[in]rst_gen_regreset general reg.
Returns
general reg value.

◆ sdrv_rstgen_reset()

status_t sdrv_rstgen_reset ( sdrv_rstgen_sig_t *  rst_sig)

Reset a reset signal.

Assert a reset signal, and then deassert it automatically.

Parameters
[in]rst_sigReset signal.
Returns
0 if OK, or a negative error code.

◆ sdrv_rstgen_status()

status_t sdrv_rstgen_status ( sdrv_rstgen_sig_t *  rst_sig)

Check reset signal status.

Parameters
[in]rst_sigReset signal.
Returns
0 if deasserted, or a negative error code.

◆ sdrv_rstgen_wdt_core_reset_enable()

status_t sdrv_rstgen_wdt_core_reset_enable ( reset_wdt_id_e  wdt,
reset_core_id_e  core,
bool  enable 
)

Config wdt cause single core reset enable.

Config watchdog timeout trigger core reset. Each core has two watchdog, WDT1 and WDT2 belongs to SF, WDT3 and WDT4 belongs to SP0/SP1, WDT5 and WDT6 belongs to SX0/SX1. SP1 and SX1 can be reset alone, if SP0 or SX0 be reset, SP1 or SX1 will reset followed.

Parameters
[in]wdtwdt id
[in]corecore id
[in]enabletrue/false
Returns
0 if success, or a negative error code.

◆ sdrv_rstgen_wdt_reset_enable()

status_t sdrv_rstgen_wdt_reset_enable ( reset_wdt_id_e  wdt,
bool  enable 
)

Config wdt cause global reset enable.

Parameters
[in]wdtwdt id
[in]enabletrue/false
Returns
0 if success, or a negative error code.

◆ sdrv_rstgen_write_general()

status_t sdrv_rstgen_write_general ( sdrv_rstgen_general_reg_t *  rst_gen_reg,
uint32_t  val 
)

Write reset general reg.

Parameters
[in]rst_gen_regreset general reg.
[in]valwrite value.
Returns
0 if success, or a negative error code.

◆ sdrv_rstgen_write_general_bit()

status_t sdrv_rstgen_write_general_bit ( sdrv_rstgen_general_reg_t *  rst_gen_reg,
uint8_t  start,
uint8_t  width,
uint32_t  val 
)

Write reset general reg bit.

Parameters
[in]rst_gen_regreset general reg.
[in]startwrite start bit.
[in]widthwrite bit width.
[in]valwrite value.
Returns
0 if success, or a negative error code.
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