SemiDrive SSDK Appication Program Interface PTG3.0
Data Structures | Functions
sdrv_power.h File Reference
#include <sdrv_common.h>
#include <types.h>
#include <regs_base.h>
#include <part.h>
#include "sdrv_smc.h"
#include "sdrv_pmu.h"

Go to the source code of this file.

Data Structures

struct  sdrv_power_analog
 
struct  sdrv_sleep_mode_config
 
struct  sdrv_hibernate_mode_config
 

Functions

status_t sdrv_power_init (sdrv_sleep_mode_config_t *sleep_cfg, sdrv_hibernate_mode_config_t *hib_cfg)
 
status_t sdrv_power_set_mode (sdrv_power_mode_e mode)
 
status_t sdrv_power_clock_set_mode (sdrv_clock_mode_e mode)
 
status_t sdrv_power_iram_reinit (sdrv_iram_e iram)
 
status_t sdrv_power_rom_disable (void)
 
status_t sdrv_power_usb_power_down (void)
 
status_t sdrv_power_dcdc_config (paddr_t dcdc_base, sdrv_power_dcdc_mode_e mode, sdrv_power_dcdc_reg_e dcdc_reg, uint8_t cfg_val)
 

Detailed Description

Copyright
Copyright (c) 2022 Semidrive Semiconductor. All rights reserved.

Macro Definition Documentation

◆ SDRV_AP_DISP_PD_MASK

#define SDRV_AP_DISP_PD_MASK   (0x10UL)

◆ SDRV_AP_MODULE_CSI_MASK

#define SDRV_AP_MODULE_CSI_MASK   (0x1UL)

◆ SDRV_AP_MODULE_DC_MASK

#define SDRV_AP_MODULE_DC_MASK   (0x2UL)

◆ SDRV_AP_MODULE_DMA_MASK

#define SDRV_AP_MODULE_DMA_MASK   (0x40UL)

◆ SDRV_AP_MODULE_G2D_MASK

#define SDRV_AP_MODULE_G2D_MASK   (0x4UL)

◆ SDRV_AP_MODULE_LVDS_MASK

#define SDRV_AP_MODULE_LVDS_MASK   (0x800UL)

◆ SDRV_AP_MODULE_SACI1_MASK

#define SDRV_AP_MODULE_SACI1_MASK   (0x10UL)

◆ SDRV_AP_MODULE_SACI2_MASK

#define SDRV_AP_MODULE_SACI2_MASK   (0x20UL)

◆ SDRV_AP_MODULE_SDRAMC_MASK

#define SDRV_AP_MODULE_SDRAMC_MASK   (0x8UL)

◆ SDRV_AP_MODULE_SEHC1_MASK

#define SDRV_AP_MODULE_SEHC1_MASK   (0x80UL)

◆ SDRV_AP_MODULE_SEHC2_MASK

#define SDRV_AP_MODULE_SEHC2_MASK   (0x100UL)

◆ SDRV_AP_MODULE_SEIP_MASK

#define SDRV_AP_MODULE_SEIP_MASK   (0x400UL)

◆ SDRV_AP_MODULE_USB_MASK

#define SDRV_AP_MODULE_USB_MASK   (0x200UL)

◆ SDRV_GAMA1_PD_MASK

#define SDRV_GAMA1_PD_MASK   (0x8UL)

◆ SDRV_IRAM1_PD_MASK

#define SDRV_IRAM1_PD_MASK   (0x1UL)

◆ SDRV_IRAM2_PD_MASK

#define SDRV_IRAM2_PD_MASK   (0x2UL)

◆ SDRV_IRAM3_PD_MASK

#define SDRV_IRAM3_PD_MASK   (0x4UL)

◆ SDRV_IRAM4_PD_MASK

#define SDRV_IRAM4_PD_MASK   (0x8UL)

◆ SDRV_PLL1_PD_MASK

#define SDRV_PLL1_PD_MASK   (0x1UL)

◆ SDRV_PLL2_PD_MASK

#define SDRV_PLL2_PD_MASK   (0x2UL)

◆ SDRV_PLL3_PD_MASK

#define SDRV_PLL3_PD_MASK   (0x4UL)

◆ SDRV_PLL4_PD_MASK

#define SDRV_PLL4_PD_MASK   (0x8UL)

◆ SDRV_PLL5_PD_MASK

#define SDRV_PLL5_PD_MASK   (0x10UL)

◆ SDRV_PLL_LVDS_PD_MASK

#define SDRV_PLL_LVDS_PD_MASK   (0x20UL)

◆ SDRV_PWR_CTRL0_PD_MASK

#define SDRV_PWR_CTRL0_PD_MASK   (0x1UL)

◆ SDRV_PWR_CTRL1_PD_MASK

#define SDRV_PWR_CTRL1_PD_MASK   (0x2UL)

◆ SDRV_PWR_CTRL2_PD_MASK

#define SDRV_PWR_CTRL2_PD_MASK   (0x4UL)

◆ SDRV_PWR_CTRL3_PD_MASK

#define SDRV_PWR_CTRL3_PD_MASK   (0x8UL)

◆ SDRV_PWR_ON0_PD_MASK

#define SDRV_PWR_ON0_PD_MASK   (0x10UL)

◆ SDRV_PWR_ON1_PD_MASK

#define SDRV_PWR_ON1_PD_MASK   (0x20UL)

◆ SDRV_PWR_ON2_PD_MASK

#define SDRV_PWR_ON2_PD_MASK   (0x40UL)

◆ SDRV_PWR_ON3_PD_MASK

#define SDRV_PWR_ON3_PD_MASK   (0x80UL)

◆ SDRV_SF_MODULE_CANFD17_24_MASK

#define SDRV_SF_MODULE_CANFD17_24_MASK   (0x20UL)

◆ SDRV_SF_MODULE_CANFD1_MASK

#define SDRV_SF_MODULE_CANFD1_MASK   (0x1UL)

◆ SDRV_SF_MODULE_CANFD2_MASK

#define SDRV_SF_MODULE_CANFD2_MASK   (0x2UL)

◆ SDRV_SF_MODULE_CANFD3_4_MASK

#define SDRV_SF_MODULE_CANFD3_4_MASK   (0x4UL)

◆ SDRV_SF_MODULE_CANFD5_8_MASK

#define SDRV_SF_MODULE_CANFD5_8_MASK   (0x8UL)

◆ SDRV_SF_MODULE_CANFD9_16_MASK

#define SDRV_SF_MODULE_CANFD9_16_MASK   (0x10UL)

◆ SDRV_SF_MODULE_DMA_MASK

#define SDRV_SF_MODULE_DMA_MASK   (0x400UL)

◆ SDRV_SF_MODULE_ENET1_MASK

#define SDRV_SF_MODULE_ENET1_MASK   (0x2000UL)

◆ SDRV_SF_MODULE_ENET2_MASK

#define SDRV_SF_MODULE_ENET2_MASK   (0x4000UL)

◆ SDRV_SF_MODULE_GAMA1_MASK

#define SDRV_SF_MODULE_GAMA1_MASK   (0x800UL)

◆ SDRV_SF_MODULE_GAMA2_MASK

#define SDRV_SF_MODULE_GAMA2_MASK   (0x1000UL)

◆ SDRV_SF_MODULE_MB_MASK

#define SDRV_SF_MODULE_MB_MASK   (0x200000UL)

◆ SDRV_SF_MODULE_VIC1_MASK

#define SDRV_SF_MODULE_VIC1_MASK   (0x8000UL)

◆ SDRV_SF_MODULE_VIC2A_MASK

#define SDRV_SF_MODULE_VIC2A_MASK   (0x10000UL)

◆ SDRV_SF_MODULE_VIC2B_MASK

#define SDRV_SF_MODULE_VIC2B_MASK   (0x20000UL)

◆ SDRV_SF_MODULE_VIC3A_MASK

#define SDRV_SF_MODULE_VIC3A_MASK   (0x40000UL)

◆ SDRV_SF_MODULE_VIC3B_MASK

#define SDRV_SF_MODULE_VIC3B_MASK   (0x80000UL)

◆ SDRV_SF_MODULE_XSPI1A_MASK

#define SDRV_SF_MODULE_XSPI1A_MASK   (0x40UL)

◆ SDRV_SF_MODULE_XSPI1B_MASK

#define SDRV_SF_MODULE_XSPI1B_MASK   (0x80UL)

◆ SDRV_SF_MODULE_XSPI2A_MASK

#define SDRV_SF_MODULE_XSPI2A_MASK   (0x100UL)

◆ SDRV_SF_MODULE_XSPI2B_MASK

#define SDRV_SF_MODULE_XSPI2B_MASK   (0x200UL)

◆ SDRV_SF_MODULE_XSPI_SLV_MASK

#define SDRV_SF_MODULE_XSPI_SLV_MASK   (0x100000UL)

◆ SDRV_SF_MODULE_XTRG_MASK

#define SDRV_SF_MODULE_XTRG_MASK   (0x400000UL)

◆ SDRV_SF_PD_MASK

#define SDRV_SF_PD_MASK   (0x1UL)

◆ SDRV_SP_PD_MASK

#define SDRV_SP_PD_MASK   (0x2UL)

◆ SDRV_SX_PD_MASK

#define SDRV_SX_PD_MASK   (0x4UL)

Typedef Documentation

◆ mcu_power_e

typedef enum mcu_power mcu_power_e

Definition for MCU power switch and IRAMC power.

◆ sdrv_clock_mode_e

typedef enum sdrv_clock_mode sdrv_clock_mode_e

Definition for core clock mode.

◆ sdrv_hibernate_mode_config_t

typedef struct sdrv_hibernate_mode_config sdrv_hibernate_mode_config_t

Definition for hibernate mode config.

◆ sdrv_iram_e

typedef enum sdrv_iram sdrv_iram_e

Definition for iram.

◆ sdrv_power_analog_t

typedef struct sdrv_power_analog sdrv_power_analog_t

Definition for soc internal analog part power control.

◆ sdrv_power_dcdc_mode_e

typedef enum sdrv_power_dcdc_mode sdrv_power_dcdc_mode_e

Definition for DCDC work mode.

◆ sdrv_power_dcdc_reg_e

typedef enum sdrv_power_dcdc_reg sdrv_power_dcdc_reg_e

DCDC reg config, each reg has 8bit. REG0,7,8 are common config. REG1~6 are separate config for HP_MODE and LP_MODE.

◆ sdrv_power_mode_e

typedef enum sdrv_power_mode sdrv_power_mode_e

Definition for system work mode.

◆ sdrv_sleep_mode_config_t

typedef struct sdrv_sleep_mode_config sdrv_sleep_mode_config_t

Definition for sleep mode config.

◆ sdrv_wakeup_src_e

typedef enum sdrv_wakeup_src sdrv_wakeup_src_e

Definition for wakeup source.

Enumeration Type Documentation

◆ mcu_power

enum mcu_power

Definition for MCU power switch and IRAMC power.

Enumerator
MCU_POWER_SF 
MCU_POWER_SP 
MCU_POWER_SX 
MCU_POWER_GAMA 
MCU_POWER_IRAM1 
MCU_POWER_IRAM2 
MCU_POWER_IRAM3 
MCU_POWER_IRAM4 
MCU_POWER_ACMP1 
MCU_POWER_ACMP2 
MCU_POWER_ACMP3 
MCU_POWER_ACMP4 
MCU_POWER_END 

◆ sdrv_clock_mode

enum sdrv_clock_mode

Definition for core clock mode.

Enumerator
SDRV_CLOCK_NORMAL 
SDRV_CLOCK_MEDIUM 
SDRV_CLOCK_LOW 

◆ sdrv_iram

enum sdrv_iram

Definition for iram.

Enumerator
SDRV_IRAM1 
SDRV_IRAM2 
SDRV_IRAM3 
SDRV_IRAM4 

◆ sdrv_power_dcdc_mode

enum sdrv_power_dcdc_mode

Definition for DCDC work mode.

Enumerator
DCDC_HP_MODE 

High performance mode

DCDC_LP_MODE 

Low performance mode

◆ sdrv_power_dcdc_reg

enum sdrv_power_dcdc_reg

DCDC reg config, each reg has 8bit. REG0,7,8 are common config. REG1~6 are separate config for HP_MODE and LP_MODE.

Enumerator
DCDC_REG_0 
DCDC_REG_1 
DCDC_REG_2 
DCDC_REG_3 
DCDC_REG_4 
DCDC_REG_5 
DCDC_REG_6 
DCDC_REG_7 
DCDC_REG_8 

◆ sdrv_power_error

enum sdrv_power_error

Power status error code.

Enumerator
SDRV_POWER_CONFIG_PARAMETER_WRONG 
SDRV_POWER_MODE_SET_WRONG 
SDRV_POWER_WAKEUP_STATUS_ERROR 
SDRV_POWER_IRAM_REINIT_TIMEOUT 
SDRV_POWER_CLOCK_SET_FAILED 
SDRV_POWER_AP_STATUS_ERROR 
SDRV_POWER_PMU_STATUS_ERROR 
SDRV_POWER_SMC_STATUS_ERROR 

◆ sdrv_power_mode

enum sdrv_power_mode

Definition for system work mode.

Enumerator
SDRV_RUN_MODE 
SDRV_SLEEP_MODE 
SDRV_HIBERNATE_MODE 
SDRV_RTC_MODE 

◆ sdrv_wakeup_src

enum sdrv_wakeup_src

Definition for wakeup source.

Enumerator
SDRV_WAKEUP_GPIO_SF 
SDRV_WAKEUP_GPIO_AP 
SDRV_WAKEUP_RTC1 
SDRV_WAKEUP_RTC2 
SDRV_WAKEUP_UART1 
SDRV_WAKEUP_UART2 
SDRV_WAKEUP_UART3 
SDRV_WAKEUP_UART4 
SDRV_WAKEUP_UART5 
SDRV_WAKEUP_UART6 
SDRV_WAKEUP_UART7 
SDRV_WAKEUP_UART8 
SDRV_WAKEUP_END 

Function Documentation

◆ sdrv_power_clock_set_mode()

status_t sdrv_power_clock_set_mode ( sdrv_clock_mode_e  mode)

Set clock mode for core and bus.

This function config clock mode for core and bus. Normal mode use default clock settings, medium mode reduce core and bus frequency to half, low mode set core and bus frequency to 24MHz.

Parameters
[in]modeclock mode defined in sdrv_clock_mode_e.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_power_dcdc_config()

status_t sdrv_power_dcdc_config ( paddr_t  dcdc_base,
sdrv_power_dcdc_mode_e  mode,
sdrv_power_dcdc_reg_e  dcdc_reg,
uint8_t  cfg_val 
)

Config DCDC REG0~8.

Parameters
[in]dcdc_baseDCDC controller base.
[in]modehigh or low performance mode.
[in]dcdc_regDCDC_REG_0 - DCDC_REG_8.
[in]cfg_valconfig value.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_power_init()

status_t sdrv_power_init ( sdrv_sleep_mode_config_t *  sleep_cfg,
sdrv_hibernate_mode_config_t *  hib_cfg 
)

Initialize clock/reset/power config under sleep and hibernate mode.

This function will mask all interrupts and gate all xcg clock expect for wakeup modules. It will reset all modules expect that need wakeup and user defined not reset in low power mode. According to user configration, config smc sleep/hibernate mode core power switch and pmu pwr ctrl/pwr on status.

Parameters
[in]sleep_cfgconfig for sleep mode
[in]hib_cfgconfig for hibernate mode
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_power_iram_reinit()

status_t sdrv_power_iram_reinit ( sdrv_iram_e  iram)

Reinit specific iram.

This function reinit specific iram. If iram is power down in hibernate, after wakeup, you need call this function before use it.

Parameters
[in]iramiram defined in sdrv_iram_e.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_power_rom_disable()

status_t sdrv_power_rom_disable ( void  )

Set rom disable.

When set rom disable, ROM code read and register access are disable until POR reset.

Returns
SDRV_STATUS_OK or error code.

◆ sdrv_power_set_mode()

status_t sdrv_power_set_mode ( sdrv_power_mode_e  mode)

Set soc to specific power mode.

This function config SMC enable wfi detect and excute wfi instrcut. After all core enter wfi, it will start hardware operation. Before enter sleep, software config all iram to retention mode. Before enter hibernate, software power down iram as pre-defined, and power down analog part. Then use SVC interrupt to save all core registers. After wakeup from sleep/hibernate, it will return from this call. Iram and analog will be powered again. If call to enter RTC mode, it will power down at once.

Parameters
[in]modemode defined in sdrv_power_mode_e.
Returns
SDRV_STATUS_OK or error code.

◆ sdrv_power_usb_power_down()

status_t sdrv_power_usb_power_down ( void  )

USB phy power down.

Returns
SDRV_STATUS_OK or error code.
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