234 lines
11 KiB
C
234 lines
11 KiB
C
/*
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*********************************************************************************************************
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* uC/USB-Host
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* The Embedded USB Host Stack
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*
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* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
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*
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* SPDX-License-Identifier: APACHE-2.0
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*
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* This software is subject to an open source license and is distributed by
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* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
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* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
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*
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* NOTICE
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*
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* Semidrive modified this file to adapt it for ssdk platform.
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* The modifications are only intended for use with Semidrive chips.
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* Copyright of all the modifications belongs to Semidrive Semiconductor.
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*
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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*
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* STANDARD OHCI DRIVER
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*
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* Filename : usbh_ohci.h
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* Version : V3.42.01
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*********************************************************************************************************
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*/
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#ifndef USBH_OHCI_MODULE_PRESENT
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#define USBH_OHCI_MODULE_PRESENT
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/*
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*********************************************************************************************************
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* INCLUDE FILES
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*********************************************************************************************************
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*/
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#include "../../Source/usbh_core.h"
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/*
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*********************************************************************************************************
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* EXTERNS
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*********************************************************************************************************
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*/
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#ifdef USBH_OHCI_MODULE
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#define USBH_OHCI_EXT
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#else
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#define USBH_OHCI_EXT extern
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#endif
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/*
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*********************************************************************************************************
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* DEFINES
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*********************************************************************************************************
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*/
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/* ----------- OHCI ED LIST NUMBER DEFINES ------------ */
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#define OHCI_ED_LIST_32MS 0u
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#define OHCI_ED_LIST_16MS 32u
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#define OHCI_ED_LIST_08MS 48u
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#define OHCI_ED_LIST_04MS 56u
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#define OHCI_ED_LIST_02MS 60u
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#define OHCI_ED_LIST_01MS 62u
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#define OHCI_ED_LIST_CTRL 63u
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#define OHCI_ED_LIST_BULK 64u
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#define OHCI_ED_LIST_SIZE (OHCI_ED_LIST_BULK + 1u)
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#define OHCI_MAX_PERIODIC_BW 90u
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/*
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*********************************************************************************************************
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* DATA TYPES
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*********************************************************************************************************
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*/
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typedef struct ohci_hcd_td OHCI_HCD_TD;
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typedef struct ohci_hcd_ed OHCI_HCD_ED;
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typedef struct ohci_oper_reg {
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CPU_REG32 Revision;
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CPU_REG32 Control;
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CPU_REG32 CommandStatus;
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CPU_REG32 InterruptStatus;
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CPU_REG32 InterruptEnable;
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CPU_REG32 InterruptDisable;
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CPU_REG32 HCCA;
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CPU_REG32 PeriodCurrentED;
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CPU_REG32 ControlHeadED;
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CPU_REG32 ControlCurrentED;
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CPU_REG32 BulkHeadED;
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CPU_REG32 BulkCurrentED;
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CPU_REG32 DoneHead;
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CPU_REG32 FmInterval;
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CPU_REG32 FmRemaining;
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CPU_REG32 FmNumber;
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CPU_REG32 PeriodicStart;
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CPU_REG32 LSThreshold;
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CPU_REG32 RhDescriptorA;
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CPU_REG32 RhDescriptorB;
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CPU_REG32 RhStatus;
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CPU_REG32 RhPortStatus[1];
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} OHCI_OPER_REG;
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/* --- HOST CONTROLLER COMMUNICATION AREA DATA TYPE --- */
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typedef struct ohci_hcca {
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CPU_REG32 IntTbl[32]; /* Interrupt Table */
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CPU_REG32 FrameNbr; /* Frame Number */
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CPU_REG32 DoneHead; /* Done Head */
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CPU_REG08 Rsvd[116]; /* Reserved for future use */
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CPU_REG08 Unknown[4]; /* Unused */
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} OHCI_HCCA;
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/* --- HOST CONTROLLER ENDPOINT DESCRIPTOR DATA TYPE -- */
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typedef struct ohci_hc_ed {
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CPU_REG32 Ctrl; /* Endpoint descriptor control */
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CPU_REG32 TailTD; /* Physical address of tail in Transfer descriptor list */
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CPU_REG32 HeadTD; /* Physcial address of head in Transfer descriptor list */
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CPU_REG32 Next; /* Physical address of next Endpoint descriptor */
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#if CONFIG_ARCH_CACHE_LINE > 16
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CPU_REG08 Rsvd[CONFIG_ARCH_CACHE_LINE - 16];
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#endif
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} OHCI_HC_ED;
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/* --- HOST CONTROLLER TRANSFER DESCRIPTOR DATA TYPE -- */
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typedef struct ohci_hc_td {
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CPU_REG32 Ctrl; /* Transfer descriptor control */
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CPU_REG32 CurBuf; /* Physical address of current buffer pointer */
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CPU_REG32 Next; /* Physical pointer to next Transfer Descriptor */
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CPU_REG32 BufEnd; /* Physical address of end of buffer */
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CPU_REG32 Offsets[4]; /* Isochronous offsets */
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} OHCI_HC_TD;
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/* --- HOST CONTROLLER ENDPOINT TRANSFER DESCRIPTOR --- */
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struct ohci_hcd_ed {
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OHCI_HC_ED *HC_EDPtr;
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CPU_INT32U DMA_HC_ED;
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OHCI_HCD_TD *Head_HCD_TDPtr;
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OHCI_HCD_TD *Tail_HCD_TDPtr;
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OHCI_HCD_ED *NextPtr;
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CPU_INT32U ListInterval;
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CPU_INT32U BW;
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CPU_BOOLEAN IsHalt;
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};
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/* HOST CONTROLLER DRIVER TRANSFER DESCRIPTOR DATA TYPE */
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struct ohci_hcd_td {
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OHCI_HC_TD *HC_TdPtr;
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CPU_INT32U DMA_HC_TD;
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OHCI_HCD_TD *NextPtr;
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USBH_URB *URBPtr; /* URB associated with this TD */
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CPU_REG08 State;
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};
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/* -------------- OHCI DMA Structure ------------------ */
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typedef struct ohci_dma {
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OHCI_HCCA *HCCAPtr; /* DMA memory HCCA descriptor */
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OHCI_HC_TD *TDPtr; /* DMA memory CTRL,BULK and INTR endpoint TD */
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OHCI_HC_ED *EDPtr; /* DMA memory for Endpoint Descriptors (ED) */
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CPU_INT08U *BufPtr;
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} OHCI_DMA;
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/* -------------- OHCI DEVICE DATA TYPE --------------- */
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typedef struct ohci_dev {
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OHCI_DMA DMA_OHCI;
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CPU_INT08U OHCI_HubBuf[sizeof(USBH_HUB_DESC)];
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OHCI_HCD_ED *EDLists[OHCI_ED_LIST_SIZE]; /* OHCI EndPoint Descriptor Lists */
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CPU_INT08U CanWakeUp; /* Port Power */
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CPU_INT08U NbrPorts; /* Number of Ports in RootHub */
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CPU_INT32U TotBW; /* Periodic list parameters */
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CPU_INT32U Branch[32]; /* Bandwidth of branches */
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MEM_POOL HC_EDPool; /* Memory pool for allocating DMA ednpoint descriptor */
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MEM_POOL HC_TDPool; /* Memory pool for allocating DMA general TDs */
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OHCI_HCD_ED *HCD_ED;
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MEM_POOL HCD_EDPool; /* Memory pool for allocating OHCI driver EDs */
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OHCI_HCD_TD *HCD_TD;
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MEM_POOL HCD_TDPool; /* Memory pool for allocating OHCI driver TDs */
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MEM_POOL BufPool;
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CPU_INT32U FrameNbr;
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OHCI_HCD_TD **OHCI_Lookup;
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} OHCI_DEV;
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/*
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*********************************************************************************************************
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* GLOBAL VARIABLES
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*********************************************************************************************************
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*/
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USBH_OHCI_EXT USBH_HC_DRV_API OHCI_DrvAPI;
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USBH_OHCI_EXT USBH_HC_RH_API OHCI_RH_API;
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/*
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*********************************************************************************************************
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* MACROS
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* FUNCTION PROTOTYPES
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* CONFIGURATION ERRORS
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* MODULE END
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*********************************************************************************************************
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*/
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#endif
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