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<p><code>#include &lt;<a class="el" href="sdrv__xspi__mst_8h_source.html">sdrv_xspi_mst.h</a>&gt;</code></p>
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Data Fields</h2></td></tr>
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<tr class="memitem:ab9b84c9a7ba5c7cb4f57a31e2c748057"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__xspi__mst__conf.html#ab9b84c9a7ba5c7cb4f57a31e2c748057">crc_en</a></td></tr>
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<tr class="memitem:a4681dd5203f60f9499ff7c071644087b"><td class="memItemLeft" align="right" valign="top">enum <a class="el" href="sdrv__xspi__mst_8h.html#a736874a33bccb6f0e85d1ee93b9a53a3">sdrv_xspi_mst_line</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__xspi__mst__conf.html#a4681dd5203f60f9499ff7c071644087b">line</a></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#abc81edd3d3caf9e6c2e0762881da6016">&#9670;&nbsp;</a></span>base</h2>
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<td class="memname">paddr_t base</td>
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<p >xspi master register base address </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ab9b84c9a7ba5c7cb4f57a31e2c748057">&#9670;&nbsp;</a></span>crc_en</h2>
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<td class="memname">bool crc_en</td>
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<p >xspi master crc enable </p>
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<td class="memname">uint8_t cs</td>
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<p >chip select </p>
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<p >xspi master dummy cycle </p>
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<a id="a788268e18842744cc0a7e06cc734582a" name="a788268e18842744cc0a7e06cc734582a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a788268e18842744cc0a7e06cc734582a">&#9670;&nbsp;</a></span>irq</h2>
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<td class="memname">uint16_t irq</td>
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<p >xspi master irq number </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a2ee30f449f3b0b88995d3ad356482b67">&#9670;&nbsp;</a></span>is_ddr</h2>
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<td class="memname">bool is_ddr</td>
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<p >xspi master use ddr or sdr mode </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a673c291a9195d1de6147e5e9a97ca633">&#9670;&nbsp;</a></span>is_training</h2>
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<td class="memname">bool is_training</td>
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<p >xspi master support training </p>
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<td class="memname">enum <a class="el" href="sdrv__xspi__mst_8h.html#a736874a33bccb6f0e85d1ee93b9a53a3">sdrv_xspi_mst_line</a> line</td>
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<p >xspi master use line num </p>
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<td class="memname">struct <a class="el" href="structsdrv__xspi__mst__addr__offset__conf.html">sdrv_xspi_mst_addr_offset_conf</a> offset</td>
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<a id="a25d6a55f649bf56e58a4190e8f4aa2f4" name="a25d6a55f649bf56e58a4190e8f4aa2f4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a25d6a55f649bf56e58a4190e8f4aa2f4">&#9670;&nbsp;</a></span>port_base</h2>
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<td class="memname">paddr_t port_base</td>
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<p >xspi master port base address </p>
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<a id="a1a39ea95d88211cf33af14c7536bf6eb" name="a1a39ea95d88211cf33af14c7536bf6eb"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1a39ea95d88211cf33af14c7536bf6eb">&#9670;&nbsp;</a></span>slv_err_resp_en</h2>
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<td class="memname">bool slv_err_resp_en</td>
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<p >xspi master slv_err_resp enable </p>
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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>Z:/01-Code/06-SSDK-DEV-Firewall/ssdk/drivers/include/<a class="el" href="sdrv__xspi__mst_8h_source.html">sdrv_xspi_mst.h</a></li>
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