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308 lines
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<div id="projectname">SemiDrive SSDK Appication Program Interface<span id="projectnumber"> PTG3.0</span>
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="headertitle"><div class="title">sdrv_acmp_csel_cfg</div></div>
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</div><!--header-->
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<div class="contents">
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<p><code>#include <<a class="el" href="sdrv__acmp_8h_source.html">sdrv_acmp.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:aac094339f8dad0c75990fe5aadbf753f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__acmp_8h.html#a5c4ae5a55b0a046fd998253d5614654e">sdrv_acmp_csel_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#aac094339f8dad0c75990fe5aadbf753f">csel_idx</a></td></tr>
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<tr class="separator:aac094339f8dad0c75990fe5aadbf753f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa4ec558cf22909a55c48a1257c5b9ee4"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#aa4ec558cf22909a55c48a1257c5b9ee4">amux_setup</a></td></tr>
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<tr class="separator:aa4ec558cf22909a55c48a1257c5b9ee4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a96383c24db8b602c7ba531110659be38"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#a96383c24db8b602c7ba531110659be38">prop_delay</a>: 5</td></tr>
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<tr class="separator:a96383c24db8b602c7ba531110659be38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3867895448541d7f938f9bf980997c0b"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#a3867895448541d7f938f9bf980997c0b">rbw</a>: 4</td></tr>
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<tr class="separator:a3867895448541d7f938f9bf980997c0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abce63bf55d16995ba7b70a5195f7d4f7"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#abce63bf55d16995ba7b70a5195f7d4f7">fbw</a>: 4</td></tr>
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<tr class="separator:abce63bf55d16995ba7b70a5195f7d4f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af014d58b62a3545722b133dd8ba5f2cc"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#af014d58b62a3545722b133dd8ba5f2cc">sample_en</a></td></tr>
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<tr class="memitem:a46b3de1e0215e6c8be1ee00fa0542ec8"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#a46b3de1e0215e6c8be1ee00fa0542ec8">mask_en</a></td></tr>
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<tr class="separator:a46b3de1e0215e6c8be1ee00fa0542ec8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a59af53b05d46290bf98e0879d90141af"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#a59af53b05d46290bf98e0879d90141af">pol_adj</a></td></tr>
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<tr class="memitem:af7b30d27a0df50749efac8574c02e756"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#af7b30d27a0df50749efac8574c02e756">sync_en</a></td></tr>
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<tr class="memitem:a66454ec644931ee2c20dd5e2165d9ab0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__acmp_8h.html#a3e82bfcac5d09236f33361f6421bc683">sdrv_acmp_reg_sel_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#a66454ec644931ee2c20dd5e2165d9ab0">refsel</a></td></tr>
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<tr class="separator:a66454ec644931ee2c20dd5e2165d9ab0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8964b7feb68a13d3028976dd45b6b478"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__acmp_8h.html#a330361150d4062cb5549cfb83c1595fd">sdrv_acmp_sd_sel_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#a8964b7feb68a13d3028976dd45b6b478">sdsel</a></td></tr>
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<tr class="memitem:a44acbd025d68ab2f3e9d1164f61db22c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__acmp_8h.html#ad7613cedb9602cfea2e3464addc0ce5e">sdrv_acmp_hcfg_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#a44acbd025d68ab2f3e9d1164f61db22c">hcfg</a></td></tr>
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<tr class="separator:a44acbd025d68ab2f3e9d1164f61db22c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeb664765c7c0a0696462e495e29615f5"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__acmp__csel__cfg.html#aeb664765c7c0a0696462e495e29615f5">dain</a></td></tr>
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</table>
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<h2 class="groupheader">Field Documentation</h2>
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<a id="aa4ec558cf22909a55c48a1257c5b9ee4" name="aa4ec558cf22909a55c48a1257c5b9ee4"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aa4ec558cf22909a55c48a1257c5b9ee4">◆ </a></span>amux_setup</h2>
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<td class="memname">uint8_t amux_setup</td>
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<p >Analog mux setup time, preparation time required for a comparison. The first period of (prop_delay + amux_setup) time in a comparison, the comparison result is not reliable. </p>
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<a id="aac094339f8dad0c75990fe5aadbf753f" name="aac094339f8dad0c75990fe5aadbf753f"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aac094339f8dad0c75990fe5aadbf753f">◆ </a></span>csel_idx</h2>
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<td class="memname"><a class="el" href="sdrv__acmp_8h.html#a5c4ae5a55b0a046fd998253d5614654e">sdrv_acmp_csel_t</a> csel_idx</td>
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</div><div class="memdoc">
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<p >Index of compare select controller </p>
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<a id="aeb664765c7c0a0696462e495e29615f5" name="aeb664765c7c0a0696462e495e29615f5"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aeb664765c7c0a0696462e495e29615f5">◆ </a></span>dain</h2>
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<td class="memname">uint8_t dain</td>
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</table>
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</div><div class="memdoc">
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<p >Reference voltage adjustment. </p>
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</div>
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<a id="abce63bf55d16995ba7b70a5195f7d4f7" name="abce63bf55d16995ba7b70a5195f7d4f7"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#abce63bf55d16995ba7b70a5195f7d4f7">◆ </a></span>fbw</h2>
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<td class="memname">uint8_t fbw</td>
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<p >Falling edge filter, unit: cycle number of clock, set 0 means bypass filter </p>
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<a id="a44acbd025d68ab2f3e9d1164f61db22c" name="a44acbd025d68ab2f3e9d1164f61db22c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a44acbd025d68ab2f3e9d1164f61db22c">◆ </a></span>hcfg</h2>
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<td class="memname"><a class="el" href="sdrv__acmp_8h.html#ad7613cedb9602cfea2e3464addc0ce5e">sdrv_acmp_hcfg_t</a> hcfg</td>
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</div><div class="memdoc">
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<p >Set hysteresis window </p>
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<a id="a46b3de1e0215e6c8be1ee00fa0542ec8" name="a46b3de1e0215e6c8be1ee00fa0542ec8"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a46b3de1e0215e6c8be1ee00fa0542ec8">◆ </a></span>mask_en</h2>
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<td class="memname">bool mask_en</td>
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<p >If sample_en is not enabled, mask_en refers to converting the above digital sampling clock into an enable signal, which will be output only when the sampling clock is high </p>
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<a id="a59af53b05d46290bf98e0879d90141af" name="a59af53b05d46290bf98e0879d90141af"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a59af53b05d46290bf98e0879d90141af">◆ </a></span>pol_adj</h2>
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<td class="memname">bool pol_adj</td>
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</div><div class="memdoc">
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<p >Analog output polar adjust </p>
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</div>
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<a id="a96383c24db8b602c7ba531110659be38" name="a96383c24db8b602c7ba531110659be38"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a96383c24db8b602c7ba531110659be38">◆ </a></span>prop_delay</h2>
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<td class="memname">uint8_t prop_delay</td>
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</div><div class="memdoc">
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<p >Propagation delay, in cycles of clock </p>
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</div>
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<a id="a3867895448541d7f938f9bf980997c0b" name="a3867895448541d7f938f9bf980997c0b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a3867895448541d7f938f9bf980997c0b">◆ </a></span>rbw</h2>
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<td class="memname">uint8_t rbw</td>
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<p >Rising edge filter, unit: cycle number of clock, set 0 means bypass filter </p>
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<a id="a66454ec644931ee2c20dd5e2165d9ab0" name="a66454ec644931ee2c20dd5e2165d9ab0"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a66454ec644931ee2c20dd5e2165d9ab0">◆ </a></span>refsel</h2>
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<td class="memname"><a class="el" href="sdrv__acmp_8h.html#a3e82bfcac5d09236f33361f6421bc683">sdrv_acmp_reg_sel_t</a> refsel</td>
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<p >select reference voltage source </p>
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</div>
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<a id="af014d58b62a3545722b133dd8ba5f2cc" name="af014d58b62a3545722b133dd8ba5f2cc"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#af014d58b62a3545722b133dd8ba5f2cc">◆ </a></span>sample_en</h2>
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<td class="memname">bool sample_en</td>
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<p >The result of analog comparison is sampled by an additional digital clock and then output. sample_en is usually set to 0, when set to 1, mask and sync will not work. </p>
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<a id="a8964b7feb68a13d3028976dd45b6b478" name="a8964b7feb68a13d3028976dd45b6b478"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a8964b7feb68a13d3028976dd45b6b478">◆ </a></span>sdsel</h2>
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<td class="memname"><a class="el" href="sdrv__acmp_8h.html#a330361150d4062cb5549cfb83c1595fd">sdrv_acmp_sd_sel_t</a> sdsel</td>
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<p >Single-ended or differential comparison mode </p>
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<a id="af7b30d27a0df50749efac8574c02e756" name="af7b30d27a0df50749efac8574c02e756"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#af7b30d27a0df50749efac8574c02e756">◆ </a></span>sync_en</h2>
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<td class="memname">bool sync_en</td>
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<p >Whether the output result is synchronized with the internal clock of acmp </p>
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<hr/>The documentation for this struct was generated from the following file:<ul>
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<li>Z:/01-Code/06-SSDK-DEV-Firewall/ssdk/drivers/include/<a class="el" href="sdrv__acmp_8h_source.html">sdrv_acmp.h</a></li>
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