350 lines
14 KiB
C
350 lines
14 KiB
C
/**
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* @file sdrv_rstgen_hw.h
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* @brief semidrive rstgen driver hardware header.
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*
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* @copyright Copyright (c) 2021 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef SDRV_RSTGEN_HW_H
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#define SDRV_RSTGEN_HW_H
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#include <types.h>
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#include <compiler.h>
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/* Define the register offsets of rstgen component */
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#define DOM_PER0_OFF(n) (0x0U + 12U*(n))
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#define DOM_PER0_DOM3_USE_PER (30U)
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#define DOM_PER0_DOM3_PRI_PER (28U)
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#define DOM_PER0_DOM3_NSE_PER (26U)
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#define DOM_PER0_DOM3_SEC_PER (24U)
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#define DOM_PER0_DOM2_USE_PER (22U)
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#define DOM_PER0_DOM2_PRI_PER (20U)
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#define DOM_PER0_DOM2_NSE_PER (18U)
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#define DOM_PER0_DOM2_SEC_PER (16U)
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#define DOM_PER0_DOM1_USE_PER (14U)
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#define DOM_PER0_DOM1_PRI_PER (12U)
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#define DOM_PER0_DOM1_NSE_PER (10U)
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#define DOM_PER0_DOM1_SEC_PER (8U)
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#define DOM_PER0_DOM0_USE_PER (6U)
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#define DOM_PER0_DOM0_PRI_PER (4U)
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#define DOM_PER0_DOM0_NSE_PER (2U)
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#define DOM_PER0_DOM0_SEC_PER (0U)
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#define DOM_PER1_OFF(n) (0x4U + 12U*(n))
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#define DOM_PER1_DOM7_USE_PER (30U)
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#define DOM_PER1_DOM7_PRI_PER (28U)
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#define DOM_PER1_DOM7_NSE_PER (26U)
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#define DOM_PER1_DOM7_SEC_PER (24U)
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#define DOM_PER1_DOM6_USE_PER (22U)
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#define DOM_PER1_DOM6_PRI_PER (20U)
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#define DOM_PER1_DOM6_NSE_PER (18U)
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#define DOM_PER1_DOM6_SEC_PER (16U)
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#define DOM_PER1_DOM5_USE_PER (14U)
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#define DOM_PER1_DOM5_PRI_PER (12U)
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#define DOM_PER1_DOM5_NSE_PER (10U)
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#define DOM_PER1_DOM5_SEC_PER (8U)
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#define DOM_PER1_DOM4_USE_PER (6U)
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#define DOM_PER1_DOM4_PRI_PER (4U)
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#define DOM_PER1_DOM4_NSE_PER (2U)
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#define DOM_PER1_DOM4_SEC_PER (0U)
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#define DOM_PER_LOCK_OFF(n) (0x8U + 12U*(n))
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#define DOM_PER_LOCK_DOM7_LOCK (7U)
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#define DOM_PER_LOCK_DOM6_LOCK (6U)
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#define DOM_PER_LOCK_DOM5_LOCK (5U)
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#define DOM_PER_LOCK_DOM4_LOCK (4U)
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#define DOM_PER_LOCK_DOM3_LOCK (3U)
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#define DOM_PER_LOCK_DOM2_LOCK (2U)
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#define DOM_PER_LOCK_DOM1_LOCK (1U)
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#define DOM_PER_LOCK_DOM0_LOCK (0U)
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/* Global reset */
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#define GLOBAL_RESET_RS_OFF 0x200U
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#define GLOBAL_RESET_RS_LOCK (31U)
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#define FM_GLOBAL_RESET_RS_RS (1U)
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#define GLOBAL_RESET_RS_EN (0U)
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#define GLOBAL_RESET_CONTROL_OFF 0x204U
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#define GLOBAL_RESET_CONTROL_SS_RDY (31U)
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#define GLOBAL_RESET_CONTROL_TEST_IST_EN (29U)
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#define GLOBAL_RESET_CONTROL_SW_GLB_RST (28U)
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#define GLOBAL_RESET_CONTROL_SW_GLB_RST_EN (27U)
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#define GLOBAL_RESET_CONTROL_RST_REQ_EN (19U)
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#define GLOBAL_RESET_CONTROL_WDT2_EN (11U)
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#define GLOBAL_RESET_CONTROL_WDT1_EN (3U)
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#define GLOBAL_RESET_CONTROL_SEC_VIO_EN (2U)
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#define GLOBAL_RESET_CONTROL_SEM_EN (1U)
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#define GLOBAL_RESET_CONTROL_SYS_PANIC_EN (0U)
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#define GLOBAL_RESET_STA_OFF 0x208U
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#define GLOBAL_RESET_STA_GLB_STA_LAST (0U)
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#define GLOBAL_RESET_STA_ALL_OFF 0x20cU
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#define GLOBAL_RESET_STA_ALL_GLB_STA_ALL (0U)
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#define GLOBAL_ERR_STA_ALL_OFF 0x210U
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#define GLOBAL_ERR_STA_ALL_ERR_STA_ALL (0U)
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/* IST reset */
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#define IST_RESET_RS_OFF 0x1000U
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#define IST_RESET_RS_LOCK (31U)
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#define FM_IST_RESET_RS_RS (1U)
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#define IST_RESET_RS_EN (0U)
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#define IST_RESET_CONTROL_OFF 0x1004U
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#define IST_RESET_CONTROL_RMON_O (31U)
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#define IST_RESET_CONTROL_RMON_I (30U)
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#define IST_RESET_CONTROL_RSTA (29U)
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#define IST_RESET_CONTROL_AUTO_CLR_RST_B (6U)
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#define IST_RESET_CONTROL_SLP_MODE (2U)
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#define IST_RESET_CONTROL_HIB_MODE (1U)
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#define IST_RESET_CONTROL_RUN_MODE (0U)
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/* Mission reset */
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#define MISSION_RESET_RS_OFF(n) (0x1100U + 8U*(n))
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#define MISSION_RESET_RS_LOCK (31U)
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#define FM_MISSION_RESET_RS_RS (1U)
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#define MISSION_RESET_RS_EN (0U)
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#define MISSION_RESET_CONTROL_OFF(n) (0x1104U + 8U*(n))
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#define MISSION_RESET_CONTROL_RMON_O (31U)
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#define MISSION_RESET_CONTROL_RMON_I (30U)
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#define MISSION_RESET_CONTROL_RSTA (29U)
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#define MISSION_RESET_CONTROL_AUTO_CLR_RST_B (6U)
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#define MISSION_RESET_CONTROL_SLP_MODE (2U)
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#define MISSION_RESET_CONTROL_HIB_MODE (1U)
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#define MISSION_RESET_CONTROL_RUN_MODE (0U)
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/* Latent reset */
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#define LATENT_RESET_RS_OFF(n) (0x1200U + 8U*(n))
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#define LATENT_RESET_RS_LOCK (31U)
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#define LATENT_RESET_RS_RS (1U)
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#define LATENT_RESET_RS_EN (0U)
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#define LATENT_RESET_CONTROL_OFF(n) (0x1204U + 8U*(n))
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#define LATENT_RESET_CONTROL_RMON_O (31U)
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#define LATENT_RESET_CONTROL_RMON_I (30U)
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#define LATENT_RESET_CONTROL_RSTA (29U)
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#define LATENT_RESET_CONTROL_LOCK (28U)
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#define LATENT_RESET_CONTROL_AUTO_CLR_RST_B (6U)
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#define LATENT_RESET_CONTROL_SLP_MODE (2U)
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#define LATENT_RESET_CONTROL_HIB_MODE (1U)
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#define LATENT_RESET_CONTROL_RUN_MODE (0U)
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/* Module reset */
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#define MODULE_RESET_RS_OFF(n) (0x1300U + 8U*(n))
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#define MODULE_RESET_RS_LOCK (31U)
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#define FM_MODULE_RESET_RS_RS (1U)
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#define MODULE_RESET_RS_EN (0U)
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#define MODULE_RESET_CONTROL_OFF(n) (0x1304U + 8U*(n))
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#define MODULE_RESET_CONTROL_RMON_O (31U)
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#define MODULE_RESET_CONTROL_RMON_I (30U)
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#define MODULE_RESET_CONTROL_RSTA (29U)
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#define MODULE_RESET_CONTROL_BTI_TOUT_VAL (8U)
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#define MODULE_RESET_CONTROL_AUTO_CLR_RST_B (6U)
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#define MODULE_RESET_CONTROL_SLP_MODE (2U)
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#define MODULE_RESET_CONTROL_HIB_MODE (1U)
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#define MODULE_RESET_CONTROL_RUN_MODE (0U)
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/* Core reset */
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#define CORE_RESET_RS_OFF(n) (0x1a00U + 8U*(n))
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#define CORE_RESET_RS_LOCK (31U)
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#define FM_CORE_RESET_RS_RS (1U)
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#define CORE_RESET_RS_EN (0U)
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#define CORE_RESET_CONTROL_OFF(n) (0x1a04U + 8U*(n))
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#define CORE_RESET_CONTROL_RMON_O (31U)
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#define CORE_RESET_CONTROL_RMON_I (30U)
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#define CORE_RESET_CONTROL_RSTA (29U)
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#define CORE_RESET_CONTROL_BTI_TOUT_VAL (8U)
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#define CORE_RESET_CONTROL_AUTO_CLR_RST_B (6U)
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#define CORE_RESET_CONTROL_RST_REQ_EN (5U)
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#define CORE_RESET_CONTROL_WDT2_RST_EN (4U)
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#define CORE_RESET_CONTROL_WDT1_RST_EN (3U)
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#define CORE_RESET_CONTROL_SLP_MODE (2U)
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#define CORE_RESET_CONTROL_HIB_MODE (1U)
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#define CORE_RESET_CONTROL_RUN_MODE (0U)
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/* DBG reset */
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#define DBG_RESET_RS_OFF 0x1b00U
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#define DBG_RESET_RS_LOCK (31U)
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#define DBG_RESET_RS_RS (1U)
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#define DBG_RESET_RS_EN (0U)
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#define DBG_RESET_CONTROL_OFF 0x1b04U
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#define DBG_RESET_CONTROL_RMON_O (31U)
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#define DBG_RESET_CONTROL_RMON_I (30U)
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#define DBG_RESET_CONTROL_RSTA (29U)
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#define DBG_RESET_CONTROL_DBG_REQ_EN (8U)
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#define DBG_RESET_CONTROL_AUTO_CLR_RST_B (6U)
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#define DBG_RESET_CONTROL_SLP_MODE (2U)
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#define DBG_RESET_CONTROL_HIB_MODE (1U)
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#define DBG_RESET_CONTROL_RUN_MODE (0U)
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/* SW reset */
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#define SW_RESET_PASSWORD_CONTROL_OFF 0x1c00U
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#define SW_RESET_PASSWORD_CONTROL_LOCK (31U)
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#define SW_RESET_PASSWORD_CONTROL_EN (0U)
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#define SW_RESET_PASSWORD_OFF 0x1c04U
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#define SW_RESET_PASSWORD_PW (0U)
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#define GENERAL_REG_RS_OFF(n) (0x2000U + 8U*(n))
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#define GENERAL_REG_RS_LOCK (31U)
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#define FM_GENERAL_REG_RS_RS (1U)
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#define GENERAL_REG_RS_EN (0U)
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#define GENERAL_REG_OFF(n) (0x2004U + 8U*(n))
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#define GENERAL_REG_GENERAL (0U)
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#define BOOT_MODE_RS_OFF 0x3000U
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#define BOOT_MODE_RS_LOCK (31U)
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#define FM_BOOT_MODE_RS_RS (1U)
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#define BOOT_MODE_RS_EN (0U)
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#define BOOT_MODE_OFF 0x3004U
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#define RESET_FLOW_TIME_RS_OFF 0x3100U
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#define RESET_FLOW_TIME_RS_LOCK (31U)
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#define RESET_FLOW_TIME_RS_RS (1U)
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#define RESET_FLOW_TIME_RS_EN (0U)
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#define RESET_FLOW_TIME_CONTROL_OFF 0x3104U
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#define RESET_FLOW_TIME_CONTROL_T4 (20U)
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#define RESET_FLOW_TIME_CONTROL_T3 (16U)
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#define RESET_FLOW_TIME_CONTROL_T2 (8U)
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#define RESET_FLOW_TIME_CONTROL_T1 (4U)
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#define RESET_FLOW_TIME_CONTROL_T0 (0U)
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#define RSTGEN_RES_RS_OFF 0x3200U
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#define RSTGEN_RES_RS_LOCK (31U)
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#define RSTGEN_RES_RS_RS (1U)
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#define RSTGEN_RES_RS_EN (0U)
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#define RSTGEN_RES_OFF 0x3204U
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#define RSTGEN_MISC_RS_OFF 0x3300U
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#define RSTGEN_MISC_RS_LOCK (31U)
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#define RSTGEN_MISC_RS_RS (1U)
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#define RSTGEN_MISC_RS_EN (0U)
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#define RSTGEN_MISC_OFF 0x3304U
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#define FM_RSTGEN_MISC_MISC (0U)
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#define RSTGEN_SUP_DOM_OFF 0x3400U
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#define RSTGEN_SUP_DOM_LOCK (31U)
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#define RSTGEN_SUP_DOM_PPROT (5U)
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#define RSTGEN_SUP_DOM_SEC_EN (4U)
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#define RSTGEN_SUP_DOM_DID (0U)
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#define RSTGEN_TOUT_RS_OFF 0x3500U
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#define RSTGEN_TOUT_RS_LOCK (31U)
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#define RSTGEN_TOUT_RS_RS (1U)
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#define RSTGEN_TOUT_RS_EN (0U)
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#define RSTGEN_IST_TOUT_OFF 0x3504U
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#define RSTGEN_IST_TOUT_TOUT_VAL (0U)
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#define RSTGEN_BTI_TOUT_OFF 0x3508U
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#define RSTGEN_BTI_TOUT_TOUT_VAL (0U)
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#define RSTGEN_FUSA_RS_OFF 0x4000U
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#define RSTGEN_FUSA_RS_LOCK (31U)
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#define RSTGEN_FUSA_RS_RS (1U)
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#define RSTGEN_FUSA_RS_EN (0U)
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#define APB_ERR_INT_OFF 0x4004U
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#define APB_ERR_INT_PADDR_INT_CLR (23U)
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#define APB_ERR_INT_PUSER_INT_CLR (22U)
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#define APB_ERR_INT_PCTRL1_INT_CLR (21U)
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#define APB_ERR_INT_PCTRL0_INT_CLR (20U)
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#define APB_ERR_INT_PWDAT_C_INT_CLR (19U)
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#define APB_ERR_INT_PWDAT_U_INT_CLR (18U)
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#define APB_ERR_INT_PWDAT_F_INT_CLR (17U)
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#define APB_ERR_INT_PADDR_INT_STA (15U)
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#define APB_ERR_INT_PUSER_INT_STA (14U)
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#define APB_ERR_INT_PCTRL1_INT_STA (13U)
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#define APB_ERR_INT_PCTRL0_INT_STA (12U)
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#define APB_ERR_INT_PWDAT_C_INT_STA (11U)
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#define APB_ERR_INT_PWDAT_U_INT_STA (10U)
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#define APB_ERR_INT_PWDAT_F_INT_STA (9U)
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#define APB_ERR_INT_PADDR_INT_EN (7U)
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#define APB_ERR_INT_PUSER_INT_EN (6U)
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#define APB_ERR_INT_PCTRL1_INT_EN (5U)
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#define APB_ERR_INT_PCTRL0_INT_EN (4U)
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#define APB_ERR_INT_PWDAT_C_INT_EN (3U)
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#define APB_ERR_INT_PWDAT_U_INT_EN (2U)
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#define APB_ERR_INT_PWDAT_F_INT_EN (1U)
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#define APB_LKSTEP_INT_OFF 0x4008U
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#define APB_LKSTEP_INT_SYNC_ERR_INT_CLR (19U)
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#define APB_LKSTEP_INT_RESP_ERR_INT_CLR (18U)
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#define APB_LKSTEP_INT_REQ_ERR_INT_CLR (17U)
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#define APB_LKSTEP_INT_CMP_ERR_INT_CLR (16U)
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#define APB_LKSTEP_INT_SYNC_ERR_INT_STA (11U)
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#define APB_LKSTEP_INT_RESP_ERR_INT_STA (10U)
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#define APB_LKSTEP_INT_REQ_ERR_INT_STA (9U)
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#define APB_LKSTEP_INT_CMP_ERR_INT_STA (8U)
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#define APB_LKSTEP_INT_SYNC_ERR_INT_EN (3U)
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#define APB_LKSTEP_INT_RESP_ERR_INT_EN (2U)
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#define APB_LKSTEP_INT_REQ_ERR_INT_EN (1U)
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#define APB_LKSTEP_INT_CMP_ERR_INT_EN (0U)
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#define RSTGEN_FUSA_INT_OFF 0x400cU
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#define RSTGEN_FUSA_INT_BTI_TOUT_ERR_CLR (21U)
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#define RSTGEN_FUSA_INT_LKSTEP_CMP_ERR_CLR (20U)
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#define RSTGEN_FUSA_INT_SYNC_ERR_CLR (19U)
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#define RSTGEN_FUSA_INT_BOOT_MODE_CHK_ERR_CLR (18U)
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#define RSTGEN_FUSA_INT_SWM_TRANS_ERR_CLR (17U)
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#define RSTGEN_FUSA_INT_SWM_CHK_ERR_CLR (16U)
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#define RSTGEN_FUSA_INT_BTI_TOUT_ERR_STA (13U)
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#define RSTGEN_FUSA_INT_LKSTEP_CMP_ERR_STA (12U)
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#define RSTGEN_FUSA_INT_SYNC_ERR_STA (11U)
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#define RSTGEN_FUSA_INT_BOOT_MODE_CHK_ERR_STA (10U)
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#define RSTGEN_FUSA_INT_SWM_TRANS_ERR_STA (9U)
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#define RSTGEN_FUSA_INT_SWM_CHK_ERR_STA (8U)
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#define RSTGEN_FUSA_INT_BTI_TOUT_ERR_EN (5U)
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#define RSTGEN_FUSA_INT_LKSTEP_CMP_ERR_EN (4U)
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#define RSTGEN_FUSA_INT_SYNC_ERR_EN (3U)
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#define RSTGEN_FUSA_INT_BOOT_MODE_CHK_ERR_EN (2U)
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#define RSTGEN_FUSA_INT_SWM_TRANS_ERR_EN (1U)
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#define RSTGEN_FUSA_INT_SWM_CHK_ERR_EN (0U)
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#define WDT_LKSTEP_INT_OFF 0x4010U
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#define WDT_LKSTEP_INT_IST_TOUT_ERR_INT_CLR (18U)
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#define WDT_LKSTEP_INT_SYNC_ERR_INT_CLR (17U)
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#define WDT_LKSTEP_INT_CMP_ERR_INT_CLR (16U)
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#define WDT_LKSTEP_INT_IST_TOUT_ERR_INT_STA (10U)
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#define WDT_LKSTEP_INT_SYNC_ERR_INT_STA (9U)
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#define WDT_LKSTEP_INT_CMP_ERR_INT_STA (8U)
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#define WDT_LKSTEP_INT_IST_TOUT_ERR_INT_EN (2U)
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#define WDT_LKSTEP_INT_SYNC_ERR_INT_EN (1U)
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#define WDT_LKSTEP_INT_CMP_ERR_INT_EN (0U)
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#define RSTGEN_INJ_EN_OFF 0x4100U
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#define RSTGEN_INJ_EN_INJ_EN (0U)
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#define RSTGEN_INJ_BIT_OFF 0x4104U
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#define RSTGEN_INJ_BIT_IRQ_INJ (29U)
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#define RSTGEN_INJ_BIT_ERR_INJ_BIT (0U)
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#define RSTGEN_INJ_BIT_1_OFF 0x4108U
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#define RSTGEN_INJ_BIT_1_ERR_INJ_BIT (0U)
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#define RSTGEN_INJ_BIT_2_OFF 0x410cU
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#define RSTGEN_INJ_BIT_2_ERR_INJ_BIT (0U)
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#define RSTGEN_FUNC_INT_RS_OFF 0x4200U
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#define RSTGEN_FUNC_INT_RS_LOCK (31U)
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#define RSTGEN_FUNC_INT_RS_RS (1U)
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#define RSTGEN_FUNC_INT_RS_EN (0U)
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#define RSTGEN_FUNC_INT_OFF 0x4204U
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#define RSTGEN_FUNC_INT_ACCESS_PER_ERR_CLR (16U)
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#define RSTGEN_FUNC_INT_ACCESS_PER_ERR_STA (8U)
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#define RSTGEN_FUNC_INT_ACCESS_PER_ERR_EN (0U)
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#endif /* SDRV_RSTGEN_HW_H */ |