708 lines
26 KiB
C
708 lines
26 KiB
C
/**
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* @file sdrv_ckgen.h
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* @brief SemiDrive clock generator driver header file.
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*
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* @copyright Copyright (c) 2020 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef SDRV_CLK_H_
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#define SDRV_CLK_H_
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#include <sdrv_common.h>
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#include <lib/list.h>
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#include <types.h>
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#include <part.h>
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#include <sdrv_rtc.h>
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#define CLK_NODE(node) (sdrv_ckgen_node_t *)&(node.clk_node)
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#define CLK_MHZ(x) ((x) * 1000 * 1000)
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#define CONFIG_CKGEN_PARENTS_NUM 5
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/**
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* @brief CKGEN status error code.
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*/
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enum sdrv_ckgen_error {
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SDRV_CKGEN_POINTER_IS_NULL = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 1),
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SDRV_CKGEN_XTAL24M_NOT_READY = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 2),
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SDRV_CKGEN_FS24M_WAIT_ACTIVE_TIMEOUT = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 3),
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SDRV_CKGEN_XTAL32K_NOT_READY = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 4),
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SDRV_CKGEN_FS32K_WAIT_ACTIVE_TIMEOUT = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 5),
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SDRV_CKGEN_PLL_NOT_LOCK = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 6),
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SDRV_CKGEN_PLL_RATE_WRONG = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 7),
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SDRV_CKGEN_PLL_LVDS_DIV2_CHG_BUSY = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 8),
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SDRV_CKGEN_PLL_LVDS_DIV7_CHG_BUSY = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 9),
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SDRV_CKGEN_PLL_LVDS_CKGEN_CHG_BUSY = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 10),
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SDRV_CKGEN_PLL_NOT_DSM_MODE = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 11),
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SDRV_CKGEN_SLICE_TYPE_ERROR = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 12),
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SDRV_CKGEN_SLICE_NO_SUITABLE_PARENT = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 13),
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SDRV_CKGEN_SLICE_MAIN_STATUS_ERROR = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 14),
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SDRV_CKGEN_SLICE_PRE_STATUS_ERROR = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 15),
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SDRV_CKGEN_SLICE_D0_ACTIVE_ERROR = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 16),
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SDRV_CKGEN_SLICE_POST_D0_ACTIVE_ERROR = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 17),
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SDRV_CKGEN_SLICE_DIV_CHG_BUSY = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 18),
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SDRV_CKGEN_BEYOND_MAX_DIVIDER = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 19),
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SDRV_CKGEN_FREQUENCY_INCORRECT = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 20),
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SDRV_CKGEN_CONSTRUCT_CLKTREE_FAILED = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 21),
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SDRV_CKGEN_PARENT_NODE_NULL = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 22),
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SDRV_CKGEN_BEYOND_MAX_AXI_RATE = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 23),
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SDRV_CKGEN_CLOCK_SET_TIMEOUT = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_CLK, 24),
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};
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/**
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* @brief Function Safe clock source.
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*/
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typedef enum sdrv_fs_src_type {
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FS_SRC_RC = 0, /**< RC oscillator */
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FS_SRC_XTAL = 1 /**< XTAL oscillator */
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} sdrv_fs_src_type_e;
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/**
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* @brief Clock node type.
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*/
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typedef enum sdrv_ckgen_type {
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CKGEN_IP_SLICE_TYPE = 0, /**< ip slice type */
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CKGEN_SF_BUS_SLICE_TYPE = 1, /**< sf/sp bus slice type */
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CKGEN_BUS_SLICE_TYPE = 2, /**< except sf/sp bus slice type */
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CKGEN_CORE_SLICE_TYPE = 3, /**< core slice type */
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CKGEN_PCG_TYPE = 4, /**< PCG type */
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CKGEN_BCG_TYPE = 5, /**< BCG type */
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CKGEN_CCG_TYPE = 6, /**< CCG type */
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CKGEN_PLL_CG_TYPE = 7, /**< PLL CG type */
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CKGEN_XTAL_CG_TYPE = 8, /**< XTAL CG type */
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CKGEN_PLL_CTRL_TYPE = 9, /**< PLL CTRL type */
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CKGEN_PLL_LVDS_TYPE = 10, /**< PLL LVDS type */
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CKGEN_RC24M_TYPE = 11, /**< RC24M type */
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CKGEN_FS24M_TYPE = 12, /**< FS24M type */
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CKGEN_RC32K_TYPE = 13, /**< RC32K type */
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CKGEN_FS32K_TYPE = 14 /**< FS32K type */
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} sdrv_ckgen_type_e;
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/**
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* @brief Low power mode for clock config.
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*/
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typedef enum sdrv_ckgen_lp_mode {
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CKGEN_RUN_MODE = 0, /**< CKGEN RUN MODE */
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CKGEN_HIB_MODE = 1, /**< CKGEN HIBERNATE MODE */
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CKGEN_SLP_MODE = 2 /**< CKGEN SLEEP MODE */
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} sdrv_ckgen_lp_mode_e;
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/**
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* @brief Config bus slice node output type.
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* For SF/SP BUS, clk_out_m for core, clk_out_n for AXI, clk_out_p for APB
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* For AP domain bus, clk_out_m not used, clk_out_n for AXI, clk_out_p for APB
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*/
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typedef enum sdrv_ckgen_bus_out_type {
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CKGEN_BUS_CLK_OUT = 0, /**< use clk_in4, no divide as output clock */
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CKGEN_BUS_CLK_OUT_M = 1, /**< output clock divided by div_m_num */
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CKGEN_BUS_CLK_OUT_N = 2, /**< output clock divided by div_n_num */
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CKGEN_BUS_CLK_OUT_P = 3, /**< output clock divided by div_p_num */
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CKGEN_BUS_CLK_OUT_Q = 4 /**< output clock divided by div_q_num */
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} sdrv_ckgen_bus_out_type_e;
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/**
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* @brief Bus slice post divide ratio.
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*/
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typedef enum sdrv_ckgen_bus_post_div {
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CKGEN_BUS_DIV_4_2_1 = 0, /**< divm/divn/divp = 4/2/1 */
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CKGEN_BUS_DIV_2_2_1 = 1 /**< divm/divn/divp = 2/2/1 */
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} sdrv_ckgen_bus_post_div_e;
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/**
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* @brief PLL Spread amplitude.
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*
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*/
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typedef enum sdrv_ckgen_ssc_amplitude {
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CKGEN_SSC_0P0_PERCENT = 0, /**< SSC_DEP 0.0% */
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CKGEN_SSC_0P1_PERCENT, /**< SSC_DEP 0.1% */
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CKGEN_SSC_0P2_PERCENT, /**< SSC_DEP 0.2% */
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CKGEN_SSC_0P3_PERCENT, /**< SSC_DEP 0.3% */
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CKGEN_SSC_0P4_PERCENT, /**< SSC_DEP 0.4% */
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CKGEN_SSC_0P5_PERCENT, /**< SSC_DEP 0.5% */
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CKGEN_SSC_0P6_PERCENT, /**< SSC_DEP 0.6% */
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CKGEN_SSC_0P7_PERCENT, /**< SSC_DEP 0.7% */
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CKGEN_SSC_0P8_PERCENT, /**< SSC_DEP 0.8% */
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CKGEN_SSC_0P9_PERCENT, /**< SSC_DEP 0.9% */
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CKGEN_SSC_1P0_PERCENT, /**< SSC_DEP 1.0% */
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CKGEN_SSC_1P1_PERCENT, /**< SSC_DEP 1.1% */
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CKGEN_SSC_1P2_PERCENT, /**< SSC_DEP 1.2% */
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CKGEN_SSC_1P3_PERCENT, /**< SSC_DEP 1.3% */
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CKGEN_SSC_1P4_PERCENT, /**< SSC_DEP 1.4% */
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CKGEN_SSC_1P5_PERCENT, /**< SSC_DEP 1.5% */
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CKGEN_SSC_1P6_PERCENT, /**< SSC_DEP 1.6% */
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CKGEN_SSC_1P7_PERCENT, /**< SSC_DEP 1.7% */
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CKGEN_SSC_1P8_PERCENT, /**< SSC_DEP 1.8% */
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CKGEN_SSC_1P9_PERCENT, /**< SSC_DEP 1.9% */
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CKGEN_SSC_2P0_PERCENT, /**< SSC_DEP 2.0% */
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CKGEN_SSC_2P1_PERCENT, /**< SSC_DEP 2.1% */
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CKGEN_SSC_2P2_PERCENT, /**< SSC_DEP 2.2% */
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CKGEN_SSC_2P3_PERCENT, /**< SSC_DEP 2.3% */
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CKGEN_SSC_2P4_PERCENT, /**< SSC_DEP 2.4% */
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CKGEN_SSC_2P5_PERCENT, /**< SSC_DEP 2.5% */
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CKGEN_SSC_2P6_PERCENT, /**< SSC_DEP 2.6% */
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CKGEN_SSC_2P7_PERCENT, /**< SSC_DEP 2.7% */
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CKGEN_SSC_2P8_PERCENT, /**< SSC_DEP 2.8% */
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CKGEN_SSC_2P9_PERCENT, /**< SSC_DEP 2.9% */
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CKGEN_SSC_3P0_PERCENT, /**< SSC_DEP 3.0% */
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CKGEN_SSC_3P1_PERCENT, /**< SSC_DEP 3.1% */
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} sdrv_ckgen_ssc_amplitude_e;
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/**
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* @brief PLL Spread mode.
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*
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*/
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typedef enum sdrv_ckgen_ssc_mode {
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CKGEN_NO_SSC = 0, /**< PLL no spread */
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CKGEN_DOWN_SPREADING, /**< PLL down spread */
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CKGEN_CENTER_SPREADING, /**< PLL center spread */
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} sdrv_ckgen_ssc_mode_e;
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/**
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* @brief PLL Spread Modulation frequency.
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*
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*/
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typedef enum sdrv_ckgen_ssc_freq {
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CKGEN_FREF_DIV_507 = 0, /**< For 16MHz ref. It's 31.5KHz */
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CKGEN_FREF_DIV_761, /**< For 24MHz ref. It's 31.5KHz */
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CKGEN_FREF_DIV_793, /**< For 25MHz ref. It's 31.5KHz */
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CKGEN_FREF_DIV_857, /**< For 27MHz ref. It's 31.5KHz */
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} sdrv_ckgen_ssc_freq_e;
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/**
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* @brief PLL spread spectrum config parameters.
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*/
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typedef struct sdrv_ckgen_pll_ssc_config {
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sdrv_ckgen_ssc_amplitude_e ampl;
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sdrv_ckgen_ssc_mode_e mode;
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sdrv_ckgen_ssc_freq_e freq;
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} sdrv_ckgen_pll_ssc_config_t;
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/**
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* @brief Abstract clock common node for driver operate.
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*/
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typedef struct sdrv_ckgen_node {
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uint32_t base; /**< CKGEN register base */
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uint16_t type; /**< Clock node type */
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uint16_t id; /**< Clock node index */
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} sdrv_ckgen_node_t;
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/**
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* @brief Abstract clock slice node for driver operate.
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*/
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typedef struct sdrv_ckgen_slice_node {
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sdrv_ckgen_node_t clk_node; /**< Abstract clock common node */
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uint8_t parents_num; /**< Slice node parent number */
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const sdrv_ckgen_node_t *
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parents[CONFIG_CKGEN_PARENTS_NUM]; /**< Parent abstract clock common node sets */
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} sdrv_ckgen_slice_node_t;
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/**
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* @brief Abstract xcg node for driver operate.
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*/
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typedef struct sdrv_ckgen_cg_node {
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sdrv_ckgen_node_t clk_node; /**< Abstract clock common node */
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const sdrv_ckgen_node_t *parent; /**< Parent abstract clock common node */
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} sdrv_ckgen_cg_node_t;
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/**
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* @brief Abstract pll node for driver operate.
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*/
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typedef struct sdrv_pll_node {
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sdrv_ckgen_node_t clk_node; /**< Abstract clock common node */
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const sdrv_ckgen_node_t *parent; /**< Parent abstract clock common node */
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} sdrv_pll_node_t;
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/**
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* @brief Clock rate config for IP/Core/PLL node.
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*/
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typedef struct sdrv_ckgen_rate_config_node {
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sdrv_ckgen_node_t *clk_node; /**< Abstract clock common node */
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uint32_t rate; /**< Clock rate for node */
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union {
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/**< For PLL node, pll spread spectrum parameters. IP/Core slice reserved. */
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sdrv_ckgen_pll_ssc_config_t *pll;
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} node_cfg;
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} sdrv_ckgen_rate_config_node_t;
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/**
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* @brief Clock rate config lists for IP/Core/PLL node.
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*/
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typedef struct sdrv_ckgen_rate_config {
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uint32_t config_num; /**< Config node numbers */
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sdrv_ckgen_rate_config_node_t config_nodes[]; /**< Clock node list */
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} sdrv_ckgen_rate_config_t;
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/**
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* @brief Clock rate config for Bus node.
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*/
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typedef struct sdrv_ckgen_bus_config_node {
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sdrv_ckgen_node_t *clk_node; /**< Abstract clock common node */
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uint32_t rate; /**< Clock rate for node */
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sdrv_ckgen_bus_post_div_e post_div; /**< Post divide for bus slice */
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} sdrv_ckgen_bus_config_node_t;
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/**
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* @brief Clock rate config lists for Bus node.
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*/
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typedef struct sdrv_ckgen_bus_config {
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uint32_t config_num; /**< Config node numbers */
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sdrv_ckgen_bus_config_node_t config_nodes[]; /**< Clock node list */
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} sdrv_ckgen_bus_config_t;
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/**
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* @brief Gate config for xcg node.
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*/
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typedef struct sdrv_ckgen_gating_config_node {
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sdrv_ckgen_node_t *clk_node; /**< Abstract clock common node */
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sdrv_ckgen_lp_mode_e mode; /**< Mode for config */
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bool gating; /**< Config gate or not */
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} sdrv_ckgen_gating_config_node_t;
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/**
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* @brief Gate config list for XCG node.
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*/
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typedef struct sdrv_ckgen_gating_config {
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uint32_t config_num; /**< Config xcg node number */
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sdrv_ckgen_gating_config_node_t config_nodes[]; /**< XCG node list */
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} sdrv_ckgen_gating_config_t;
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/**
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* @brief IP clock enable/disable config node.
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*/
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typedef struct sdrv_ckgen_ip_clock_config_node {
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const sdrv_ckgen_node_t **ip_nodes; /**< IP XCG list */
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sdrv_ckgen_lp_mode_e mode; /**< Mode for config */
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bool enable; /**< Enable or disable */
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} sdrv_ckgen_ip_clock_config_node_t;
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/**
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* @brief IP clock enable or disable config.
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*/
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typedef struct sdrv_ckgen_ip_clock_config {
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uint32_t config_num; /**< Config xcg node number */
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sdrv_ckgen_ip_clock_config_node_t config_nodes[]; /**< IP node list */
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} sdrv_ckgen_ip_clock_config_t;
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/**
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* @brief Initialize clock config for system setup.
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*/
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typedef struct sdrv_ckgen_config {
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sdrv_ckgen_bus_config_t const *pre_bus_config; /**< Before config pll, optional change Core/Bus to FS24M */
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sdrv_ckgen_rate_config_t const *pll_config; /**< PLL rate config */
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sdrv_ckgen_bus_config_t const *bus_config; /**< System bus rate config, this include SF/SP core rate */
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sdrv_ckgen_rate_config_t const *core_config; /**< Core rate config, now only config SX rate */
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sdrv_ckgen_rate_config_t const *ip_config; /**< IP rate config */
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sdrv_ckgen_ip_clock_config_t const *enable_config; /**< IP clock enable or disable config */
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sdrv_ckgen_gating_config_t const *gating_config; /**< Clock gate config for each xcg under Run/Sleep/Hibernate mode */
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} sdrv_ckgen_config_t;
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#if CONFIG_CLK_DUMP
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/**
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* @brief Definition for clock tree node.
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*/
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typedef struct sdrv_clk {
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const char *name;
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const sdrv_ckgen_node_t *ckgen_ref;
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struct list_node node;
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struct list_node child;
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} sdrv_clk_t;
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/**
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* @brief System default total clock node list.
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*/
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typedef struct sdrv_clk_config {
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uint32_t config_num;
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sdrv_clk_t config_nodes[];
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} sdrv_clk_config_t;
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/**
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* @brief Dump system clock tree.
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*
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* @param [in] clk_config system total clock node list.
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* @param [in] clk_node the root clock node begin to dump, if set NULL means dump all clock.
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* @return SDRV_STATUS_OK or error code.
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*/
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status_t sdrv_clktree_dump(sdrv_clk_config_t *clk_config, sdrv_clk_t *clk_node);
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#endif /* CONFIG_CLK_DUMP */
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/**
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* @brief CKGEN XCG List
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*/
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typedef struct sdrv_ckgen_xcg_set {
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uint32_t base; /**< Ckgen controller base */
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sdrv_ckgen_type_e cg_type; /**< CG Type */
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uint32_t num; /**< CG Total Number */
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} sdrv_ckgen_xcg_set_t;
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#if CONFIG_RTC_SS_DYNAMIC_PCLK
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#include <armv7-r/irq.h>
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#include <clock_ip.h>
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#if CONFIG_RTC_SS_DYNAMIC_PCLK_IRQ_DISABLE
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#define RTC_SS_ACCESS_START() \
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irq_state_t _state = arch_irq_save(); \
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sdrv_ckgen_clock_config(CLK_NODE(g_ckgen_gating_rtc_pclk), true); \
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SDRV_RTC_REG_PARITY_ERR_ENABLE();
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#define RTC_SS_ACCESS_END() \
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SDRV_RTC_REG_PARITY_ERR_DISABLE(); \
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sdrv_ckgen_clock_config(CLK_NODE(g_ckgen_gating_rtc_pclk), false); \
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arch_irq_restore(_state);
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#else /* CONFIG_RTC_SS_DYNAMIC_PCLK_IRQ_DISABLE */
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int sdrv_rtc_ss_pclk_enable(void);
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int sdrv_rtc_ss_pclk_disable(void);
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#define RTC_SS_ACCESS_START() sdrv_rtc_ss_pclk_enable();
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#define RTC_SS_ACCESS_END() sdrv_rtc_ss_pclk_disable();
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#endif /* CONFIG_RTC_SS_DYNAMIC_PCLK_IRQ_DISABLE */
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#else
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#define RTC_SS_ACCESS_START()
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#define RTC_SS_ACCESS_END()
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#endif /* CONFIG_RTC_SS_DYNAMIC_PCLK */
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/**
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* @brief Config XTAL24M oscillator.
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*
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* This function enable or disable xtal24m oscillator.
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*
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* @param [in] ckgen ckgen node type must be CKGEN_FS24M_TYPE.
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* @param [in] enable true represents enable oscillator, false represents disable oscillator.
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* @return true represents success, false represents fail.
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*/
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int sdrv_xtal24m_enable(sdrv_ckgen_node_t *ckgen, bool enable);
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/**
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* @brief Config XTAL24M oscillator.
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*
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* This function config 24M clock from external active crystal.
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*
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* @param [in] ckgen ckgen node type must be CKGEN_FS24M_TYPE.
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* @return true represents success, false represents fail.
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*/
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int sdrv_xtal24m_from_active_crystal(sdrv_ckgen_node_t *ckgen);
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/**
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* @brief Config FS24M clock source.
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*
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* This function select FS24M clock source, RC oscillator or XTAL oscillator.
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*
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* @param [in] ckgen ckgen node type must be CKGEN_FS24M_TYPE.
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* @param [in] src RC oscillator or XTAL oscillator
|
|
* @return true represents success, false represents fail.
|
|
*/
|
|
int sdrv_fs24m_change_src(sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src);
|
|
|
|
/**
|
|
* @brief Get FS32K real output clock frequency.
|
|
*
|
|
* This function use FS24M to check FS32K clock frequency. So you must make sure
|
|
* FS24M is accurate. If you want check RC32K frequency, first change FS32K source
|
|
* to RC, then call this function. If you want check XTAL32K frequency, first change
|
|
* FS32K source to XTAL, then call this function.
|
|
*
|
|
* @param [in] ckgen ckgen node type must be CKGEN_FS24M_TYPE.
|
|
* @return Real FS32K output frequency.
|
|
*/
|
|
uint32_t sdrv_ckgen_get_fs32k_real_frequency(sdrv_ckgen_node_t *ckgen);
|
|
|
|
/**
|
|
* @brief Config XTAL32K oscillator.
|
|
*
|
|
* This function enable or disable xtal32k oscillator.
|
|
*
|
|
* @param [in] ckgen ckgen node type must be CKGEN_FS32K_TYPE.
|
|
* @param [in] enable true represents enable oscillator, false represents disable oscillator.
|
|
* @return true represents success, false represents fail.
|
|
*/
|
|
int sdrv_xtal32k_enable(sdrv_ckgen_node_t *ckgen, bool enable);
|
|
|
|
/**
|
|
* @brief Config XTAL32K oscillator.
|
|
*
|
|
* This function enable or disable xtal32k oscillator without wait ready status.
|
|
*
|
|
* @param [in] ckgen ckgen node type must be CKGEN_FS32K_TYPE.
|
|
* @param [in] enable true represents enable oscillator, false represents disable oscillator.
|
|
* @return true represents success, false represents fail.
|
|
*/
|
|
int sdrv_xtal32k_enable_nowait(sdrv_ckgen_node_t *ckgen, bool enable);
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|
|
|
/**
|
|
* @brief Get xtal32k ready status.
|
|
*
|
|
* This function get xtal32k ready status.
|
|
*
|
|
* @param [in] ckgen ckgen node type must be CKGEN_FS32K_TYPE.
|
|
* @return true represents xtal32k ready, false represents xtal32 not ready.
|
|
*/
|
|
bool sdrv_xtal32k_get_ready_status(sdrv_ckgen_node_t *ckgen);
|
|
|
|
/**
|
|
* @brief Config XTAL32K oscillator.
|
|
*
|
|
* This function config 32k clock from external active crystal.
|
|
*
|
|
* @param [in] ckgen ckgen node type must be CKGEN_FS32K_TYPE.
|
|
* @return true represents success, false represents fail.
|
|
*/
|
|
int sdrv_xtal32k_from_active_crystal(sdrv_ckgen_node_t *ckgen);
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|
|
|
/**
|
|
* @brief Config FS32K clock source.
|
|
*
|
|
* This function select FS32K clock source, RC oscillator or XTAL oscillator.
|
|
*
|
|
* @param [in] ckgen ckgen node type must be CKGEN_FS32K_TYPE.
|
|
* @param [in] src RC oscillator or XTAL oscillator
|
|
* @return true represents success, false represents fail.
|
|
*/
|
|
int sdrv_fs32k_change_src(sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src);
|
|
|
|
/**
|
|
* @brief Config FS32K clock source without wait active status.
|
|
*
|
|
* This function select FS32K clock source, RC oscillator or XTAL oscillator.
|
|
*
|
|
* @param [in] ckgen ckgen node type must be CKGEN_FS32K_TYPE.
|
|
* @param [in] src RC oscillator or XTAL oscillator
|
|
* @return true represents success, false represents fail.
|
|
*/
|
|
int sdrv_fs32k_change_src_nowait(sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src);
|
|
|
|
/**
|
|
* @brief Get FS32K clock source active status.
|
|
*
|
|
* This function get FS32K clock source, RC oscillator or XTAL oscillator, active status.
|
|
*
|
|
* @param [in] ckgen ckgen node type must be CKGEN_FS32K_TYPE.
|
|
* @param [in] src RC oscillator or XTAL oscillator
|
|
* @return true represents clock source as FS32K
|
|
*/
|
|
bool sdrv_fs32k_get_src_active_status(sdrv_ckgen_node_t *ckgen, sdrv_fs_src_type_e src);
|
|
|
|
/**
|
|
* @brief Control low power voltage detector power on or down.
|
|
*
|
|
* @param [in] ckgen ckgen node type must be CKGEN_FS32K_TYPE.
|
|
* @param [in] power_on True or False.
|
|
* @return true represents success, false represents fail.
|
|
*/
|
|
int sdrv_fs32k_lpvd_power_ctrl(sdrv_ckgen_node_t *ckgen, bool power_on);
|
|
|
|
/**
|
|
* @brief Config PLL rate.
|
|
*
|
|
* This function config clock rate for specific PLL.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CKGEN_PLL_CTRL_TYPE or CKGEN_PLL_LVDS_TYPE.
|
|
* @param [in] rate clock rate to be set.
|
|
* @return SDRV_STATUS_OK or error code.
|
|
*/
|
|
status_t sdrv_pll_set_rate(sdrv_ckgen_node_t *ckgen, uint32_t rate);
|
|
|
|
/**
|
|
* @brief Config PLL rate with delta-sigma modulator enable config.
|
|
*
|
|
* This function config clock rate for specific PLL, and when rate configed work as integer pll,
|
|
* it's up to user whether enable fractional.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CKGEN_PLL_CTRL_TYPE or CKGEN_PLL_LVDS_TYPE.
|
|
* @param [in] rate clock rate to be set.
|
|
* @param [in] ssc_cfg pll spread spectrum config.
|
|
* @return SDRV_STATUS_OK or error code.
|
|
*/
|
|
status_t sdrv_pll_set_rate_with_dsm(sdrv_ckgen_node_t *ckgen, uint32_t rate,
|
|
sdrv_ckgen_pll_ssc_config_t *ssc_cfg);
|
|
|
|
/**
|
|
* @brief Get PLL rate.
|
|
*
|
|
* This function get clock rate for specific PLL.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CKGEN_PLL_CTRL_TYPE or CKGEN_PLL_LVDS_TYPE.
|
|
* @return pll clock rate.
|
|
*/
|
|
uint32_t sdrv_pll_get_rate(sdrv_ckgen_node_t *ckgen);
|
|
|
|
/**
|
|
* @brief Get PLL lock detector status.
|
|
*
|
|
* This function check whether pll is locked.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CKGEN_PLL_CTRL_TYPE.
|
|
* @return true represets locked, false represents unlocked, negative is error code.
|
|
*/
|
|
status_t sdrv_pll_is_locked(sdrv_ckgen_node_t *ckgen);
|
|
|
|
/**
|
|
* @brief Config clock rate for Core/IP slice node.
|
|
*
|
|
* This function configures expected clock rate for specific ckgen node, it will
|
|
* search all his parent nodes, and select a closest clock rate at last.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CKGEN_IP_SLICE_TYPE or CKGEN_CORE_SLICE_TYPE.
|
|
* @param [in] rate expected clock rate.
|
|
* @return SDRV_STATUS_OK or error code.
|
|
*/
|
|
status_t sdrv_ckgen_set_rate(sdrv_ckgen_node_t *ckgen, uint32_t rate);
|
|
|
|
/**
|
|
* @brief Get clock rate for Core/IP slice node.
|
|
*
|
|
* This function get clock rate for CORE or IP slice node.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CKGEN_IP_SLICE_TYPE or CKGEN_CORE_SLICE_TYPE.
|
|
* @return CORE/IP clock rate.
|
|
*/
|
|
uint32_t sdrv_ckgen_get_rate(sdrv_ckgen_node_t *ckgen);
|
|
|
|
/**
|
|
* @brief Config clock rate for Bus slice node.
|
|
*
|
|
* This function configure expected clock rate for specific ckgen BUS slice node,
|
|
* since bus slice can output clock direct, or clock divide by m/n/p/q, and their ratio only
|
|
* has two option, one is 4:2:1, other is 2:2:1. Clk_out_m is for core clock rate, Clk_out_n
|
|
* is for AXI bus clock rate, Clk_out_p is for APB bus clock rate.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CKGEN_SF_BUS_SLICE_TYPE or CKGEN_BUS_SLICE_TYPE.
|
|
* @param [in] rate clock rate to be set for Clk_out_m.
|
|
* @param [in] div m/n/p,q ratio select.
|
|
* @return SDRV_STATUS_OK or error code.
|
|
*/
|
|
status_t sdrv_ckgen_bus_set_rate(sdrv_ckgen_node_t *ckgen, uint32_t rate,
|
|
sdrv_ckgen_bus_post_div_e div);
|
|
|
|
/**
|
|
* @brief Get clock rate for Bus slice node.
|
|
*
|
|
* This function can get Bus slice clock rate, it can get clk_in4 clock directly without divide, or
|
|
* Clk_out_m/Clk_out_n/Clk_out_p/Clk_out_q divided by m/n/p/q.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CKGEN_SF_BUS_SLICE_TYPE or CKGEN_BUS_SLICE_TYPE.
|
|
* @param [in] clk_out Clk_out/Clk_out_m/Clk_out_n/Clk_out_p/Clk_out_q.
|
|
* @return clock rate.
|
|
*/
|
|
uint32_t sdrv_ckgen_bus_get_rate(sdrv_ckgen_node_t *ckgen,
|
|
sdrv_ckgen_bus_out_type_e clk_out);
|
|
|
|
/**
|
|
* @brief Set CG NODE whether participate in low power handshake.
|
|
*
|
|
* This function config CG Node lowpower mask bit. If set to mask, cg status is ignored under low power
|
|
* handshake. Otherwize, cg status is considerd into low power handshake.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CG NODE.
|
|
* @param [in] mask true or false.
|
|
* @return SDRV_STATUS_OK or error code.
|
|
*/
|
|
status_t sdrv_ckgen_cg_mask(sdrv_ckgen_node_t *ckgen, bool mask);
|
|
|
|
/**
|
|
* @brief Config xcg status under run/sleep/hibernate mode.
|
|
*
|
|
* This function configure clock gating status in run/sleep/hibernate mode,
|
|
* when system enter run/sleep/hibernate mode, hardware auto enable or disable
|
|
* clock as configured.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CG NODE.
|
|
* @param [in] lp_mode Run/Sleep/Hibernate.
|
|
* @param [in] gating gating enable or disable.
|
|
* @return SDRV_STATUS_OK or error code.
|
|
*/
|
|
status_t sdrv_ckgen_set_gate(sdrv_ckgen_node_t *ckgen,
|
|
sdrv_ckgen_lp_mode_e lp_mode, bool gating);
|
|
|
|
/**
|
|
* @brief Config clock enable or disable in run mode.
|
|
*
|
|
* This function configure clock gating status in run mode.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CG NODE.
|
|
* @param [in] enable clock enable or disable.
|
|
* @return 0 represents success, otherwise failed.
|
|
*/
|
|
status_t sdrv_ckgen_clock_config(sdrv_ckgen_node_t *ckgen, bool enable);
|
|
|
|
/**
|
|
* @brief Config IP clock enable/disable in run/sleep/hibernate mode.
|
|
*
|
|
* This function config all xcg belongs to this IP in run/sleep/hibernate mode.
|
|
*
|
|
* @param [in] ckgen_ip CG Node list belongs to this IP.
|
|
* @param [in] mode Run/Sleep/Hibernate.
|
|
* @param [in] enable clock enable or disable.
|
|
* @return SDRV_STATUS_OK or error code.
|
|
*/
|
|
status_t sdrv_ckgen_ip_clock_enable(const sdrv_ckgen_node_t *ckgen_ip[],
|
|
sdrv_ckgen_lp_mode_e mode, bool enable);
|
|
|
|
/**
|
|
* @brief Config PLL power down under run/sleep/hibernate mode.
|
|
*
|
|
* This function config enable or disable PLL power under run/sleep/hibernate mode.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CKGEN_PLL_CG_TYPE.
|
|
* @param [in] lp_mode Run/Sleep/Hibernate.
|
|
* @param [in] power_down power down enable or disable.
|
|
* @return SDRV_STATUS_OK or error code.
|
|
*/
|
|
status_t sdrv_ckgen_set_pll_power(sdrv_ckgen_node_t *ckgen,
|
|
sdrv_ckgen_lp_mode_e lp_mode, bool power_down);
|
|
|
|
/**
|
|
* @brief Get ckgen xcg node gating status.
|
|
*
|
|
* This function check whether xcg node is gated.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be CG NODE.
|
|
* @return true represents clock is gated, false represents clock is active, negative is error code.
|
|
*/
|
|
status_t sdrv_ckgen_is_gated(sdrv_ckgen_node_t *ckgen);
|
|
|
|
/**
|
|
* @brief Get slice node gating status.
|
|
*
|
|
* This function check whether slice node is gated.
|
|
*
|
|
* @param [in] ckgen ckgen node type can be IP/Core/Bus slice.
|
|
* @return true represents clock is gated, false represents clock is active, negative is error code.
|
|
*/
|
|
status_t sdrv_ckgen_slice_gated(sdrv_ckgen_node_t *ckgen);
|
|
|
|
/**
|
|
* @brief Config All xcg gate or active.
|
|
*
|
|
* This function config PCG/BCG/CCG all gate or active.
|
|
*
|
|
* @param [in] xcg xcg info.
|
|
* @param [in] mode run mode.
|
|
* @param [in] gate true or false.
|
|
* @return SDRV_STATUS_OK or error code.
|
|
*/
|
|
status_t sdrv_ckgen_xcg_type_set(sdrv_ckgen_xcg_set_t *xcg, sdrv_ckgen_lp_mode_e mode, bool gate);
|
|
|
|
/**
|
|
* @brief System clock initialize.
|
|
*
|
|
* This function initialize all system clock as pre-defined. It will change core clock to
|
|
* 24M, then config PLL, after PLL is locked, config BUS and CORE to expect rate. After that
|
|
* config IP clock if defined, and enable or disable clock gate.
|
|
*
|
|
* @param [in] config pre-defined clock config list.
|
|
* @return SDRV_STATUS_OK or error code.
|
|
*/
|
|
status_t sdrv_ckgen_init(sdrv_ckgen_config_t *config);
|
|
|
|
#endif /* SDRV_CLK_H_ */
|