317 lines
12 KiB
C
317 lines
12 KiB
C
/*
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*********************************************************************************************************
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* uC/USB-Host
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* The Embedded USB Host Stack
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*
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* Copyright 2004-2021 Silicon Laboratories Inc. www.silabs.com
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*
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* SPDX-License-Identifier: APACHE-2.0
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*
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* This software is subject to an open source license and is distributed by
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* Silicon Laboratories Inc. pursuant to the terms of the Apache License,
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* Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
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*
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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*
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* GENERIC EHCI DRIVER
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*
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* Filename : usbh_ehci.h
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* Version : V3.42.01
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*********************************************************************************************************
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*/
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#ifndef USBH_EHCI_H
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#define USBH_EHCI_H
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/*
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*********************************************************************************************************
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* INCLUDE HEADER FILES
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*********************************************************************************************************
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*/
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#include "../../Source/usbh_core.h"
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/*
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*********************************************************************************************************
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* CONSTANTS
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*********************************************************************************************************
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*/
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#define EHCI_MAX_ITD 10u /* Max nbr of iTD per EP for HS isoc xfer */
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#define EHCI_MAX_SITD 10u /* Max nbr of siTD per EP for FS isoc xfer */
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#define EHCI_MAX_PERIODIC_BW 90u
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#define EHCI_PORT_POWERED_ALWAYS 0u
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#define EHCI_PORT_POWERED_INDIVIDUAL 1u
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#define EHCI_MAX_PERIODIC_LIST_SIZE (256u * 2u)
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#define EHCI_TIMESTAMP_MICROSEC 1u
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#define EHCI_TIMESTAMP_MILLISEC 2u
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/* ----------- EHCI QH LIST NUMBER DEFINES ------------ */
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#define EHCI_QH_LIST_256MS 0u
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#define EHCI_QH_LIST_128MS 256u
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#define EHCI_QH_LIST_64MS 384u
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#define EHCI_QH_LIST_32MS 448u
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#define EHCI_QH_LIST_16MS 480u
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#define EHCI_QH_LIST_08MS 496u
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#define EHCI_QH_LIST_04MS 504u
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#define EHCI_QH_LIST_02MS 508u
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#define EHCI_QH_LIST_01MS 510u
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#define EHCI_INTR_QH_LIST_SIZE (EHCI_QH_LIST_01MS + 1u)
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#define EHCI_MAX_BW_PER_MICRO_FRAME 3072u
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#define EHCI_BW_FLAG_CONSUME 1u
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#define EHCI_BW_FLAG_PRODUCE 2u
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/*
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*********************************************************************************************************
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* LOCAL DEFINES
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* LOCAL DATA TYPES
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* LOCAL GLOBAL VARIABLES
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* MACROS
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*********************************************************************************************************
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*/
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#ifndef EHCI_CFG_ONRESET_EN /* En callback to setup auxiliary registers on reset. */
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#define EHCI_CFG_ONRESET_EN DEF_DISABLED
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#endif
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#define USBH_EHCI_CFG_PERIODIC_EN DEF_ENABLED
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/*
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*********************************************************************************************************
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* MAXIMUM PACKET SIZES
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*********************************************************************************************************
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*/
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#define MPS_HS 1024u /* Maximum Packet Size for High Speed device */
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#define MPS_FS 1023u /* Maximum Packet Size for Full Speed device */
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#define MPS_LS 64u /* Maximum Packet Size for Low Speed device */
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/*
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*********************************************************************************************************
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* TYPE DEFINITIONS
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*********************************************************************************************************
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*/
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typedef struct ehci_isoc_ep_desc EHCI_ISOC_EP_DESC;
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typedef struct ehci_isoc_ep_urb EHCI_ISOC_EP_URB;
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typedef struct ehci_intr_info EHCI_INTR_INFO;
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typedef struct ehci_qh {
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CPU_REG32 QHHorLinkPtr;
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CPU_REG32 QHEpCapChar[2];
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CPU_REG32 QHCurQTDPtr;
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CPU_REG32 QHNxtQTDPtr;
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CPU_REG32 QHAltNxtQTDPtr;
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CPU_REG32 QHToken;
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CPU_REG32 QHBufPagePtrList[5];
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/* Fields not part of qH struct defined in EHCI spec */
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USBH_EP *EPPtr;
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CPU_INT32U QTDHead;
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CPU_INT08U SMask;
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CPU_INT08U BWStartFrame;
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CPU_INT16U FrameInterval;
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CPU_INT08U Rsvd[4]; /* Padding to align the struct on a 32-byte boundary */
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} EHCI_QH;
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typedef struct ehci_qtd {
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CPU_REG32 QTDNxtPtr;
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CPU_REG32 QTDAltNxtPtr;
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CPU_REG32 QTDToken;
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CPU_REG32 QTDBufPagePtrList[5];
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} EHCI_QTD;
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typedef struct ehci_sitd {
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CPU_REG32 SITDNxtLinkPtr;
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CPU_REG32 SITDEpCapChar[2];
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CPU_REG32 SITDStsCtrl;
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CPU_REG32 SITDBufPagePtrList[2];
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CPU_REG32 SITDBackLinkPtr;
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} EHCI_SITD;
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typedef struct ehci_itd {
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CPU_REG32 ITDNxtLinkPtr;
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CPU_REG32 ITDStsAndCntrl[8];
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CPU_REG32 ITDBufPagePtrList[7];
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} EHCI_ITD;
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struct ehci_isoc_ep_desc {
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void *TDTailPtr;
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USBH_EP *EPPtr;
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CPU_INT08U SMask;
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CPU_INT08U CMask;
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CPU_INT08U TCnt;
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CPU_INT08U AppStartFrame;
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CPU_INT08U NbrFrame;
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CPU_INT16U FrameInterval;
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EHCI_ISOC_EP_DESC *NxtEPDesc;
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};
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struct ehci_isoc_ep_urb {
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CPU_INT32U iTD_Addr;
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CPU_INT08U AppStartFrame;
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CPU_INT08U NbrFrame;
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};
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typedef struct ehci_cap {
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CPU_INT08U CapLen;
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CPU_INT16U HCIVersion;
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CPU_INT32U HCSParams;
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CPU_INT32U HCCParams;
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CPU_INT08U HCSPPortRoute[15];
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} EHCI_CAP;
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typedef struct ehci_cap_reg {
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CPU_REG32 CapLen_HCIVersion;
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CPU_REG32 HCSParams;
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CPU_REG32 HCCParams;
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CPU_REG08 HCSPPortRoute[15];
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} EHCI_CAP_REG;
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typedef struct ehci_oper_reg {
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CPU_REG32 USBCmd;
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CPU_REG32 USBSts;
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CPU_REG32 USBIntr;
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CPU_REG32 FrameIx;
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CPU_REG32 CtrlDSSeg;
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CPU_REG32 PeriodicListBase;
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CPU_REG32 AsyncListAddr;
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CPU_REG32 Rsvd[9];
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CPU_REG32 CfgFlag;
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CPU_REG32 PortSC[1];
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} EHCI_OPER_REG;
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typedef struct ehci_dma {
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EHCI_QTD *QTDPtr; /* DMA memory CTRL,BULK and INTR QTD */
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EHCI_QH *QHPtr; /* DMA memory for Queue Head (QH) */
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EHCI_ITD *ITDPtr;
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CPU_INT08U *BufPtr;
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} EHCI_DMA;
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#if (USBH_EHCI_CFG_PERIODIC_EN == DEF_ENABLED)
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struct ehci_intr_info {
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CPU_INT08U IntrPlaceholderIx; /* Index of Intr placeholder in QHLists array. */
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CPU_INT16U FrameInterval;
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USBH_EP *EpPtr;
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EHCI_INTR_INFO *NxtIntrInfo;
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};
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#endif
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typedef struct ehci_dev { /* -------------------- EHCI Device ------------------- */
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EHCI_CAP HcCap; /* Pointer to Capability structure */
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EHCI_DMA DMA_EHCI;
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CPU_INT08U EHCI_HubBuf[sizeof(USBH_HUB_DESC)];
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EHCI_QH *AsyncQHHead; /* Asynchronous list head */
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CPU_INT08U NbrPorts; /* Number of Ports in RootHub */
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MEM_POOL HC_QHPool; /* Memory pool for allocating HC QHs */
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MEM_POOL HC_QTDPool; /* Memory pool for allocating HC QTDs */
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MEM_POOL BufPool;
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CPU_INT32U PortResetChng; /* Port Reset Change status variable */
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EHCI_CAP_REG *HcCapReg; /* Pointer to Host Controller Capability Registers */
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EHCI_OPER_REG *HcOperReg; /* Pointer to Host Controller Operational Registers */
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#if (USBH_EHCI_CFG_PERIODIC_EN == DEF_ENABLED)
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CPU_INT32U *PeriodicListBase;
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EHCI_QH *QHLists[EHCI_INTR_QH_LIST_SIZE]; /* HCD qH placeholder array for Intr ep. */
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MEM_POOL HC_ITDPool; /* Memory pool for allocating HC iTDs */
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MEM_POOL IntrInfoPool; /* Memory pool for allocating Intr info struct. */
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MEM_POOL HC_Isoc_EP_DescPool; /* Memory pool for allocating HCD Isoc EP struct */
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MEM_POOL HC_Isoc_EP_URBPool;
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CPU_INT16U MaxPeriodicBWArr[256][8]; /* Maximum Periodic Bandwidth */
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EHCI_ISOC_EP_DESC *HeadIsocEPDesc; /* Isochronous list head pointer */
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EHCI_INTR_INFO *HeadIntrInfo; /* Intr info list head pointer. */
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#endif
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CPU_INT32U FNOCnt; /* Counter for Frame List Rollover */
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CPU_BOOLEAN HC_Started; /* Indicate if EHCI HC is started. */
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CPU_INT08U DrvType; /* Indicate which EHCI drv type. */
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} EHCI_DEV;
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/*
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*********************************************************************************************************
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* GLOBAL VARIABLES
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*********************************************************************************************************
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*/
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#ifdef USBH_EHCI_MODULE
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#define USBH_EHCI_EXT
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#else
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#define USBH_EHCI_EXT extern
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#endif
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USBH_EHCI_EXT USBH_HC_DRV_API EHCI_DrvAPI;
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USBH_EHCI_EXT USBH_HC_DRV_API EHCI_DrvAPI_Synopsys;
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USBH_EHCI_EXT USBH_HC_RH_API EHCI_RH_API;
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/*
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*********************************************************************************************************
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* FUNCTION PROTOTYPES
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* CONFIGURATION ERRORS
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*********************************************************************************************************
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*/
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/*
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*********************************************************************************************************
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* MODULE END
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*********************************************************************************************************
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*/
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#endif
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