78 lines
3.4 KiB
C
78 lines
3.4 KiB
C
/**
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* @file cpu_cfg.h
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*
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* Copyright (c) 2021 Semidrive Semiconductor.
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* All rights reserved.
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*
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* Description: CPU Configuration file for USB Device & Host.
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*
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* Revision History:
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* -----------------
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*/
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#ifndef CPU_CFG_MODULE_PRESENT
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#define CPU_CFG_MODULE_PRESENT
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/*
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*********************************************************************************************************
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* CPU TIMESTAMP CONFIGURATION
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*
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* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
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*
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* (a) CPU_CFG_TS_32_EN enable/disable 32-bit CPU timestamp feature
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* (b) CPU_CFG_TS_64_EN enable/disable 64-bit CPU timestamp feature
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*
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* (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
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*
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* CPU_WORD_SIZE_08 8-bit word size
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* CPU_WORD_SIZE_16 16-bit word size
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* CPU_WORD_SIZE_32 32-bit word size
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* CPU_WORD_SIZE_64 64-bit word size
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*
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* (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets
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* (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word
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* size SHOULD be configured (e.g. to 16-bits). However, the minimum supported word
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* size for CPU timestamp timers is 8-bits.
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*
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* See also 'cpu_core.h FUNCTION PROTOTYPES CPU_TS_TmrRd() Note #2a'.
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*********************************************************************************************************
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*/
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/* Configure CPU timestamp features (see Note #1) : */
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#define CPU_CFG_TS_32_EN DEF_DISABLED
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#define CPU_CFG_TS_64_EN DEF_DISABLED
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/* DEF_DISABLED CPU timestamps DISABLED */
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/* DEF_ENABLED CPU timestamps ENABLED */
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/* Configure CPU timestamp timer word size ... */
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/* ... (see Note #2) : */
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#define CPU_CFG_TS_TMR_SIZE CPU_WORD_SIZE_32
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/*
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*********************************************************************************************************
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* CACHE MANAGEMENT
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*
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* Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache management API.
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*
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* (2) This option only enables the cache management functions.
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* It does not enable any hardware caches, which should be configured in startup code.
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* Caches must be configured and enabled by the time CPU_Init() is called.
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*
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* (3) This option is usually required for device drivers which use a DMA engine to transmit
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* buffers that are located in cached memory.
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*********************************************************************************************************
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*/
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/* Defines CPU data word-memory order (see Note #1). */
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#if CONFIG_ARCH_WITH_CACHE
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#define CPU_CFG_CACHE_MGMT_EN DEF_ENABLED
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#else
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#define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED
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#endif
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#endif
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