86 lines
2.4 KiB
C
86 lines
2.4 KiB
C
/**
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* @file sdrv_wdt_reg.h
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* @brief Sdrv watchdog head source.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef SDRV_TAISHAN_WDT_REG_H_
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#define SDRV_TAISHAN_WDT_REG_H_
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#define WDT_CTRL (0x00u)
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#define WDT_CTRL_SOFT_RST (0u)
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#define WDT_CTRL_WDT_EN (1u)
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#define WDT_CTRL_CLK_SRC_LSB (2u)
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#define WDT_CTRL_CLK_SRC_MASK (0x7u)
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#define WDT_CTRL_WTC_SRC (5u)
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#define WDT_CTRL_AUTO_RESTART (6u)
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#define WDT_CTRL_DBG_HALT_EN (7u)
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#define WDT_CTRL_WDT_EN_SRC (8u)
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#define WDT_CTRL_SELFTEST_TRIG (9u)
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#define WDT_CTRL_WDT_EN_STA (10u)
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#define WDT_CTRL_PRE_DIV_NUM_LSB (16u)
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#define WDT_CTRL_PRE_DIV_NUM_MASK (0xFFFFu)
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#define WDT_WTC (0x04u)
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#define WDT_WTC_VAL_MASK (0xFFFFFFFFu)
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#define WDT_WRC_CTRL (0x08u)
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#define WDT_WRC_CTRL_MODEM0 (0u)
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#define WDT_WRC_CTRL_MODEM1 (1u)
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#define WDT_WRC_CTRL_SEQ_REFR (2u)
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#define WDT_WRC_CTRL_REFR_TRIG (3u)
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#define WDT_WRC_VAL (0x0Cu)
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#define WDT_WRC_VAL_MASK (0xFFFFFFFFu)
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#define WDT_WRC_SEQ (0x10u)
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#define WDT_WRC_SEQ_MASK (0xFFFFFFFFu)
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#define WDT_RST_CTRL (0x14u)
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#define WDT_RST_CTRL_RST_CNT_MASK (0xFFFFu)
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#define WDT_RST_CTRL_INT_RST_EN (16u)
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#define WDT_RST_CTRL_INT_RST_MODE (17u)
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#define WDT_RST_CTRL_WDT_RST_EN (18u)
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#define WDT_RST_CTRL_RST_WIN_LSB (20u)
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#define WDT_RST_CTRL_RST_WIN_MASK (0xFFu)
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#define WDT_EXT_RST_CTRL (0x18u)
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#define WDT_EXT_RST_CTRL_RST_CNT_MASK (0xFFFFu)
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#define WDT_EXT_RST_CTRL_EXT_RST_EN (16u)
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#define WDT_EXT_RST_CTRL_EXT_RST_MODE (17u)
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#define WDT_EXT_RST_CTRL_RST_WIN_LSB (20u)
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#define WDT_EXT_RST_CTRL_RST_WIN_MASK (0xFFu)
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#define WDT_EXT_RST_CTRL_EXT_RST_REQ_POL (28u)
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#define WDT_CNT (0x1Cu)
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#define WDT_TWS (0x20u)
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#define WDT_INT (0x24u)
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#define WDT_INT_ILL_WIN_REFE_INT_EN (0u)
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#define WDT_INT_ILL_SEQ_REFE_INT_EN (1u)
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#define WDT_INT_OVERFLOW_INT_EN (2u)
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#define WDT_INT_ILL_WIN_REFE_INT_STA (3u)
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#define WDT_INT_ILL_SEQ_REFE_INT_STA (4u)
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#define WDT_INT_OVERFLOW_INT_STA (5u)
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#define WDT_INT_ILL_WIN_REFE_INT_CLR (6u)
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#define WDT_INT_ILL_SEQ_REFE_INT_CLR (7u)
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#define WDT_INT_OVERFLOW_INT_CLR (8u)
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#define WDT_RST_REQ_MON (0x28u)
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#define WDT_RST_REQ_MON_INT_RST_REQ_MON (0u)
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#define WDT_RST_REQ_MON_INT_RST_REQ_REC (2u)
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#define WDT_LOCK (0x40u)
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#define WDT_LOCK_CTL_LOCK (0u)
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#define WDT_LOCK_WTC_LOCK (1u)
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#define WDT_LOCK_WRC_LOCK (2u)
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#define WDT_LOCK_RST_LOCK (3u)
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#define WDT_LOCK_EXT_RST_LOCK (4u)
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#define WDT_LOCK_INT_LOCK (5u)
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#define WDT_LOCK_CLK_SRC_LOCK (6u)
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#endif /* SDRV_TAISHAN_WDT_REG_H_ */
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