507 lines
25 KiB
C
507 lines
25 KiB
C
/** ************************************************************************************************
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* SEMIDRIVE Copyright Statement
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* Copyright (c) SEMIDRIVE. All rights reserved
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*
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* This software and all rights therein are owned by SEMIDRIVE, and are
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* protected by copyright law and other relevant laws, regulations and
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* protection. Without SEMIDRIVE's prior written consent and/or related rights,
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* please do not use this software or any potion thereof in any form or by any
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* means. You may not reproduce, modify or distribute this software except in
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* compliance with the License. Unless required by applicable law or agreed to
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* in writing, software distributed under the License is distributed on
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* an 'AS IS' basis, WITHOUT WARRANTIES OF ANY KIND, either express or implied.
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*
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**************************************************************************************************/
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/** ************************************************************************************************
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* \file sdrv_firewall_gpio.c
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* \brief SSDK Firewall GPIO Driver
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*
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* <table>
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* <tr><th>Date <th>Version
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* <tr><td>2023/11/29 <td>1.0.0
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* </table>
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**************************************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************************************
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* Include header files
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**************************************************************************************************/
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#include <reg.h>
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#include "sdrv_firewall_gpio.h"
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/***************************************************************************************************
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* Private Macro definition
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**************************************************************************************************/
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/** \brief The offset bit of privilege mode permission for domain0. */
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#define FIREWALL_GPIO_DOM0_PRIVILEGED_BIT (4U)
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/** \brief The offset bit of user mode permission for domain0. */
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#define FIREWALL_GPIO_DOM0_USER_BIT (6U)
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/** \brief The offset bit of privilege mode permission for domain1. */
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#define FIREWALL_GPIO_DOM1_PRIVILEGED_BIT (12U)
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/** \brief The offset bit of user mode permission for domain1. */
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#define FIREWALL_GPIO_DOM1_USER_BIT (14U)
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/** \brief The offset bit of privilege mode permission for domain2. */
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#define FIREWALL_GPIO_DOM2_PRIVILEGED_BIT (20U)
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/** \brief The offset bit of user mode permission for domain2. */
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#define FIREWALL_GPIO_DOM2_USER_BIT (22U)
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/** \brief The offset bit of privilege mode permission for domain3. */
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#define FIREWALL_GPIO_DOM3_PRIVILEGED_BIT (28U)
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/** \brief The offset bit of user mode permission for domain3. */
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#define FIREWALL_GPIO_DOM3_USER_BIT (30U)
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/** \brief The offset bit of privilege mode permission for domain4. */
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#define FIREWALL_GPIO_DOM4_PRIVILEGED_BIT (4U)
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/** \brief The offset bit of user mode permission for domain4. */
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#define FIREWALL_GPIO_DOM4_USER_BIT (6U)
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/** \brief The offset bit of privilege mode permission for domain5. */
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#define FIREWALL_GPIO_DOM5_PRIVILEGED_BIT (12U)
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/** \brief The offset bit of user mode permission for domain5. */
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#define FIREWALL_GPIO_DOM5_USER_BIT (14U)
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/** \brief The offset bit of privilege mode permission for domain6. */
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#define FIREWALL_GPIO_DOM6_PRIVILEGED_BIT (20U)
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/** \brief The offset bit of user mode permission for domain6. */
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#define FIREWALL_GPIO_DOM6_USER_BIT (22U)
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/** \brief The offset bit of privilege mode permission for domain7. */
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#define FIREWALL_GPIO_DOM7_PRIVILEGED_BIT (28U)
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/** \brief The offset bit of user mode permission for domain7. */
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#define FIREWALL_GPIO_DOM7_USER_BIT (30U)
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/** \brief The offset address of the gpio permission0 register. */
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#define FIREWALL_GPIO_DOM_PER0N_0 ((uint32_t)0x00U)
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/** \brief The size of the gpio permission0 register. */
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#define FIREWALL_GPIO_DOM_PER0N_SIZE ((uint32_t)0x0CU)
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/** \brief The offset address of the gpio permission0 register for different cores. */
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#define FIREWALL_GPIO_DOM_PER0N_ADDR(n) \
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(FIREWALL_GPIO_DOM_PER0N_0 + ((n)*FIREWALL_GPIO_DOM_PER0N_SIZE))
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/** \brief The offset address of the gpio permission1 register. */
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#define FIREWALL_GPIO_DOM_PER1N_0 ((uint32_t)0x04U)
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/** \brief The size of the gpio permission1 register. */
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#define FIREWALL_GPIO_DOM_PER1N_SIZE ((uint32_t)0x0CU)
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/** \brief The offset address of the gpio permission1 register for different cores. */
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#define FIREWALL_GPIO_DOM_PER1N_ADDR(n) \
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(FIREWALL_GPIO_DOM_PER1N_0 + ((n)*FIREWALL_GPIO_DOM_PER1N_SIZE))
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/** \brief The offset address of the gpio permission lock register. */
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#define FIREWALL_GPIO_DOM_PER_LOCKN_0 ((uint32_t)0x08U)
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/** \brief The size of the gpio permission lock register. */
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#define FIREWALL_GPIO_DOM_PER_LOCKN_SIZE ((uint32_t)0x0CU)
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/** \brief The bit mask of locking the gpio permission. */
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#define FIREWALL_GPIO_DOM_PER_LOCK (0xFFUL)
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/** \brief The offset address of the gpio permission lock register for different cores. */
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#define FIREWALL_GPIO_DOM_PER_LOCKN_ADDR(n) \
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(FIREWALL_GPIO_DOM_PER_LOCKN_0 + ((n)*FIREWALL_GPIO_DOM_PER_LOCKN_SIZE))
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/** \brief The offset address of the gpio core select register. */
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#define FIREWALL_GPIO_DGSELN_0 ((uint32_t)0x140U)
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/** \brief The size of the gpio core select register. */
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#define FIREWALL_GPIO_DGSELN_SIZE ((uint32_t)0x04U)
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/** \brief The offset bit of the gpio core select. */
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#define FIREWALL_GPIO_RGN_DGSEL_BIT (1U)
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/** \brief The bit mask of enabling the gpio permission control. */
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#define FIREWALL_GPIO_RGN_EN (1UL)
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/** \brief The bit mask of locking the gpio permission control. */
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#define FIREWALL_GPIO_RGN_LOCK (1UL << 31U)
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/** \brief The offset address of the gpio core select register for different pin channels. */
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#define FIREWALL_GPIO_DGSELN_ADDR(n) \
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(FIREWALL_GPIO_DGSELN_0 + ((n)*FIREWALL_GPIO_DGSELN_SIZE))
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/***************************************************************************************************
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* Private Function Declarations
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**************************************************************************************************/
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static status_t sdrv_firewall_gpio_select_core(
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const sdrv_gpio_channel_cfg_t *gpio_channel_cfg, uint8_t core_id);
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static status_t sdrv_firewall_gpio_permission_configure(
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const sdrv_gpio_core_cfg_t *gpio_cfg);
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/***************************************************************************************************
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* Global Function Declarations
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**************************************************************************************************/
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/**
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* @brief Configure the gpio rule space and perimissions.
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*
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* This function Configure the gpio rule space and perimissions.
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* This function should be called only once.
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*
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* @param[in] io_cfg the configuration of pin permission.
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* @param[in] core_num the number of cores.
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*
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* @return The result of this function.
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* @details - return FIREWALL_E_OK : Configure the gpio rule space and perimissions success.
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* - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
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* - return FIREWALL_E_GPIO_CORE_NUM : The number of the core configurations is unvalid.
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*/
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status_t sdrv_firewall_gpio_rulespace_configure(
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const sdrv_gpio_core_cfg_t *io_cfg, uint8_t core_num)
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{
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status_t ret_val = FIREWALL_E_OK;
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uint8_t core_id;
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if (NULL == io_cfg)
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{
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ret_val = FIREWALL_E_NULL_POINTER;
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}
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else if (FIREWALL_GPIO_CORE_MAXNUM < core_num)
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{
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ret_val = FIREWALL_E_GPIO_CORE_NUM;
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}
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else
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{
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/* #20 Configure the rule of gpio pins. */
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for (core_id = 0U; core_id < core_num; ++core_id)
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{
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/* Assign gpio pins to the specified core. */
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ret_val = sdrv_firewall_gpio_select_core(
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&io_cfg[core_id].gpio_channel_cfg,
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io_cfg[core_id].gpio_core_id);
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if (FIREWALL_E_OK == ret_val)
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{
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/* Configure the permissions of gpio pins for the core. */
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ret_val =
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sdrv_firewall_gpio_permission_configure(&io_cfg[core_id]);
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} /* else not needed */
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if (FIREWALL_E_OK != ret_val)
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{
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break;
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} /* else not needed */
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}
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}
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return ret_val;
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}
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/**
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* @brief Lock the configurations of the gpio rule space and perimissions.
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*
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* This function locks the configurations of the gpio rule space and perimissions.
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* This function is called by sdrv_firewall_init().
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* This function should be called after sdrv_firewall_gpio_rulespace_configure().
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*/
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void sdrv_firewall_gpio_rulespace_Lock(void)
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{
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uint32_t gpio_base = 0U;
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uint16_t channel_id;
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uint16_t channel_num;
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uint32_t temp_val;
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uint8_t core_id;
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/* #10 Lock the assignment of all gpio pins. */
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for (channel_num = 0U; channel_num < FIREWALL_GPIO_CHANNEL_MAXNUM;
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++channel_num)
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{
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channel_id = channel_num;
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(void)sdrv_firewall_gpio_get_base_addr(&channel_id, &gpio_base);
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temp_val = readl(gpio_base + FIREWALL_GPIO_DGSELN_ADDR(channel_id));
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writel(temp_val | (uint32_t)FIREWALL_GPIO_RGN_LOCK,
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gpio_base + FIREWALL_GPIO_DGSELN_ADDR(channel_id));
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}
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/* #20 Lock the permissions of gpio pins for different cores. */
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for (core_id = 0U; core_id < FIREWALL_GPIO_CORE_MAXNUM; ++core_id)
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{
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writel((uint32_t)FIREWALL_GPIO_DOM_PER_LOCK,
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FIREWALL_APB_GPIO_SF_BASE +
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FIREWALL_GPIO_DOM_PER_LOCKN_ADDR(core_id));
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#ifdef FIREWALL_APB_GPIO_AP_BASE
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writel((uint32_t)FIREWALL_GPIO_DOM_PER_LOCK,
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FIREWALL_APB_GPIO_AP_BASE +
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FIREWALL_GPIO_DOM_PER_LOCKN_ADDR(core_id));
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#endif /* #ifdef FIREWALL_APB_GPIO_AP_BASE */
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}
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}
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/***************************************************************************************************
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* Private Function Declarations
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**************************************************************************************************/
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/**
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* @brief Configure the gpio pin rule space.
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*
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* This function is called by sdrv_firewall_gpio_rulespace_configure().
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*
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* @param[in] gpio_channel_cfg The pointer to the gpio pin configurations.
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* @param[in] core_id The id of the core.
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*
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* @return The result of this function.
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* @details - return FIREWALL_E_OK : Configure the gpio rule space success.
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* - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
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* - return FIREWALL_E_GPIO_CHANNEL_NUM : The number of the gpio pin channels is unvalid.
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*/
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static status_t sdrv_firewall_gpio_select_core(
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const sdrv_gpio_channel_cfg_t *gpio_channel_cfg, uint8_t core_id)
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{
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status_t ret_val = FIREWALL_E_OK;
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uint32_t gpio_base = 0U;
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uint16_t channel_id;
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uint16_t channel_cfgnum;
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uint16_t channel_num;
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uint32_t temp_val;
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/* #10 Check the parameters. */
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if (NULL == gpio_channel_cfg->gpio_channel_id)
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{
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ret_val = FIREWALL_E_NULL_POINTER;
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}
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else if (FIREWALL_GPIO_CHANNEL_MAXNUM < gpio_channel_cfg->gpio_channel_num)
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{
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ret_val = FIREWALL_E_GPIO_CHANNEL_NUM;
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}
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else
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{
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channel_cfgnum = gpio_channel_cfg->gpio_channel_num;
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/* #20 Assign gpio pins to the specified core. */
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for (channel_num = 0U; channel_num < channel_cfgnum; ++channel_num)
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{
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channel_id = gpio_channel_cfg->gpio_channel_id[channel_num];
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if (!sdrv_firewall_gpio_get_base_addr(&channel_id, &gpio_base))
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{
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ret_val = FIREWALL_E_GPIO_CHANNEL_ID;
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}
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if (FIREWALL_E_OK == ret_val)
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{
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/* Select the assignment of the gpio pin. */
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writel((uint32_t)core_id << FIREWALL_GPIO_RGN_DGSEL_BIT,
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gpio_base + FIREWALL_GPIO_DGSELN_ADDR(channel_id));
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/* Enable the assignment of the gpio pin. */
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temp_val =
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readl(gpio_base + FIREWALL_GPIO_DGSELN_ADDR(channel_id));
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writel(temp_val | (uint32_t)FIREWALL_GPIO_RGN_EN,
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gpio_base + FIREWALL_GPIO_DGSELN_ADDR(channel_id));
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} /* else not needed */
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}
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}
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return ret_val;
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}
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/**
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* @brief Configure the permissions of the gpio pin for the core.
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*
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* This function is called by sdrv_firewall_gpio_rulespace_configure().
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*
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* @param[in] gpio_cfg The pointer to the gpio pin configurations.
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*
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* @return The result of this function.
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* @details - return FIREWALL_E_OK : Configure the gpio rule space perimissions success.
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* - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
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* - return FIREWALL_E_GPIO_CORE_ID : The id of the core is unvalid.
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*/
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static status_t sdrv_firewall_gpio_permission_configure(
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const sdrv_gpio_core_cfg_t *gpio_cfg)
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{
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status_t ret_val = FIREWALL_E_OK;
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uint32_t domain_permission0;
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uint32_t domain_permission1;
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/* #10 Check the parameters. */
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if (NULL == gpio_cfg)
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{
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ret_val = FIREWALL_E_NULL_POINTER;
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}
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else
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{
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/* Config lock/unlock/dma domain permission. */
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domain_permission0 = (uint32_t)FIREWALL_PERMISSION_RW
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<< FIREWALL_GPIO_DOM0_PRIVILEGED_BIT;
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domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_RW
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<< FIREWALL_GPIO_DOM0_USER_BIT;
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domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM1_PRIVILEGED_BIT;
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domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM1_USER_BIT;
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/* #20 Configure permissions of gpio pins for the specified core. */
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switch (gpio_cfg->gpio_core_id)
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{
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#ifdef FIREWALL_GPIO_DGSEL_CORE0
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case FIREWALL_GPIO_DGSEL_CORE0:
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/* Configure permissions of gpio pins for all core domains. */
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domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM2_PRIVILEGED_BIT;
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domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM2_USER_BIT;
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domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM3_PRIVILEGED_BIT;
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domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM3_USER_BIT;
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domain_permission1 = (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM4_PRIVILEGED_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM4_USER_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM5_PRIVILEGED_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM5_USER_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM6_PRIVILEGED_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM6_USER_BIT;
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domain_permission1 |=
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((uint32_t)gpio_cfg->gpio_privileged_permission)
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<< FIREWALL_GPIO_DOM7_PRIVILEGED_BIT;
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domain_permission1 |= ((uint32_t)gpio_cfg->gpio_user_permission)
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<< FIREWALL_GPIO_DOM7_USER_BIT;
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break;
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#endif /* #ifdef FIREWALL_GPIO_DGSEL_CORE0 */
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#ifdef FIREWALL_GPIO_DGSEL_CORE1
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case FIREWALL_GPIO_DGSEL_CORE1:
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/* Configure permissions of gpio pins for all core domains. */
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domain_permission0 |=
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((uint32_t)gpio_cfg->gpio_privileged_permission)
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<< FIREWALL_GPIO_DOM2_PRIVILEGED_BIT;
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domain_permission0 |= ((uint32_t)gpio_cfg->gpio_user_permission)
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<< FIREWALL_GPIO_DOM2_USER_BIT;
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domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM3_PRIVILEGED_BIT;
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domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM3_USER_BIT;
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domain_permission1 = (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM4_PRIVILEGED_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM4_USER_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM5_PRIVILEGED_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM5_USER_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM6_PRIVILEGED_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM6_USER_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM7_PRIVILEGED_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM7_USER_BIT;
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break;
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#endif /* #ifdef FIREWALL_GPIO_DGSEL_CORE1 */
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#ifdef FIREWALL_GPIO_DGSEL_CORE2
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case FIREWALL_GPIO_DGSEL_CORE2:
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/* Configure permissions of gpio pins for all core domains. */
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domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM2_PRIVILEGED_BIT;
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domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM2_USER_BIT;
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domain_permission0 |=
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((uint32_t)gpio_cfg->gpio_privileged_permission)
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<< FIREWALL_GPIO_DOM3_PRIVILEGED_BIT;
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domain_permission0 |= ((uint32_t)gpio_cfg->gpio_user_permission)
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<< FIREWALL_GPIO_DOM3_USER_BIT;
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domain_permission1 = (uint32_t)FIREWALL_PERMISSION_NONE
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<< FIREWALL_GPIO_DOM4_PRIVILEGED_BIT;
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domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM4_USER_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM5_PRIVILEGED_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM5_USER_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM6_PRIVILEGED_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM6_USER_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM7_PRIVILEGED_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM7_USER_BIT;
|
|
break;
|
|
#endif /* #ifdef FIREWALL_GPIO_DGSEL_CORE2 */
|
|
#ifdef FIREWALL_GPIO_DGSEL_CORE3
|
|
case FIREWALL_GPIO_DGSEL_CORE3:
|
|
/* Configure permissions of gpio pins for all core domains. */
|
|
domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM2_PRIVILEGED_BIT;
|
|
domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM2_USER_BIT;
|
|
domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM3_PRIVILEGED_BIT;
|
|
domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM3_USER_BIT;
|
|
|
|
domain_permission1 =
|
|
((uint32_t)gpio_cfg->gpio_privileged_permission)
|
|
<< FIREWALL_GPIO_DOM4_PRIVILEGED_BIT;
|
|
domain_permission1 |= ((uint32_t)gpio_cfg->gpio_user_permission)
|
|
<< FIREWALL_GPIO_DOM4_USER_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM5_PRIVILEGED_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM5_USER_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM6_PRIVILEGED_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM6_USER_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM7_PRIVILEGED_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM7_USER_BIT;
|
|
break;
|
|
#endif /* #ifdef FIREWALL_GPIO_DGSEL_CORE3 */
|
|
#ifdef FIREWALL_GPIO_DGSEL_CORE4
|
|
case FIREWALL_GPIO_DGSEL_CORE4:
|
|
/* Configure permissions of gpio pins for all core domains. */
|
|
domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM2_PRIVILEGED_BIT;
|
|
domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM2_USER_BIT;
|
|
domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM3_PRIVILEGED_BIT;
|
|
domain_permission0 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM3_USER_BIT;
|
|
|
|
domain_permission1 = (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM4_PRIVILEGED_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM4_USER_BIT;
|
|
domain_permission1 |=
|
|
((uint32_t)gpio_cfg->gpio_privileged_permission)
|
|
<< FIREWALL_GPIO_DOM5_PRIVILEGED_BIT;
|
|
domain_permission1 |= ((uint32_t)gpio_cfg->gpio_user_permission)
|
|
<< FIREWALL_GPIO_DOM5_USER_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM6_PRIVILEGED_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM6_USER_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM7_PRIVILEGED_BIT;
|
|
domain_permission1 |= (uint32_t)FIREWALL_PERMISSION_NONE
|
|
<< FIREWALL_GPIO_DOM7_USER_BIT;
|
|
break;
|
|
#endif /* #ifdef FIREWALL_GPIO_DGSEL_CORE4 */
|
|
default:
|
|
{
|
|
ret_val = FIREWALL_E_GPIO_CORE_ID;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Set permission registers. */
|
|
writel(domain_permission0,
|
|
FIREWALL_APB_GPIO_SF_BASE +
|
|
FIREWALL_GPIO_DOM_PER0N_ADDR(gpio_cfg->gpio_core_id));
|
|
writel(domain_permission1,
|
|
FIREWALL_APB_GPIO_SF_BASE +
|
|
FIREWALL_GPIO_DOM_PER1N_ADDR(gpio_cfg->gpio_core_id));
|
|
#ifdef FIREWALL_APB_GPIO_AP_BASE
|
|
writel(domain_permission0,
|
|
FIREWALL_APB_GPIO_AP_BASE +
|
|
FIREWALL_GPIO_DOM_PER0N_ADDR(gpio_cfg->gpio_core_id));
|
|
writel(domain_permission1,
|
|
FIREWALL_APB_GPIO_AP_BASE +
|
|
FIREWALL_GPIO_DOM_PER1N_ADDR(gpio_cfg->gpio_core_id));
|
|
#endif /* #ifdef FIREWALL_APB_GPIO_AP_BASE */
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
/* End of file */
|