443 lines
15 KiB
C
443 lines
15 KiB
C
/**
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* @file sdrv_power.h
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* @brief SemiDrive power manager header file.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef SDRV_POWER_H_
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#define SDRV_POWER_H_
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#include <sdrv_common.h>
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#include <types.h>
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#include <regs_base.h>
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#include <part.h>
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#include "sdrv_smc.h"
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#include "sdrv_pmu.h"
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#if CONFIG_E3 || CONFIG_D3
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#define SDRV_SF_MODULE_CANFD1_MASK (0x1UL)
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#define SDRV_SF_MODULE_CANFD2_MASK (0x2UL)
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#define SDRV_SF_MODULE_CANFD3_4_MASK (0x4UL)
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#define SDRV_SF_MODULE_CANFD5_8_MASK (0x8UL)
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#define SDRV_SF_MODULE_CANFD9_16_MASK (0x10UL)
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#define SDRV_SF_MODULE_CANFD17_24_MASK (0x20UL)
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#define SDRV_SF_MODULE_XSPI1A_MASK (0x40UL)
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#define SDRV_SF_MODULE_XSPI1B_MASK (0x80UL)
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#define SDRV_SF_MODULE_XSPI2A_MASK (0x100UL)
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#define SDRV_SF_MODULE_XSPI2B_MASK (0x200UL)
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#define SDRV_SF_MODULE_DMA_MASK (0x400UL)
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#define SDRV_SF_MODULE_GAMA1_MASK (0x800UL)
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#define SDRV_SF_MODULE_GAMA2_MASK (0x1000UL)
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#define SDRV_SF_MODULE_ENET1_MASK (0x2000UL)
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#define SDRV_SF_MODULE_ENET2_MASK (0x4000UL)
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#define SDRV_SF_MODULE_VIC1_MASK (0x8000UL)
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#define SDRV_SF_MODULE_VIC2A_MASK (0x10000UL)
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#define SDRV_SF_MODULE_VIC2B_MASK (0x20000UL)
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#define SDRV_SF_MODULE_VIC3A_MASK (0x40000UL)
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#define SDRV_SF_MODULE_VIC3B_MASK (0x80000UL)
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#define SDRV_SF_MODULE_XSPI_SLV_MASK (0x100000UL)
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#define SDRV_SF_MODULE_MB_MASK (0x200000UL)
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#define SDRV_SF_MODULE_XTRG_MASK (0x400000UL)
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#define SDRV_SF_PD_MASK (0x1UL)
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#define SDRV_SP_PD_MASK (0x2UL)
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#define SDRV_SX_PD_MASK (0x4UL)
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#define SDRV_GAMA1_PD_MASK (0x8UL)
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#define SDRV_AP_DISP_PD_MASK (0x10UL)
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#endif /* #if CONFIG_E3 || CONFIG_D3 */
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#if CONFIG_E3L || CONFIG_D3L
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/* If SF_BOOT set power down in hib, Module reset below can't be mask:
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CANFD16, CANFD21, CANFD3, CANFD4, CANFD5, CANFD6, CANFD7, CANFD23
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XSPI1A, XSPI1B, DMA_RST0, DMA_RST1, ENET1, VIC1, XSPI_SLV, XTRG
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If AP_MIX set power down in hib, Module reset below can't be mask:
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SACI2, SEHC1, USB, SEIP
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*/
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#define SDRV_SF_MODULE_CANFD16_MASK (0x1UL)
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#define SDRV_SF_MODULE_CANFD21_MASK (0x2UL)
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#define SDRV_SF_MODULE_CANFD3_MASK (0x4UL)
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#define SDRV_SF_MODULE_CANFD4_MASK (0x8UL)
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#define SDRV_SF_MODULE_CANFD5_MASK (0x10UL)
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#define SDRV_SF_MODULE_CANFD6_MASK (0x20UL)
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#define SDRV_SF_MODULE_CANFD7_MASK (0x40UL)
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#define SDRV_SF_MODULE_CANFD23_MASK (0x80UL)
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#define SDRV_SF_MODULE_XSPI1A_MASK (0x100UL)
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#define SDRV_SF_MODULE_XSPI1B_MASK (0x200UL)
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#define SDRV_SF_MODULE_DMA_RST0_MASK (0x400UL)
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#define SDRV_SF_MODULE_DMA_RST1_MASK (0x800UL)
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#define SDRV_SF_MODULE_ENET1_MASK (0x1000UL)
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#define SDRV_SF_MODULE_VIC1_MASK (0x2000UL)
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#define SDRV_SF_MODULE_XSPI_SLV_MASK (0x4000UL)
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#define SDRV_SF_MODULE_XTRG_MASK (0x8000UL)
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#define SDRV_SF_MODULE_SACI2_MASK (0x10000UL)
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#define SDRV_SF_MODULE_SEHC1_MASK (0x20000UL)
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#define SDRV_SF_MODULE_USB_MASK (0x40000UL)
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#define SDRV_SF_MODULE_SEIP_MASK (0x80000UL)
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#define SDRV_SF_MODULE_CSLITE_MASK (0x100000UL)
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#define SDRV_SF_PD_MASK (0x1UL)
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#define SDRV_SF_BOOT_PD_MASK (0x2UL)
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#define SDRV_AP_MIX_PD_MASK (0x4UL)
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#endif /* #if CONFIG_E3L || CONFIG_D3L */
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#define SDRV_AP_MODULE_CSI_MASK (0x1UL)
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#define SDRV_AP_MODULE_DC_MASK (0x2UL)
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#define SDRV_AP_MODULE_G2D_MASK (0x4UL)
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#define SDRV_AP_MODULE_SDRAMC_MASK (0x8UL)
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#define SDRV_AP_MODULE_SACI1_MASK (0x10UL)
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#define SDRV_AP_MODULE_SACI2_MASK (0x20UL)
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#define SDRV_AP_MODULE_DMA_MASK (0x40UL)
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#define SDRV_AP_MODULE_SEHC1_MASK (0x80UL)
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#define SDRV_AP_MODULE_SEHC2_MASK (0x100UL)
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#define SDRV_AP_MODULE_USB_MASK (0x200UL)
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#define SDRV_AP_MODULE_SEIP_MASK (0x400UL)
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#define SDRV_AP_MODULE_LVDS_MASK (0x800UL)
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#define SDRV_PLL1_PD_MASK (0x1UL)
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#define SDRV_PLL2_PD_MASK (0x2UL)
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#define SDRV_PLL3_PD_MASK (0x4UL)
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#define SDRV_PLL4_PD_MASK (0x8UL)
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#define SDRV_PLL5_PD_MASK (0x10UL)
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#define SDRV_PLL_LVDS_PD_MASK (0x20UL)
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#define SDRV_PWR_CTRL0_PD_MASK (0x1UL)
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#define SDRV_PWR_CTRL1_PD_MASK (0x2UL)
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#define SDRV_PWR_CTRL2_PD_MASK (0x4UL)
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#define SDRV_PWR_CTRL3_PD_MASK (0x8UL)
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#define SDRV_PWR_ON0_PD_MASK (0x10UL)
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#define SDRV_PWR_ON1_PD_MASK (0x20UL)
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#define SDRV_PWR_ON2_PD_MASK (0x40UL)
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#define SDRV_PWR_ON3_PD_MASK (0x80UL)
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#define SDRV_IRAM1_PD_MASK (0x1UL)
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#define SDRV_IRAM2_PD_MASK (0x2UL)
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#define SDRV_IRAM3_PD_MASK (0x4UL)
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#define SDRV_IRAM4_PD_MASK (0x8UL)
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/**
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* @brief Power status error code.
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*/
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enum sdrv_power_error {
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SDRV_POWER_CONFIG_PARAMETER_WRONG = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_POWER, 0),
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SDRV_POWER_MODE_SET_WRONG = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_POWER, 1),
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SDRV_POWER_WAKEUP_STATUS_ERROR = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_POWER, 2),
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SDRV_POWER_IRAM_REINIT_TIMEOUT = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_POWER, 3),
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SDRV_POWER_CLOCK_SET_FAILED = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_POWER, 4),
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SDRV_POWER_AP_STATUS_ERROR = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_POWER, 5),
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SDRV_POWER_PMU_STATUS_ERROR = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_POWER, 6),
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SDRV_POWER_SMC_STATUS_ERROR = SDRV_ERROR_STATUS(SDRV_STATUS_GROUP_POWER, 7),
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};
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/**
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* @brief Definition for MCU power switch and IRAMC power.
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*/
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typedef enum mcu_power {
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MCU_POWER_SF = 0,
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MCU_POWER_SP,
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MCU_POWER_SX,
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MCU_POWER_GAMA,
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MCU_POWER_IRAM1,
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MCU_POWER_IRAM2,
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MCU_POWER_IRAM3,
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MCU_POWER_IRAM4,
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MCU_POWER_ACMP1,
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MCU_POWER_ACMP2,
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MCU_POWER_ACMP3,
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MCU_POWER_ACMP4,
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MCU_POWER_END = 0xFFFFFFFF,
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} mcu_power_e;
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/**
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* @brief Definition for wakeup source.
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*/
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typedef enum sdrv_wakeup_src {
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SDRV_WAKEUP_GPIO_SF = 0UL,
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SDRV_WAKEUP_GPIO_AP,
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SDRV_WAKEUP_RTC1,
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SDRV_WAKEUP_RTC2,
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SDRV_WAKEUP_UART1,
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SDRV_WAKEUP_UART2,
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SDRV_WAKEUP_UART3,
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SDRV_WAKEUP_UART4,
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SDRV_WAKEUP_UART5,
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SDRV_WAKEUP_UART6,
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SDRV_WAKEUP_UART7,
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SDRV_WAKEUP_UART8,
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#ifdef APB_UART9_BASE
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SDRV_WAKEUP_UART9,
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SDRV_WAKEUP_UART10,
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SDRV_WAKEUP_UART11,
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SDRV_WAKEUP_UART12,
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#endif
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#ifdef APB_UART13_BASE
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SDRV_WAKEUP_UART13,
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SDRV_WAKEUP_UART14,
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SDRV_WAKEUP_UART15,
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SDRV_WAKEUP_UART16,
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#endif
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#ifdef APB_CANFD1_BASE
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SDRV_WAKEUP_CANFD1,
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SDRV_WAKEUP_CANFD2,
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#endif
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#ifdef APB_CANFD3_BASE
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SDRV_WAKEUP_CANFD3,
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SDRV_WAKEUP_CANFD4,
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#endif
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#ifdef APB_CANFD5_BASE
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SDRV_WAKEUP_CANFD5,
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SDRV_WAKEUP_CANFD6,
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#endif
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#ifdef APB_CANFD7_BASE
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SDRV_WAKEUP_CANFD7,
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#endif
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#ifdef APB_CANFD8_BASE
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SDRV_WAKEUP_CANFD8,
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SDRV_WAKEUP_CANFD9,
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SDRV_WAKEUP_CANFD10,
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SDRV_WAKEUP_CANFD11,
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SDRV_WAKEUP_CANFD12,
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SDRV_WAKEUP_CANFD13,
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SDRV_WAKEUP_CANFD14,
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SDRV_WAKEUP_CANFD15,
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#endif
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#ifdef APB_CANFD16_BASE
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SDRV_WAKEUP_CANFD16,
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#endif
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#ifdef APB_CANFD17_BASE
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SDRV_WAKEUP_CANFD17,
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SDRV_WAKEUP_CANFD18,
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SDRV_WAKEUP_CANFD19,
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SDRV_WAKEUP_CANFD20,
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#endif
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#ifdef APB_CANFD21_BASE
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SDRV_WAKEUP_CANFD21,
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#endif
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#ifdef APB_CANFD22_BASE
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SDRV_WAKEUP_CANFD22,
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#endif
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#ifdef APB_CANFD23_BASE
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SDRV_WAKEUP_CANFD23,
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#endif
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#ifdef APB_CANFD24_BASE
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SDRV_WAKEUP_CANFD24,
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#endif
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SDRV_WAKEUP_END = 0x7FFFFFFFUL,
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} sdrv_wakeup_src_e;
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/**
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* @brief Definition for system work mode.
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*/
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typedef enum sdrv_power_mode {
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SDRV_RUN_MODE,
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SDRV_SLEEP_MODE,
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SDRV_HIBERNATE_MODE,
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SDRV_RTC_MODE,
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} sdrv_power_mode_e;
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/**
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* @brief Definition for DCDC work mode.
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*/
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typedef enum sdrv_power_dcdc_mode {
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DCDC_HP_MODE, /**< High performance mode */
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DCDC_LP_MODE, /**< Low performance mode */
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} sdrv_power_dcdc_mode_e;
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/**
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* @brief DCDC reg config, each reg has 8bit. REG0,7,8 are common config.
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* REG1~6 are separate config for HP_MODE and LP_MODE.
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*/
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typedef enum sdrv_power_dcdc_reg {
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DCDC_REG_0,
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DCDC_REG_1,
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DCDC_REG_2,
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DCDC_REG_3,
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DCDC_REG_4,
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DCDC_REG_5,
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DCDC_REG_6,
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DCDC_REG_7,
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DCDC_REG_8,
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} sdrv_power_dcdc_reg_e;
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/**
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* @brief Definition for iram.
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*/
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typedef enum sdrv_iram {
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SDRV_IRAM1 = 0,
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SDRV_IRAM2,
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SDRV_IRAM3,
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SDRV_IRAM4,
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} sdrv_iram_e;
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/**
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* @brief Definition for core clock mode.
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*/
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typedef enum sdrv_clock_mode {
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SDRV_CLOCK_NORMAL,
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SDRV_CLOCK_MEDIUM,
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SDRV_CLOCK_LOW,
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} sdrv_clock_mode_e;
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/**
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* @brief Definition for soc internal analog part power control.
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*/
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typedef struct sdrv_power_analog {
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bool vd_sf_pd; /**< Saf domain Voltage Detect IP analog */
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bool por_sf_pd; /**< Saf domain POR IP analog */
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bool rc24m_pd; /**< RC24M analog */
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bool bgr_sf_pd; /**< BGR33_SF */
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bool bgr_ana_pd; /**< BGR33_ANA */
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bool bgr_ldo_pd; /**< BGR33_LDO */
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bool analog_cven33_pd; /**< Analog IP CVEN33 power, include pt-sns, adc, acmp */
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bool vd_ap_pd; /**< AP domain Voltage Detect IP analog */
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bool por_ap_pd; /**< AP domain POR IP analog */
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bool bgr_ap_pd; /**< BGR33_AP */
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bool bgr_disp_pd; /**< BGR33_DISP */
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bool bgr_sf_auto_en; /**< Enable BGR33_SF auto power down in hibernate mode with rc_24m_disable config */
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bool bgr_ldo_auto_en; /**< Enable BGR33_LDO auto power down in hibernate mode with PMU pwron2 config */
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} sdrv_power_analog_t;
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/**
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* @brief Definition for sleep mode config.
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*/
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typedef struct sdrv_sleep_mode_config {
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sdrv_wakeup_src_e *wakeup_srcs; /**< wakeup ip list */
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uint32_t sf_module_reset_mask; /**< saf domain module not reset bitmap
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OR'ed value in macro defined SDRV_SF_MODULE_xxx
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config this if you want specific module not be reset after wakeup */
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uint32_t ap_module_reset_mask; /**< ap domain module not reset bitmap
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OR'ed value in macro defined SDRV_AP_MODULE_xxx
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config this if you want specific module not be reset after wakeup */
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uint32_t pll_pd_mask; /**< pll not power down bitmap
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OR'ed value in macro defined SDRV_PLLxxx
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config this if you want specific PLL work in sleep mode */
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bool xtal_24m_disable; /**< whether xtal 24m disable in sleep mode */
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} sdrv_sleep_mode_config_t;
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/**
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* @brief Definition for hibernate mode config.
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*/
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typedef struct sdrv_hibernate_mode_config {
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sdrv_wakeup_src_e *wakeup_srcs; /**< wakeup ip list */
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uint32_t sf_module_reset_mask; /**< saf domain module not reset bitmap
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OR'ed value in macro defined SDRV_SF_MODULE_xxx
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config this if you want specific module not be reset after wakeup */
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uint32_t ap_module_reset_mask; /**< ap domain module not reset bitmap
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OR'ed value in macro defined SDRV_AP_MODULE_xxx
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config this if you want specific module not be reset after wakeup */
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uint32_t pll_pd_mask; /**< pll not power down bitmap
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OR'ed value in macro defined SDRV_PLLxxx
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config this if you want specific PLL work in sleep mode */
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uint32_t core_pd_mask; /**< core not power down bitmap
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OR'ed value in macro pre-defined, for example, if sf keep power, you should set bit SDRV_SF_PD_MASK */
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uint32_t iram_pd_mask; /**< iram not power down bitmap
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OR'ed value in macro defined SDRV_IRAMxxx
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if iram is power down, you must reinit it after wakeup */
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bool xtal_24m_disable; /**< whether xtal 24m disable in hibernate mode */
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bool rc_24m_disable; /**< whether rc 24m disable in hibernate mode */
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bool ap_domain_powered; /**< whether AP domain keep power supply in hibernate mode */
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uint32_t regulator_pd_mask; /**< external/internal regulator not power down bitmap
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OR'ed value in macro defined SDRV_PWR_xxx */
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sdrv_power_analog_t analog_power; /**< define analog power on or off in hibernate */
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} sdrv_hibernate_mode_config_t;
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/**
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* @brief Initialize clock/reset/power config under sleep and hibernate mode.
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*
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* This function will mask all interrupts and gate all xcg clock expect for wakeup modules. It will reset all
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* modules expect that need wakeup and user defined not reset in low power mode. According to user configration,
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* config smc sleep/hibernate mode core power switch and pmu pwr ctrl/pwr on status.
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*
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* @param [in] sleep_cfg config for sleep mode
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* @param [in] hib_cfg config for hibernate mode
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* @return SDRV_STATUS_OK or error code.
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*/
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status_t sdrv_power_init(sdrv_sleep_mode_config_t *sleep_cfg,
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sdrv_hibernate_mode_config_t *hib_cfg);
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/**
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* @brief Set soc to specific power mode.
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*
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* This function config SMC enable wfi detect and excute wfi instrcut. After all core enter wfi, it will start hardware
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* operation. Before enter sleep, software config all iram to retention mode. Before enter hibernate, software power down
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* iram as pre-defined, and power down analog part. Then use SVC interrupt to save all core registers. After wakeup from
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* sleep/hibernate, it will return from this call. Iram and analog will be powered again. If call to enter RTC mode, it
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* will power down at once.
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*
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* @param [in] mode mode defined in sdrv_power_mode_e.
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* @return SDRV_STATUS_OK or error code.
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*/
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status_t sdrv_power_set_mode(sdrv_power_mode_e mode);
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/**
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* @brief Set clock mode for core and bus.
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*
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* This function config clock mode for core and bus. Normal mode use default clock settings, medium mode reduce core and bus
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* frequency to half, low mode set core and bus frequency to 24MHz.
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*
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* @param [in] mode clock mode defined in sdrv_clock_mode_e.
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* @return SDRV_STATUS_OK or error code.
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*/
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status_t sdrv_power_clock_set_mode(sdrv_clock_mode_e mode);
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/**
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* @brief Reinit specific iram.
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*
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* This function reinit specific iram. If iram is power down in hibernate, after wakeup, you need call this function before
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* use it.
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*
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* @param [in] iram iram defined in sdrv_iram_e.
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* @return SDRV_STATUS_OK or error code.
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*/
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status_t sdrv_power_iram_reinit(sdrv_iram_e iram);
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/**
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* @brief Set rom disable.
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*
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* When set rom disable, ROM code read and register access are disable until POR reset.
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*
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* @return SDRV_STATUS_OK or error code.
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*/
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status_t sdrv_power_rom_disable(void);
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/**
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* @brief USB phy power down.
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*
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* @return SDRV_STATUS_OK or error code.
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*/
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status_t sdrv_power_usb_power_down(void);
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/**
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* @brief Config DCDC REG0~8.
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*
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* @param [in] dcdc_base DCDC controller base.
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* @param [in] mode high or low performance mode.
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* @param [in] dcdc_reg DCDC_REG_0 - DCDC_REG_8.
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* @param [in] cfg_val config value.
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* @return SDRV_STATUS_OK or error code.
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*/
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status_t sdrv_power_dcdc_config(paddr_t dcdc_base, sdrv_power_dcdc_mode_e mode,
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sdrv_power_dcdc_reg_e dcdc_reg, uint8_t cfg_val);
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#endif /* SDRV_POWER_H_ */
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