296 lines
8.0 KiB
C
296 lines
8.0 KiB
C
/**
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* @file ske_basic.h
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* @brief Semidrive CRYPTO ske basic header file.
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*
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* @copyright Copyright (c) 2021 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef SKE_BASIC_H
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#define SKE_BASIC_H
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#include "register_base_addr.h"
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#include "sdrv_crypto_utility.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SUPPORT_SKE_DES
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#define SUPPORT_SKE_TDES_128
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#define SUPPORT_SKE_TDES_192
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#define SUPPORT_SKE_AES_128
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#define SUPPORT_SKE_AES_192
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#define SUPPORT_SKE_AES_256
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#define SUPPORT_SKE_SM4
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#define SUPPORT_SKE_MODE_ECB
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#define SUPPORT_SKE_MODE_CBC
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#define SUPPORT_SKE_MODE_CFB
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#define SUPPORT_SKE_MODE_OFB
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#define SUPPORT_SKE_MODE_CTR
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#define SUPPORT_SKE_MODE_XTS
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#define SUPPORT_SKE_MODE_GCM
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#define SUPPORT_SKE_MODE_CMAC
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#define SUPPORT_SKE_MODE_CBC_MAC
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#define SKE_HP_DMA_FUNCTION
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#define SKE_SECURE_PORT_FUNCTION
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#ifdef SKE_SECURE_PORT_FUNCTION
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/* if key is from secure port, the max key index(or the number of keys) */
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#define SKE_MAX_KEY_IDX (9)
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#endif
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/* some register offset */
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#define SKE_HP_REVERSE_BYTE_ORDER_IN_WORD_OFFSET (24)
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#define SKE_HP_MODE_OFFSET (28)
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#define SKE_HP_CRYPTO_OFFSET (11)
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#define SKE_HP_UP_CFG_OFFSET (12)
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#define SKE_HP_DMA_OFFSET (16)
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#define SKE_HP_DMA_LL_OFFSET (17)
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#define SKE_HP_LAST_DATA_OFFSET (16)
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/* SKE register struct */
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typedef struct ske_hp_reg {
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uint32_t ctrl; /* Offset: 0x000 (W1S) SKE Control Register */
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uint32_t cfg; /* Offset: 0x004 (R/W) SKE Config Register */
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uint32_t sr; /* Offset: 0x008 (R) SKE Status Register */
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uint32_t risr; /* Offset: 0x00C (W0C) SKE Interrupt Source Register */
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uint32_t imcr; /* Offset: 0x010 (R/W) SKE Interrupt Enable Register */
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uint32_t misr; /* Offset: 0x014 (R) SKE Interrupt Output Register */
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uint32_t rev1[1];
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uint32_t sp; /* Offset: 0x01C (R/W) SKE Secure Port Register */
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uint32_t key1[8]; /* Offset: 0x020 (R/W) Key1 */
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uint32_t key2[8]; /* Offset: 0x040 (R/W) Key2 */
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uint32_t ske_a_len_l; /* Offset: 0x060 (R/W) CCM/GCM mode AAD length low
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Register */
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uint32_t ske_a_len_h; /* Offset: 0x064 (R/W) CCM/GCM mode AAD length high
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Register */
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uint32_t ske_c_len_l; /* Offset: 0x068 (R/W) CCM/GCM/XTS mode
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plaintext/ciphertext length low Register */
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uint32_t ske_c_len_h; /* Offset: 0x06C (R/W) CCM/GCM/XTS mode
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plaintext/ciphertext length high Register */
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uint32_t iv[4]; /* Offset: 0x070 (R/W) Initial Vector */
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uint32_t m_din_cr; /* Offset: 0x080 (R/W) SKE Input Register */
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uint32_t rev3[3];
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uint32_t m_din[4]; /* Offset: 0x090 (R/W) SKE Input Register */
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uint32_t rev4[4];
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uint32_t m_dout[4]; /* Offset: 0x0B0 (R) SKE Output Register */
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uint32_t rev5[15];
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uint32_t ske_version; /* Offset: 0x0FC (R) SKE Version Register */
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uint32_t ske_seed[36]; /* Offset: 0x100 (R/W) SKE Seed Register */
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uint32_t ske_alarm; /* Offset: 0x190 (R/W) SKE Alarm Register */
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uint32_t rev6[91];
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uint32_t dma_cr; /* Offset: 0x300 (R/W) DMA Config register */
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uint32_t dma_sr; /* Offset: 0x304 (W0C) DMA Status register */
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uint32_t dma_to; /* Offset: 0x308 (R/W) DMA Timeout Threshold register */
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uint32_t rev7[1];
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uint32_t
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dma_sa_l; /* Offset: 0x310 (R/W) DMA Source Address Low part register */
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uint32_t dma_sa_h; /* Offset: 0x314 (R/W) DMA Source Address High part
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register */
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uint32_t rev8[2];
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uint32_t dma_da_l; /* Offset: 0x320 (R/W) DMA Destination Address Low part
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register */
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uint32_t dma_da_h; /* Offset: 0x324 (R/W) DMA Destination Address High part
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register */
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uint32_t rev9[2];
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uint32_t dma_rlen; /* Offset: 0x330 (R/W) DMA read Length register */
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uint32_t dma_wlen; /* Offset: 0x334 (R/W) DMA write Length register */
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uint32_t rev10[2];
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uint32_t dma_awcc; /* Offset: 0x340 (R/W) DMA AWCC register */
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uint32_t dma_arcc; /* Offset: 0x344 (R/W) DMA ARCC register */
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uint32_t dma_llp_l;
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uint32_t dma_llp_h;
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} ske_hp_reg_t;
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/* SKE Operation Mode */
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typedef enum {
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SKE_MODE_BYPASS = 0,
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#ifdef SUPPORT_SKE_MODE_ECB
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SKE_MODE_ECB = 1,
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#endif
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#ifdef SUPPORT_SKE_MODE_XTS
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SKE_MODE_XTS = 2,
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#endif
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#ifdef SUPPORT_SKE_MODE_CBC
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SKE_MODE_CBC = 3,
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#endif
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#ifdef SUPPORT_SKE_MODE_CFB
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SKE_MODE_CFB = 4,
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#endif
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#ifdef SUPPORT_SKE_MODE_OFB
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SKE_MODE_OFB = 5,
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#endif
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#ifdef SUPPORT_SKE_MODE_CTR
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SKE_MODE_CTR = 6,
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#endif
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#ifdef SUPPORT_SKE_MODE_CMAC
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SKE_MODE_CMAC = 7,
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#endif
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#ifdef SUPPORT_SKE_MODE_CBC_MAC
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SKE_MODE_CBC_MAC = 8,
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#endif
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#ifdef SUPPORT_SKE_MODE_GCM
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SKE_MODE_GCM = 9,
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#endif
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#ifdef SUPPORT_SKE_MODE_CCM
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SKE_MODE_CCM = 10,
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#endif
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} SKE_MODE;
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typedef enum {
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SKE_CRYPTO_ENCRYPT = 0,
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SKE_CRYPTO_DECRYPT,
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} SKE_CRYPTO;
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typedef enum {
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#ifdef SUPPORT_SKE_DES
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SKE_ALG_DES = 0,
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#endif
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#ifdef SUPPORT_SKE_TDES_128
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SKE_ALG_TDES_128 = 1,
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#endif
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#ifdef SUPPORT_SKE_TDES_192
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SKE_ALG_TDES_192 = 2,
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#endif
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#ifdef SUPPORT_SKE_TDES_EEE_128
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SKE_ALG_TDES_EEE_128 = 3,
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#endif
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#ifdef SUPPORT_SKE_TDES_EEE_192
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SKE_ALG_TDES_EEE_192 = 4,
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#endif
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#ifdef SUPPORT_SKE_AES_128
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SKE_ALG_AES_128 = 5,
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#endif
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#ifdef SUPPORT_SKE_AES_192
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SKE_ALG_AES_192 = 6,
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#endif
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#ifdef SUPPORT_SKE_AES_256
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SKE_ALG_AES_256 = 7,
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#endif
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#ifdef SUPPORT_SKE_SM4
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SKE_ALG_SM4 = 8,
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#endif
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} SKE_ALG;
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enum SKE_RET_CODE {
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SKE_SUCCESS = 0,
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SKE_BUFFER_NULL,
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SKE_CONFIG_INVALID,
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SKE_INPUT_INVALID,
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SKE_ATTACK_ALARM,
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SKE_ERROR,
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};
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typedef enum {
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SKE_NO_PADDING,
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SKE_ZERO_PADDING,
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} SKE_PADDING;
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typedef struct {
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uint8_t block_bytes;
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uint8_t block_words;
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} ske_ctx_t;
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typedef struct {
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uint32_t src_addr;
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uint32_t dst_addr;
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uint32_t next_llp;
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uint32_t last_len;
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} dma_ll_node_t;
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uint32_t ske_get_version(void);
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void ske_hp_set_cpu_mode(void);
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void ske_hp_set_dma_mode(void);
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void ske_hp_enable_dma_linked_list(void);
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void ske_hp_disable_dma_linked_list(void);
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void ske_hp_set_endian_uint32(void);
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void ske_hp_enable_secure_port(uint16_t sp_key_idx);
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void ske_hp_disable_secure_port(void);
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void ske_hp_set_crypto(SKE_CRYPTO crypto);
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void ske_hp_set_alg(SKE_ALG ske_alg);
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void ske_hp_set_mode(SKE_MODE mode);
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void ske_hp_set_last_block(uint32_t is_last_block);
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void ske_hp_set_last_block_len(uint32_t bytes);
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uint32_t ske_hp_set_seed(void);
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void ske_hp_start(void);
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uint32_t ske_hp_calc_wait_till_done(void);
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void ske_hp_set_key_uint32(uint32_t *key, uint32_t idx, uint32_t key_words);
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void ske_hp_set_iv_uint32(uint32_t *iv, uint32_t block_words);
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#if (defined(SUPPORT_SKE_MODE_GCM) || defined(SUPPORT_SKE_MODE_CCM))
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void ske_hp_set_aad_len_uint32(uint32_t aad_bytes);
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#endif
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#if (defined(SUPPORT_SKE_MODE_GCM) || defined(SUPPORT_SKE_MODE_CCM) || \
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defined(SUPPORT_SKE_MODE_XTS))
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void ske_hp_set_c_len_uint32(uint32_t c_bytes);
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#endif
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void ske_hp_simple_set_input_block(uint32_t *in, uint32_t block_words);
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void ske_hp_simple_get_output_block(uint32_t *out, uint32_t block_words);
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uint32_t ske_hp_expand_key(void);
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#ifdef SKE_HP_DMA_FUNCTION
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uint32_t ske_hp_dma_operate(ske_ctx_t *ctx, uint32_t *in, uint32_t *out,
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uint32_t in_words, uint32_t out_words);
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#if (defined(SUPPORT_SKE_MODE_CMAC) || defined(SUPPORT_SKE_MODE_CMAC))
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uint32_t ske_hp_dma_operate_without_output(ske_ctx_t *ctx, uint32_t *in,
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uint32_t in_words);
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#endif
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#endif
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uint32_t ske_hp_update_blocks_no_output(ske_ctx_t *ctx, uint8_t *in,
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uint32_t bytes);
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uint32_t ske_hp_update_blocks_internal(ske_ctx_t *ctx, uint8_t *in,
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uint8_t *out, uint32_t bytes);
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uint32_t ske_hp_wait_till_output();
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#ifdef __cplusplus
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}
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#endif
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#endif
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