113 lines
2.1 KiB
C
113 lines
2.1 KiB
C
/**
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* @file sdrv_adc_chmux.h
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* @brief SemiDrive ADC channel mux definition file.
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*
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* @copyright Copyright (c) 2021 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef SDRV_ADC_CHMUX_H
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#define SDRV_ADC_CHMUX_H
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enum adc1_ch5n_mux {
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ADC1_CH5N_MUX_A0 = 0u,
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ADC1_CH5N_MUX_A2,
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ADC1_CH5N_MUX_A4,
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ADC1_CH5N_MUX_A6,
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ADC1_CH5N_MUX_A8,
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ADC1_CH5N_MUX_A10,
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ADC1_CH5N_MUX_A12,
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ADC1_CH5N_MUX_A14
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};
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enum adc1_ch5p_mux {
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ADC1_CH5P_MUX_A1 = 0u,
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ADC1_CH5P_MUX_A3,
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ADC1_CH5P_MUX_A5,
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ADC1_CH5P_MUX_A7,
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ADC1_CH5P_MUX_A9,
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ADC1_CH5P_MUX_A11,
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ADC1_CH5P_MUX_A13,
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ADC1_CH5P_MUX_A15
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};
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enum adc2_ch4n_mux {
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ADC2_CH4N_MUX_A0 = 0u,
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ADC2_CH4N_MUX_A2,
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ADC2_CH4N_MUX_A4,
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ADC2_CH4N_MUX_A6,
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ADC2_CH4N_MUX_A8,
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ADC2_CH4N_MUX_A10,
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ADC2_CH4N_MUX_A12,
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ADC2_CH4N_MUX_A14
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};
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enum adc2_ch4p_mux {
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ADC2_CH4P_MUX_A1 = 0u,
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ADC2_CH4P_MUX_A3,
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ADC2_CH4P_MUX_A5,
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ADC2_CH4P_MUX_A7,
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ADC2_CH4P_MUX_A9,
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ADC2_CH4P_MUX_A11,
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ADC2_CH4P_MUX_A13,
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ADC2_CH4P_MUX_A15
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};
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enum adc2_ch5n_mux {
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ADC2_CH5N_MUX_C0 = 0u,
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ADC2_CH5N_MUX_C2,
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ADC2_CH5N_MUX_C4,
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ADC2_CH5N_MUX_C6,
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ADC2_CH5N_MUX_C8,
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ADC2_CH5N_MUX_C10,
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ADC2_CH5N_MUX_C12,
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ADC2_CH5N_MUX_C14
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};
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enum adc2_ch5p_mux {
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ADC2_CH5P_MUX_C1 = 0u,
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ADC2_CH5P_MUX_C3,
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ADC2_CH5P_MUX_C5,
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ADC2_CH5P_MUX_C7,
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ADC2_CH5P_MUX_C9,
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ADC2_CH5P_MUX_C11,
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ADC2_CH5P_MUX_C13,
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ADC2_CH5P_MUX_C15
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};
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enum adc2_ch6n_mux {
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ADC2_CH6N_MUX_B8 = 0u,
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ADC2_CH6N_MUX_B9,
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ADC2_CH6N_MUX_B10,
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ADC2_CH6N_MUX_B11,
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ADC2_CH6N_MUX_B12,
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ADC2_CH6N_MUX_B13,
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ADC2_CH6N_MUX_B14,
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ADC2_CH6N_MUX_B15
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};
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enum adc3_ch5n_mux {
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ADC3_CH5N_MUX_C0 = 0u,
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ADC3_CH5N_MUX_C2,
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ADC3_CH5N_MUX_C4,
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ADC3_CH5N_MUX_C6,
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ADC3_CH5N_MUX_C8,
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ADC3_CH5N_MUX_C10,
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ADC3_CH5N_MUX_C12,
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ADC3_CH5N_MUX_C14
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};
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enum adc3_ch5p_mux {
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ADC3_CH5P_MUX_C1 = 0u,
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ADC3_CH5P_MUX_C3,
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ADC3_CH5P_MUX_C5,
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ADC3_CH5P_MUX_C7,
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ADC3_CH5P_MUX_C9,
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ADC3_CH5P_MUX_C11,
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ADC3_CH5P_MUX_C13,
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ADC3_CH5P_MUX_C15
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};
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#endif /* SDRV_ADC_CHMUX_H */
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