dc_reg.h

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#ifndef DC_REG_H__
#define DC_REG_H__
 
/* DC registers (RMW mode) definition */
 
#define REG(x) (x)
/* CTRL */
#define DC_DC_CTRL REG(0x0)
#define DC_CTRL_SW_RST_SHIFT 31
#define DC_CTRL_SW_RST_MASK 1UL << DC_CTRL_SW_RST_SHIFT
#define DC_CTRL_UNDERRUN_CLR_MODE_SHIFT 3
#define DC_CTRL_UNDERRUN_CLR_MODE_MASK 1UL << DC_CTRL_UNDERRUN_CLR_MODE_SHIFT
#define DC_CTRL_MLC_DISCARD_MODE_SHIFT 2
#define DC_CTRL_MLC_DISCARD_MODE_MASK 1UL << DC_CTRL_MLC_DISCARD_MODE_SHIFT
#define DC_CTRL_MS_MODE_SHIFT 1
#define DC_CTRL_MS_MODE_MASK 0x1 << DC_CTRL_MS_MODE_SHIFT
#define DC_CTRL_SF_MODE_SHIFT 0
#define DC_CTRL_SF_MODE_MASK 1UL << DC_CTRL_SF_MODE_SHIFT
 
/* FLC */
#define DC_FLC_CTRL REG(0x4)
#define CRC32_TRIG_SHIFT 3
#define CRC32_TRIG_MASK 1UL << CRC32_TRIG_SHIFT
#define TCON_TRIG_SHIFT 2
#define TCON_TRIG_MASK 1UL << TCON_TRIG_SHIFT
#define DI_TRIG_SHIFT 1
#define DI_TRIG_MASK 1UL << DI_TRIG_SHIFT
#define FLC_TRIG_SHIFT 0
#define FLC_TRIG_MASK 1 << FLC_TRIG_SHIFT
 
#define DC_FLC_UPDATE REG(0x8)
#define DC_FLC_UP_FORCE_SHIFT 0
#define DC_FLC_UP_FORCE_MASK 1UL << DC_FLC_UP_FORCE_SHIFT
 
#define DC_SDMA_CTRL REG(0x10)
#define SDMA_CTRL_GAMMA_EN_SHIFT 4
#define SDMA_CTRL_GAMMA_EN_MASK 0xF << SDMA_CTRL_GAMMA_EN_SHIFT
#define SDMA_CTRL_SDMA_EN_SHIFT 0
#define SDMA_CTRL_SDMA_EN_MASK 0x1 << SDMA_CTRL_SDMA_EN_SHIFT
 
#define DC_INT_MASK REG(0x20)
#define DC_INT_STATUS REG(0x24)
#define DC_INIT_DEF_MASK 0x3FFFFFFF
 
#define RDMA_SHIFT 0
#define RDMA_MASK 1UL << RDMA_SHIFT
 
#define RLE_SHIFT 1
#define RLE_MASK 1UL << RLE_SHIFT
 
#define MLC_SHIFT 2
#define MLC_MASK 1UL << MLC_SHIFT
 
#define TCON_SOF_SHIFT 3
#define TCON_SOF_MASK 1UL << TCON_SOF_SHIFT
 
#define TCON_EOF_SHIFT 4
#define TCON_EOF_MASK 1UL << TCON_EOF_SHIFT
 
#define TCON_UNDERRUN_SHIFT 5
#define TCON_UNDERRUN_MASK 1UL << TCON_UNDERRUN_SHIFT
 
#define DC_UNDERRUN_SHIFT 6
#define DC_UNDERRUN_MASK 1UL << DC_UNDERRUN_SHIFT
 
#define SDMA_DONE_SHIFT 7
#define SDMA_DONE_MASK 1UL << SDMA_DONE_SHIFT
 
#define TCON_LAYER_KICK_SHIFT 8
#define TCON_LAYER_KICK_MASK 0xFFFFF << TCON_LAYER_KICK_SHIFT
 
#define CSI_TIMING_DECT_DONE_SHIFT 28
#define CSI_TIMING_DECT_DONE_MASK 1UL << CSI_TIMING_DECT_DONE_SHIFT
 
#define CSI_TCON_VSYNC_DLY_DONE_SHIFT 29
#define CSI_TCON_VSYNC_DLY_DONE_MASK 1UL << CSI_TCON_VSYNC_DLY_DONE_SHIFT
 
#define DC_SF_FLC_CTRL REG(0x100)
#define DC_SF_INT_MASK REG(0x120)
#define DC_SF_INT_STATUS REG(0x124)
/* offset definition see DC_FLC_xxx */
 
/* RDMA */
#define RDMA_CHN_JMP 0x20
#define RDMA_CHN_COUNT 4
#define DC_RDMA_DFIFO_WML_(i) (REG(0x1000) + RDMA_CHN_JMP * (i))
#define RDMA_DFIFO_WML_SHIFT 0
#define RDMA_DFIFO_WML_MASK (0xFFFF << RDMA_DFIFO_WML_SHIFT)
 
#define DC_RDMA_DFIFO_DEPTH_(i) (REG(0x1004) + RDMA_CHN_JMP * (i))
#define RDMA_DFIFO_DEPTH_SHIFT 0
#define RDMA_DFIFO_DEPTH_MASK (0xFFFF << RDMA_DFIFO_DEPTH_SHIFT)
 
#define DC_RDMA_CFIFO_DEPTH_(i) (REG(0x1008) + RDMA_CHN_JMP * (i))
#define RDMA_CFIFO_DEPTH_SHIFT 0
#define RDMA_CFIFO_DEPTH_MASK (0xFFFF << RDMA_DFIFO_DEPTH_SHIFT)
 
#define DC_RDMA_CH_PRIO_(i) (REG(0x100c) + RDMA_CHN_JMP * (i))
#define RDMA_CH_PRIO_SCHE_SHIFT 16
#define RDMA_CH_PRIO_SCHE_MASK 0x3f << RDMA_CH_PRIO_SCHE_SHIFT
#define RDMA_CH_PRIO_P1_SHIFT 8
#define RDMA_CH_PRIO_P1_MASK 0x3f << RDMA_CH_PRIO_P1_SHIFT
#define RDMA_CH_PRIO_P0_SHIFT 0
#define RDMA_CH_PRIO_P0_MASK 0x3f << RDMA_CH_PRIO_P0_SHIFT
 
#define DC_RDMA_BURST_(i) (REG(0x1010) + RDMA_CHN_JMP * (i))
#define RDMA_BURST_MODE_SHIFT 3
#define RDMA_BURST_MODE_MASK 0x1UL << RDMA_BURST_MODE_SHIFT
#define RDMA_BURST_LEN_SHIFT 0
#define RDMA_BURST_LEN_MASK 0x7UL << RDMA_BURST_LEN_SHIFT
 
#define DC_RDMA_AXI_USER_(i) (REG(0x1014) + RDMA_CHN_JMP * (i))
#define RDMA_AXI_USER_SHIFT 0
#define RDMA_AXI_USER_MASK 0xFFFFF << RDMA_AXI_USER_SHIFT
 
#define DC_RDMA_AXI_CTRL_(i) (REG(0x1018) + RDMA_CHN_JMP * (i))
#define RDMA_AXI_CTRL_PORT_SHIFT 4
#define RDMA_AXI_CTRL_PORT_MASK 0x3 << RDMA_AXI_CTRL_PORT_SHIFT
#define RDMA_AXI_CTRL_CACHE_SHIFT 0
#define RDMA_AXI_CTRL_CACHE_MASK 0xF << RDMA_AXI_CTRL_CACHE_SHIFT
 
#define DC_RDMA_PRES_WML_(i) (REG(0x101c) + RDMA_CHN_JMP * (i))
#define RDMA_PRES_REQ_INTERVAL_SHIFT 16
#define RDMA_PRES_REQ_INTERVAL_MASK 0x3FF << RDMA_PRES_REQ_INTERVAL_SHIFT
#define RDMA_PRES_WML_DOWN_SHIFT 4
#define RDMA_PRES_WML_DOWN_MASK 0x7 << RDMA_PRES_WML_DOWN_SHIFT
#define RDMA_PRES_WML_UP_SHIFT 0
#define RDMA_PRES_WML_UP_MASK 0x7 << RDMA_PRES_WML_UP_SHIFT
 
#define DC_RDMA_CTRL REG(0x1100)
#define RDMA_CTRL_CFG_LOAD_SHIFT 1
#define RDMA_CTRL_CFG_LOAD_MASK 0x1UL << RDMA_CTRL_CFG_LOAD_SHIFT
#define RDMA_CTRL_ARB_SEL_SHIFT 0
#define RDMA_CTRL_ARB_SEL_MASK 0x1UL << RDMA_CTRL_ARB_SEL_SHIFT
 
#define DC_RDMA_DFIFO_FULL REG(0x1200)
#define DC_RDMA_DFIFO_EMPTY REG(0x1204)
#define DC_RDMA_CFIFO_FULL REG(0x1208)
#define DC_RDMA_CFIFO_EMPTY REG(0x120c)
#define DC_RDMA_CH_IDLE REG(0x1210)
#define DC_RDMA_INT_MASK REG(0x1220)
#define DC_RDMA_INT_STATUS REG(0x1224)
#define RDMA_INT_DEF_MASK 0x7F
#define RDMA_CH_6_SHIFT 6
#define RDMA_CH_6_MASK 1UL << RDMA_CH_6_SHIFT
#define RDMA_CH_5_SHIFT 5
#define RDMA_CH_5_MASK 1UL << RDMA_CH_5_SHIFT
#define RDMA_CH_4_SHIFT 4
#define RDMA_CH_4_MASK 1UL << RDMA_CH_4_SHIFT
#define RDMA_CH_3_SHIFT 3
#define RDMA_CH_3_MASK 1UL << RDMA_CH_3_SHIFT
#define RDMA_CH_2_SHIFT 2
#define RDMA_CH_2_MASK 1UL << RDMA_CH_2_SHIFT
#define RDMA_CH_1_SHIFT 1
#define RDMA_CH_1_MASK 1UL << RDMA_CH_1_SHIFT
#define RDMA_CH_0_SHIFT 0
#define RDMA_CH_0_MASK 1UL << RDMA_CH_0_SHIFT
 
#define DC_RDMA_DEBUG_CTRL REG(0x1240)
#define RDMA_SEL_SHIFT 0
#define RDMA_SEL_MASK 0xF << RDMA_SEL_SHIFT
#define DC_RDMA_DEBUG_STA REG(0x1244)
#define RDMA_CFIFO_DEP_SHIFT 16
#define RDMA_CFIFO_DEP_MASK 0xFFFF << RDMA_CFIFO_DEP_SHIFT
#define RDMA_DFIFO_DEP_SHIFT 0
#define RDMA_DFIFO_DEP_MASK 0xFFFF << RDMA_DFIFO_DEP_SHIFT
 
#define S_RDMA_DFIFO_WML_(i) (REG(0x1400) + RDMA_CHN_JMP * (i))
#define S_RDMA_DFIFO_DEPTH_(i) (REG(0x1404) + RDMA_CHN_JMP * (i))
#define S_RDMA_CFIFO_DEPTH_(i) (REG(0x1408) + RDMA_CHN_JMP * (i))
#define S_RDMA_CH_PRIO_(i) (REG(0x140c) + RDMA_CHN_JMP * (i))
#define S_RDMA_BURST_(i) (REG(0x1410) + RDMA_CHN_JMP * (i))
#define S_RDMA_AXI_USER_(i) (REG(0x1414) + RDMA_CHN_JMP * (i))
#define S_RDMA_AXI_CTRL_(i) (REG(0x1418) + RDMA_CHN_JMP * (i))
#define S_RDMA_PRES_WML_(i) (REG(0x141c) + RDMA_CHN_JMP * (i))
#define S_RDMA_CTRL REG(0x1500)
#define S_RDMA_DFIFO_FULL REG(0x1600)
#define S_RDMA_DFIFO_EMPTY REG(0x1604)
#define S_RDMA_CFIFO_FULL REG(0x1608)
#define S_RDMA_CFIFO_EMPTY REG(0x160c)
#define S_RDMA_CH_IDLE REG(0x1610)
#define S_RDMA_INT_MASK REG(0x1620)
#define S_RDMA_INT_STATUS REG(0x1624)
#define S_RDMA_DEBUG_CTRL REG(0x1640)
#define S_RDMA_DEBUG_STA REG(0x1644)
 
/* GP */
#define DC_GP_PIX_COMP REG(0x2000)
#define BPV_SHIFT 24
#define BPV_MASK 0xF << BPV_SHIFT
#define BPU_SHIFT 16
#define BPU_MASK 0xF << BPU_SHIFT
#define BPY_SHIFT 8
#define BPY_MASK 0x1F << BPY_SHIFT
#define BPA_SHIFT 0
#define BPA_MASK 0xF << BPA_SHIFT
 
#define DC_GP_FRM_CTRL REG(0x2004)
#define ENDIAN_CTRL_SHIFT 16
#define ENDIAN_CTRL_MASK 0x7 << ENDIAN_CTRL_SHIFT
#define COMP_SWAP_SHIFT 12
#define COMP_SWAP_MASK 0xF << COMP_SWAP_SHIFT
#define ROT_SHIFT 8
#define ROT_MASK 0x7 << ROT_SHIFT
#define RGB_YUV_SHIFT 7
#define RGB_YUV_MASK 1UL << RGB_YUV_SHIFT
#define UV_SWAP_SHIFT 6
#define UV_SWAP_MASK 1 << UV_SWAP_SHIFT
#define UV_MODE_SHIFT 4
#define UV_MODE_MASK 0x3 << UV_MODE_SHIFT
#define MODE_MODE_SHIFT 2
#define MODE_MODE_MASK 0x3 << MODE_MODE_SHIFT
#define FMT_SHIFT 0
#define FMT_MASK 0x3 << FMT_SHIFT
 
#define DC_GP_FRM_SIZE REG(0x2008)
#define FRM_HEIGHT_SHIFT 16
#define FRM_HEIGHT_MASK (unsigned int)0xFFFF << FRM_HEIGHT_SHIFT
#define FRM_WIDTH_SHIFT 0
#define FRM_WIDTH_MASK 0xFFFF << FRM_WIDTH_SHIFT
 
#define DC_GP_Y_BADDR_L REG(0x200c)
#define BADDR_L_Y_SHIFT 0
#define BADDR_L_Y_MASK 0xFFFFFFFF << BADDR_L_Y_SHIFT
 
#define DC_GP_Y_BADDR_H REG(0x2010)
#define BADDR_H_Y_SHIFT 0
#define BADDR_H_Y_MASK 0xFF << BADDR_H_Y_SHIFT
 
#define DC_GP_U_BADDR_L REG(0x2014)
#define BADDR_L_U_SHIFT 0
#define BADDR_L_U_MASK 0xFFFFFFFF << BADDR_L_U_SHIFT
 
#define DC_GP_U_BADDR_H REG(0x2018)
#define BADDR_H_U_SHIFT 0
#define BADDR_H_U_MASK 0xFF << BADDR_H_U_SHIFT
 
#define DC_GP_V_BADDR_L REG(0x201c)
#define BADDR_L_V_SHIFT 0
#define BADDR_L_V_MASK 0xFFFFFFFF << BADDR_L_V_SHIFT
 
#define DC_GP_V_BADDR_H REG(0x2020)
#define BADDR_H_V_SHIFT 0
#define BADDR_H_V_MASK 0xFF << BADDR_H_V_SHIFT
 
#define DC_GP_Y_STRIDE REG(0x202c)
#define STRIDE_Y_SHIFT 0
#define STRIDE_Y_MASK 0x3FFFFUL << STRIDE_Y_SHIFT
 
#define DC_GP_U_STRIDE REG(0x2030)
#define STRIDE_U_SHIFT 0
#define STRIDE_U_MASK 0x3FFFFUL << STRIDE_U_SHIFT
 
#define DC_GP_V_STRIDE REG(0x2034)
#define STRIDE_V_SHIFT 0
#define STRIDE_V_MASK 0x3FFFFUL << STRIDE_V_SHIFT
 
#define DC_GP_FRM_OFFSET REG(0x2040)
#define FRM_Y_SHIFT 16
#define FRM_Y_MASK 0xFFFFUL << FRM_Y_SHIFT
#define FRM_X_SHIFT 0
#define FRM_X_MASK 0xFFFFUL << FRM_X_SHIFT
 
#define DC_GP_YUVUP_CTRL REG(0x2044)
#define DC_GP_YUVUP_EN_SHIFT 31
#define DC_GP_YUVUP_EN_MASK (unsigned int)0x1 << DC_GP_YUVUP_EN_SHIFT
#define DC_GP_YUVUP_VOFSET_SHIFT 6
#define DC_GP_YUVUP_VOFSET_MASK 0x3 << DC_GP_YUVUP_VOFSET_SHIFT
#define DC_GP_YUVUP_HOFSET_SHIFT 4
#define DC_GP_YUVUP_HOFSET_MASK 0x3 << DC_GP_YUVUP_HOFSET_SHIFT
#define DC_GP_YUVUP_FILTER_MODE_SHIFT 3
#define DC_GP_YUVUP_FILTER_MODE_MASK 0x1 << DC_GP_YUVUP_FILTER_MODE_SHIFT
#define DC_GP_YUVUP_UPV_BYPASS_SHIFT 2
#define DC_GP_YUVUP_UPV_BYPASS_MASK 0x1 << DC_GP_YUVUP_UPV_BYPASS_SHIFT
#define DC_GP_YUVUP_UPH_BYPASS_SHIFT 1
#define DC_GP_YUVUP_UPH_BYPASS_MASK 0x1 << DC_GP_YUVUP_UPH_BYPASS_SHIFT
#define DC_GP_YUVUP_BYPASS_SHIFT 0
#define DC_GP_YUVUP_BYPASS_MASK 0x1 << DC_GP_YUVUP_BYPASS_SHIFT
 
/* GP CSC */
#define DC_GP_CSC_CTRL REG(0x2200)
#define GP_CSC_ALPHA_SHIFT 2
#define GP_CSC_ALPHA_MASK 0x1 << GP_CSC_ALPHA_SHIFT
#define GP_CSC_SBUP_CONV_SHIFT 1
#define GP_CSC_SBUP_CONV_MASK 0x1 << GP_CSC_SBUP_CONV_SHIFT
#define GP_CSC_BYPASS_SHIFT 0
#define GP_CSC_BYPASS_MASK 0x1 << GP_CSC_BYPASS_SHIFT
 
#define DC_GP_CSC_COEF1 REG(0x2204)
#define GP_CSC_COEF1_A01_SHIFT 16
#define GP_CSC_COEF1_A01_MASK 0x3FFF << GP_CSC_COEF1_A01_SHIFT
#define GP_CSC_COEF1_A00_SHIFT 0
#define GP_CSC_COEF1_A00_MASK 0x3FFF << GP_CSC_COEF1_A00_SHIFT
 
#define DC_GP_CSC_COEF2 REG(0x2208)
#define GP_CSC_COEF2_A10_SHIFT 16
#define GP_CSC_COEF2_A10_MASK 0x3FFF << GP_CSC_COEF2_A10_SHIFT
#define GP_CSC_COEF2_A02_SHIFT 0
#define GP_CSC_COEF2_A02_MASK 0x3FFF << GP_CSC_COEF2_A02_SHIFT
 
#define DC_GP_CSC_COEF3 REG(0x220c)
#define GP_CSC_COEF3_A12_SHIFT 16
#define GP_CSC_COEF3_A12_MASK 0x3FFF << GP_CSC_COEF3_A12_SHIFT
#define GP_CSC_COEF3_A11_SHIFT 0
#define GP_CSC_COEF3_A11_MASK 0x3FFF << GP_CSC_COEF3_A11_SHIFT
 
#define DC_GP_CSC_COEF4 REG(0x2210)
#define GP_CSC_COEF4_A21_SHIFT 16
#define GP_CSC_COEF4_A21_MASK 0x3FFF << GP_CSC_COEF4_A21_SHIFT
#define GP_CSC_COEF4_A20_SHIFT 0
#define GP_CSC_COEF4_A20_MASK 0x3FFF << GP_CSC_COEF4_A20_SHIFT
 
#define DC_GP_CSC_COEF5 REG(0x2214)
#define GP_CSC_COEF5_B0_SHIFT 16
#define GP_CSC_COEF5_B0_MASK 0x3FFF << GP_CSC_COEF5_B0_SHIFT
#define GP_CSC_COEF5_A22_SHIFT 0
#define GP_CSC_COEF5_A22_MASK 0x3FFF << GP_CSC_COEF5_A22_SHIFT
 
#define DC_GP_CSC_COEF6 REG(0x2218)
#define GP_CSC_COEF6_B2_SHIFT 16
#define GP_CSC_COEF6_B2_MASK 0x3FFF << GP_CSC_COEF6_B2_SHIFT
#define GP_CSC_COEF6_B1_SHIFT 0
#define GP_CSC_COEF6_B1_MASK 0x3FFF << GP_CSC_COEF6_B1_SHIFT
 
#define DC_GP_CSC_COEF7 REG(0x221c)
#define GP_CSC_COEF7_C1_SHIFT 16
#define GP_CSC_COEF7_C1_MASK 0x3FF << GP_CSC_COEF7_C1_SHIFT
#define GP_CSC_COEF7_C0_SHIFT 0
#define GP_CSC_COEF7_C0_MASK 0x3FF << GP_CSC_COEF7_C0_SHIFT
 
#define DC_GP_CSC_COEF8 REG(0x2220)
#define GP_CSC_COEF8_C2_SHIFT 0
#define GP_CSC_COEF8_C2_MASK 0x3FF << GP_CSC_COEF8_C2_SHIFT
 
/* GP HSDK */
#define DC_GP_HSDK_CTRL REG(0x2d00)
#define GP_HSDK_MODE_SHIFT 1
#define GP_HSDK_MODE_MASK 3 << GP_HSDK_MODE_SHIFT
#define GP_HSDK_EN_SHIFT 0
#define GP_HSDK_EN_MASK 1 << GP_HSDK_EN_SHIFT
 
#define DC_GP_HSDK_STATUS REG(0x2d04)
#define GP_HSDK_Y_RDY_1_SHIFT 3
#define GP_HSDK_Y_RDY_1_MASK 1 << GP_HSDK_Y_RDY_1_SHIFT
#define GP_HSDK_Y_RDY_0_SHIFT 0
#define GP_HSDK_Y_RDY_0_MASK 1 << GP_HSDK_Y_RDY_0_SHIFT
 
/* GP RST */
#define DC_GP_SW_RST REG(0x2e00)
#define GP_SW_RST_SHIFT 0
#define GP_SW_RST_MASK 1 << GP_SW_RST_SHIFT
 
/* GP SDW */
#define DC_GP_SDW_CTRL REG(0x2f00)
#define GP_SDW_CTRL_TRIG_SHIFT 0
#define GP_SDW_CTRL_TRIG_MASK 1 << GP_SDW_CTRL_TRIG_SHIFT
 
/* SP */
#define SP_JMP 0x1000
#define SP_COUNT 2 // One is normal SP, Other one is S_SP
 
/* SHIFT MASK define see DC_GP_XX area */
#define DC_SP_PIX_COMP_(i) (REG(0x5000) + SP_JMP * i)
#define DC_SP_FRM_CTRL_(i) (REG(0x5004) + SP_JMP * i)
#define DC_SP_FRM_SIZE_(i) (REG(0x5008) + SP_JMP * i)
#define DC_SP_Y_BADDR_L_(i) (REG(0x500c) + SP_JMP * i)
#define DC_SP_Y_BADDR_H_(i) (REG(0x5010) + SP_JMP * i)
#define DC_SP_Y_STRIDE_(i) (REG(0x502c) + SP_JMP * i)
 
#define DC_SP_FRM_OFFSET_(i) (REG(0x5040) + SP_JMP * i)
 
/* RLE */
#define DC_RLE_Y_LEN_(i) (REG(0x5100) + SP_JMP * i)
#define RLE_Y_LEN_Y_SHIFT 0
#define RLE_Y_LEN_Y_MASK 0xFFFFFF << RLE_Y_LEN_Y_SHIFT
 
#define DC_RLE_Y_CHECK_SUM_(i) (REG(0x5110) + SP_JMP * i)
#define RLE_Y_CHECK_SUM_Y_SHIFT 0
#define RLE_Y_CHECK_SUM_Y_MASK 0xFFFFFFFF << RLE_Y_CHECK_SUM_Y_SHIFT
 
#define DC_RLE_CTRL_(i) (REG(0x5120) + SP_JMP * i)
#define RLE_DATA_SIZE_SHIFT 1
#define RLE_DATA_SIZE_MASK 0x3 << RLE_DATA_SIZE_SHIFT
#define RLE_EN_SHIFT 0
#define RLE_EN_MASK 0x1 << RLE_EN_SHIFT
 
#define DC_RLE_Y_CHECK_SUM_ST_(i) (REG(0x5130) + SP_JMP * i)
#define DC_RLE_U_CHECK_SUM_ST_(i) (REG(0x5134) + SP_JMP * i)
#define DC_RLE_V_CHECK_SUM_ST_(i) (REG(0x5138) + SP_JMP * i)
#define DC_RLE_A_CHECK_SUM_ST_(i) (REG(0x513c) + SP_JMP * i)
 
#define DC_RLE_INT_MASK_(i) (REG(0x5140) + SP_JMP * i)
#define DC_RLE_INT_STATUS_(i) (REG(0x5144) + SP_JMP * i)
#define DC_RLE_INT_V_ERR_SHIFT 3
#define DC_RLE_INT_V_ERR_MASK 0x1 << RLE_INT_V_ERR_SHIFT
#define DC_RLE_INT_U_ERR_SHIFT 2
#define DC_RLE_INT_U_ERR_MASK 0x1 << RLE_INT_U_ERR_SHIFT
#define DC_RLE_INT_Y_ERR_SHIFT 1
#define DC_RLE_INT_Y_ERR_MASK 0x1 << RLE_INT_Y_ERR_SHIFT
#define DC_RLE_INT_A_ERR_SHIFT 0
#define DC_RLE_INT_A_ERR_MASK 0x1 << RLE_INT_A_ERR_SHIFT
 
/* CLUT */
#define DC_CLUT_A_CTRL_(i) (REG(0x5200) + SP_JMP * i)
#define CLUT_HAS_ALPHA_SHIFT 18
#define CLUT_HAS_ALPHA_MASK 0x1 << CLUT_HAS_ALPHA_SHIFT
#define CLUT_A_Y_SEL_SHIFT 17
#define CLUT_A_Y_SEL_MASK 0x1 << CLUT_A_Y_SEL_SHIFT
#define CLUT_A_BYPASS_SHIFT 16
#define CLUT_A_BYPASS_MASK 0x1 << CLUT_A_BYPASS_SHIFT
#define CLUT_A_OFFSET_SHIFT 8
#define CLUT_A_OFFSET_MASK 0xFF << CLUT_A_OFFSET_SHIFT
#define CLUT_A_DEPTH_SHIFT 0
#define CLUT_A_DEPTH_MASK 0xF << CLUT_A_DEPTH_SHIFT
 
#define DC_CLUT_Y_CTRL_(i) (REG(0x5204) + SP_JMP * i)
#define CLUT_Y_BYPASS_SHIFT 16
#define CLUT_Y_BYPASS_MASK 0x1 << CLUT_Y_BYPASS_SHIFT
#define CLUT_Y_OFFSET_SHIFT 8
#define CLUT_Y_OFFSET_MASK 0xFF << CLUT_Y_OFFSET_SHIFT
#define CLUT_Y_DEPTH_SHIFT 0
#define CLUT_Y_DEPTH_MASK 0xF << CLUT_Y_DEPTH_SHIFT
 
#define DC_CLUT_U_CTRL_(i) (REG(0x5208) + SP_JMP * i)
#define CLUT_U_Y_SEL_SHIFT 17
#define CLUT_U_Y_SEL_MASK 0x1 << CLUT_U_Y_SEL_SHIFT
#define CLUT_U_BYPASS_SHIFT 16
#define CLUT_U_BYPASS_MASK 0x1 << CLUT_U_BYPASS_SHIFT
#define CLUT_U_OFFSET_SHIFT 8
#define CLUT_U_OFFSET_MASK 0xFF << CLUT_U_OFFSET_SHIFT
#define CLUT_U_DEPTH_SHIFT 0
#define CLUT_U_DEPTH_MASK 0xF << CLUT_U_DEPTH_SHIFT
 
#define DC_CLUT_V_CTRL_(i) (REG(0x520c) + SP_JMP * i)
#define CLUT_V_Y_SEL_SHIFT 17
#define CLUT_V_Y_SEL_MASK 0x1 << CLUT_V_Y_SEL_SHIFT
#define CLUT_V_BYPASS_SHIFT 16
#define CLUT_V_BYPASS_MASK 0x1 << CLUT_V_BYPASS_SHIFT
#define CLUT_V_OFFSET_SHIFT 8
#define CLUT_V_OFFSET_MASK 0xFF << CLUT_V_OFFSET_SHIFT
#define CLUT_V_DEPTH_SHIFT 0
#define CLUT_V_DEPTH_MASK 0xF << CLUT_V_DEPTH_SHIFT
 
#define DC_CLUT_READ_CTRL_(i) (REG(0x5210) + SP_JMP * i)
#define CLUT_APB_SEL_SHIFT 0
#define CLUT_APB_SEL_MASK 0x1 << CLUT_APB_SEL_SHIFT
 
#define DC_CLUT_BADDRL_(i) (REG(0x5214) + SP_JMP * i)
#define CLUT_BADDRL_SHIFT 0
#define CLIT_BADDRL_MASK 0xFFFFFFFF << CLUT_BADDRL_SHIFT
 
#define DC_CLUT_BADDRH_(i) (REG(0x5218) + SP_JMP * i)
#define CLUT_BADDRH_SHIFT 0
#define CLIT_BADDRH_MASK 0xFF << CLUT_BADDRH_SHIFT
 
#define DC_CLUT_LOAD_CTRL_(i) (REG(0x521c) + SP_JMP * i)
#define CLUT_LOAD_CTRL_EN_SHIFT 0
#define CLUT_LOAD_CTRL_EN_MASK 1 << CLUT_LOAD_CTRL_EN_SHIFT
 
/* SP RST */
#define DC_SP_SW_RST_(i) (REG(0x5e00) + SP_JMP * i)
#define SP_SW_RST_SHIFT 0
#define SP_SW_RST_MASK 1 << SP_SW_RST_SHIFT
 
/* SP_SDW_CTRL */
#define DC_SP_SDW_CTRL_(i) (REG(0x5f00) + SP_JMP * i)
#define SP_SDW_CTRL_TRIG_SHIFT 0
#define SP_SDW_CTRL_TRIG_MASK 0x1 << SP_SDW_CTRL_TRIG_SHIFT
 
/* MLC */
#define MLC_LAYER_JMP 0x30
#define MLC_LAYER_COUNT 4
#define MLC_PATH_JMP 0x4
#define MLC_PATH_COUNT 5
 
#define DC_MLC_SF_CTRL_(i) (REG(0x7000) + MLC_LAYER_JMP * (i))
#define MLC_SF_PROT_VAL_SHIFT 8
#define MLC_SF_PROT_VAL_MASK 0x3F << MLC_SF_PROT_VAL_SHIFT
#define MLC_SF_VPOS_PROT_EN_SHIFT 7
#define MLC_SF_VPOS_PROT_EN_MASK 0x1 << MLC_SF_VPOS_PROT_EN_SHIFT
#define MLC_SF_SLOWDOWN_EN_SHIFT 6
#define MLC_SF_SLOWDOWN_EN_MASK 0x1 << MLC_SF_SLOWDOWN_EN_SHIFT
#define MLC_SF_AFLU_PSEL_SHIFT 5
#define MLC_SF_AFLU_PSEL_MASK 0x1 << MLC_SF_AFLU_PSEL_SHIFT
#define MLC_SF_AFLU_EN_SHIFT 4
#define MLC_SF_AFLU_EN_MASK 0x1 << MLC_SF_AFLU_EN_SHIFT
#define MLC_SF_CKEY_EN_SHIFT 3
#define MLC_SF_CKEY_EN_MASK 0x1 << MLC_SF_CKEY_EN_SHIFT
#define MLC_SF_G_ALPHA_EN_SHIFT 2
#define MLC_SF_G_ALPHA_EN_MASK 0x1 << MLC_SF_G_ALPHA_EN_SHIFT
#define MLC_SF_CROP_EN_SHIFT 1
#define MLC_SF_CROP_EN_MASK 0x1 << MLC_SF_CROP_EN_SHIFT
#define MLC_SF_EN_SHIFT 0
#define MLC_SF_EN_MASK 0x1 << MLC_SF_EN_SHIFT
 
#define DC_MLC_SF_H_SPOS_(i) (REG(0x7004) + MLC_LAYER_JMP * (i))
#define MLC_SF_H_SPOS_H_SHIFT 0
#define MLC_SF_H_SPOS_H_MASK 0x1FFFF << MLC_SF_H_SPOS_H_SHIFT
 
#define DC_MLC_SF_V_SPOS_(i) (REG(0x7008) + MLC_LAYER_JMP * (i))
#define MLC_SF_V_SPOS_V_SHIFT 0
#define MLC_SF_V_SPOS_V_MASK 0x1FFFF << MLC_SF_V_SPOS_V_SHIFT
 
#define DC_MLC_SF_SIZE_(i) (REG(0x700c) + MLC_LAYER_JMP * (i))
#define MLC_SF_SIZE_V_SHIFT 16
#define MLC_SF_SIZE_V_MASK 0xFFFF << MLC_SF_SIZE_V_SHIFT
#define MLC_SF_SIZE_H_SHIFT 0
#define MLC_SF_SIZE_H_MASK 0xFFFF << MLC_SF_SIZE_H_SHIFT
 
#define DC_MLC_SF_CROP_H_POS_(i) (REG(0x7010) + MLC_LAYER_JMP * (i))
#define DC_MLC_SF_CROP_V_POS_(i) (REG(0x7014) + MLC_LAYER_JMP * (i))
#define MLC_SF_CROP_END_SHIFT 16
#define MLC_SF_CROP_END_MASK 0xFFFF << MLC_SF_CROP_END_SHIFT
#define MLC_SF_CROP_START_SHIFT 0
#define MLC_SF_CROP_START_MASK 0xFFFF << MLC_SF_CROP_START_SHIFT
 
#define DC_MLC_SF_G_ALPHA_(i) (REG(0x7018) + MLC_LAYER_JMP * (i))
#define MLC_SF_G_ALPHA_A_SHIFT 0
#define MLC_SF_G_ALPHA_A_MASK 0xFF << MLC_SF_G_ALPHA_A_SHIFT
 
#define DC_MLC_SF_CKEY_ALPHA_(i) (REG(0x701c) + MLC_LAYER_JMP * (i))
#define MLC_SF_CKEY_ALPHA_A_SHIFT 0
#define MLC_SF_CKEY_ALPHA_A_MASK 0xFF << MLC_SF_CKEY_ALPHA_A_SHIFT
 
#define DC_MLC_SF_CKEY_R_LV_(i) (REG(0x7020) + MLC_LAYER_JMP * (i))
#define DC_MLC_SF_CKEY_G_LV_(i) (REG(0x7024) + MLC_LAYER_JMP * (i))
#define DC_MLC_SF_CKEY_B_LV_(i) (REG(0x7028) + MLC_LAYER_JMP * (i))
#define MLC_SF_CKEY_LV_UP_SHIFT 16
#define MLC_SF_CKEY_LV_UP_MASK 0x3FF << MLC_SF_CKEY_LV_UP_SHIFT
#define MLC_SF_CKEY_LV_DN_SHIFT 0
#define MLC_SF_CKEY_LV_DN_MASK 0x3FF << MLC_SF_CKEY_LV_DN_SHIFT
 
#define DC_MLC_SF_AFLU_TIME_(i) (REG(0x702c) + MLC_LAYER_JMP * (i))
#define MLC_SF_AFLU_TIMER_SHIFT 0
#define MLC_SF_AFLU_TIMER_MASK 0xFFFFFFFF << MLC_SF_AFLU_TIMER_SHIFT
 
#define DC_MLC_PATH_CTRL_(i) (REG(0x7200) + MLC_PATH_JMP * (i))
#define ALPHA_BLD_IDX_SHIFT 16
#define ALPHA_BLD_IDX_MASK 0xF << ALPHA_BLD_IDX_SHIFT
#define LAYER_OUT_IDX_SHIFT 0
#define LAYER_OUT_IDX_MASK 0xF << LAYER_OUT_IDX_SHIFT
 
#define DC_MLC_BG_CTRL REG(0x7220)
#define BG_A_SHIFT 8
#define BG_A_MASK 0xFF << BG_A_SHIFT
#define AFLU_EN_SHIFT 7
#define AFLU_EN_MASK 0x1 << AFLU_EN_SHIFT
#define FSTART_SEL_SHIFT 4
#define FSTART_SEL_MASK 0x7 << FSTART_SEL_SHIFT
#define BG_A_SEL_SHIFT 2
#define BG_A_SEL_MASK 0x1 << BG_A_SEL_SHIFT
#define BG_EN_SHIFT 1
#define BG_EN_MASK 0x1 << BG_EN_SHIFT
#define ALPHA_BLD_BYPS_SHIFT 0
#define ALPHA_BLD_BYPS_MASK 0x1 << ALPHA_BLD_BYPS_SHIFT
 
#define DC_MLC_BG_COLOR REG(0x7224)
#define BG_COLOR_R_SHIFT 20
#define BG_COLOR_R_MASK 0x3FF << BG_COLOR_R_SHIFT
#define BG_COLOR_G_SHIFT 10
#define BG_COLOR_G_MASK 0x3FF << BG_COLOR_G_SHIFT
#define BG_COLOR_B_SHIFT 0
#define BG_COLOR_B_MASK 0x3FF << BG_COLOR_B_SHIFT
 
#define DC_MLC_BG_AFLU_TIME REG(0x7228)
#define MLC_BG_AFLU_TIMER_SHIFT 0
#define MLC_BG_AFLU_TIMER_MASK 0xFFFFFFFF << MLC_BG_AFLU_TIMER_SHIFT
 
#define DC_MLC_CANVAS_COLOR REG(0x7230)
#define CANVAS_COLOR_R_SHIFT 20
#define CANVAS_COLOR_R_MASK 0x3FF << CANVAS_COLOR_R_SHIFT
#define CANVAS_COLOR_G_SHIFT 10
#define CANVAS_COLOR_G_MASK 0x3FF << CANVAS_COLOR_G_SHIFT
#define CANVAS_COLOR_B_SHIFT 0
#define CANVAS_COLOR_B_MASK 0x3FF << CANVAS_COLOR_B_SHIFT
 
#define DC_MLC_CLK_RATIO REG(0x7234)
#define MLC_CLK_RATIO_SHIFT 0
#define MLC_CLK_RATIO_MASK 0xFFFF << MLC_CLK_RATIO_SHIFT
 
#define DC_MLC_INT_MASK REG(0x7240)
#define MLC_MASK_ERR_L_5_SHIFT 12
#define MLC_MASK_ERR_L_5_MASK 0x1 << MLC_MASK_ERR_L_5_SHIFT
#define MLC_MASK_ERR_L_4_SHIFT 11
#define MLC_MASK_ERR_L_4_MASK 0x1 << MLC_MASK_ERR_L_4_SHIFT
#define MLC_MASK_ERR_L_3_SHIFT 10
#define MLC_MASK_ERR_L_3_MASK 0x1 << MLC_MASK_ERR_L_3_SHIFT
#define MLC_MASK_ERR_L_2_SHIFT 9
#define MLC_MASK_ERR_L_2_MASK 0x1 << MLC_MASK_ERR_L_2_SHIFT
#define MLC_MASK_ERR_L_1_SHIFT 8
#define MLC_MASK_ERR_L_1_MASK 0x1 << MLC_MASK_ERR_L_1_SHIFT
#define MLC_MASK_ERR_L_0_SHIFT 7
#define MLC_MASK_ERR_L_0_MASK 0x1 << MLC_MASK_ERR_L_0_SHIFT
#define MLC_MASK_FLU_L_5_SHIFT 6
#define MLC_MASK_FLU_L_5_MASK 0x1 << MLC_MASK_FLU_L_5_SHIFT
#define MLC_MASK_FLU_L_4_SHIFT 5
#define MLC_MASK_FLU_L_4_MASK 0x1 << MLC_MASK_FLU_L_4_SHIFT
#define MLC_MASK_FLU_L_3_SHIFT 4
#define MLC_MASK_FLU_L_3_MASK 0x1 << MLC_MASK_FLU_L_3_SHIFT
#define MLC_MASK_FLU_L_2_SHIFT 3
#define MLC_MASK_FLU_L_2_MASK 0x1 << MLC_MASK_FLU_L_2_SHIFT
#define MLC_MASK_FLU_L_1_SHIFT 2
#define MLC_MASK_FLU_L_1_MASK 0x1 << MLC_MASK_FLU_L_1_SHIFT
#define MLC_MASK_FLU_L_0_SHIFT 1
#define MLC_MASK_FLU_L_0_MASK 0x1 << MLC_MASK_FLU_L_0_SHIFT
#define MLC_MASK_FRM_END_SHIFT 0
#define MLC_MASK_FRM_END_MASK 0x1 << MLC_MASK_FRM_END_SHIFT
 
#define DC_MLC_INT_STATUS REG(0x7244)
#define MLC_S_SLOWD_L_5_SHIFT 27
#define MLC_S_SLOWD_L_5_MASK 0x1 << MLC_S_SLOWD_L_5_SHIFT
#define MLC_S_SLOWD_L_4_SHIFT 26
#define MLC_S_SLOWD_L_4_MASK 0x1 << MLC_S_SLOWD_L_4_SHIFT
#define MLC_S_SLOWD_L_3_SHIFT 25
#define MLC_S_SLOWD_L_3_MASK 0x1 << MLC_S_SLOWD_L_3_SHIFT
#define MLC_S_SLOWD_L_2_SHIFT 24
#define MLC_S_SLOWD_L_2_MASK 0x1 << MLC_S_SLOWD_L_2_SHIFT
#define MLC_S_SLOWD_L_1_SHIFT 23
#define MLC_S_SLOWD_L_1_MASK 0x1 << MLC_S_SLOWD_L_1_SHIFT
#define MLC_S_SLOWD_L_0_SHIFT 22
#define MLC_S_SLOWD_L_0_MASK 0x1 << MLC_S_SLOWD_L_0_SHIFT
#define MLC_S_CROP_E_L_5_SHIFT 21
#define MLC_S_CROP_E_L_5_MASK 0x1 << MLC_S_CROP_E_L_5_SHIFT
#define MLC_S_CROP_E_L_4_SHIFT 20
#define MLC_S_CROP_E_L_4_MASK 0x1 << MLC_S_CROP_E_L_4_SHIFT
#define MLC_S_CROP_E_L_3_SHIFT 19
#define MLC_S_CROP_E_L_3_MASK 0x1 << MLC_S_CROP_E_L_3_SHIFT
#define MLC_S_CROP_E_L_2_SHIFT 18
#define MLC_S_CROP_E_L_2_MASK 0x1 << MLC_S_CROP_E_L_2_SHIFT
#define MLC_S_CROP_E_L_1_SHIFT 17
#define MLC_S_CROP_E_L_1_MASK 0x1 << MLC_S_CROP_E_L_1_SHIFT
#define MLC_S_CROP_E_L_0_SHIFT 16
#define MLC_S_CROP_E_L_0_MASK 0x1 << MLC_S_CROP_E_L_0_SHIFT
#define MLC_S_E_L_5_SHIFT 12
#define MLC_S_E_L_5_MASK 0x1 << MLC_S_E_L_5_SHIFT
#define MLC_S_E_L_4_SHIFT 11
#define MLC_S_E_L_4_MASK 0x1 << MLC_S_E_L_4_SHIFT
#define MLC_S_E_L_3_SHIFT 10
#define MLC_S_E_L_3_MASK 0x1 << MLC_S_E_L_3_SHIFT
#define MLC_S_E_L_2_SHIFT 9
#define MLC_S_E_L_2_MASK 0x1 << MLC_S_E_L_2_SHIFT
#define MLC_S_E_L_1_SHIFT 8
#define MLC_S_E_L_1_MASK 0x1 << MLC_S_E_L_1_SHIFT
#define MLC_S_E_L_0_SHIFT 7
#define MLC_S_E_L_0_MASK 0x1 << MLC_S_E_L_0_SHIFT
#define MLC_S_FLU_L_5_SHIFT 6
#define MLC_S_FLU_L_5_MASK 0x1 << MLC_S_FLU_L_5_SHIFT
#define MLC_S_FLU_L_4_SHIFT 5
#define MLC_S_FLU_L_4_MASK 0x1 << MLC_S_FLU_L_4_SHIFT
#define MLC_S_FLU_L_3_SHIFT 4
#define MLC_S_FLU_L_3_MASK 0x1 << MLC_S_FLU_L_3_SHIFT
#define MLC_S_FLU_L_2_SHIFT 3
#define MLC_S_FLU_L_2_MASK 0x1 << MLC_S_FLU_L_2_SHIFT
#define MLC_S_FLU_L_1_SHIFT 2
#define MLC_S_FLU_L_1_MASK 0x1 << MLC_S_FLU_L_1_SHIFT
#define MLC_S_FLU_L_0_SHIFT 1
#define MLC_S_FLU_L_0_MASK 0x1 << MLC_S_FLU_L_0_SHIFT
#define MLC_S_FRM_END_SHIFT 0
#define MLC_S_FRM_END_MASK 0x1 << MLC_S_FRM_END_SHIFT
 
#define MLC_SF_CTRL_S_(i) (REG(0x8000) + MLC_LAYER_JMP * (i))
#define MLC_SF_H_SPOS_S_(i) (REG(0x8004) + MLC_LAYER_JMP * (i))
#define MLC_SF_V_SPOS_S_(i) (REG(0x8008) + MLC_LAYER_JMP * (i))
#define MLC_SF_SIZE_S_(i) (REG(0x800c) + MLC_LAYER_JMP * (i))
#define MLC_SF_CROP_H_POS_S_(i) (REG(0x8010) + MLC_LAYER_JMP * (i))
#define MLC_SF_CROP_V_POS_S_(i) (REG(0x8014) + MLC_LAYER_JMP * (i))
#define MLC_SF_G_ALPHA_S_(i) (REG(0x8018) + MLC_LAYER_JMP * (i))
#define MLC_SF_CKEY_ALPHA_S_(i) (REG(0x801c) + MLC_LAYER_JMP * (i))
#define MLC_SF_CKEY_R_LV_S_(i) (REG(0x8020) + MLC_LAYER_JMP * (i))
#define MLC_SF_CKEY_G_LV_S_(i) (REG(0x8024) + MLC_LAYER_JMP * (i))
#define MLC_SF_CKEY_B_LV_S_(i) (REG(0x8028) + MLC_LAYER_JMP * (i))
#define MLC_SF_AFLU_TIME_S_(i) (REG(0x802c) + MLC_LAYER_JMP * (i))
#define MLC_PATH_CTRL_S_(i) (REG(0x8200) + MLC_PATH_JMP * (i))
#define MLC_BG_CTRL_S REG(0x8220)
#define MLC_BG_COLOR_S REG(0x8224)
#define MLC_BG_AFLU_TIME_S REG(0x8228)
#define MLC_CANVAS_COLOR_S REG(0x8230)
#define MLC_CLK_RATIO_S REG(0x8234)
#define MLC_INT_MASK_S REG(0x8240)
#define MLC_INT_STATUS_S REG(0x8244)
 
/* TCON */
#define KICK_LAYER_JMP 0x8
#define KICK_LAYER_COUNT 7
 
#define TCON_H_PARA_1 REG(0x9000)
#define TCON_HACT_SHIFT 16
#define TCON_HACT_MASK (unsigned int)0xFFFF << TCON_HACT_SHIFT
#define TCON_HTOL_SHIFT 0
#define TCON_HTOL_MASK 0xFFFF << TCON_HTOL_SHIFT
 
#define TCON_H_PARA_2 REG(0x9004)
#define TCON_HSBP_SHIFT 16
#define TCON_HSBP_MASK (unsigned int)0xFFFF << TCON_HSBP_SHIFT
#define TCON_HSYNC_SHIFT 0
#define TCON_HSYNC_MASK 0xFFFF << TCON_HSYNC_SHIFT
 
#define TCON_V_PARA_1 REG(0x9008)
#define TCON_VACT_SHIFT 16
#define TCON_VACT_MASK (unsigned int)0xFFFF << TCON_VACT_SHIFT
#define TCON_VTOL_SHIFT 0
#define TCON_VTOL_MASK 0xFFFF << TCON_VTOL_SHIFT
 
#define TCON_V_PARA_2 REG(0x900c)
#define TCON_VSBP_SHIFT 16
#define TCON_VSBP_MASK (unsigned int)0xFFFF << TCON_VSBP_SHIFT
#define TCON_VSYNC_SHIFT 0
#define TCON_VSYNC_MASK 0xFFFF << TCON_VSYNC_SHIFT
 
#define TCON_CTRL REG(0x9010)
#define TCON_PIX_SCR_SHIFT 6
#define TCON_PIX_SCR_MASK 0x3 << TCON_PIX_SCR_SHIFT
#define TCON_DSP_CLK_EN_SHIFT 5
#define TCON_DSP_CLK_EN_MASK 0x1 << TCON_DSP_CLK_EN_SHIFT
#define TCON_DSP_CLK_POL_SHIFT 4
#define TCON_DSP_CLK_POL_MASK 0x1 << TCON_DSP_CLK_POL_SHIFT
#define TCON_DE_POL_SHITF 3
#define TCON_DE_POL_MASK 0x1 << TCON_DE_POL_SHITF
#define TCON_VSYNC_POL_SHIFT 2
#define TCON_VSYNC_POL_MASK 0x1 << TCON_VSYNC_POL_SHIFT
#define TCON_HSYNC_POL_SHIFT 1
#define TCON_HSYNC_POL_MASK 0x1 << TCON_HSYNC_POL_SHIFT
#define TCON_EN_SHIFT 0
#define TCON_EN_MASK 0x1 << TCON_EN_SHIFT
 
#define TCON_LAYER_KICK_COOR_(i) (REG(0x9020) + KICK_LAYER_JMP * (i))
#define TCON_LAYER_KICK_Y_SHIFT 16
#define TCON_LAYER_KICK_Y_MASK (unsigned int)0xFFFF << TCON_LAYER_KICK_Y_SHIFT
#define TCON_LAYER_KICK_X_SHIFT 0
#define TCON_LAYER_KICK_X_MASK 0xFFFF << TCON_LAYER_KICK_X_SHIFT
 
#define TCON_LAYER_KICK_EN_(i) (REG(0x9024) + KICK_LAYER_JMP * (i))
#define TCON_LAYER_KICK_EN_SHIFT 0
#define TCON_LAYER_KICK_EN_MASK 0x1 << TCON_LAYER_KICK_EN_SHIFT
 
#define TCON_UNDERRUN_CNT REG(0x9100)
#define TCON_UNDERRUN_S_SHIFT 0
#define TCON_UNDERRUN_S_MASK 0xFFFFFFFF << TCON_UNDERRUN_S_SHIFT
 
#define TCON_CSI_FRAM_LOCK_CTRL REG(0x9500)
#define TCON_DE_DLY_SHIFT 16
#define TCON_DE_DLY_MASK (unsigned int)0xFFFF << TCON_DE_DLY_SHIFT
#define AUTO_ADJ_EN_SHIFT 8
#define AUTO_ADJ_EN_MASK 0x1 << AUTO_ADJ_EN_SHIFT
#define FRM_RATIO_SHIFT 4
#define FRM_RATIO_MASK 0x3 << FRM_RATIO_SHIFT
#define VS_MASK_SHIFT 2
#define VS_MASK_MASK 0x3 << VS_MASK_SHIFT
#define VS_POL_SHIFT 1
#define VS_POL_MASK 0x1 << VS_POL_SHIFT
#define HS_POL_SHIFT 0
#define HS_POL_MASK 0x1 << HS_POL_SHIFT
 
#define TCON_CSI_TIMING_DETECT REG(0x9504)
#define TCON_CSI_HTOL REG(0x9510)
#define TCON_CSI_VTOL REG(0x9514)
#define TCON_CSI_VSBP REG(0x9518)
#define TCON_CSI_VSYNC REG(0x951C)
#define TCON_VSYNC_COUNT REG(0x9520)
/* TCON SDW */
#define TCON_SDW_CONTROL REG(0x9600)
#define TCON_SDW_CTRL_TRIG_SHIFT 0
#define TCON_SDW_CTRL_TRIG_MASK 0x1 << TCON_SDW_CTRL_TRIG_SHIFT
 
/* DC_CSC */
#define DC_DC_CSC_CTRL REG(0xa000)
#define DC_CSC_ALPHA_SHIFT 2
#define DC_CSC_ALPHA_MASK 0x1 << DC_CSC_ALPHA_SHIFT
#define DC_CSC_SBUP_CONV_SHIFT 1
#define DC_CSC_SBUP_CONV_MASK 0x1 << DC_CSC_SBUP_CONV_SHIFT
#define DC_CSC_BYPASS_SHIFT 0
#define DC_CSC_BYPASS_MASK 0x1 << DC_CSC_BYPASS_SHIFT
 
#define DC_DC_CSC_COEF1 REG(0xa004)
#define DC_CSC_COEF1_A01_SHIFT 16
#define DC_CSC_COEF1_A01_MASK 0x3FFF << DC_CSC_COEF1_A01_SHIFT
#define DC_CSC_COEF1_A00_SHIFT 0
#define DC_CSC_COEF1_A00_MASK 0x3FFF << DC_CSC_COEF1_A00_SHIFT
 
#define DC_DC_CSC_COEF2 REG(0xa008)
#define DC_CSC_COEF2_A10_SHIFT 16
#define DC_CSC_COEF2_A10_MASK 0x3FFF << DC_CSC_COEF2_A10_SHIFT
#define DC_CSC_COEF2_A02_SHIFT 0
#define DC_CSC_COEF2_A02_MASK 0x3FFF << DC_CSC_COEF2_A02_SHIFT
 
#define DC_DC_CSC_COEF3 REG(0xa00c)
#define DC_CSC_COEF3_A12_SHIFT 16
#define DC_CSC_COEF3_A12_MASK 0x3FFF << DC_CSC_COEF3_A12_SHIFT
#define DC_CSC_COEF3_A11_SHIFT 0
#define DC_CSC_COEF3_A11_MASK 0x3FFF << DC_CSC_COEF3_A11_SHIFT
 
#define DC_DC_CSC_COEF4 REG(0xa010)
#define DC_CSC_COEF4_A21_SHIFT 16
#define DC_CSC_COEF4_A21_MASK 0x3FFF << DC_CSC_COEF4_A21_SHIFT
#define DC_CSC_COEF4_A20_SHIFT 0
#define DC_CSC_COEF4_A20_MASK 0x3FFF << DC_CSC_COEF4_A20_SHIFT
 
#define DC_DC_CSC_COEF5 REG(0xa014)
#define DC_CSC_COEF5_B0_SHIFT 16
#define DC_CSC_COEF5_B0_MASK 0x3FFF << DC_CSC_COEF5_B0_SHIFT
#define DC_CSC_COEF5_A22_SHIFT 0
#define DC_CSC_COEF5_A22_MASK 0x3FFF << DC_CSC_COEF5_A22_SHIFT
 
#define DC_DC_CSC_COEF6 REG(0xa018)
#define DC_CSC_COEF6_B2_SHIFT 16
#define DC_CSC_COEF6_B2_MASK 0x3FFF << DC_CSC_COEF6_B2_SHIFT
#define DC_CSC_COEF6_B1_SHIFT 0
#define DC_CSC_COEF6_B1_MASK 0x3FFF << DC_CSC_COEF6_B1_SHIFT
 
#define DC_DC_CSC_COEF7 REG(0xa01c)
#define DC_CSC_COEF7_C1_SHIFT 16
#define DC_CSC_COEF7_C1_MASK 0x3FF << DC_CSC_COEF7_C1_SHIFT
#define DC_CSC_COEF7_C0_SHIFT 0
#define DC_CSC_COEF7_C0_MASK 0x3FF << DC_CSC_COEF7_C0_SHIFT
 
#define DC_DC_CSC_COEF8 REG(0xa020)
#define DC_CSC_COEF8_C2_SHIFT 0
#define DC_CSC_COEF8_C2_MASK 0x3FF << DC_CSC_COEF8_C2_SHIFT
 
#define GAMMA_CTRL REG(0xc000)
#define GAMMA_APB_RD_TO_SHIFT 8
#define GAMMA_APB_RD_TO_MASK 0xFF << GAMMA_APB_RD_TO_SHIFT
#define GMMA_BYPASS_SHIFT 0
#define GMMA_BYPASS_MASK 0x1 << GMMA_BYPASS_SHIFT
 
#define DITHER_CTRL REG(0xc004)
#define DITHER_V_DEP_SHIFT 16
#define DITHER_V_DEP_MASK 0xF << DITHER_V_DEP_SHIFT
#define DITHER_U_DEP_SHIFT 12
#define DITHER_U_DEP_MASK 0xF << DITHER_U_DEP_SHIFT
#define DITHER_Y_DEP_SHIFT 8
#define DITHER_Y_DEP_MASK 0xF << DITHER_Y_DEP_SHIFT
#define DITHER_MODE_12_SHIFT 6
#define DITHER_MODE_12_MASK 0x1 << DITHER_MODE_12_SHIFT
#define DITHER_SPA_LSB_EXP_MODE_SHIFT 4
#define DITHER_SPA_LSB_EXP_MODE_MASK 0x3 << DITHER_SPA_LSB_EXP_MODE_SHIFT
#define DITHER_SPA_1ST_SHIFT 3
#define DITHER_SPA_1ST_MASK 0x3 << DITHER_SPA_1ST_SHIFT
#define DITHER_SPA_EN_SHIFT 2
#define DITHER_SPA_EN_MASK 0x1 << DITHER_SPA_EN_SHIFT
#define DITHER_TEM_EN_SHIFT 1
#define DITHER_TEM_EN_MASK 0x1 << DITHER_TEM_EN_SHIFT
#define DITHER_BYPASS_SHIFT 0
#define DITHER_BYPASS_MASK 0x1 << DITHER_BYPASS_SHIFT
 
/* CRC32 */
#define CRC_BLK_JMP 0x4
#define CRC_BLK_COUNT 8
 
#define CRC32_CTRL REG(0xe000)
#define CRC32_VSYNC_POL_SHIFT 9
#define CRC32_VSYNC_POL_MASK 0x1 << CRC32_VSYNC_POL_SHIFT
#define CRC32_HSYNC_POL_SHIFT 8
#define CRC32_HSYNC_POL_MASK 0x1 << CRC32_HSYNC_POL_SHIFT
#define CRC32_DATA_EN_POL_SHIFT 7
#define CRC32_DATA_EN_POL_MASK 0x1 << CRC32_DATA_EN_POL_SHIFT
#define CRC32_GLOBAL_ENABLE_SHIFT 0
#define CRC32_GLOBAL_ENABLE_MASK 0x1 << CRC32_GLOBAL_ENABLE_SHIFT
 
#define CRC32_INT_ST REG(0xe004)
#define CRC32_INT_MASK REG(0xe008)
#define CRC_ERROR_7_SHIFT 15
#define CRC_ERROR_7_MASK 0x1 << CRC_ERROR_7_SHIFT
#define CRC_ERROR_6_SHIFT 14
#define CRC_ERROR_6_MASK 0x1 << CRC_ERROR_6_SHIFT
#define CRC_ERROR_5_SHIFT 13
#define CRC_ERROR_5_MASK 0x1 << CRC_ERROR_5_SHIFT
#define CRC_ERROR_4_SHIFT 12
#define CRC_ERROR_4_MASK 0x1 << CRC_ERROR_4_SHIFT
#define CRC_ERROR_3_SHIFT 11
#define CRC_ERROR_3_MASK 0x1 << CRC_ERROR_3_SHIFT
#define CRC_ERROR_2_SHIFT 10
#define CRC_ERROR_2_MASK 0x1 << CRC_ERROR_2_SHIFT
#define CRC_ERROR_1_SHIFT 9
#define CRC_ERROR_1_MASK 0x1 << CRC_ERROR_1_SHIFT
#define CRC_ERROR_0_SHIFT 8
#define CRC_ERROR_0_MASK 0x1 << CRC_ERROR_0_SHIFT
#define CRC_DONE_7_SHIFT 7
#define CRC_DONE_7_MASK 0x1 << CRC_DONE_7_SHIFT
#define CRC_DONE_6_SHIFT 6
#define CRC_DONE_6_MASK 0x1 << CRC_DONE_6_SHIFT
#define CRC_DONE_5_SHIFT 5
#define CRC_DONE_5_MASK 0x1 << CRC_DONE_5_SHIFT
#define CRC_DONE_4_SHIFT 4
#define CRC_DONE_4_MASK 0x1 << CRC_DONE_4_SHIFT
#define CRC_DONE_3_SHIFT 3
#define CRC_DONE_3_MASK 0x1 << CRC_DONE_3_SHIFT
#define CRC_DONE_2_SHIFT 2
#define CRC_DONE_2_MASK 0x1 << CRC_DONE_2_SHIFT
#define CRC_DONE_1_SHIFT 1
#define CRC_DONE_1_MASK 0x1 << CRC_DONE_1_SHIFT
#define CRC_DONE_0_SHIFT 0
#define CRC_DONE_0_MASK 0x1 << CRC_DONE_0_SHIFT
 
#define CRC32_BLOCK_CTRL0_(i) (REG(0xe010) + CRC_BLK_JMP * (i))
#define CRC32_BLOCK_ENABLE_SHIFT 31
#define CRC32_BLOCK_ENABLE_MASK (unsigned int)0x1 << CRC32_BLOCK_ENABLE_SHIFT
#define CRC32_BLOCK_LOCK_SHIFT 30
#define CRC32_BLOCK_LOCK_MASK 0X1 << CRC32_BLOCK_LOCK_SHIFT
#define CRC32_POS_START_Y_SHIFT 16
#define CRC32_POS_START_Y_MASK 0x3FFF << CRC32_POS_START_Y_SHIFT
#define CRC32_POS_START_X_SHIFT 0
#define CRC32_POS_START_X_MASK 0x3FFF << CRC32_POS_START_X_SHIFT
 
#define CRC32_BLOCK_CTRL1_(i) (REG(0xe014) + CRC_BLK_JMP * (i))
#define CRC32_POS_END_Y_SHIFT 16
#define CRC32_POS_END_Y_MASK 0x3FFF << CRC32_POS_END_Y_SHIFT
#define CRC32_POS_END_X_SHIFT 0
#define CRC32_POS_END_X_MASK 0x3FFF << CRC32_POS_END_X_SHIFT
 
#define CRC32_BLOCK_EXPECT_DATA_(i) (REG(0xe018) + CRC_BLK_JMP * (i))
#define CRC32_EXPECT_DATA_SHIFT 0
#define CRC32_EXPECT_DATA_MASK 0xFFFFFFFF << CRC32_EXPECT_DATA_SHIFT
 
#define CRC32_BLOCK_RESULT_DATA_(i) (REG(0xe01c) + CRC_BLK_JMP * (i))
#define CRC32_RESULT_DATA_SHIFT 0
#define CRC32_RESULT_DATA_MASK 0xFFFFFFFF << CRC32_RESULT_DATA_SHIFT
 
#endif /* DC_REG_H__ */