增加所有文件

drivers/source/power/sdrv_dcdc_reg.h

@@ -0,0 +1,43 @@
+/**
+ * @file sdrv_dcdc_reg.h
+ * @brief Semidrive DCDC register.
+ *
+ * @copyright Copyright (c) 2022  Semidrive Semiconductor.
+ *            All rights reserved.
+ */
+
+#ifndef SDRV_POWER_DCDC_REG_H_
+#define SDRV_POWER_DCDC_REG_H_
+
+#include <types.h>
+
+#define DCDC_REG_8_LSB  (0u)
+#define DCDC_REG_8_MASK (0xFFu)
+#define DCDC_REG_7_LSB  (8u)
+#define DCDC_REG_7_MASK (0xFFu)
+#define DCDC_REG_0_LSB  (16u)
+#define DCDC_REG_0_MASK (0xFFu)
+
+#define DCDC_REG_3_LSB  (0u)
+#define DCDC_REG_3_MASK (0xFFu)
+#define DCDC_REG_2_LSB  (8u)
+#define DCDC_REG_2_MASK (0xFFu)
+#define DCDC_REG_1_LSB  (16u)
+#define DCDC_REG_1_MASK (0xFFu)
+
+#define DCDC_REG_6_LSB  (0u)
+#define DCDC_REG_6_MASK (0xFFu)
+#define DCDC_REG_5_LSB  (8u)
+#define DCDC_REG_5_MASK (0xFFu)
+#define DCDC_REG_4_LSB  (16u)
+#define DCDC_REG_4_MASK (0xFFu)
+
+#define ANA_COM_CFG  (0xCu)
+
+#define HP_MOD_CFG0  (0x10u)
+#define HP_MOD_CFG1  (0x14u)
+
+#define LP_MOD_CFG0  (0x18u)
+#define LP_MOD_CFG1  (0x1Cu)
+
+#endif /* SDRV_POWER_DCDC_REG_H_ */

drivers/source/power/sdrv_power_core_context.c

@@ -0,0 +1,77 @@
+/**
+ * @file sdrv_power_core_context.c
+ * @brief Sdrv power driver source.
+ *
+ * @copyright Copyright (c) 2022  Semidrive Semiconductor.
+ *            All rights reserved.
+ */
+
+#include <armv7-r/fpu.h>
+#include <armv7-r/cache.h>
+#include <armv7-r/register.h>
+#include <armv7-r/irq.h>
+#include <armv7-r/pmu.h>
+#include <compiler.h>
+#include <reset_ip.h>
+#include <sdrv_rstgen.h>
+#include "sdrv_power_core_context.h"
+
+extern int arm_saveusercontext(uint32_t *saveregs);
+extern void arm_fullcontextrestore(uint32_t *restoreregs);
+
+
+static uint32_t cpu_regs[XCPTCONTEXT_REGS + MPUCONTEXT_REGS];
+
+
+__WEAK void sdrv_power_tcm_save(void)
+{
+}
+
+__WEAK void sdrv_power_tcm_restore(void)
+{
+}
+
+uint32_t arm_context_read_flag(void)
+{
+    return sdrv_rstgen_read_general(&reset_general_reg_sf_boot);
+}
+
+void arm_context_write_flag(uint32_t val)
+{
+    sdrv_rstgen_write_general(&reset_general_reg_sf_boot, val);
+}
+
+void arm_context_save(void)
+{
+    sdrv_power_tcm_save();
+
+    arm_saveusercontext(cpu_regs);
+}
+
+void arm_context_restore(void)
+{
+    if (sdrv_rstgen_read_general(&reset_general_reg_sf_boot) == CONTEXT_RESTORE_FLAG) {
+        sdrv_power_tcm_restore();
+
+        arch_enable_cache(ICACHE);
+        arch_enable_cache(DCACHE);
+
+#if CONFIG_ARM_WITH_PMU
+        /* udelay use cycle counter, must re-start */
+        pmu_enable();
+        pmu_start_cycle_cntr(false);
+#endif
+
+#if CONFIG_ARCH_WITH_FPU
+        arm_fpu_enable();
+#endif
+
+#if CONFIG_VIC_IRQ_INTERRUPT_MODE
+        arch_vectored_irq_enable(1U);
+#else
+        arch_vectored_irq_enable(0U);
+#endif
+
+        arm_fullcontextrestore(cpu_regs);
+    }
+}

drivers/source/power/sdrv_power_core_context.h

@@ -0,0 +1,26 @@
+/**
+ * @file sdrv_power_core_context.h
+ * @brief Taishan power manager head source.
+ *
+ * @copyright Copyright (c) 2022  Semidrive Semiconductor.
+ *            All rights reserved.
+ */
+
+#ifndef SDRV_TAISHAN_POWER_CORE_CONTEXT_H_
+#define SDRV_TAISHAN_POWER_CORE_CONTEXT_H_
+
+/* saf rstgen general 7 */
+#define CONTEXT_RESTORE_FLAG_REG  0xf069203c
+#define CONTEXT_RESTORE_FLAG      0x1a2b3c4d
+
+#define MPUCONTEXT_REGS    (3 * 16 + 1)
+
+uint32_t arm_context_read_flag(void);
+
+void arm_context_write_flag(uint32_t val);
+
+void arm_context_save(void);
+
+void arm_context_restore(void);
+
+#endif /* SDRV_TAISHAN_POWER_CORE_CONTEXT_H_ */