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liumin
2025-11-07 20:19:23 +08:00
parent b7376523b6
commit 846bd3bbda
8445 changed files with 3006231 additions and 5934 deletions
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105
drivers/include/crypto/cacc/ral/eccp_curve.h Normal file
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/**
* @file eccp_curve.h
* @brief Semidrive CRYPTO eccp_curve header file.
*
* @copyright Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef ECCP_CURVE_H
#define ECCP_CURVE_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "sdrv_crypto_utility.h"
/* sample ecc curve */
#define SUPPORT_BRAINPOOLP160R1
#define SUPPORT_SECP192R1
#define SUPPORT_SECP224R1
#define SUPPORT_SECP256R1
#define SUPPORT_SECP384R1
#define SUPPORT_BRAINPOOLP512R1
#define SUPPORT_SECP521R1
#define POINT_NOT_COMPRESSED (0x04)
/* eccp curve struct */
typedef struct {
uint32_t eccp_p_bitLen; /* bit length of prime p */
uint32_t eccp_n_bitLen; /* bit length of order n */
uint32_t *eccp_p;
uint32_t *eccp_p_h;
uint32_t *eccp_a;
uint32_t *eccp_b;
uint32_t *eccp_Gx;
uint32_t *eccp_Gy;
uint32_t *eccp_n;
uint32_t *eccp_n_h;
uint32_t *eccp_half_Gx;
uint32_t *eccp_half_Gy;
} eccp_curve_t;
#ifdef SUPPORT_BRAINPOOLP160R1
extern const eccp_curve_t brainpoolp160r1[1];
#endif
#ifdef SUPPORT_SECP192R1
extern const eccp_curve_t secp192r1[1];
#endif
#ifdef SUPPORT_SECP224R1
extern const eccp_curve_t secp224r1[1];
#endif
#ifdef SUPPORT_SECP256R1
extern const eccp_curve_t secp256r1[1];
#endif
#ifdef SUPPORT_SECP384R1
extern const eccp_curve_t secp384r1[1];
#endif
#ifdef SUPPORT_BRAINPOOLP512R1
extern const eccp_curve_t brainpoolp512r1[1];
#endif
#ifdef SUPPORT_SECP521R1
extern const eccp_curve_t secp521r1[1];
#endif
/********* Curve25519 struct *********/
typedef struct {
uint32_t p_bitLen; /* bit length of prime p */
uint32_t *p;
uint32_t *p_h;
uint32_t *a24; /* (A-2)/4 */
uint32_t *u;
uint32_t *v;
uint32_t *n; /* order of curve or point(Gx,Gy) */
uint32_t *n_h;
uint32_t *h;
} mont_curve_t;
/********* Edward Curve 25519 struct *********/
typedef struct {
uint32_t p_bitLen; /* bit length of prime p */
uint32_t *p;
uint32_t *p_h;
uint32_t *d;
uint32_t *Gx;
uint32_t *Gy;
uint32_t *n; /* order of curve or point(Gx,Gy) */
uint32_t *n_h;
uint32_t *h;
} edward_curve_t;
#ifdef __cplusplus
}
#endif
#endif

292
drivers/include/crypto/cacc/ral/hash_basic.h Normal file
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/**
* @file hash_basic.h
* @brief Semidrive CRYPTO hash basic header file.
*
* @copyright Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef HASH_BASIC_H
#define HASH_BASIC_H
#include "register_base_addr.h"
#include "sdrv_crypto_utility.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SUPPORT_HASH_SM3
#define SUPPORT_HASH_MD5
#define SUPPORT_HASH_SHA256
#define SUPPORT_HASH_SHA384
#define SUPPORT_HASH_SHA512
#define SUPPORT_HASH_SHA1
#define SUPPORT_HASH_SHA224
#define SUPPORT_HASH_SHA512_224
#define SUPPORT_HASH_SHA512_256
#define SUPPORT_HASH_SHA3_224
#define SUPPORT_HASH_SHA3_256
#define SUPPORT_HASH_SHA3_384
#define SUPPORT_HASH_SHA3_512
#define HASH_DMA_FUNCTION
#define HMAC_SECURE_PORT_FUNCTION
#ifdef HMAC_SECURE_PORT_FUNCTION
#define HMAC_MAX_KEY_IDX \
(8) /* if key is from secure port, the max key index(or the number of \
keys) */
#define HMAC_MAX_SP_KEY_SIZE \
(64) /* for secure port key, max bytes of one key */
#endif
/* some register offset */
#define HASH_HMAC_OFFSET (4)
#define HASH_REVERSE_BYTE_ORDER_IN_WORD_OFFSET (8)
#define HASH_LAST_BLOCK_OFFSET (16)
#define HASH_DMA_OFFSET (16)
/* HASH register struct */
typedef struct hash_reg {
uint32_t hash_ctrl; /* Offset: 0x000 (R/W) Control register */
uint32_t hash_cfg; /* Offset: 0x004 (R/W) Config register */
uint32_t rev_1[2];
uint32_t hash_risr; /* Offset: 0x010 (W0C) Resource of Interrupt Status
register */
uint32_t hash_imcr; /* Offset: 0x014 (R/W) Interrupt Management and Control
register */
uint32_t
hash_misr; /* Offset: 0x018 (R) Multiple Interrupt Status register */
uint32_t rev_2[5];
uint32_t hash_msg_len[4]; /* Offset: 0x030 (R/W) message total length
register */
uint32_t hash_msg_cnt[4]; /* Offset: 0x040 (R/W) message been handled
length register */
uint32_t rev_3[4];
uint32_t
hash_key_len; /* Offset: 0x060 (R/W) HMAC KEY total length register */
uint32_t rev_4[3];
uint32_t hash_key_cnt; /* Offset: 0x070 (R/W) HMAC KEY been handled length
register */
uint32_t rev_5[15];
uint32_t hash_mdin_cr; /* Offset: 0x0B0 (R/W) Data flag register */
uint32_t rev_6[3];
uint32_t hash_m_din; /* Offset: 0x0C0 (W) Hash message Input register */
uint32_t rev_7[14];
uint32_t hash_version; /* Offset: 0x0FC (R) Version register */
uint32_t
hash_in[50]; /* Offset: 0x100 (W) Hash iterator Input register */
uint32_t rev_8[14];
uint32_t hash_out[50]; /* Offset: 0x200 (R) Output register */
uint32_t rev_9[14];
uint32_t dma_cr; /* Offset: 0x300 (R) DMA config register */
uint32_t dma_sr; /* Offset: 0x304 (R/W) DMA Status register */
uint32_t dma_to; /* Offset: 0x308 (R/W) DMA Status register */
uint32_t rev_10[1];
uint32_t dma_sa_l; /* Offset: 0x310 (R/W) DMA Source Address Low part
register */
uint32_t dma_sa_h; /* Offset: 0x314 (R/W) DMA Source Address High part
register */
uint32_t rev_11[2];
uint32_t dma_da_l; /* Offset: 0x320 (R/W) DMA Destination Address Low part
register */
uint32_t dma_da_h; /* Offset: 0x324 (R/W) DMA Destination Address High part
register */
uint32_t rev_12[2];
uint32_t dma_rlen; /* Offset: 0x330 (R/W) DMA read data length register */
uint32_t dma_wlen; /* Offset: 0x334 (R/W) DMA write data length register */
} hash_reg_t;
/* HASH max length */
#if (defined(SUPPORT_HASH_SHA3_224) || defined(SUPPORT_HASH_SHA3_256) || \
defined(SUPPORT_HASH_SHA3_384) || defined(SUPPORT_HASH_SHA3_512))
#define HASH_DIGEST_MAX_WORD_LEN (16)
#define HASH_BLOCK_MAX_WORD_LEN (36)
#elif (defined(SUPPORT_HASH_SHA384) || defined(SUPPORT_HASH_SHA512) || \
defined(SUPPORT_HASH_SHA512_224) || defined(SUPPORT_HASH_SHA512_256))
#define HASH_DIGEST_MAX_WORD_LEN (16)
#define HASH_BLOCK_MAX_WORD_LEN (32)
#else
#define HASH_DIGEST_MAX_WORD_LEN (8)
#define HASH_BLOCK_MAX_WORD_LEN (16)
#endif
#define HASH_BLOCK_MAX_BYTE_LEN (HASH_BLOCK_MAX_WORD_LEN << 2)
#if (defined(SUPPORT_HASH_SHA3_224) || defined(SUPPORT_HASH_SHA3_256) || \
defined(SUPPORT_HASH_SHA3_384) || defined(SUPPORT_HASH_SHA3_512))
#define HASH_ITERATOR_MAX_WORD_LEN (50)
#else
#define HASH_ITERATOR_MAX_WORD_LEN HASH_DIGEST_MAX_WORD_LEN
#endif
#if (defined(SUPPORT_HASH_SHA384) || defined(SUPPORT_HASH_SHA512) || \
defined(SUPPORT_HASH_SHA512_224) || defined(SUPPORT_HASH_SHA512_256))
#define HASH_TOTAL_LEN_MAX_WORD_LEN (4)
#else
#define HASH_TOTAL_LEN_MAX_WORD_LEN (2)
#endif
/* HASH algorithm definition */
typedef enum {
#ifdef SUPPORT_HASH_SM3
HASH_SM3 = 0,
#endif
#ifdef SUPPORT_HASH_MD5
HASH_MD5 = 1,
#endif
#ifdef SUPPORT_HASH_SHA256
HASH_SHA256 = 2,
#endif
#ifdef SUPPORT_HASH_SHA384
HASH_SHA384 = 3,
#endif
#ifdef SUPPORT_HASH_SHA512
HASH_SHA512 = 4,
#endif
#ifdef SUPPORT_HASH_SHA1
HASH_SHA1 = 5,
#endif
#ifdef SUPPORT_HASH_SHA224
HASH_SHA224 = 6,
#endif
#ifdef SUPPORT_HASH_SHA512_224
HASH_SHA512_224 = 7,
#endif
#ifdef SUPPORT_HASH_SHA512_256
HASH_SHA512_256 = 8,
#endif
#ifdef SUPPORT_HASH_SHA3_224
HASH_SHA3_224 = 9,
#endif
#ifdef SUPPORT_HASH_SHA3_256
HASH_SHA3_256 = 10,
#endif
#ifdef SUPPORT_HASH_SHA3_384
HASH_SHA3_384 = 11,
#endif
#ifdef SUPPORT_HASH_SHA3_512
HASH_SHA3_512 = 12,
#endif
} HASH_ALG;
/* HASH return code */
enum HASH_RET_CODE {
HASH_SUCCESS = 0,
HASH_BUFFER_NULL,
HASH_CONFIG_INVALID,
HASH_INPUT_INVALID,
HASH_LEN_OVERFLOW,
HASH_ERROR,
};
typedef void (*HASH_CALLBACK)(void);
uint32_t hash_get_version(void);
void hash_set_cpu_mode(void);
void hash_set_dma_mode(void);
void hash_set_hash_mode(void);
void hash_set_hmac_mode(void);
void hash_set_hmac_key_mode(void);
void hash_clear_hmac_key_mode(void);
void hash_clear_risp(void);
void hash_set_hmac_key_cnt(uint32_t bitlen);
void hash_set_hmac_key_len(uint32_t bitlen);
void hash_hmac_key_opr_one_block(uint32_t *key, uint32_t block_byte_len);
void hash_hmac_key_opr(uint8_t *key, uint32_t key_bytes);
void hash_hmac_disable_secure_port(void);
void hash_hmac_enable_secure_port(uint16_t sp_key_idx);
void hash_hmac_sp_key_opr(uint32_t key_bits);
void hash_set_alg(HASH_ALG hash_alg);
uint32_t hash_check_whether_sha3_alg(HASH_ALG hash_alg);
void hash_update_config(void);
void hash_enable_cpu_interruption(void);
void hash_disable_cpu_interruption(void);
void hash_enable_dma_interruption(void);
void hash_disable_dma_interruption(void);
void hash_clear_dma_ch_en(void);
void hash_set_last_block(uint8_t tag);
void hash_set_endian_uint32(void);
void hash_get_iterator(uint8_t *iterator, uint8_t hash_iterator_words);
void hash_set_iterator(uint32_t *iterator, uint8_t hash_iterator_words);
void hash_clear_msg_len(void);
void hash_set_msg_len(uint32_t bytelen);
void hash_set_msg_total_bit_len(uint32_t *msg_total_bits,
uint32_t block_byte_len);
void hash_start(void);
void hash_wait_till_done(void);
void hash_input_msg(uint8_t *msg, uint32_t msg_words);
void hash_input_msg_u8(uint8_t *msg, uint32_t msg_bytes);
void hash_set_dma_ctl0(uint32_t ctl0);
void hash_set_dma_ctl1(uint32_t ctl1);
void hash_set_dma_ch_ctl(uint32_t ch_ctl);
void hash_set_dma_sublen(uint32_t sublen);
void hash_set_dma_ch_rctl(uint32_t ch_rctl);
void hash_set_dma_ch_wctl(uint32_t ch_wctl);
void hash_set_dma_wlen(uint32_t wlen);
void hash_clear_dma_sa_da(void);
#ifdef HASH_DMA_FUNCTION
void hash_dma_operate(uint32_t *msg, uint32_t *iterator, uint32_t msgBitLen,
HASH_CALLBACK callback);
#endif
#ifdef __cplusplus
}
#endif
#endif

248
drivers/include/crypto/cacc/ral/pke.h Normal file
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/**
* @file pke.h
* @brief Semidrive CRYPTO pke header file.
*
* @copyright Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef PKE_H
#define PKE_H
#ifdef __cplusplus
extern "C" {
#endif
#include "eccp_curve.h"
#include "register_base_addr.h"
#include "sdrv_crypto_utility.h"
#define PKE_SEC
#define SUPPORT_SM2 1
#define SUPPORT_C25519 1
#ifdef SUPPORT_C25519
extern const edward_curve_t ed25519[1];
#endif
/***************** PKE register *******************/
#define PKE_CTRL (*((volatile uint32_t *)(PKE_BASE_ADDR)))
#define PKE_CFG (*((volatile uint32_t *)(PKE_BASE_ADDR + 0x04)))
#define PKE_MC_PTR (*((volatile uint32_t *)(PKE_BASE_ADDR + 0x08)))
#define PKE_RISR (*((volatile uint32_t *)(PKE_BASE_ADDR + 0x0C)))
#define PKE_IMCR (*((volatile uint32_t *)(PKE_BASE_ADDR + 0x10)))
#define PKE_MISR (*((volatile uint32_t *)(PKE_BASE_ADDR + 0x14)))
#define PKE_RT_CODE (*((volatile uint32_t *)(PKE_BASE_ADDR + 0x24)))
#ifdef PKE_SEC
#define PKE_RAND_SEED (*((volatile uint32_t *)(PKE_BASE_ADDR + 0x40)))
#define PKE_RC_EN (*((volatile uint32_t *)(PKE_BASE_ADDR + 0x60)))
#define PKE_RC_KEY (*((volatile uint32_t *)(PKE_BASE_ADDR + 0x64)))
#define PKE_RC_D_NONCE (*((volatile uint32_t *)(PKE_BASE_ADDR + 0x68)))
#define PKE_RC_A_NONCE (*((volatile uint32_t *)(PKE_BASE_ADDR + 0x6C)))
#endif
#define PKE_VERSION (*((volatile uint32_t *)(PKE_BASE_ADDR + 0xFC)))
#define PKE_A(a, step) \
((volatile uint32_t *)(PKE_BASE_ADDR + 0x0400 + (a) * (step)))
#define PKE_B(a, step) \
((volatile uint32_t *)(PKE_BASE_ADDR + 0x1000 + (a) * (step)))
/*********** PKE register action offset ************/
#define PKE_INT_ENABLE_OFFSET (8)
#define PKE_START_CALC (1)
/***************** PKE microcode ******************/
#define MICROCODE_PDBL (0x04)
#define MICROCODE_PADD (0x08)
#define MICROCODE_PVER (0x0C)
#define MICROCODE_PMUL (0x10)
#define MICROCODE_MODEXP (0x14)
#define MICROCODE_MODMUL (0x18)
#define MICROCODE_MODINV (0x1C)
#define MICROCODE_MODADD (0x20)
#define MICROCODE_MODSUB (0x24)
#define MICROCODE_MGMR_PRE_H (0x28)
#define MICROCODE_INTMUL (0x2C)
#define MICROCODE_Ed25519_PMUL (0x30)
#define MICROCODE_Ed25519_PADD (0x34)
#define MICROCODE_C25519_PMUL (0x38)
#define MICROCODE_MODRES (0x3C)
#define MICROCODE_INTADD (0x40)
#define MICROCODE_INTSUB (0x44)
#define MICROCODE_PMULF (0x48)
#define MICROCODE_MGMR_PRE_H_MM (0x4C)
#define MICROCODE_MGMR_PRE_N0 (0x50)
#ifdef PKE_SEC
#define MICROCODE_PMUL_SEC (0x54)
#define MICROCODE_MODEXP_WITH_PUBKEY (0x58)
#define MICROCODE_MODEXP_MGMR_LADDER (0x5C)
#endif
/*********** some PKE algorithm operand length ************/
#define OPERAND_MAX_BIT_LEN (4096)
#define OPERAND_MAX_WORD_LEN (GET_WORD_LEN(OPERAND_MAX_BIT_LEN))
#define ECCP_MAX_BIT_LEN (521)
#define ECCP_MAX_BYTE_LEN (GET_BYTE_LEN(ECCP_MAX_BIT_LEN))
#define ECCP_MAX_WORD_LEN (GET_WORD_LEN(ECCP_MAX_BIT_LEN))
#define C25519_BYTE_LEN (256 / 8)
#define C25519_WORD_LEN (256 / 32)
#define Ed25519_BYTE_LEN C25519_BYTE_LEN
#define Ed25519_WORD_LEN C25519_WORD_LEN
#define MAX_RSA_WORD_LEN OPERAND_MAX_WORD_LEN
#define MAX_RSA_BIT_LEN (MAX_RSA_WORD_LEN << 5)
#define MIN_RSA_BIT_LEN (512)
/******************* PKE return code ********************/
enum PKE_RET_CODE {
PKE_SUCCESS = 0,
PKE_STOP,
PKE_NO_MODINV,
PKE_NOT_ON_CURVE,
PKE_INVALID_MC,
PKE_ZERO_ALL,
PKE_INTEGER_TOO_BIG,
PKE_INVALID_INPUT,
PKE_ERROR,
};
typedef void *(*KDF_FUNC)(const void *input, uint32_t bytelen, uint8_t *key,
uint32_t keybytelen);
uint32_t pke_get_version(void);
uint32_t pke_get_operand_bytes(void);
uint32_t pke_modinv(const uint32_t *modulus, const uint32_t *a, uint32_t *ainv,
uint32_t modwordlen, uint32_t awordlen);
uint32_t pke_modadd(const uint32_t *modulus, const uint32_t *a,
const uint32_t *b, uint32_t *out, uint32_t wordlen);
uint32_t pke_modsub(const uint32_t *modulus, const uint32_t *a,
const uint32_t *b, uint32_t *out, uint32_t wordlen);
uint32_t pke_add(const uint32_t *a, const uint32_t *b, uint32_t *out,
uint32_t wordlen);
uint32_t pke_sub(const uint32_t *a, const uint32_t *b, uint32_t *out,
uint32_t wordlen);
uint32_t pke_mul(const uint32_t *a, const uint32_t *b, uint32_t *out,
uint32_t ab_wordLen);
uint32_t pke_mul_internal(const uint32_t *a, const uint32_t *b, uint32_t *out,
uint32_t a_wordlen, uint32_t b_wordlen,
uint32_t out_wordlen);
uint32_t pke_pre_calc_mont(const uint32_t *modulus, uint32_t bitlen,
uint32_t *H);
uint32_t pke_pre_calc_mont_no_output(const uint32_t *modulus, uint32_t wordlen);
void pke_load_pre_calc_mont(uint32_t *H, uint32_t wordlen);
uint32_t pke_modmul_internal(const uint32_t *modulus, const uint32_t *a,
const uint32_t *b, uint32_t *out,
uint32_t wordlen);
uint32_t pke_modmul(const uint32_t *modulus, const uint32_t *a,
const uint32_t *b, uint32_t *out, uint32_t wordlen);
uint32_t pke_modexp(const uint32_t *modulus, const uint32_t *exponent,
const uint32_t *base, uint32_t *out, uint32_t mod_wordlen,
uint32_t exp_wordlen);
uint32_t pke_mod(uint32_t *a, uint32_t awordlen, uint32_t *b, uint32_t *b_h,
uint32_t bwordlen, uint32_t *c);
uint32_t eccp_pointMul(eccp_curve_t *curve, uint32_t *k, uint32_t *Px,
uint32_t *Py, uint32_t *Qx, uint32_t *Qy);
uint32_t eccp_pointMul_Shamir(eccp_curve_t *curve, uint32_t *k1, uint32_t *P1x,
uint32_t *P1y, uint32_t *k2, uint32_t *P2x,
uint32_t *P2y, uint32_t *Qx, uint32_t *Qy);
uint32_t eccp_pointMul_Shamir_safe(eccp_curve_t *curve, uint32_t *k1,
uint32_t *P1x, uint32_t *P1y, uint32_t *k2,
uint32_t *P2x, uint32_t *P2y, uint32_t *Qx,
uint32_t *Qy);
uint32_t eccp_pointMul_base(eccp_curve_t *curve, uint32_t *k, uint32_t *Qx,
uint32_t *Qy);
uint32_t eccp_pointAdd(eccp_curve_t *curve, uint32_t *P1x, uint32_t *P1y,
uint32_t *P2x, uint32_t *P2y, uint32_t *Qx,
uint32_t *Qy);
void pke_set_operand_width(uint32_t bitlen);
void pke_load_operand(uint32_t *baseaddr, uint32_t *data, uint32_t wordlen);
void pke_clear_interrupt(void);
void pke_set_microcode(uint32_t addr);
void pke_start(void);
uint32_t pke_check_rt_code(void);
void pke_wait_till_done(void);
/* recommended not to define */
#define ECCP_POINT_DOUBLE
#ifdef ECCP_POINT_DOUBLE
uint32_t eccp_pointDouble(eccp_curve_t *curve, uint32_t *Px, uint32_t *Py,
uint32_t *Qx, uint32_t *Qy);
#endif
uint32_t eccp_pointVerify(eccp_curve_t *curve, uint32_t *Px, uint32_t *Py);
uint32_t eccp_get_pubkey_from_prikey(eccp_curve_t *curve, uint8_t *prikey,
uint8_t *pubkey);
uint32_t eccp_getkey(eccp_curve_t *curve, uint8_t *prikey, uint8_t *pubkey);
#ifdef SUPPORT_C25519
uint32_t x25519_pointMul(mont_curve_t *curve, uint32_t *k, uint32_t *Pu,
uint32_t *Qu);
uint32_t ed25519_pointMul(edward_curve_t *curve, uint32_t *k, uint32_t *Px,
uint32_t *Py, uint32_t *Qx, uint32_t *Qy);
uint32_t ed25519_pointAdd(edward_curve_t *curve, uint32_t *P1x, uint32_t *P1y,
uint32_t *P2x, uint32_t *P2y, uint32_t *Qx,
uint32_t *Qy);
uint32_t ed25519_decode_point(edward_curve_t *curve, uint8_t in_y[32],
uint8_t out_x[32], uint8_t out_y[32]);
#endif
#ifdef PKE_SEC
uint32_t pke_sec_init(void);
uint32_t pke_sec_uninit(void);
uint32_t pke_modexp_ladder(const uint32_t *modulus, const uint32_t *exponent,
const uint32_t *base, uint32_t *out,
uint32_t mod_wordlen, uint32_t exp_wordlen);
uint32_t pke_modexp_with_pub(const uint32_t *modulus, const uint32_t *exponent,
const uint32_t *pub, const uint32_t *base,
uint32_t *out, uint32_t mod_wordlen,
uint32_t exp_wordlen, uint32_t pub_wordlen);
uint32_t eccp_pointMul_sec(eccp_curve_t *curve, uint32_t *k, uint32_t *Px,
uint32_t *Py, uint32_t *Qx, uint32_t *Qy);
#endif
#ifdef __cplusplus
}
#endif
#endif

63
drivers/include/crypto/cacc/ral/pke_prime.h Normal file
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/**
* @file pke_prime.h
* @brief Semidrive CRYPTO pke prime header file.
*
* @copyright Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef PKE_PRIME_H
#define PKE_PRIME_H
#include "stdint.h"
#ifdef __cplusplus
extern "C" {
#endif
/* 1:use hardware; 2:use software */
#define BIGINT_DIV_CHOICE (2)
#if (BIGINT_DIV_CHOICE == 1)
typedef struct {
uint32_t low;
uint32_t high;
} double_uint32_t;
#elif (BIGINT_DIV_CHOICE == 2)
typedef uint32_t double_uint32_t;
#endif
/* 1:use Fermat primality test; 2:use Miller<65>CRabin primality test */
#define PRIMALITY_TEST_CHOICE (1)
#if (PRIMALITY_TEST_CHOICE == 1)
#define FERMAT_ROUND (3)
#elif (PRIMALITY_TEST_CHOICE == 2)
#define MILLER_RABIN_ROUND (3)
#endif
/* prime table level(total number of small prime numbers) */
#define PTL_MAX (400) /* the max PTL value */
#define PTL_512 \
(400) /* the best PTL value for prime bit length 512 (RSA1024) */
#define PTL_1024 \
(400) /* the best PTL value for prime bit length 1024 (RSA2048) */
#define NOT_PRIME (0xFFFFFFFF)
#define MAYBE_PRIME (0)
extern const uint16_t primetable[PTL_MAX];
extern const double_uint32_t primetable_s[PTL_MAX];
extern const uint16_t primetable_r[PTL_MAX];
uint32_t get_prime(uint32_t p[], uint32_t pbitlen);
uint32_t bigint_div_table_high(uint32_t *a, uint32_t awordlen, uint16_t *r,
double_uint32_t *s, uint16_t *high_result,
uint32_t PTL);
uint32_t bigint_div_table_low(uint32_t *a, uint16_t *r, double_uint32_t *s,
uint16_t *high_result, uint32_t PTL);
#ifdef __cplusplus
}
#endif
#endif

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drivers/include/crypto/cacc/ral/register_base_addr.h Normal file
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/*****************************************************************************
*
*
*Copyright (c) 2021-2029 Semidrive Incorporated. All rights reserved.
*Software License Agreement
*
******************************************************************************
*/
#ifndef REGISTER_BASE_ADDR_H
#define REGISTER_BASE_ADDR_H
/*including int32_t definition*/
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*just for temporary use*/
/* iram3 0x600000 */
#define CACC_TEST_DMA_RAM_BASE (0x580000UL)
/*register base address*/
/*PKE register base address*/
#define PKE_BASE_ADDR (0x021C0000UL)
/*TRNG register base address*/
#define TRNG_BASE_ADDR (0x021C4000UL)
/*SKE_HP register base address*/
#define SKE_HP_BASE_ADDR (0x021C8000UL)
/*HASH register base address*/
#define HASH_BASE_ADDR (0x021CC000UL)
#define APB_SEIP_BASE_ADDR (0xF3100000UL)
#define OTP_KEY_CTRL (*((volatile uint32_t *)(0x021DD804UL)))
#ifdef __cplusplus
}
#endif
#endif

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drivers/include/crypto/cacc/ral/ske_basic.h Normal file
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/**
* @file ske_basic.h
* @brief Semidrive CRYPTO ske basic header file.
*
* @copyright Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef SKE_BASIC_H
#define SKE_BASIC_H
#include "register_base_addr.h"
#include "sdrv_crypto_utility.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SUPPORT_SKE_DES
#define SUPPORT_SKE_TDES_128
#define SUPPORT_SKE_TDES_192
#define SUPPORT_SKE_AES_128
#define SUPPORT_SKE_AES_192
#define SUPPORT_SKE_AES_256
#define SUPPORT_SKE_SM4
#define SUPPORT_SKE_MODE_ECB
#define SUPPORT_SKE_MODE_CBC
#define SUPPORT_SKE_MODE_CFB
#define SUPPORT_SKE_MODE_OFB
#define SUPPORT_SKE_MODE_CTR
#define SUPPORT_SKE_MODE_XTS
#define SUPPORT_SKE_MODE_GCM
#define SUPPORT_SKE_MODE_CMAC
#define SUPPORT_SKE_MODE_CBC_MAC
#define SKE_HP_DMA_FUNCTION
#define SKE_SECURE_PORT_FUNCTION
#ifdef SKE_SECURE_PORT_FUNCTION
/* if key is from secure port, the max key index(or the number of keys) */
#define SKE_MAX_KEY_IDX (9)
#endif
/* some register offset */
#define SKE_HP_REVERSE_BYTE_ORDER_IN_WORD_OFFSET (24)
#define SKE_HP_MODE_OFFSET (28)
#define SKE_HP_CRYPTO_OFFSET (11)
#define SKE_HP_UP_CFG_OFFSET (12)
#define SKE_HP_DMA_OFFSET (16)
#define SKE_HP_DMA_LL_OFFSET (17)
#define SKE_HP_LAST_DATA_OFFSET (16)
/* SKE register struct */
typedef struct ske_hp_reg {
uint32_t ctrl; /* Offset: 0x000 (W1S) SKE Control Register */
uint32_t cfg; /* Offset: 0x004 (R/W) SKE Config Register */
uint32_t sr; /* Offset: 0x008 (R) SKE Status Register */
uint32_t risr; /* Offset: 0x00C (W0C) SKE Interrupt Source Register */
uint32_t imcr; /* Offset: 0x010 (R/W) SKE Interrupt Enable Register */
uint32_t misr; /* Offset: 0x014 (R) SKE Interrupt Output Register */
uint32_t rev1[1];
uint32_t sp; /* Offset: 0x01C (R/W) SKE Secure Port Register */
uint32_t key1[8]; /* Offset: 0x020 (R/W) Key1 */
uint32_t key2[8]; /* Offset: 0x040 (R/W) Key2 */
uint32_t ske_a_len_l; /* Offset: 0x060 (R/W) CCM/GCM mode AAD length low
Register */
uint32_t ske_a_len_h; /* Offset: 0x064 (R/W) CCM/GCM mode AAD length high
Register */
uint32_t ske_c_len_l; /* Offset: 0x068 (R/W) CCM/GCM/XTS mode
plaintext/ciphertext length low Register */
uint32_t ske_c_len_h; /* Offset: 0x06C (R/W) CCM/GCM/XTS mode
plaintext/ciphertext length high Register */
uint32_t iv[4]; /* Offset: 0x070 (R/W) Initial Vector */
uint32_t m_din_cr; /* Offset: 0x080 (R/W) SKE Input Register */
uint32_t rev3[3];
uint32_t m_din[4]; /* Offset: 0x090 (R/W) SKE Input Register */
uint32_t rev4[4];
uint32_t m_dout[4]; /* Offset: 0x0B0 (R) SKE Output Register */
uint32_t rev5[15];
uint32_t ske_version; /* Offset: 0x0FC (R) SKE Version Register */
uint32_t ske_seed[36]; /* Offset: 0x100 (R/W) SKE Seed Register */
uint32_t ske_alarm; /* Offset: 0x190 (R/W) SKE Alarm Register */
uint32_t rev6[91];
uint32_t dma_cr; /* Offset: 0x300 (R/W) DMA Config register */
uint32_t dma_sr; /* Offset: 0x304 (W0C) DMA Status register */
uint32_t dma_to; /* Offset: 0x308 (R/W) DMA Timeout Threshold register */
uint32_t rev7[1];
uint32_t
dma_sa_l; /* Offset: 0x310 (R/W) DMA Source Address Low part register */
uint32_t dma_sa_h; /* Offset: 0x314 (R/W) DMA Source Address High part
register */
uint32_t rev8[2];
uint32_t dma_da_l; /* Offset: 0x320 (R/W) DMA Destination Address Low part
register */
uint32_t dma_da_h; /* Offset: 0x324 (R/W) DMA Destination Address High part
register */
uint32_t rev9[2];
uint32_t dma_rlen; /* Offset: 0x330 (R/W) DMA read Length register */
uint32_t dma_wlen; /* Offset: 0x334 (R/W) DMA write Length register */
uint32_t rev10[2];
uint32_t dma_awcc; /* Offset: 0x340 (R/W) DMA AWCC register */
uint32_t dma_arcc; /* Offset: 0x344 (R/W) DMA ARCC register */
uint32_t dma_llp_l;
uint32_t dma_llp_h;
} ske_hp_reg_t;
/* SKE Operation Mode */
typedef enum {
SKE_MODE_BYPASS = 0,
#ifdef SUPPORT_SKE_MODE_ECB
SKE_MODE_ECB = 1,
#endif
#ifdef SUPPORT_SKE_MODE_XTS
SKE_MODE_XTS = 2,
#endif
#ifdef SUPPORT_SKE_MODE_CBC
SKE_MODE_CBC = 3,
#endif
#ifdef SUPPORT_SKE_MODE_CFB
SKE_MODE_CFB = 4,
#endif
#ifdef SUPPORT_SKE_MODE_OFB
SKE_MODE_OFB = 5,
#endif
#ifdef SUPPORT_SKE_MODE_CTR
SKE_MODE_CTR = 6,
#endif
#ifdef SUPPORT_SKE_MODE_CMAC
SKE_MODE_CMAC = 7,
#endif
#ifdef SUPPORT_SKE_MODE_CBC_MAC
SKE_MODE_CBC_MAC = 8,
#endif
#ifdef SUPPORT_SKE_MODE_GCM
SKE_MODE_GCM = 9,
#endif
#ifdef SUPPORT_SKE_MODE_CCM
SKE_MODE_CCM = 10,
#endif
} SKE_MODE;
typedef enum {
SKE_CRYPTO_ENCRYPT = 0,
SKE_CRYPTO_DECRYPT,
} SKE_CRYPTO;
typedef enum {
#ifdef SUPPORT_SKE_DES
SKE_ALG_DES = 0,
#endif
#ifdef SUPPORT_SKE_TDES_128
SKE_ALG_TDES_128 = 1,
#endif
#ifdef SUPPORT_SKE_TDES_192
SKE_ALG_TDES_192 = 2,
#endif
#ifdef SUPPORT_SKE_TDES_EEE_128
SKE_ALG_TDES_EEE_128 = 3,
#endif
#ifdef SUPPORT_SKE_TDES_EEE_192
SKE_ALG_TDES_EEE_192 = 4,
#endif
#ifdef SUPPORT_SKE_AES_128
SKE_ALG_AES_128 = 5,
#endif
#ifdef SUPPORT_SKE_AES_192
SKE_ALG_AES_192 = 6,
#endif
#ifdef SUPPORT_SKE_AES_256
SKE_ALG_AES_256 = 7,
#endif
#ifdef SUPPORT_SKE_SM4
SKE_ALG_SM4 = 8,
#endif
} SKE_ALG;
enum SKE_RET_CODE {
SKE_SUCCESS = 0,
SKE_BUFFER_NULL,
SKE_CONFIG_INVALID,
SKE_INPUT_INVALID,
SKE_ATTACK_ALARM,
SKE_ERROR,
};
typedef enum {
SKE_NO_PADDING,
SKE_ZERO_PADDING,
} SKE_PADDING;
typedef struct {
uint8_t block_bytes;
uint8_t block_words;
} ske_ctx_t;
typedef struct {
uint32_t src_addr;
uint32_t dst_addr;
uint32_t next_llp;
uint32_t last_len;
} dma_ll_node_t;
uint32_t ske_get_version(void);
void ske_hp_set_cpu_mode(void);
void ske_hp_set_dma_mode(void);
void ske_hp_enable_dma_linked_list(void);
void ske_hp_disable_dma_linked_list(void);
void ske_hp_set_endian_uint32(void);
void ske_hp_enable_secure_port(uint16_t sp_key_idx);
void ske_hp_disable_secure_port(void);
void ske_hp_set_crypto(SKE_CRYPTO crypto);
void ske_hp_set_alg(SKE_ALG ske_alg);
void ske_hp_set_mode(SKE_MODE mode);
void ske_hp_set_last_block(uint32_t is_last_block);
void ske_hp_set_last_block_len(uint32_t bytes);
uint32_t ske_hp_set_seed(void);
void ske_hp_start(void);
uint32_t ske_hp_calc_wait_till_done(void);
void ske_hp_set_key_uint32(uint32_t *key, uint32_t idx, uint32_t key_words);
void ske_hp_set_iv_uint32(uint32_t *iv, uint32_t block_words);
#if (defined(SUPPORT_SKE_MODE_GCM) || defined(SUPPORT_SKE_MODE_CCM))
void ske_hp_set_aad_len_uint32(uint32_t aad_bytes);
#endif
#if (defined(SUPPORT_SKE_MODE_GCM) || defined(SUPPORT_SKE_MODE_CCM) || \
defined(SUPPORT_SKE_MODE_XTS))
void ske_hp_set_c_len_uint32(uint32_t c_bytes);
#endif
void ske_hp_simple_set_input_block(uint32_t *in, uint32_t block_words);
void ske_hp_simple_get_output_block(uint32_t *out, uint32_t block_words);
uint32_t ske_hp_expand_key(void);
#ifdef SKE_HP_DMA_FUNCTION
uint32_t ske_hp_dma_operate(ske_ctx_t *ctx, uint32_t *in, uint32_t *out,
uint32_t in_words, uint32_t out_words);
#if (defined(SUPPORT_SKE_MODE_CMAC) || defined(SUPPORT_SKE_MODE_CMAC))
uint32_t ske_hp_dma_operate_without_output(ske_ctx_t *ctx, uint32_t *in,
uint32_t in_words);
#endif
#endif
uint32_t ske_hp_update_blocks_no_output(ske_ctx_t *ctx, uint8_t *in,
uint32_t bytes);
uint32_t ske_hp_update_blocks_internal(ske_ctx_t *ctx, uint8_t *in,
uint8_t *out, uint32_t bytes);
uint32_t ske_hp_wait_till_output();
#ifdef __cplusplus
}
#endif
#endif

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/**
* @file trng.h
* @brief Semidrive CRYPTO trng header file.
*
* @copyright Copyright (c) 2021 Semidrive Semiconductor.
* All rights reserved.
*/
#ifndef TRNG_H
#define TRNG_H
#include "register_base_addr.h"
#ifdef __cplusplus
extern "C" {
#endif
/* TRNG register address */
#define TRNG_CR (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x0000))
#define TRNG_MSEL (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x0004))
#define TRNG_SR (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x0008))
#define TRNG_DR (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x000C))
#define TRNG_VERSION (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x0010))
#define TRNG_RESEED (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x0040))
#define TRNG_HT_CR (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x0060))
#define TRNG_HT_SR (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x0070))
#define RO_SRC_EN1 (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x0080))
#define RO_SRC_EN2 (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x0084))
#define SCLK_FREQ (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x0088))
#define TERO_CR (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x00B0))
#define TERO_THOLD (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x00B4))
#define TERO_CNT(i) (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x00C0 + 4 * i))
#define TERO_SR (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x00D0))
#define TERO_DR (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x00D4))
#define TERO_RCR(i) (*(volatile uint32_t *)(TRNG_BASE_ADDR + 0x00E0 + 4 * i))
/* TRNG freq config */
#define TRNG_RO_FREQ_4 (0)
#define TRNG_RO_FREQ_8 (1)
#define TRNG_RO_FREQ_16 (2)
#define TRNG_RO_FREQ_32 (3)
/* TRNG action offset */
#define TRNG_GLOBAL_INT_OFFSET (24)
#define TRNG_READ_EMPTY_INT_OFFSET (17)
#define TRNG_DATA_INT_OFFSET (16)
#define TRNG_RO_ENTROPY_OFFSET (4)
#define TRNG_TERO_THRESHOLD_OFFSET (24)
#define TRNG_TERO_ENTROPY_OFFSET (8)
/* TRNG return code */
enum TRNG_RET_CODE {
TRNG_SUCCESS = 0,
TRNG_BUFFER_NULL,
TRNG_INVALID_INPUT,
TRNG_INVALID_CONFIG,
TRNG_HT_ERROR,
TRNG_ERROR
};
uint32_t trng_get_version(void);
void trng_global_int_enable(void);
void trng_global_int_disable(void);
void trng_empty_read_int_enable(void);
void trng_empty_read_int_disable(void);
void trng_data_int_enable(void);
void trng_data_int_disable(void);
void trng_enable(void);
void trng_disable(void);
uint32_t trng_ro_entropy_config(uint8_t cfg);
uint32_t trng_ro_sub_entropy_config(uint8_t sn, uint16_t cfg);
void trng_set_mode(uint8_t with_post_processing);
void trng_reseed(void);
uint32_t trng_set_freq(uint8_t freq);
uint32_t get_rand_internal(uint8_t *a, uint32_t bytes);
uint32_t get_rand_fast(uint8_t *rand, uint32_t bytes);
uint32_t get_rand(uint8_t *rand, uint32_t bytes);
uint32_t get_hrng(uint8_t *dst, uint32_t size);
void tero_enable(void);
void tero_disable(void);
uint32_t tero_set_stop_threshold(uint8_t threshold_value);
uint32_t tero_entropy_config(uint8_t cfg);
void tero_set_output_rng(void);
void tero_set_output_osc_times(void);
void tero_set_osc_sel(uint8_t cfg);
void tero_set_osc_times_lower_limit(uint16_t value);
void tero_set_osc_times_upper_limit(uint16_t value);
uint32_t get_tero_rand(uint8_t *a, uint32_t bytes);
#ifdef __cplusplus
}
#endif
#endif