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3905 lines
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<div class="textblock"><code>#include <<a class="el" href="sdrv__common_8h_source.html">sdrv_common.h</a>></code><br />
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<code>#include <types.h></code><br />
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<code>#include <part.h></code><br />
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<p><a href="sdrv__smc_8h_source.html">Go to the source code of this file.</a></p>
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Data Structures</h2></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__smc__domain__timeout.html">sdrv_smc_domain_timeout</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__smc__soc__timeout.html">sdrv_smc_soc_timeout</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__smc__soc__wakeup__ctrl.html">sdrv_smc_soc_wakeup_ctrl</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__smc__global__control.html">sdrv_smc_global_control</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__smc.html">sdrv_smc</a></td></tr>
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Macros</h2></td></tr>
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<tr class="memitem:a143769e1dcbc8e081ce367e3eec7b19b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a143769e1dcbc8e081ce367e3eec7b19b">SDRV_SMC_IGNORE_AP</a>   (0x1u)</td></tr>
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<tr class="memitem:a201bacfdeda5912cce206c979b267f9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a201bacfdeda5912cce206c979b267f9f">SDRV_SMC_AP_LP_ALIGN_SAF</a>   (0x2u)</td></tr>
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<tr class="separator:a201bacfdeda5912cce206c979b267f9f"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="typedef-members" name="typedef-members"></a>
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Typedefs</h2></td></tr>
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<tr class="memitem:a9d575fcc7c646e80a63e1ffc2b920243"><td class="memItemLeft" align="right" valign="top">typedef enum <a class="el" href="sdrv__smc_8h.html#af11a15739fa66069a0527afb32eaec79">sdrv_smc_domain</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a></td></tr>
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<tr class="separator:a9d575fcc7c646e80a63e1ffc2b920243"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4c8e260972003c664e03130a3b8577d8"><td class="memItemLeft" align="right" valign="top">typedef enum <a class="el" href="sdrv__smc_8h.html#ac3bc39ebe997d449205b1b8d41c55564">sdrv_smc_power_switch</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a></td></tr>
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<tr class="separator:a4c8e260972003c664e03130a3b8577d8"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="enum-members" name="enum-members"></a>
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Enumerations</h2></td></tr>
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<tr class="memitem:af11a15739fa66069a0527afb32eaec79"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#af11a15739fa66069a0527afb32eaec79">sdrv_smc_domain</a> { <a class="el" href="sdrv__smc_8h.html#af11a15739fa66069a0527afb32eaec79a1d2b9beb4a9e1e01f1fd3d80ab0bbc8d">SDRV_SMC_SAF</a>
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, <a class="el" href="sdrv__smc_8h.html#af11a15739fa66069a0527afb32eaec79a803ee7c6517ffe6200a3bf9e5de6c563">SDRV_SMC_AP</a>
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}</td></tr>
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<tr class="separator:af11a15739fa66069a0527afb32eaec79"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac3bc39ebe997d449205b1b8d41c55564"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#ac3bc39ebe997d449205b1b8d41c55564">sdrv_smc_power_switch</a> { <br />
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  <a class="el" href="sdrv__smc_8h.html#ac3bc39ebe997d449205b1b8d41c55564a857933bf829758823fa5381763226a35">SDRV_SMC_POWER_SWITCH_SF</a> = 0
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, <a class="el" href="sdrv__smc_8h.html#ac3bc39ebe997d449205b1b8d41c55564aa164f22ae11fe41fa5ebf220ad139881">SDRV_SMC_POWER_SWITCH_SP</a>
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, <a class="el" href="sdrv__smc_8h.html#ac3bc39ebe997d449205b1b8d41c55564aa58025e3ec9a1a8193c331f73fd7d063">SDRV_SMC_POWER_SWITCH_SX</a>
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, <a class="el" href="sdrv__smc_8h.html#ac3bc39ebe997d449205b1b8d41c55564ab2d1c03be255c4a9eba913a3d9c6b6f0">SDRV_SMC_POWER_SWITCH_GAMA1</a>
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, <br />
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  <a class="el" href="sdrv__smc_8h.html#ac3bc39ebe997d449205b1b8d41c55564a8269945aa3ea5e291759d2329063f766">SDRV_SMC_POWER_SWITCH_AP_DISP</a>
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<br />
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}</td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
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Functions</h2></td></tr>
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<tr class="memitem:a13bb96490ed8feba47b2910a45c72763"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a13bb96490ed8feba47b2910a45c72763">sdrv_smc_ctrl_global_control_config</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#a809608502ea90f54c704aba21e92eb4d">sdrv_smc_global_control_t</a> *config)</td></tr>
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<tr class="memitem:a0eabb9edbd268388d9e6468cf86e9a42"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a0eabb9edbd268388d9e6468cf86e9a42">sdrv_smc_ctrl_set_primary_core</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> domain, <a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> id)</td></tr>
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<tr class="memitem:abba9ba5f4b054e4d924631be8ce67bc3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#abba9ba5f4b054e4d924631be8ce67bc3">sdrv_smc_ctrl_set_lowpower_mode</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> domain, <a class="el" href="sdrv__smc_8h.html#af78cd18eab2cb72950ca48b72d59e76a">sdrv_smc_mode_e</a> mode)</td></tr>
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<tr class="memitem:a61b6772cb2295f71ac06382a2f300578"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a61b6772cb2295f71ac06382a2f300578">sdrv_smc_ctrl_lowpower_enable</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> domain, bool enable)</td></tr>
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<tr class="memitem:a97012208ce0a3510bb1e266ce104d7b8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a97012208ce0a3510bb1e266ce104d7b8">sdrv_smc_ctrl_power_switch_config</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a> power_switch, <a class="el" href="sdrv__smc_8h.html#af78cd18eab2cb72950ca48b72d59e76a">sdrv_smc_mode_e</a> mode, bool power_down_enable)</td></tr>
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<tr class="memitem:a48cfc4b2fa5bb1c971a9a5ace598f602"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a48cfc4b2fa5bb1c971a9a5ace598f602">sdrv_smc_ctrl_power_switch_delay_config</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a> power_switch, uint32_t iso_en, uint32_t pg, uint32_t po, uint32_t iso_dis)</td></tr>
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<tr class="memitem:ab5c25ecdf5c0bd87dc0a4b599e096fea"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#ab5c25ecdf5c0bd87dc0a4b599e096fea">sdrv_smc_ctrl_ram_lowpower_config</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#a234e369ae73fd526d0a67d22ba499be1">sdrv_smc_ram_e</a> ram, <a class="el" href="sdrv__smc_8h.html#af78cd18eab2cb72950ca48b72d59e76a">sdrv_smc_mode_e</a> mode, uint32_t ram_mode)</td></tr>
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<tr class="memitem:a966c4dde355bfd8e2401c5b0ebf3be8b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a966c4dde355bfd8e2401c5b0ebf3be8b">sdrv_smc_ctrl_domain_timeout_config</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> domain, <a class="el" href="sdrv__smc_8h.html#a8b8ac896699c2665c6444bd520de9cf4">sdrv_smc_domain_timeout_t</a> *config)</td></tr>
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<tr class="memitem:a2a0c5025d692090d2c097bef9db1d8aa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a2a0c5025d692090d2c097bef9db1d8aa">sdrv_smc_ctrl_domain_misc_config</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> domain, bool lp_trans_req, uint32_t irq_mask_dly, bool ill_trans_wkup_en)</td></tr>
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<tr class="memitem:a5c9f531177ce85c18f4131e6065712ce"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a5c9f531177ce85c18f4131e6065712ce">sdrv_smc_ctrl_ap_domain_config</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, uint32_t ap_bitmap)</td></tr>
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<tr class="memitem:a8d45f0ae895c4e3f71b896f773ce2af4"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a8d45f0ae895c4e3f71b896f773ce2af4">sdrv_smc_ctrl_get_core_wakeup_irq_status</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl)</td></tr>
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<tr class="memitem:a78f9b24feb00bf48a35fc23e1242833d"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a78f9b24feb00bf48a35fc23e1242833d">sdrv_smc_ctrl_software_power_switch_gate_status</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a> power_switch)</td></tr>
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<tr class="memitem:a09c6d351bf87ff2f6f5ca4d8ae2dd63d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a09c6d351bf87ff2f6f5ca4d8ae2dd63d">sdrv_smc_ctrl_timeout_status_monitor</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl)</td></tr>
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<tr class="memitem:afde1aaccc34abef0e9647f04bc719fcc"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#afde1aaccc34abef0e9647f04bc719fcc">sdrv_smc_ctrl_interrupt_monitor_status</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> core, uint32_t irq_num)</td></tr>
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<tr class="memitem:abff365997981a9cc56dbd92896d60012"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#abff365997981a9cc56dbd92896d60012">sdrv_smc_ctrl_debug_monitor</a> (<a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> *smc_ctrl, <a class="el" href="sdrv__smc_8h.html#abb3f522232c2289164ab47c888105aa0">sdrv_smc_debug_mux_e</a> dbg_mux)</td></tr>
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<tr class="memitem:ac6254a2a6d4000e876a85fb3ef4a0ac6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#ac6254a2a6d4000e876a85fb3ef4a0ac6">sdrv_smc_status_monitor</a> (void)</td></tr>
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<tr class="memitem:a63a56ec3dbcf99bf7ec772bc46e533b6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a63a56ec3dbcf99bf7ec772bc46e533b6">sdrv_smc_wakeup_interrupt_enable</a> (<a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> core, uint32_t irq_num)</td></tr>
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<tr class="memitem:af7b92154af0daadc43adbe05000886ef"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#af7b92154af0daadc43adbe05000886ef">sdrv_smc_wakeup_interrupt_disable</a> (<a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> core, uint32_t irq_num)</td></tr>
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<tr class="memitem:a1e9dc0f5a0c6f9e359584eab0efd9684"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a1e9dc0f5a0c6f9e359584eab0efd9684">sdrv_smc_all_interrupt_monitor_clear</a> (void)</td></tr>
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<tr class="memitem:a8f578b39af1be0cd2adceedd0ddc3ab3"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a8f578b39af1be0cd2adceedd0ddc3ab3">sdrv_smc_interrupt_monitor_status</a> (<a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> core, uint32_t irq_num)</td></tr>
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<tr class="memitem:ab871ff9c47a07bfe101f824c7f85520b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#ab871ff9c47a07bfe101f824c7f85520b">sdrv_smc_clear_interrupt_monitor_status</a> (<a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> core, uint32_t irq_num)</td></tr>
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<tr class="memitem:a333a67f3327876d2916e8b2a47518d04"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a333a67f3327876d2916e8b2a47518d04">sdrv_smc_record_interrupt_monitor_status</a> (void)</td></tr>
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<tr class="memitem:a04babe9cc4f20c8c8b410eec00de4995"><td class="memItemLeft" align="right" valign="top"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a04babe9cc4f20c8c8b410eec00de4995">sdrv_smc_ap_domain_handshake</a> (bool enable)</td></tr>
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<tr class="separator:a04babe9cc4f20c8c8b410eec00de4995"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a345e3747fb34c9cfe847deb112acb74f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="sdrv__smc_8h.html#a345e3747fb34c9cfe847deb112acb74f">sdrv_smc_debug_monitor</a> (<a class="el" href="sdrv__smc_8h.html#abb3f522232c2289164ab47c888105aa0">sdrv_smc_debug_mux_e</a> dbg_mux)</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><dl class="section copyright"><dt>Copyright</dt><dd>Copyright (c) 2022 Semidrive Semiconductor. All rights reserved. </dd></dl>
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</div><h2 class="groupheader">Macro Definition Documentation</h2>
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<a id="af2f53cb141a47167d5f1f48ee82bd82e" name="af2f53cb141a47167d5f1f48ee82bd82e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#af2f53cb141a47167d5f1f48ee82bd82e">◆ </a></span>RAM_LP_PG_EN</h2>
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<td class="memname">#define RAM_LP_PG_EN   0x4u</td>
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<a id="abf9e408e97e20d7cfcb4f93198d931de" name="abf9e408e97e20d7cfcb4f93198d931de"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#abf9e408e97e20d7cfcb4f93198d931de">◆ </a></span>RAM_LP_RET1N</h2>
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<td class="memname">#define RAM_LP_RET1N   0x2u</td>
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<h2 class="memtitle"><span class="permalink"><a href="#aa35c4a211db9a7041389d2c2dee68217">◆ </a></span>RAM_LP_RET2N</h2>
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<td class="memname">#define RAM_LP_RET2N   0x1u</td>
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<a id="ac6d34ec85a54301e3eb731f7e52bcc5f" name="ac6d34ec85a54301e3eb731f7e52bcc5f"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ac6d34ec85a54301e3eb731f7e52bcc5f">◆ </a></span>SDRV_SF_CKGEN_BCG_NUM</h2>
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<td class="memname">#define SDRV_SF_CKGEN_BCG_NUM   15</td>
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<a id="a73383c31e4da95275ab7f0ad1bc6fb38" name="a73383c31e4da95275ab7f0ad1bc6fb38"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a73383c31e4da95275ab7f0ad1bc6fb38">◆ </a></span>SDRV_SF_CKGEN_CCG_NUM</h2>
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<td class="memname">#define SDRV_SF_CKGEN_CCG_NUM   5</td>
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<a id="a4f7a0491b7537577aa5c1944a585b645" name="a4f7a0491b7537577aa5c1944a585b645"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a4f7a0491b7537577aa5c1944a585b645">◆ </a></span>SDRV_SF_CKGEN_PCG_NUM</h2>
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<td class="memname">#define SDRV_SF_CKGEN_PCG_NUM   334</td>
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<a id="a201bacfdeda5912cce206c979b267f9f" name="a201bacfdeda5912cce206c979b267f9f"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a201bacfdeda5912cce206c979b267f9f">◆ </a></span>SDRV_SMC_AP_LP_ALIGN_SAF</h2>
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<td class="memname">#define SDRV_SMC_AP_LP_ALIGN_SAF   (0x2u)</td>
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<p >AP domain wakeup with SAF domain </p>
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<h2 class="memtitle"><span class="permalink"><a href="#aab1d667052aac9c6d318cc36b3ce18e8">◆ </a></span>SDRV_SMC_AP_WK_ALIGN_SAF</h2>
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<td class="memname">#define SDRV_SMC_AP_WK_ALIGN_SAF   (0x4u)</td>
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<a id="a3f94a366585e7462f1d8a055b177c98b" name="a3f94a366585e7462f1d8a055b177c98b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a3f94a366585e7462f1d8a055b177c98b">◆ </a></span>SDRV_SMC_ASYNC_INT_IOC</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_IOC   (237 + 16)</td>
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<a id="a9af7cd509577a0991d9de5b437e737f0" name="a9af7cd509577a0991d9de5b437e737f0"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a9af7cd509577a0991d9de5b437e737f0">◆ </a></span>SDRV_SMC_ASYNC_INT_USB</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_USB   (236 + 16)</td>
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<p>SMC additional wakeup irq num. </p>
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<a id="a8506965e836baa1c928f740559584406" name="a8506965e836baa1c928f740559584406"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a8506965e836baa1c928f740559584406">◆ </a></span>SDRV_SMC_ASYNC_INT_VIC1_AP_GPIO</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_VIC1_AP_GPIO   (239 + 16)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a1dadd12cd43c04b25b81fcfa0211b365">◆ </a></span>SDRV_SMC_ASYNC_INT_VIC1_SF_GPIO</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_VIC1_SF_GPIO   (238 + 16)</td>
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<a id="a5da7f61d6835ccaec6a4e69f430eaa53" name="a5da7f61d6835ccaec6a4e69f430eaa53"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a5da7f61d6835ccaec6a4e69f430eaa53">◆ </a></span>SDRV_SMC_ASYNC_INT_VIC2A_AP_GPIO</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_VIC2A_AP_GPIO   (241 + 16)</td>
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<a id="acc9a9a6eaf41e09957221485ac305687" name="acc9a9a6eaf41e09957221485ac305687"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#acc9a9a6eaf41e09957221485ac305687">◆ </a></span>SDRV_SMC_ASYNC_INT_VIC2A_SF_GPIO</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_VIC2A_SF_GPIO   (240 + 16)</td>
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<a id="a019af5deb6a7509991958cf23c81d67b" name="a019af5deb6a7509991958cf23c81d67b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a019af5deb6a7509991958cf23c81d67b">◆ </a></span>SDRV_SMC_ASYNC_INT_VIC2B_AP_GPIO</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_VIC2B_AP_GPIO   (243 + 16)</td>
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<a id="a5fa258c0fcc8ee4c4dd2859aac7e190c" name="a5fa258c0fcc8ee4c4dd2859aac7e190c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a5fa258c0fcc8ee4c4dd2859aac7e190c">◆ </a></span>SDRV_SMC_ASYNC_INT_VIC2B_SF_GPIO</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_VIC2B_SF_GPIO   (242 + 16)</td>
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<a id="a27bb7cf46fd067358d7c7992936b579c" name="a27bb7cf46fd067358d7c7992936b579c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a27bb7cf46fd067358d7c7992936b579c">◆ </a></span>SDRV_SMC_ASYNC_INT_VIC3A_AP_GPIO</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_VIC3A_AP_GPIO   (245 + 16)</td>
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<a id="ae76fe270b8748c6c3a051bcf4d12e4eb" name="ae76fe270b8748c6c3a051bcf4d12e4eb"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ae76fe270b8748c6c3a051bcf4d12e4eb">◆ </a></span>SDRV_SMC_ASYNC_INT_VIC3A_SF_GPIO</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_VIC3A_SF_GPIO   (244 + 16)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a69b517621120eb02dac9e1a95da89bd9">◆ </a></span>SDRV_SMC_ASYNC_INT_VIC3B_AP_GPIO</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_VIC3B_AP_GPIO   (247 + 16)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a43574cb50e5a41758bc3cd7ab5b7013a">◆ </a></span>SDRV_SMC_ASYNC_INT_VIC3B_SF_GPIO</h2>
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<td class="memname">#define SDRV_SMC_ASYNC_INT_VIC3B_SF_GPIO   (246 + 16)</td>
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<a id="ad3417285d1d8884e99e9b5a7d186b82a" name="ad3417285d1d8884e99e9b5a7d186b82a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ad3417285d1d8884e99e9b5a7d186b82a">◆ </a></span>SDRV_SMC_CHIP_ENABLE</h2>
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<td class="memname">#define SDRV_SMC_CHIP_ENABLE   (<a class="el" href="sdrv__smc_8h.html#abf9e408e97e20d7cfcb4f93198d931de">RAM_LP_RET1N</a> | <a class="el" href="sdrv__smc_8h.html#aa35c4a211db9a7041389d2c2dee68217">RAM_LP_RET2N</a>)</td>
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<a id="a143769e1dcbc8e081ce367e3eec7b19b" name="a143769e1dcbc8e081ce367e3eec7b19b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a143769e1dcbc8e081ce367e3eec7b19b">◆ </a></span>SDRV_SMC_IGNORE_AP</h2>
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<td class="memname">#define SDRV_SMC_IGNORE_AP   (0x1u)</td>
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<p>AP power state impacts to SMC state machine. </p>
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<p >< AP status is ignored. Only Safety SMC state used for SWM transtion. AP domain enter low power mode with SAF domain </p>
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</div>
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<a id="a5f33198c2fb193a40a846f172fa6a417" name="a5f33198c2fb193a40a846f172fa6a417"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a5f33198c2fb193a40a846f172fa6a417">◆ </a></span>SDRV_SMC_POWER_DOWN</h2>
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<td class="memname">#define SDRV_SMC_POWER_DOWN   (<a class="el" href="sdrv__smc_8h.html#af2f53cb141a47167d5f1f48ee82bd82e">RAM_LP_PG_EN</a> | <a class="el" href="sdrv__smc_8h.html#abf9e408e97e20d7cfcb4f93198d931de">RAM_LP_RET1N</a> | <a class="el" href="sdrv__smc_8h.html#aa35c4a211db9a7041389d2c2dee68217">RAM_LP_RET2N</a>)</td>
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<a id="a6a93093e3c0a15a146c472f1e57fec6a" name="a6a93093e3c0a15a146c472f1e57fec6a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a6a93093e3c0a15a146c472f1e57fec6a">◆ </a></span>SDRV_SMC_RETENTION_1</h2>
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<td class="memname">#define SDRV_SMC_RETENTION_1   (<a class="el" href="sdrv__smc_8h.html#af2f53cb141a47167d5f1f48ee82bd82e">RAM_LP_PG_EN</a> | <a class="el" href="sdrv__smc_8h.html#aa35c4a211db9a7041389d2c2dee68217">RAM_LP_RET2N</a>)</td>
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<a id="aa66f0425e17c974cdfc431c62008901e" name="aa66f0425e17c974cdfc431c62008901e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aa66f0425e17c974cdfc431c62008901e">◆ </a></span>SDRV_SMC_RETENTION_2</h2>
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<td class="memname">#define SDRV_SMC_RETENTION_2   (<a class="el" href="sdrv__smc_8h.html#af2f53cb141a47167d5f1f48ee82bd82e">RAM_LP_PG_EN</a> | <a class="el" href="sdrv__smc_8h.html#abf9e408e97e20d7cfcb4f93198d931de">RAM_LP_RET1N</a>)</td>
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<a id="a0dd14ac4070a4c0bf981c3de7f6fe41e" name="a0dd14ac4070a4c0bf981c3de7f6fe41e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a0dd14ac4070a4c0bf981c3de7f6fe41e">◆ </a></span>SDRV_SMC_SELECTIVE_PRECHARGE</h2>
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<td class="memname">#define SDRV_SMC_SELECTIVE_PRECHARGE   (<a class="el" href="sdrv__smc_8h.html#aa35c4a211db9a7041389d2c2dee68217">RAM_LP_RET2N</a>)</td>
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<a id="aa0ac37534510b94097ad7de95b495636" name="aa0ac37534510b94097ad7de95b495636"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aa0ac37534510b94097ad7de95b495636">◆ </a></span>SDRV_SMC_SWM_HIB</h2>
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<td class="memname">#define SDRV_SMC_SWM_HIB   (0x2u)</td>
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<a id="a6d83c9e19a51271948d66f0865f93aa7" name="a6d83c9e19a51271948d66f0865f93aa7"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a6d83c9e19a51271948d66f0865f93aa7">◆ </a></span>SDRV_SMC_SWM_RTC</h2>
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<td class="memname">#define SDRV_SMC_SWM_RTC   (0x3u)</td>
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<a id="a158a68fbc522a46807621c103cc403e7" name="a158a68fbc522a46807621c103cc403e7"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a158a68fbc522a46807621c103cc403e7">◆ </a></span>SDRV_SMC_SWM_RUN</h2>
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<td class="memname">#define SDRV_SMC_SWM_RUN   (0x0u)</td>
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<a id="a1e7620f438d5601fbe28bbfe1babb946" name="a1e7620f438d5601fbe28bbfe1babb946"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a1e7620f438d5601fbe28bbfe1babb946">◆ </a></span>SDRV_SMC_SWM_SLP</h2>
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<td class="memname">#define SDRV_SMC_SWM_SLP   (0x1u)</td>
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<h2 class="groupheader">Typedef Documentation</h2>
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<a id="ae2d3768b5393309e1646099913e6dd77" name="ae2d3768b5393309e1646099913e6dd77"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ae2d3768b5393309e1646099913e6dd77">◆ </a></span>sdrv_smc_core_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__smc_8h.html#add55d80ee61ce6fb26c7e4fe12622ffe">sdrv_smc_core</a> <a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a></td>
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<p>CPU cores managed by SMC. </p>
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</div>
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</div>
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<a id="abb3f522232c2289164ab47c888105aa0" name="abb3f522232c2289164ab47c888105aa0"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#abb3f522232c2289164ab47c888105aa0">◆ </a></span>sdrv_smc_debug_mux_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__smc_8h.html#a64308655c350821f95e3981bea7ee391">sdrv_smc_debug_mux</a> <a class="el" href="sdrv__smc_8h.html#abb3f522232c2289164ab47c888105aa0">sdrv_smc_debug_mux_e</a></td>
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</tr>
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</div><div class="memdoc">
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<p>SMC debug mux sel. </p>
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</div>
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</div>
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<a id="a9d575fcc7c646e80a63e1ffc2b920243" name="a9d575fcc7c646e80a63e1ffc2b920243"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a9d575fcc7c646e80a63e1ffc2b920243">◆ </a></span>sdrv_smc_domain_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__smc_8h.html#af11a15739fa66069a0527afb32eaec79">sdrv_smc_domain</a> <a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a></td>
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</table>
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</div><div class="memdoc">
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<p>SMC domains. </p>
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<p >The chip is composed of 3 power domains, Safety, AP and RTC. SMC manages power states of Safety and AP domains, while RTC is the always on domain. </p>
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</div>
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</div>
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<a id="a8b8ac896699c2665c6444bd520de9cf4" name="a8b8ac896699c2665c6444bd520de9cf4"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a8b8ac896699c2665c6444bd520de9cf4">◆ </a></span>sdrv_smc_domain_timeout_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__smc__domain__timeout.html">sdrv_smc_domain_timeout</a> <a class="el" href="sdrv__smc_8h.html#a8b8ac896699c2665c6444bd520de9cf4">sdrv_smc_domain_timeout_t</a></td>
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<p>Definition for domain timeout setting. </p>
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</div>
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<a id="a809608502ea90f54c704aba21e92eb4d" name="a809608502ea90f54c704aba21e92eb4d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a809608502ea90f54c704aba21e92eb4d">◆ </a></span>sdrv_smc_global_control_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__smc__global__control.html">sdrv_smc_global_control</a> <a class="el" href="sdrv__smc_8h.html#a809608502ea90f54c704aba21e92eb4d">sdrv_smc_global_control_t</a></td>
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<p>Definition for SMC global control setting. </p>
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<a id="aa4544f83b8f2ffab016c4c18d315ad63" name="aa4544f83b8f2ffab016c4c18d315ad63"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aa4544f83b8f2ffab016c4c18d315ad63">◆ </a></span>sdrv_smc_handshake_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__smc_8h.html#a863d309f20be6dd05493f2af8226fd50">sdrv_smc_handshake</a> <a class="el" href="sdrv__smc_8h.html#aa4544f83b8f2ffab016c4c18d315ad63">sdrv_smc_handshake_e</a></td>
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<p>SMC handshake signals with other on chip modules. </p>
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<a id="af78cd18eab2cb72950ca48b72d59e76a" name="af78cd18eab2cb72950ca48b72d59e76a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#af78cd18eab2cb72950ca48b72d59e76a">◆ </a></span>sdrv_smc_mode_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__smc_8h.html#a2b436842bf803cf49adaaa8823e58b45">sdrv_smc_mode</a> <a class="el" href="sdrv__smc_8h.html#af78cd18eab2cb72950ca48b72d59e76a">sdrv_smc_mode_e</a></td>
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<p>SMC power modes. </p>
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<a id="a4c8e260972003c664e03130a3b8577d8" name="a4c8e260972003c664e03130a3b8577d8"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a4c8e260972003c664e03130a3b8577d8">◆ </a></span>sdrv_smc_power_switch_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__smc_8h.html#ac3bc39ebe997d449205b1b8d41c55564">sdrv_smc_power_switch</a> <a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a></td>
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<p>Power switches. </p>
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<p >Power switches are controlled by the SMC to turn on or turn off module power in Sleep or Hibernate modes. </p>
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<a id="a234e369ae73fd526d0a67d22ba499be1" name="a234e369ae73fd526d0a67d22ba499be1"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a234e369ae73fd526d0a67d22ba499be1">◆ </a></span>sdrv_smc_ram_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__smc_8h.html#a3783e686434403767bbdd946500364aa">sdrv_smc_ram</a> <a class="el" href="sdrv__smc_8h.html#a234e369ae73fd526d0a67d22ba499be1">sdrv_smc_ram_e</a></td>
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<p>On chip RAMs that have low power modes controlled by SMC. </p>
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<a id="a0265ee8df64a78504d5a71ecd3ece7dd" name="a0265ee8df64a78504d5a71ecd3ece7dd"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a0265ee8df64a78504d5a71ecd3ece7dd">◆ </a></span>sdrv_smc_soc_timeout_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__smc__soc__timeout.html">sdrv_smc_soc_timeout</a> <a class="el" href="sdrv__smc_8h.html#a0265ee8df64a78504d5a71ecd3ece7dd">sdrv_smc_soc_timeout_t</a></td>
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<p>Definition for SOC SWM timeout setting. </p>
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<a id="a2664e0233e64841be2a42a8b4b56b574" name="a2664e0233e64841be2a42a8b4b56b574"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a2664e0233e64841be2a42a8b4b56b574">◆ </a></span>sdrv_smc_soc_wakeup_ctrl_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__smc__soc__wakeup__ctrl.html">sdrv_smc_soc_wakeup_ctrl</a> <a class="el" href="sdrv__smc_8h.html#a2664e0233e64841be2a42a8b4b56b574">sdrv_smc_soc_wakeup_ctrl_t</a></td>
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<p>Definition for soc wakeup timeout control setting. </p>
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<a id="a921f7d74cf2d64c107b216a683fc86a7" name="a921f7d74cf2d64c107b216a683fc86a7"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a921f7d74cf2d64c107b216a683fc86a7">◆ </a></span>sdrv_smc_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__smc.html">sdrv_smc</a> <a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>System work mode controller instance. </p>
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</div>
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</div>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
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<a id="add55d80ee61ce6fb26c7e4fe12622ffe" name="add55d80ee61ce6fb26c7e4fe12622ffe"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#add55d80ee61ce6fb26c7e4fe12622ffe">◆ </a></span>sdrv_smc_core</h2>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">enum <a class="el" href="sdrv__smc_8h.html#add55d80ee61ce6fb26c7e4fe12622ffe">sdrv_smc_core</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>CPU cores managed by SMC. </p>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="add55d80ee61ce6fb26c7e4fe12622ffeac34b6657442ed09ded5a71058bae695f" name="add55d80ee61ce6fb26c7e4fe12622ffeac34b6657442ed09ded5a71058bae695f"></a>SDRV_SMC_CORE_SF </td><td class="fielddoc"><p >cluster 0 </p>
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</td></tr>
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<tr><td class="fieldname"><a id="add55d80ee61ce6fb26c7e4fe12622ffea0b6efab653a9f345c646d9e1e4cd6c8e" name="add55d80ee61ce6fb26c7e4fe12622ffea0b6efab653a9f345c646d9e1e4cd6c8e"></a>SDRV_SMC_CORE_SP0 </td><td class="fielddoc"><p >cluster 2, core 0 </p>
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</td></tr>
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<tr><td class="fieldname"><a id="add55d80ee61ce6fb26c7e4fe12622ffea6897f2cc17ce4c574b8723552bd30f22" name="add55d80ee61ce6fb26c7e4fe12622ffea6897f2cc17ce4c574b8723552bd30f22"></a>SDRV_SMC_CORE_SP1 </td><td class="fielddoc"><p >cluster 2, core 1 </p>
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</td></tr>
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<tr><td class="fieldname"><a id="add55d80ee61ce6fb26c7e4fe12622ffeae941f8c1e890a48d8240899bc26a89e0" name="add55d80ee61ce6fb26c7e4fe12622ffeae941f8c1e890a48d8240899bc26a89e0"></a>SDRV_SMC_CORE_SX0 </td><td class="fielddoc"><p >cluster 1, core 0 </p>
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</td></tr>
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<tr><td class="fieldname"><a id="add55d80ee61ce6fb26c7e4fe12622ffea6cd939783fc479ecf5d741125b4dc84f" name="add55d80ee61ce6fb26c7e4fe12622ffea6cd939783fc479ecf5d741125b4dc84f"></a>SDRV_SMC_CORE_SX1 </td><td class="fielddoc"><p >cluster 1, core 1 </p>
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</td></tr>
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</table>
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</div>
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</div>
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<a id="a64308655c350821f95e3981bea7ee391" name="a64308655c350821f95e3981bea7ee391"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a64308655c350821f95e3981bea7ee391">◆ </a></span>sdrv_smc_debug_mux</h2>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">enum <a class="el" href="sdrv__smc_8h.html#a64308655c350821f95e3981bea7ee391">sdrv_smc_debug_mux</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>SMC debug mux sel. </p>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a64308655c350821f95e3981bea7ee391a390035120839dc46bc83d0220e9b54c2" name="a64308655c350821f95e3981bea7ee391a390035120839dc46bc83d0220e9b54c2"></a>SDRV_SMC_DBG_HK_SAF </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a64308655c350821f95e3981bea7ee391a51d10376f2947e71037b3c7d069b4e2d" name="a64308655c350821f95e3981bea7ee391a51d10376f2947e71037b3c7d069b4e2d"></a>SDRV_SMC_DBG_HK_AP </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a64308655c350821f95e3981bea7ee391a377bfcd170e7eba15eae4deac0b840b3" name="a64308655c350821f95e3981bea7ee391a377bfcd170e7eba15eae4deac0b840b3"></a>SDRV_SMC_DBG_HK_PMU </td><td class="fielddoc"></td></tr>
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</table>
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</div>
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</div>
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<a id="af11a15739fa66069a0527afb32eaec79" name="af11a15739fa66069a0527afb32eaec79"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#af11a15739fa66069a0527afb32eaec79">◆ </a></span>sdrv_smc_domain</h2>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">enum <a class="el" href="sdrv__smc_8h.html#af11a15739fa66069a0527afb32eaec79">sdrv_smc_domain</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>SMC domains. </p>
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<p >The chip is composed of 3 power domains, Safety, AP and RTC. SMC manages power states of Safety and AP domains, while RTC is the always on domain. </p>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="af11a15739fa66069a0527afb32eaec79a1d2b9beb4a9e1e01f1fd3d80ab0bbc8d" name="af11a15739fa66069a0527afb32eaec79a1d2b9beb4a9e1e01f1fd3d80ab0bbc8d"></a>SDRV_SMC_SAF </td><td class="fielddoc"><p >Safety power domain </p>
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</td></tr>
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<tr><td class="fieldname"><a id="af11a15739fa66069a0527afb32eaec79a803ee7c6517ffe6200a3bf9e5de6c563" name="af11a15739fa66069a0527afb32eaec79a803ee7c6517ffe6200a3bf9e5de6c563"></a>SDRV_SMC_AP </td><td class="fielddoc"><p >AP power domain </p>
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</td></tr>
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</table>
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</div>
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</div>
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<a id="a3f4ba74aa0d949d4a3749958b8454ed8" name="a3f4ba74aa0d949d4a3749958b8454ed8"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a3f4ba74aa0d949d4a3749958b8454ed8">◆ </a></span>sdrv_smc_error</h2>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">enum <a class="el" href="sdrv__smc_8h.html#a3f4ba74aa0d949d4a3749958b8454ed8">sdrv_smc_error</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>SMC status error code. </p>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a3f4ba74aa0d949d4a3749958b8454ed8a316c3f30b80bafc18abbce1caa72f72d" name="a3f4ba74aa0d949d4a3749958b8454ed8a316c3f30b80bafc18abbce1caa72f72d"></a>SDRV_SMC_CONFIG_TYPE_WRONG </td><td class="fielddoc"></td></tr>
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<tr><td class="fieldname"><a id="a3f4ba74aa0d949d4a3749958b8454ed8a8f9d3b890a288f766b96eb55915bd6df" name="a3f4ba74aa0d949d4a3749958b8454ed8a8f9d3b890a288f766b96eb55915bd6df"></a>SDRV_SMC_CONFIG_NOT_SUPPORT </td><td class="fielddoc"></td></tr>
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</table>
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</div>
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</div>
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<a id="a863d309f20be6dd05493f2af8226fd50" name="a863d309f20be6dd05493f2af8226fd50"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a863d309f20be6dd05493f2af8226fd50">◆ </a></span>sdrv_smc_handshake</h2>
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<div class="memitem">
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<div class="memproto">
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<tr>
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<td class="memname">enum <a class="el" href="sdrv__smc_8h.html#a863d309f20be6dd05493f2af8226fd50">sdrv_smc_handshake</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>SMC handshake signals with other on chip modules. </p>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a863d309f20be6dd05493f2af8226fd50ab01332f380020ef09c4ec6d344ccab59" name="a863d309f20be6dd05493f2af8226fd50ab01332f380020ef09c4ec6d344ccab59"></a>SDRV_SMC_HK_AP_CKGEN </td><td class="fielddoc"><p >handshake with AP clock generator </p>
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</td></tr>
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<tr><td class="fieldname"><a id="a863d309f20be6dd05493f2af8226fd50adb73a52087d3bdbb33e1ccac9013258d" name="a863d309f20be6dd05493f2af8226fd50adb73a52087d3bdbb33e1ccac9013258d"></a>SDRV_SMC_HK_AP_RSTGEN </td><td class="fielddoc"><p >handshake with AP reset generator </p>
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</td></tr>
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<tr><td class="fieldname"><a id="a863d309f20be6dd05493f2af8226fd50af40c446be46213041a16c7cc04884a81" name="a863d309f20be6dd05493f2af8226fd50af40c446be46213041a16c7cc04884a81"></a>SDRV_SMC_HK_SAF_CKGEN </td><td class="fielddoc"><p >handshake with Safety clock generator </p>
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</td></tr>
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<tr><td class="fieldname"><a id="a863d309f20be6dd05493f2af8226fd50aa5db86014d4b4d20969fad2b2b6692e4" name="a863d309f20be6dd05493f2af8226fd50aa5db86014d4b4d20969fad2b2b6692e4"></a>SDRV_SMC_HK_SAF_RSTGEN </td><td class="fielddoc"><p >handshake with Safety reset generator </p>
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</td></tr>
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<tr><td class="fieldname"><a id="a863d309f20be6dd05493f2af8226fd50a99f84040ef2a5322f63a11dae3a8a7ee" name="a863d309f20be6dd05493f2af8226fd50a99f84040ef2a5322f63a11dae3a8a7ee"></a>SDRV_SMC_HK_PMU </td><td class="fielddoc"><p >handshake with PMU </p>
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</td></tr>
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</table>
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</div>
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</div>
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<a id="a2b436842bf803cf49adaaa8823e58b45" name="a2b436842bf803cf49adaaa8823e58b45"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a2b436842bf803cf49adaaa8823e58b45">◆ </a></span>sdrv_smc_mode</h2>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">enum <a class="el" href="sdrv__smc_8h.html#a2b436842bf803cf49adaaa8823e58b45">sdrv_smc_mode</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>SMC power modes. </p>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a2b436842bf803cf49adaaa8823e58b45ac542d7e27f8635a686ce85b46c055bbb" name="a2b436842bf803cf49adaaa8823e58b45ac542d7e27f8635a686ce85b46c055bbb"></a>SDRV_SMC_SLEEP </td><td class="fielddoc"><p >Sleep mode</p>
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<ul>
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<li>CPUs inactive. CPU clocks are gated.</li>
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<li>PLL power down.</li>
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<li>24M XTAL power on or off.</li>
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<li>Periplerals are clock gated, except clocks requried by wake up sources.</li>
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<li>RAM in retention mode. Hibernate mode</li>
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<li>CPU power down</li>
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<li>AP domain power down</li>
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<li>PLL and 24M XTAL power down</li>
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<li>Safety domain periplerals clock gated</li>
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<li>RAM in retention mode </li>
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</ul>
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</td></tr>
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<tr><td class="fieldname"><a id="a2b436842bf803cf49adaaa8823e58b45a261f60c2dde77d4c4f8a4138823a1d8e" name="a2b436842bf803cf49adaaa8823e58b45a261f60c2dde77d4c4f8a4138823a1d8e"></a>SDRV_SMC_HIBERNATE </td><td class="fielddoc"></td></tr>
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</table>
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</div>
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</div>
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<a id="ac3bc39ebe997d449205b1b8d41c55564" name="ac3bc39ebe997d449205b1b8d41c55564"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ac3bc39ebe997d449205b1b8d41c55564">◆ </a></span>sdrv_smc_power_switch</h2>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">enum <a class="el" href="sdrv__smc_8h.html#ac3bc39ebe997d449205b1b8d41c55564">sdrv_smc_power_switch</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Power switches. </p>
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<p >Power switches are controlled by the SMC to turn on or turn off module power in Sleep or Hibernate modes. </p>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ac3bc39ebe997d449205b1b8d41c55564a857933bf829758823fa5381763226a35" name="ac3bc39ebe997d449205b1b8d41c55564a857933bf829758823fa5381763226a35"></a>SDRV_SMC_POWER_SWITCH_SF </td><td class="fielddoc"><p >CR5_SF_MIX power switch </p>
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</td></tr>
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<tr><td class="fieldname"><a id="ac3bc39ebe997d449205b1b8d41c55564aa164f22ae11fe41fa5ebf220ad139881" name="ac3bc39ebe997d449205b1b8d41c55564aa164f22ae11fe41fa5ebf220ad139881"></a>SDRV_SMC_POWER_SWITCH_SP </td><td class="fielddoc"><p >CR5_SP_MIX power switch </p>
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</td></tr>
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<tr><td class="fieldname"><a id="ac3bc39ebe997d449205b1b8d41c55564aa58025e3ec9a1a8193c331f73fd7d063" name="ac3bc39ebe997d449205b1b8d41c55564aa58025e3ec9a1a8193c331f73fd7d063"></a>SDRV_SMC_POWER_SWITCH_SX </td><td class="fielddoc"><p >CR5_SX_MIX power switch </p>
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</td></tr>
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<tr><td class="fieldname"><a id="ac3bc39ebe997d449205b1b8d41c55564ab2d1c03be255c4a9eba913a3d9c6b6f0" name="ac3bc39ebe997d449205b1b8d41c55564ab2d1c03be255c4a9eba913a3d9c6b6f0"></a>SDRV_SMC_POWER_SWITCH_GAMA1 </td><td class="fielddoc"><p >SP_SS gama1 power switch </p>
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</td></tr>
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<tr><td class="fieldname"><a id="ac3bc39ebe997d449205b1b8d41c55564a8269945aa3ea5e291759d2329063f766" name="ac3bc39ebe997d449205b1b8d41c55564a8269945aa3ea5e291759d2329063f766"></a>SDRV_SMC_POWER_SWITCH_AP_DISP </td><td class="fielddoc"><p >AP_SS disp power switch </p>
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</td></tr>
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</table>
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</div>
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</div>
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<a id="a3783e686434403767bbdd946500364aa" name="a3783e686434403767bbdd946500364aa"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a3783e686434403767bbdd946500364aa">◆ </a></span>sdrv_smc_ram</h2>
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<div class="memitem">
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<tr>
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<td class="memname">enum <a class="el" href="sdrv__smc_8h.html#a3783e686434403767bbdd946500364aa">sdrv_smc_ram</a></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>On chip RAMs that have low power modes controlled by SMC. </p>
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<table class="fieldtable">
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a3783e686434403767bbdd946500364aaaeb72161666851aadac40c0437da31c13" name="a3783e686434403767bbdd946500364aaaeb72161666851aadac40c0437da31c13"></a>SDRV_SMC_RAM_SF </td><td class="fielddoc"><p >SF core RAM </p>
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</td></tr>
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<tr><td class="fieldname"><a id="a3783e686434403767bbdd946500364aaa46f47955fbda1c1cb02bbbe9f20467e0" name="a3783e686434403767bbdd946500364aaa46f47955fbda1c1cb02bbbe9f20467e0"></a>SDRV_SMC_RAM_SP </td><td class="fielddoc"><p >SP core RAM </p>
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</td></tr>
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<tr><td class="fieldname"><a id="a3783e686434403767bbdd946500364aaa3ed04f405caee99d91db0502b0e26eb2" name="a3783e686434403767bbdd946500364aaa3ed04f405caee99d91db0502b0e26eb2"></a>SDRV_SMC_RAM_SX </td><td class="fielddoc"><p >SX core RAM </p>
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</td></tr>
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<tr><td class="fieldname"><a id="a3783e686434403767bbdd946500364aaa493acc56e1eeaf7c93429c4087e7f9bf" name="a3783e686434403767bbdd946500364aaa493acc56e1eeaf7c93429c4087e7f9bf"></a>SDRV_SMC_RAM_GAMA1 </td><td class="fielddoc"><p >GAMA internal RAM </p>
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</td></tr>
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<tr><td class="fieldname"><a id="a3783e686434403767bbdd946500364aaac65398cfc878b5beae4c0b554687f874" name="a3783e686434403767bbdd946500364aaac65398cfc878b5beae4c0b554687f874"></a>SDRV_SMC_RAM_SF_MISC </td><td class="fielddoc"><p >Other RAMs in Safety subsystem </p>
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</td></tr>
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<tr><td class="fieldname"><a id="a3783e686434403767bbdd946500364aaa63cb5e37fbd20637ca2f1b5a0552860e" name="a3783e686434403767bbdd946500364aaa63cb5e37fbd20637ca2f1b5a0552860e"></a>SDRV_SMC_RAM_AP </td><td class="fielddoc"><p >RAMs in AP subsystem </p>
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</td></tr>
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<tr><td class="fieldname"><a id="a3783e686434403767bbdd946500364aaa777a30a080cd845ae5841b74e74d363f" name="a3783e686434403767bbdd946500364aaa777a30a080cd845ae5841b74e74d363f"></a>SDRV_SMC_RAM_DISP </td><td class="fielddoc"><p >RAMs in display domain </p>
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</td></tr>
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</table>
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</div>
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</div>
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<h2 class="groupheader">Function Documentation</h2>
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<a id="a1e9dc0f5a0c6f9e359584eab0efd9684" name="a1e9dc0f5a0c6f9e359584eab0efd9684"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a1e9dc0f5a0c6f9e359584eab0efd9684">◆ </a></span>sdrv_smc_all_interrupt_monitor_clear()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_all_interrupt_monitor_clear </td>
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<td>(</td>
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<p>Clear all interrupt monitor register status. </p>
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<p >This function will clear all interrupt status in interrupt monitor register. </p><dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#adb50fab7d7853f6c58d2dcfedf21a2a5">◆ </a></span>sdrv_smc_all_wakeup_interrupt_disable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_all_wakeup_interrupt_disable </td>
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<td>(</td>
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<td class="paramtype">void </td>
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<p>Mask all interrupt for SMC. </p>
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<p >This function mask all interrupt source in low power mode. </p><dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#aa6f538f1566ce83f9285fe5709b550a9">◆ </a></span>sdrv_smc_ap_domain_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ap_domain_config </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>ap_bitmap</em></td><td>)</td>
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<p>AP domain smc config. </p>
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<p >This function configures whether AP power state has impacts to the SMC state machine.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">ap_bitmap</td><td>OR'ed value of the following macros: SDRV_SMC_IGNORE_AP SDRV_SMC_AP_LP_ALIGN_SAF SDRV_SMC_AP_WK_ALIGN_SAF </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a04babe9cc4f20c8c8b410eec00de4995">◆ </a></span>sdrv_smc_ap_domain_handshake()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ap_domain_handshake </td>
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<td>(</td>
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<td class="paramname"><em>enable</em></td><td>)</td>
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<p>Config SMC whether handshake with AP domain. </p>
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<p >This function config SMC ignore AP domain.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>true represents SMC will handshake with AP, false represents SMC will not handshake with AP. </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a1f0551f692d0999d9550d5cddb81bd11">◆ </a></span>sdrv_smc_clear_core_wakeup_ack()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_clear_core_wakeup_ack </td>
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<p>Clear all core wakeup acknowledge. </p>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a90c096b7b5219127d8416cf5ab4fa614">◆ </a></span>sdrv_smc_clear_core_wakeup_irq_status()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_clear_core_wakeup_irq_status </td>
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<p>Clear wakeup core irq status. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">clr</td><td>clear status bit. bit0:cr5_saf, bit1:cr5_sp0, bit2:cr5_sp1, bit3:cr5_sx0, bit4:cr5_sx1 </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ab871ff9c47a07bfe101f824c7f85520b">◆ </a></span>sdrv_smc_clear_interrupt_monitor_status()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_clear_interrupt_monitor_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> </td>
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<td class="paramname"><em>core</em>, </td>
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<td class="paramtype">uint32_t </td>
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<p>Clear specific core interrupt status in interrupt monitor register. </p>
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<p >This function clear the interrupt status for specific core.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">core</td><td>core id </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">irq_num</td><td>irq number </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#abd5d3603339b4ebb9b8ce87b00042d0a">◆ </a></span>sdrv_smc_clear_timeout_illegal_status()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_clear_timeout_illegal_status </td>
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<p>Clear SMC timeout and illegal transition error status. </p>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#acf5fd481aa1ed5c8258e443f6a682555">◆ </a></span>sdrv_smc_core_wakeup_irq_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_core_wakeup_irq_config </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<p>Set wakeup core irq enable or disable. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">err_wkup</td><td>smc error wakeup core irq enable bit0:cr5_saf, bit1:cr5_sp0, bit2:cr5_sp1, bit3:cr5_sx0, bit4:cr5_sx1 </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">bk_wkup</td><td>smc wakeup core irq enable bit0:cr5_saf, bit1:cr5_sp0, bit2:cr5_sp1, bit3:cr5_sx0, bit4:cr5_sx1 </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ad06a6d7663f8d007b43e4d9da55fb7c5">◆ </a></span>sdrv_smc_ctrl_all_interrupt_monitor_clear()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_all_interrupt_monitor_clear </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<p>Clear all interrupt monitor register status. </p>
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<p >This function will clear all interrupt status in interrupt monitor register.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#af5629187b907735ada00acd35d3ee732">◆ </a></span>sdrv_smc_ctrl_all_wakeup_interrupt_disable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_all_wakeup_interrupt_disable </td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<p>Mask all interrupt for SMC. </p>
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<p >This function mask all interrupt source in low power mode.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a5c9f531177ce85c18f4131e6065712ce">◆ </a></span>sdrv_smc_ctrl_ap_domain_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_ap_domain_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>ap_bitmap</em> </td>
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<p>AP domain smc config. </p>
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<p >This function configures whether AP power state has impacts to the SMC state machine.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">ap_bitmap</td><td>OR'ed value of the following macros: SDRV_SMC_IGNORE_AP SDRV_SMC_AP_LP_ALIGN_SAF SDRV_SMC_AP_WK_ALIGN_SAF </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a92fa53737f3e0323625d9f935cf02388">◆ </a></span>sdrv_smc_ctrl_ap_domain_handshake()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_ap_domain_handshake </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em> </td>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</div><div class="memdoc">
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<p>Config SMC whether handshake with AP domain. </p>
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<p >This function config SMC ignore AP domain.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>true represents SMC will handshake with AP, false represents SMC will not handshake with AP. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="ac4febdad22c38a12c41cd9ae9a5bff5d" name="ac4febdad22c38a12c41cd9ae9a5bff5d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ac4febdad22c38a12c41cd9ae9a5bff5d">◆ </a></span>sdrv_smc_ctrl_clear_core_wakeup_ack()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_clear_core_wakeup_ack </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em></td><td>)</td>
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<td></td>
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<p>Clear all core wakeup acknowledge. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a668e1b755354c92e9ed83ef2380af4b8" name="a668e1b755354c92e9ed83ef2380af4b8"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a668e1b755354c92e9ed83ef2380af4b8">◆ </a></span>sdrv_smc_ctrl_clear_core_wakeup_irq_status()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_clear_core_wakeup_irq_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>clr</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Clear wakeup core irq status. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">clr</td><td>clear status bit. bit0:cr5_saf, bit1:cr5_sp0, bit2:cr5_sp1, bit3:cr5_sx0, bit4:cr5_sx1 </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="aa50fef77c50eaf1b20737f384656f845" name="aa50fef77c50eaf1b20737f384656f845"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aa50fef77c50eaf1b20737f384656f845">◆ </a></span>sdrv_smc_ctrl_clear_interrupt_monitor_status()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_clear_interrupt_monitor_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> </td>
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<td class="paramname"><em>core</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>irq_num</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Clear specific core interrupt status in interrupt monitor register. </p>
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<p >This function clear the interrupt status for specific core.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">core</td><td>core id </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">irq_num</td><td>irq number </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="ad5f361d5407af9f995f5b6728462999b" name="ad5f361d5407af9f995f5b6728462999b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ad5f361d5407af9f995f5b6728462999b">◆ </a></span>sdrv_smc_ctrl_clear_timeout_illegal_status()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_clear_timeout_illegal_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<p>Clear SMC timeout and illegal transition error status. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a29708ed59ed6af13f4b50306c228ec50" name="a29708ed59ed6af13f4b50306c228ec50"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a29708ed59ed6af13f4b50306c228ec50">◆ </a></span>sdrv_smc_ctrl_core_wakeup_irq_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_core_wakeup_irq_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>err_wkup</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>bk_wkup</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Set wakeup core irq enable or disable. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">err_wkup</td><td>smc error wakeup core irq enable bit0:cr5_saf, bit1:cr5_sp0, bit2:cr5_sp1, bit3:cr5_sx0, bit4:cr5_sx1 </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">bk_wkup</td><td>smc wakeup core irq enable bit0:cr5_saf, bit1:cr5_sp0, bit2:cr5_sp1, bit3:cr5_sx0, bit4:cr5_sx1 </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="abff365997981a9cc56dbd92896d60012" name="abff365997981a9cc56dbd92896d60012"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#abff365997981a9cc56dbd92896d60012">◆ </a></span>sdrv_smc_ctrl_debug_monitor()</h2>
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<td class="memname">uint32_t sdrv_smc_ctrl_debug_monitor </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#abb3f522232c2289164ab47c888105aa0">sdrv_smc_debug_mux_e</a> </td>
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<td class="paramname"><em>dbg_mux</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</div><div class="memdoc">
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<p>Debug for SMC status. </p>
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<p >This function choose a debug output type, and return the debug value.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">dbg_mux</td><td>mux defined in sdrv_smc_debug_mux_e. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>uint32_t </dd></dl>
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</div>
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</div>
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<a id="a2a0c5025d692090d2c097bef9db1d8aa" name="a2a0c5025d692090d2c097bef9db1d8aa"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a2a0c5025d692090d2c097bef9db1d8aa">◆ </a></span>sdrv_smc_ctrl_domain_misc_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_domain_misc_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> </td>
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<td class="paramname"><em>domain</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>lp_trans_req</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>irq_mask_dly</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>ill_trans_wkup_en</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Config SMC Saf or AP domain misc. </p>
|
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<dl class="params"><dt>Parameters</dt><dd>
|
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<table class="params">
|
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">domain</td><td>SDRV_SMC_SAF or SDRV_SMC_AP. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">lp_trans_req</td><td>LP mode transition request. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">irq_mask_dly</td><td>Interrupt mask delay. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">ill_trans_wkup_en</td><td>Swm illegal transfer wakeup enable. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a966c4dde355bfd8e2401c5b0ebf3be8b" name="a966c4dde355bfd8e2401c5b0ebf3be8b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a966c4dde355bfd8e2401c5b0ebf3be8b">◆ </a></span>sdrv_smc_ctrl_domain_timeout_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_domain_timeout_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> </td>
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<td class="paramname"><em>domain</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a8b8ac896699c2665c6444bd520de9cf4">sdrv_smc_domain_timeout_t</a> * </td>
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<td class="paramname"><em>config</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Config SMC Saf or AP domain tiemout setting. </p>
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<dl class="params"><dt>Parameters</dt><dd>
|
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<table class="params">
|
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
|
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<tr><td class="paramdir">[in]</td><td class="paramname">domain</td><td>SDRV_SMC_SAF or SDRV_SMC_AP. </td></tr>
|
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<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>domain timeout setting. </td></tr>
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</table>
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</dd>
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</dl>
|
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a8d45f0ae895c4e3f71b896f773ce2af4">◆ </a></span>sdrv_smc_ctrl_get_core_wakeup_irq_status()</h2>
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<td class="memname">uint32_t sdrv_smc_ctrl_get_core_wakeup_irq_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em></td><td>)</td>
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<p>Get wakeup core irq status. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>uint32_t bit0:cr5_saf, bit1:cr5_sp0, bit2:cr5_sp1, bit3:cr5_sx0, bit4:cr5_sx1 </dd></dl>
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</div>
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<a id="a13bb96490ed8feba47b2910a45c72763" name="a13bb96490ed8feba47b2910a45c72763"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a13bb96490ed8feba47b2910a45c72763">◆ </a></span>sdrv_smc_ctrl_global_control_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_global_control_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a809608502ea90f54c704aba21e92eb4d">sdrv_smc_global_control_t</a> * </td>
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<td class="paramname"><em>config</em> </td>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>Config Safety/AP domain global control setting. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>global control setting. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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<a id="a08c145dcc6a4a6513a335960590cfdec" name="a08c145dcc6a4a6513a335960590cfdec"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a08c145dcc6a4a6513a335960590cfdec">◆ </a></span>sdrv_smc_ctrl_illegal_status_monitor()</h2>
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<td class="memname">uint32_t sdrv_smc_ctrl_illegal_status_monitor </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em></td><td>)</td>
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<td></td>
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<p>Get SMC illegal transition event monitor status. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>uint32_t </dd></dl>
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</div>
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</div>
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<a id="afde1aaccc34abef0e9647f04bc719fcc" name="afde1aaccc34abef0e9647f04bc719fcc"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#afde1aaccc34abef0e9647f04bc719fcc">◆ </a></span>sdrv_smc_ctrl_interrupt_monitor_status()</h2>
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<td class="memname">bool sdrv_smc_ctrl_interrupt_monitor_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> </td>
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<td class="paramname"><em>core</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>irq_num</em> </td>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</div><div class="memdoc">
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<p>Get specific core interrupt status in interrupt monitor register. </p>
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<p >This function get the interrupt status for specific core.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">core</td><td>core id </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">irq_num</td><td>irq number </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>true represents irq occurs, false represents no interrupt occurs. </dd></dl>
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</div>
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</div>
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<a id="a61b6772cb2295f71ac06382a2f300578" name="a61b6772cb2295f71ac06382a2f300578"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a61b6772cb2295f71ac06382a2f300578">◆ </a></span>sdrv_smc_ctrl_lowpower_enable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_lowpower_enable </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> </td>
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<td class="paramname"><em>domain</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em> </td>
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<td></td>
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<td>)</td>
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<p>Enable or disable low power for specific domain. </p>
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<p >This function enable or disable low power mode for a domain. If enabled, when all CPUs enter wfi, SMC will start low power procedure.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">domain</td><td>safety or ap domain </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>true/false </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a97012208ce0a3510bb1e266ce104d7b8" name="a97012208ce0a3510bb1e266ce104d7b8"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a97012208ce0a3510bb1e266ce104d7b8">◆ </a></span>sdrv_smc_ctrl_power_switch_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_power_switch_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a> </td>
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<td class="paramname"><em>power_switch</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#af78cd18eab2cb72950ca48b72d59e76a">sdrv_smc_mode_e</a> </td>
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<td class="paramname"><em>mode</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>power_down_enable</em> </td>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>Control power switchs in low power mode. </p>
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<p >This function configures power switch states (on or off) in domain low power mode.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">power_switch</td><td>The power switch to configure. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>The SMC low power mode to configure the switch for. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">power_down_enable</td><td>True to turn off the switch in low power mode. False to leave the power switch on in lower power mode. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<a id="a48cfc4b2fa5bb1c971a9a5ace598f602" name="a48cfc4b2fa5bb1c971a9a5ace598f602"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a48cfc4b2fa5bb1c971a9a5ace598f602">◆ </a></span>sdrv_smc_ctrl_power_switch_delay_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_power_switch_delay_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a> </td>
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<td class="paramname"><em>power_switch</em>, </td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>iso_en</em>, </td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>pg</em>, </td>
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<td class="paramkey"></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>po</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>iso_dis</em> </td>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>Config Power switch in low power delay control. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">power_switch</td><td>The power switch to configure. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">iso_en</td><td>isolation enable delay between LP process start to X_iso_en pose. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">pg</td><td>power gate delay between X_iso_en pose to X_pwr_gate pose. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">po</td><td>power on delay between RUN process start to X_pwr_gate nege. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">iso_dis</td><td>isolation disable delay between X_pwr_gate nege to X_iso_en_nege. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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<a id="a920f8af657f77dcf07bd3efaabe5fa1e" name="a920f8af657f77dcf07bd3efaabe5fa1e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a920f8af657f77dcf07bd3efaabe5fa1e">◆ </a></span>sdrv_smc_ctrl_pre_divider_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_pre_divider_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint16_t </td>
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<td class="paramname"><em>div_32k</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint8_t </td>
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<td class="paramname"><em>div_24m</em> </td>
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<td></td>
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<td>)</td>
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<p>Set pre-divider number for 24M and 32K clock. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">div_32k</td><td>pre div number for clk32k. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">div_24m</td><td>pre div number for clk24m. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<a id="ab5c25ecdf5c0bd87dc0a4b599e096fea" name="ab5c25ecdf5c0bd87dc0a4b599e096fea"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ab5c25ecdf5c0bd87dc0a4b599e096fea">◆ </a></span>sdrv_smc_ctrl_ram_lowpower_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_ram_lowpower_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a234e369ae73fd526d0a67d22ba499be1">sdrv_smc_ram_e</a> </td>
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<td class="paramname"><em>ram</em>, </td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#af78cd18eab2cb72950ca48b72d59e76a">sdrv_smc_mode_e</a> </td>
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<td class="paramname"><em>mode</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>ram_mode</em> </td>
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<td></td>
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<td>)</td>
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<p>Configure low power modes for core RAM. </p>
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<p >This function configures low power modes for core RAMs, i.e, module interal RAM, CPU cache and TCM, in SMC sleep or hibernate modes.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">ram</td><td>RAM type. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>The SMC low power mode to configure RAM mode for. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">ram_mode</td><td>RAM mode in SMC low power mode. Possible values are: SDRV_SMC_CHIP_ENABLE SDRV_SMC_SELECTIVE_PRECHARGE SDRV_SMC_RETENTION_1 SDRV_SMC_RETENTION_2 SDRV_SMC_POWER_DOWN </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a49ba6ea5397a59faf1f85b6ff2f2e327">◆ </a></span>sdrv_smc_ctrl_rc24m_hibernate_enable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_rc24m_hibernate_enable </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em> </td>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</div><div class="memdoc">
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<p>Configure RC oscillator state in hibernate mode. </p>
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<p >This function configures on chip 24M RC oscillator state in SMC hibernate mode.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>True to enable the RC oscillator in hibernate mode. False to turn off the oscillator in hibernate mode. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="abb599e179b8a949f00f672d315c25c5b" name="abb599e179b8a949f00f672d315c25c5b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#abb599e179b8a949f00f672d315c25c5b">◆ </a></span>sdrv_smc_ctrl_record_interrupt_monitor_status()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_record_interrupt_monitor_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em></td><td>)</td>
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<td></td>
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<p>This function record monitor interrupt status when exit WFI. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="aa2964ad23063ce7a90a768ac0c8c7bc0" name="aa2964ad23063ce7a90a768ac0c8c7bc0"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aa2964ad23063ce7a90a768ac0c8c7bc0">◆ </a></span>sdrv_smc_ctrl_set_core_wakeup_ack()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_set_core_wakeup_ack </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>ack</em> </td>
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<td></td>
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<td>)</td>
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</table>
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</div><div class="memdoc">
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<p>Set core wakeup acknowledge. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">ack</td><td>bit0:cr5_saf, bit1:cr5_sp0, bit2:cr5_sp1, bit3:cr5_sx0, bit4:cr5_sx1 </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="abba9ba5f4b054e4d924631be8ce67bc3" name="abba9ba5f4b054e4d924631be8ce67bc3"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#abba9ba5f4b054e4d924631be8ce67bc3">◆ </a></span>sdrv_smc_ctrl_set_lowpower_mode()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_set_lowpower_mode </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> </td>
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<td class="paramname"><em>domain</em>, </td>
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<td class="paramkey"></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#af78cd18eab2cb72950ca48b72d59e76a">sdrv_smc_mode_e</a> </td>
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<td class="paramname"><em>mode</em> </td>
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<td></td>
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<td>)</td>
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<p>Set low power mode for specific domain. </p>
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<p >This function sets the low power mode of specific domain. The domain will enter required low power mode after its primary CPU and all CPUs belongs to this domain enters WFI.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">domain</td><td>Safety or AP domain </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>Sleep or hibernate after primary CPU WFI </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a0eabb9edbd268388d9e6468cf86e9a42" name="a0eabb9edbd268388d9e6468cf86e9a42"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a0eabb9edbd268388d9e6468cf86e9a42">◆ </a></span>sdrv_smc_ctrl_set_primary_core()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_set_primary_core </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> </td>
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<td class="paramname"><em>domain</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> </td>
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<td class="paramname"><em>id</em> </td>
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<td></td>
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<td>)</td>
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<p>Set primary core id for a power domain. </p>
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<p >This function sets primary core id for a domain. Only the primary CPU of one domain can configure SMC registers of this domain.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">domain</td><td>Safety or AP domain </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">id</td><td>core id </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<a id="a1d7ab80194316e93053aa76ad5dcbb0f" name="a1d7ab80194316e93053aa76ad5dcbb0f"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a1d7ab80194316e93053aa76ad5dcbb0f">◆ </a></span>sdrv_smc_ctrl_smc_misc_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_smc_misc_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>lpbk_force_check_en</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>permission_err_en</em> </td>
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<td></td>
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<td>)</td>
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<p>Config SMC misc. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">lpbk_force_check_en</td><td>lpbk force check enable, loopback wdt div number check without req/ack active. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">permission_err_en</td><td>enable for permission error as apbslverr. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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<a id="a9e871ca141ea3cab0754386ac569632c" name="a9e871ca141ea3cab0754386ac569632c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a9e871ca141ea3cab0754386ac569632c">◆ </a></span>sdrv_smc_ctrl_soc_misc_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_soc_misc_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>ill_trans_wkup_en</em> </td>
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<td>)</td>
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<p>Config SOC misc. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">ill_trans_wkup_en</td><td>Swm illegal transfer wakeup enable. </td></tr>
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</dd>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<a id="a9ee6522b642f59f575351314e1e131b5" name="a9ee6522b642f59f575351314e1e131b5"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a9ee6522b642f59f575351314e1e131b5">◆ </a></span>sdrv_smc_ctrl_soc_swm_timeout_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_soc_swm_timeout_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a0265ee8df64a78504d5a71ecd3ece7dd">sdrv_smc_soc_timeout_t</a> * </td>
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<td class="paramname"><em>config</em> </td>
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<td></td>
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<td>)</td>
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<p>Set soc swm timeout setting. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>soc timeout settings. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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<a id="a0704595ffbaee790010340e0ef26bf19" name="a0704595ffbaee790010340e0ef26bf19"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a0704595ffbaee790010340e0ef26bf19">◆ </a></span>sdrv_smc_ctrl_soc_wakeup_control_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_soc_wakeup_control_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a2664e0233e64841be2a42a8b4b56b574">sdrv_smc_soc_wakeup_ctrl_t</a> * </td>
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<td class="paramname"><em>config</em> </td>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>Set soc wakeup control setting. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>soc wakeup control settings. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a78f9b24feb00bf48a35fc23e1242833d" name="a78f9b24feb00bf48a35fc23e1242833d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a78f9b24feb00bf48a35fc23e1242833d">◆ </a></span>sdrv_smc_ctrl_software_power_switch_gate_status()</h2>
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<td class="memname">bool sdrv_smc_ctrl_software_power_switch_gate_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a> </td>
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<td class="paramname"><em>power_switch</em> </td>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>Get power switch software power gate status. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">power_switch</td><td>The power switch to read. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>Power gate status. </dd></dl>
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</div>
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</div>
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<a id="ae94253bce9a65493990aab4e4110f279" name="ae94253bce9a65493990aab4e4110f279"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ae94253bce9a65493990aab4e4110f279">◆ </a></span>sdrv_smc_ctrl_status_monitor()</h2>
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<td class="memname">uint32_t sdrv_smc_ctrl_status_monitor </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em></td><td>)</td>
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<p>Get SWM status monitor register. </p>
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<p >This function get SOC/SAF/AP system work mode, futhermode, get SAF/AP internal system work mode.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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</table>
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</dd>
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<dl class="section return"><dt>Returns</dt><dd>uint32_t 0x1 Run, 0x2 Sleep, 0x4 Hibernate bit[3:0]-SAF_SWM, bit[7:4]-AP_SWM, bit[11:8]-SOC_SWM 0x1 Run, 0x2 LP Proc, 0x4 Run Proc, 0x8 LP bit[20:16]-SAF_INTER_SWM, bit[25:21]-AP_INTER_SWM </dd></dl>
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</div>
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<a id="a09c6d351bf87ff2f6f5ca4d8ae2dd63d" name="a09c6d351bf87ff2f6f5ca4d8ae2dd63d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a09c6d351bf87ff2f6f5ca4d8ae2dd63d">◆ </a></span>sdrv_smc_ctrl_timeout_status_monitor()</h2>
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<td class="memname">uint32_t sdrv_smc_ctrl_timeout_status_monitor </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em></td><td>)</td>
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<td></td>
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<p>Get SMC timeout event monitor status. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>uint32_t </dd></dl>
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</div>
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</div>
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<a id="ac6e1e9eb8ad46d927680b8ac8d5478d3" name="ac6e1e9eb8ad46d927680b8ac8d5478d3"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ac6e1e9eb8ad46d927680b8ac8d5478d3">◆ </a></span>sdrv_smc_ctrl_trigger_software_handshake()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_trigger_software_handshake </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#aa4544f83b8f2ffab016c4c18d315ad63">sdrv_smc_handshake_e</a> </td>
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<td class="paramname"><em>handshake</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>smc_swm</em> </td>
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<tr>
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<td></td>
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<td>)</td>
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<p>Software trigger SMC handshake with other module. </p>
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<p >This function trigger SMC handshake with other module, after handshake successful, that module will in low power mode, it will use configuration in low power mode.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">handshake</td><td>module to handshake </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_swm</td><td>system work mode, can be following macro: SDRV_SMC_SWM_RUN SDRV_SMC_SWM_SLP SDRV_SMC_SWM_HIB SDRV_SMC_SWM_RTC </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="ad822eef58815efae2e7b862238beefe9" name="ad822eef58815efae2e7b862238beefe9"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ad822eef58815efae2e7b862238beefe9">◆ </a></span>sdrv_smc_ctrl_trigger_software_power_switch()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_trigger_software_power_switch </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a> </td>
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<td class="paramname"><em>power_switch</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>power_down_enable</em> </td>
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<td></td>
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<td>)</td>
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</table>
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</div><div class="memdoc">
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<p>Software trigger SMC control power switch in run mode. </p>
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<p >This function can software override power switch value.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">power_switch</td><td>The power switch to configure. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">power_down_enable</td><td>True to turn off the switch, False to turn on the switch. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a538e41ff088a8bb105c9359c554be02e" name="a538e41ff088a8bb105c9359c554be02e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a538e41ff088a8bb105c9359c554be02e">◆ </a></span>sdrv_smc_ctrl_trigger_software_ram_lowpower()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_trigger_software_ram_lowpower </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a234e369ae73fd526d0a67d22ba499be1">sdrv_smc_ram_e</a> </td>
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<td class="paramname"><em>ram</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>ram_mode</em> </td>
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<td></td>
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<td>)</td>
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<p>Software trigger SMC control core ram power down in run mode. </p>
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<p >This function can software override core ram power down value.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">ram</td><td>RAM type. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">ram_mode</td><td>RAM mode override by software. Possible values are: SDRV_SMC_CHIP_ENABLE SDRV_SMC_SELECTIVE_PRECHARGE SDRV_SMC_RETENTION_1 SDRV_SMC_RETENTION_2 SDRV_SMC_POWER_DOWN </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a63788d4a46436d87f7e4857e373d9f47" name="a63788d4a46436d87f7e4857e373d9f47"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a63788d4a46436d87f7e4857e373d9f47">◆ </a></span>sdrv_smc_ctrl_wakeup_interrupt_disable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_wakeup_interrupt_disable </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> </td>
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<td class="paramname"><em>core</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>irq_num</em> </td>
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<td></td>
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<p>Disable wakeup interrupt for specific core. </p>
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<p >This function disable interrupt to wakeup specific core in low power mode.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">core</td><td>core id </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">irq_num</td><td>irq number </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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<a id="a4e617bbf23124ca621688850b4250fb3" name="a4e617bbf23124ca621688850b4250fb3"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a4e617bbf23124ca621688850b4250fb3">◆ </a></span>sdrv_smc_ctrl_wakeup_interrupt_enable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ctrl_wakeup_interrupt_enable </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a921f7d74cf2d64c107b216a683fc86a7">sdrv_smc_t</a> * </td>
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<td class="paramname"><em>smc_ctrl</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> </td>
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<td class="paramname"><em>core</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>irq_num</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enable wakeup interrupt for specific core. </p>
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<p >This function enable interrupt to wakeup specific core in low power mode.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_ctrl</td><td>SMC controller instance </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">core</td><td>core id </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">irq_num</td><td>irq number </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a345e3747fb34c9cfe847deb112acb74f" name="a345e3747fb34c9cfe847deb112acb74f"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a345e3747fb34c9cfe847deb112acb74f">◆ </a></span>sdrv_smc_debug_monitor()</h2>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<td class="memname">uint32_t sdrv_smc_debug_monitor </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#abb3f522232c2289164ab47c888105aa0">sdrv_smc_debug_mux_e</a> </td>
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<td class="paramname"><em>dbg_mux</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<p>Debug for SMC status. </p>
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<p >This function choose a debug output type, and return the debug value.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">dbg_mux</td><td>mux defined in sdrv_smc_debug_mux_e. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>uint32_t </dd></dl>
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</div>
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</div>
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<a id="acd746bca097cb92aae602614dc441144" name="acd746bca097cb92aae602614dc441144"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#acd746bca097cb92aae602614dc441144">◆ </a></span>sdrv_smc_domain_misc_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_domain_misc_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> </td>
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<td class="paramname"><em>domain</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>lp_trans_req</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>irq_mask_dly</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>ill_trans_wkup_en</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Config SMC Saf or AP domain misc. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">domain</td><td>SDRV_SMC_SAF or SDRV_SMC_AP. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">lp_trans_req</td><td>LP mode transition request. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">irq_mask_dly</td><td>Interrupt mask delay. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">ill_trans_wkup_en</td><td>Swm illegal transfer wakeup enable. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a59c7425c21e828c1cd3f7ced88d69730" name="a59c7425c21e828c1cd3f7ced88d69730"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a59c7425c21e828c1cd3f7ced88d69730">◆ </a></span>sdrv_smc_domain_timeout_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_domain_timeout_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> </td>
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<td class="paramname"><em>domain</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a8b8ac896699c2665c6444bd520de9cf4">sdrv_smc_domain_timeout_t</a> * </td>
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<td class="paramname"><em>config</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Config SMC Saf or AP domain timeout setting. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">domain</td><td>SDRV_SMC_SAF or SDRV_SMC_AP. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>domain timeout setting config. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="ab059a6c17479ff6d96ee877b61f477cd" name="ab059a6c17479ff6d96ee877b61f477cd"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ab059a6c17479ff6d96ee877b61f477cd">◆ </a></span>sdrv_smc_get_core_wakeup_irq_status()</h2>
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<div class="memitem">
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<td class="memname">uint32_t sdrv_smc_get_core_wakeup_irq_status </td>
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<td>(</td>
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<td class="paramtype">void </td>
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<td class="paramname"></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<p>Get wakeup core irq status. </p>
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<dl class="section return"><dt>Returns</dt><dd>uint32_t bit0:cr5_saf, bit1:cr5_sp0, bit2:cr5_sp1, bit3:cr5_sx0, bit4:cr5_sx1 </dd></dl>
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</div>
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</div>
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<a id="aac7372b792999b33c7c391bebb33fd82" name="aac7372b792999b33c7c391bebb33fd82"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aac7372b792999b33c7c391bebb33fd82">◆ </a></span>sdrv_smc_global_control_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_global_control_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a809608502ea90f54c704aba21e92eb4d">sdrv_smc_global_control_t</a> * </td>
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<td class="paramname"><em>config</em></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Config Safety/AP domain global control setting. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>global control setting. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a46ee66318bfe63f1178e6f0a34cf93ef" name="a46ee66318bfe63f1178e6f0a34cf93ef"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a46ee66318bfe63f1178e6f0a34cf93ef">◆ </a></span>sdrv_smc_illegal_status_monitor()</h2>
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<td class="memname">uint32_t sdrv_smc_illegal_status_monitor </td>
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<td>(</td>
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<td class="paramtype">void </td>
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<td class="paramname"></td><td>)</td>
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<td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Get SMC illegal transition event monitor status. </p>
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<dl class="section return"><dt>Returns</dt><dd>uint32_t </dd></dl>
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</div>
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</div>
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<a id="a8f578b39af1be0cd2adceedd0ddc3ab3" name="a8f578b39af1be0cd2adceedd0ddc3ab3"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a8f578b39af1be0cd2adceedd0ddc3ab3">◆ </a></span>sdrv_smc_interrupt_monitor_status()</h2>
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<div class="memitem">
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<td class="memname">bool sdrv_smc_interrupt_monitor_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> </td>
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<td class="paramname"><em>core</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>irq_num</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Get specific core interrupt status in interrupt monitor register. </p>
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<p >This function get the interrupt status for specific core.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
|
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<tr><td class="paramdir">[in]</td><td class="paramname">core</td><td>core id </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">irq_num</td><td>irq number </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>true represents irq occurs, false represents no interrupt occurs. </dd></dl>
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</div>
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</div>
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<a id="ab602b19b5751f8a13448c1c840c018ee" name="ab602b19b5751f8a13448c1c840c018ee"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ab602b19b5751f8a13448c1c840c018ee">◆ </a></span>sdrv_smc_lowpower_enable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_lowpower_enable </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> </td>
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<td class="paramname"><em>domain</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
|
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<td></td>
|
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<td class="paramtype">bool </td>
|
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<td class="paramname"><em>enable</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enable or disable low power for specific domain. </p>
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<p >This function enable or disable low power mode for a domain. If enabled, when all CPUs enter wfi, SMC will start low power procedure.</p>
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<dl class="params"><dt>Parameters</dt><dd>
|
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<table class="params">
|
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<tr><td class="paramdir">[in]</td><td class="paramname">domain</td><td>safety or ap domain </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>true/false </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a4006be66b5aaf9c3d53e5a488dc98007" name="a4006be66b5aaf9c3d53e5a488dc98007"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a4006be66b5aaf9c3d53e5a488dc98007">◆ </a></span>sdrv_smc_power_switch_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_power_switch_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a> </td>
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<td class="paramname"><em>power_switch</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#af78cd18eab2cb72950ca48b72d59e76a">sdrv_smc_mode_e</a> </td>
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<td class="paramname"><em>mode</em>, </td>
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</tr>
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<tr>
|
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<td class="paramkey"></td>
|
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<td></td>
|
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<td class="paramtype">bool </td>
|
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<td class="paramname"><em>power_down_enable</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Control power switchs in low power mode. </p>
|
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<p >This function configures power switch states (on or off) in domain low power mode.</p>
|
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<dl class="params"><dt>Parameters</dt><dd>
|
|
<table class="params">
|
|
<tr><td class="paramdir">[in]</td><td class="paramname">power_switch</td><td>The power switch to configure. </td></tr>
|
|
<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>The SMC low power mode to configure the switch for. </td></tr>
|
|
<tr><td class="paramdir">[in]</td><td class="paramname">power_down_enable</td><td>True to turn off the switch in low power mode. False to leave the power switch on in lower power mode. </td></tr>
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</table>
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</dd>
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</dl>
|
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="ad9758c2e8aa0f687f9089ac5e26cd65e" name="ad9758c2e8aa0f687f9089ac5e26cd65e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ad9758c2e8aa0f687f9089ac5e26cd65e">◆ </a></span>sdrv_smc_power_switch_delay_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_power_switch_delay_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a> </td>
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<td class="paramname"><em>power_switch</em>, </td>
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</tr>
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<tr>
|
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<td class="paramkey"></td>
|
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<td></td>
|
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<td class="paramtype">uint32_t </td>
|
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<td class="paramname"><em>iso_en</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>pg</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>po</em>, </td>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>iso_dis</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</div><div class="memdoc">
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<p>Config Power switch in low power delay control. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">power_switch</td><td>The power switch to configure. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">iso_en</td><td>isolation enable delay between LP process start to X_iso_en pose. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">pg</td><td>power gate delay between X_iso_en pose to X_pwr_gate pose. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">po</td><td>power on delay between RUN process start to X_pwr_gate nege. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">iso_dis</td><td>isolation disable delay between X_pwr_gate nege to X_iso_en_nege. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a0a1279a5e564b20b4a2b3174e4efb80a" name="a0a1279a5e564b20b4a2b3174e4efb80a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a0a1279a5e564b20b4a2b3174e4efb80a">◆ </a></span>sdrv_smc_pre_divider_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_pre_divider_config </td>
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<td>(</td>
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<td class="paramtype">uint16_t </td>
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<td class="paramname"><em>div_32k</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint8_t </td>
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<td class="paramname"><em>div_24m</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Set pre-divider number for 24M and 32K clock. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">div_32k</td><td>pre div number for clk32k. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">div_24m</td><td>pre div number for clk24m. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="abdabef5878f4bcbed88486983b97b0d8" name="abdabef5878f4bcbed88486983b97b0d8"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#abdabef5878f4bcbed88486983b97b0d8">◆ </a></span>sdrv_smc_ram_lowpower_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_ram_lowpower_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a234e369ae73fd526d0a67d22ba499be1">sdrv_smc_ram_e</a> </td>
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<td class="paramname"><em>ram</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#af78cd18eab2cb72950ca48b72d59e76a">sdrv_smc_mode_e</a> </td>
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<td class="paramname"><em>mode</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>ram_mode</em> </td>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</div><div class="memdoc">
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<p>Configure low power modes for core RAM. </p>
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<p >This function configures low power modes for core RAMs, i.e, module interal RAM, CPU cache and TCM, in SMC sleep or hibernate modes.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">ram</td><td>RAM type. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>The SMC low power mode to configure RAM mode for. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">ram_mode</td><td>RAM mode in SMC low power mode. Possible values are: SDRV_SMC_CHIP_ENABLE SDRV_SMC_SELECTIVE_PRECHARGE SDRV_SMC_RETENTION_1 SDRV_SMC_RETENTION_2 SDRV_SMC_POWER_DOWN </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a32b16a30e58a26de09d8f6d0c3735b5e" name="a32b16a30e58a26de09d8f6d0c3735b5e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a32b16a30e58a26de09d8f6d0c3735b5e">◆ </a></span>sdrv_smc_rc24m_hibernate_enable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_rc24m_hibernate_enable </td>
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<td>(</td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<p>Configure RC oscillator state in hibernate mode. </p>
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<p >This function configures on chip 24M RC oscillator state in SMC hibernate mode.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>True to enable the RC oscillator in hibernate mode. False to turn off the oscillator in hibernate mode. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a333a67f3327876d2916e8b2a47518d04" name="a333a67f3327876d2916e8b2a47518d04"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a333a67f3327876d2916e8b2a47518d04">◆ </a></span>sdrv_smc_record_interrupt_monitor_status()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_record_interrupt_monitor_status </td>
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<td>(</td>
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<td class="paramtype">void </td>
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<td class="paramname"></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<p>This function record monitor interrupt status when exit WFI. </p>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a62ec3044c615e7a1b057f829ab3848d6" name="a62ec3044c615e7a1b057f829ab3848d6"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a62ec3044c615e7a1b057f829ab3848d6">◆ </a></span>sdrv_smc_set_core_wakeup_ack()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_set_core_wakeup_ack </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>ack</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<p>Set core wakeup acknowledge. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">ack</td><td>bit0:cr5_saf, bit1:cr5_sp0, bit2:cr5_sp1, bit3:cr5_sx0, bit4:cr5_sx1 </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="ab27084695283bfd49df5bbf9af128ff3" name="ab27084695283bfd49df5bbf9af128ff3"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ab27084695283bfd49df5bbf9af128ff3">◆ </a></span>sdrv_smc_set_lowpower_mode()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_set_lowpower_mode </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> </td>
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<td class="paramname"><em>domain</em>, </td>
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</tr>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#af78cd18eab2cb72950ca48b72d59e76a">sdrv_smc_mode_e</a> </td>
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<td class="paramname"><em>mode</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>Set low power mode for specific domain. </p>
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<p >This function sets the low power mode of specific domain. The domain will enter required low power mode after its primary CPU and all CPUs belongs to this domain enters WFI.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">domain</td><td>Safety or AP domain </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>Sleep or hibernate after primary CPU WFI </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="add883d2291390667d7bb3de14c2a592d" name="add883d2291390667d7bb3de14c2a592d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#add883d2291390667d7bb3de14c2a592d">◆ </a></span>sdrv_smc_set_primary_core()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_set_primary_core </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a9d575fcc7c646e80a63e1ffc2b920243">sdrv_smc_domain_e</a> </td>
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<td class="paramname"><em>domain</em>, </td>
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<tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> </td>
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<td class="paramname"><em>id</em> </td>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Set primary core id for a power domain. </p>
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<p >This function sets primary core id for a domain. Only the primary CPU of one domain can configure SMC registers of this domain.</p>
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<dl class="params"><dt>Parameters</dt><dd>
|
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">domain</td><td>Safety or AP domain </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">id</td><td>core id </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="afa976b62e4f00aa2345ab58ded94aa63" name="afa976b62e4f00aa2345ab58ded94aa63"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#afa976b62e4f00aa2345ab58ded94aa63">◆ </a></span>sdrv_smc_smc_misc_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_smc_misc_config </td>
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<td>(</td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>lpbk_force_check_en</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>permission_err_en</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Config SMC misc. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">lpbk_force_check_en</td><td>lpbk force check enable, loopback wdt div number check without req/ack active. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">permission_err_en</td><td>enable for permission error as apbslverr. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="ab2097d1781c96bb90a792244da12ef99" name="ab2097d1781c96bb90a792244da12ef99"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ab2097d1781c96bb90a792244da12ef99">◆ </a></span>sdrv_smc_soc_misc_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_soc_misc_config </td>
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<td>(</td>
|
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<td class="paramtype">bool </td>
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<td class="paramname"><em>ill_trans_wkup_en</em></td><td>)</td>
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<td></td>
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</div><div class="memdoc">
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<p>Config SOC misc. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">ill_trans_wkup_en</td><td>Swm illegal transfer wakeup enable. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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<a id="a537821cf11af4ebed6fc76c03eb06fe7" name="a537821cf11af4ebed6fc76c03eb06fe7"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a537821cf11af4ebed6fc76c03eb06fe7">◆ </a></span>sdrv_smc_soc_swm_timeout_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_soc_swm_timeout_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a0265ee8df64a78504d5a71ecd3ece7dd">sdrv_smc_soc_timeout_t</a> * </td>
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<td class="paramname"><em>config</em></td><td>)</td>
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<td></td>
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</table>
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</div><div class="memdoc">
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<p>Set soc swm timeout setting. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>soc timeout settings. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<a id="a647ba2b325a954baf2ec7b19873612f7" name="a647ba2b325a954baf2ec7b19873612f7"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a647ba2b325a954baf2ec7b19873612f7">◆ </a></span>sdrv_smc_soc_wakeup_control_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_soc_wakeup_control_config </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a2664e0233e64841be2a42a8b4b56b574">sdrv_smc_soc_wakeup_ctrl_t</a> * </td>
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<td class="paramname"><em>config</em></td><td>)</td>
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<td></td>
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<p>Set soc wakeup control setting. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>soc wakeup control settings. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<a id="a571c30a692a1e77fb37c658177c8ecaf" name="a571c30a692a1e77fb37c658177c8ecaf"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a571c30a692a1e77fb37c658177c8ecaf">◆ </a></span>sdrv_smc_software_power_switch_gate_status()</h2>
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<td class="memname">bool sdrv_smc_software_power_switch_gate_status </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a> </td>
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<td class="paramname"><em>power_switch</em></td><td>)</td>
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<td></td>
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<p>Get power switch software power gate status. </p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">power_switch</td><td>The power switch to read. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>Power gate status. </dd></dl>
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</div>
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</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ac6254a2a6d4000e876a85fb3ef4a0ac6">◆ </a></span>sdrv_smc_status_monitor()</h2>
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<td class="memname">uint32_t sdrv_smc_status_monitor </td>
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<td>(</td>
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<td class="paramtype">void </td>
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<td class="paramname"></td><td>)</td>
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<td></td>
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<p>Get SWM status monitor register. </p>
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<p >This function get SOC/SAF/AP system work mode, futhermode, get SAF/AP internal system work mode.</p>
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<dl class="section return"><dt>Returns</dt><dd>uint32_t 0x1 Run, 0x2 Sleep, 0x4 Hibernate bit[3:0]-SAF_SWM, bit[7:4]-AP_SWM, bit[11:8]-SOC_SWM 0x1 Run, 0x2 LP Proc, 0x4 Run Proc, 0x8 LP bit[20:16]-SAF_INTER_SWM, bit[25:21]-AP_INTER_SWM </dd></dl>
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<a id="a440839a4458af3b1e3cee4cb556ce599" name="a440839a4458af3b1e3cee4cb556ce599"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a440839a4458af3b1e3cee4cb556ce599">◆ </a></span>sdrv_smc_timeout_status_monitor()</h2>
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<td class="memname">uint32_t sdrv_smc_timeout_status_monitor </td>
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<td>(</td>
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<td class="paramtype">void </td>
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<td class="paramname"></td><td>)</td>
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<p>Get SMC timeout event monitor status. </p>
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<dl class="section return"><dt>Returns</dt><dd>uint32_t </dd></dl>
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</div>
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<a id="a50fe83de0d16b9cabe6515b0e2fe6f48" name="a50fe83de0d16b9cabe6515b0e2fe6f48"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a50fe83de0d16b9cabe6515b0e2fe6f48">◆ </a></span>sdrv_smc_trigger_software_handshake()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_trigger_software_handshake </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#aa4544f83b8f2ffab016c4c18d315ad63">sdrv_smc_handshake_e</a> </td>
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<td class="paramname"><em>handshake</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>smc_swm</em> </td>
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</tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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<p>Software trigger SMC handshake with other module. </p>
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<p >This function trigger SMC handshake with other module, after handshake successful, that module will in low power mode, it will use configuration in low power mode.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">handshake</td><td>module to handshake </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">smc_swm</td><td>system work mode, can be following macro: SDRV_SMC_SWM_RUN SDRV_SMC_SWM_SLP SDRV_SMC_SWM_HIB SDRV_SMC_SWM_RTC </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="ad02128326b1f5e25179f9d9d74248d68" name="ad02128326b1f5e25179f9d9d74248d68"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ad02128326b1f5e25179f9d9d74248d68">◆ </a></span>sdrv_smc_trigger_software_power_switch()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_trigger_software_power_switch </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a4c8e260972003c664e03130a3b8577d8">sdrv_smc_power_switch_e</a> </td>
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<td class="paramname"><em>power_switch</em>, </td>
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</tr>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>power_down_enable</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<p>Software trigger SMC control power switch in run mode. </p>
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<p >This function can software override power switch value.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">power_switch</td><td>The power switch to configure. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">power_down_enable</td><td>True to turn off the switch, False to turn on the switch. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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</div>
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<a id="a96a60d3571a66d4a7a7587cd7da966ce" name="a96a60d3571a66d4a7a7587cd7da966ce"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a96a60d3571a66d4a7a7587cd7da966ce">◆ </a></span>sdrv_smc_trigger_software_ram_lowpower()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_trigger_software_ram_lowpower </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#a234e369ae73fd526d0a67d22ba499be1">sdrv_smc_ram_e</a> </td>
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<td class="paramname"><em>ram</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>ram_mode</em> </td>
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<td></td>
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<td>)</td>
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</div><div class="memdoc">
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<p>Software trigger SMC control core ram power down in run mode. </p>
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<p >This function can software override core ram power down value.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">ram</td><td>RAM type. </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">ram_mode</td><td>RAM mode override by software. Possible values are: SDRV_SMC_CHIP_ENABLE SDRV_SMC_SELECTIVE_PRECHARGE SDRV_SMC_RETENTION_1 SDRV_SMC_RETENTION_2 SDRV_SMC_POWER_DOWN </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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</div>
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<a id="af7b92154af0daadc43adbe05000886ef" name="af7b92154af0daadc43adbe05000886ef"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#af7b92154af0daadc43adbe05000886ef">◆ </a></span>sdrv_smc_wakeup_interrupt_disable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_wakeup_interrupt_disable </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> </td>
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<td class="paramname"><em>core</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>irq_num</em> </td>
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<td></td>
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<p>Disable wakeup interrupt for specific core. </p>
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<p >This function disable interrupt to wakeup specific core in low power mode.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">core</td><td>core id </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">irq_num</td><td>irq number </td></tr>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<a id="a63a56ec3dbcf99bf7ec772bc46e533b6" name="a63a56ec3dbcf99bf7ec772bc46e533b6"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a63a56ec3dbcf99bf7ec772bc46e533b6">◆ </a></span>sdrv_smc_wakeup_interrupt_enable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_smc_wakeup_interrupt_enable </td>
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<td>(</td>
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<td class="paramtype"><a class="el" href="sdrv__smc_8h.html#ae2d3768b5393309e1646099913e6dd77">sdrv_smc_core_e</a> </td>
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<td class="paramname"><em>core</em>, </td>
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<td class="paramtype">uint32_t </td>
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<p>Enable wakeup interrupt for specific core. </p>
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<p >This function enable interrupt to wakeup specific core in low power mode.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramdir">[in]</td><td class="paramname">core</td><td>core id </td></tr>
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<tr><td class="paramdir">[in]</td><td class="paramname">irq_num</td><td>irq number </td></tr>
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</dd>
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<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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