207 lines
6.6 KiB
C
207 lines
6.6 KiB
C
/*
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* pmu.h
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*
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* Copyright (c) 2019 Semidrive Semiconductor.
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* All rights reserved.
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*
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* Description: Cortex V7R Performance Monitor driver.
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*
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* Revision History:
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* -----------------
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*/
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#ifndef INCLUDE_ARCH_PMU_H
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#define INCLUDE_ARCH_PMU_H
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#include <types.h>
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#include <armv7-r/register.h>
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typedef enum pmu_evt_cntr {
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PMU_EVT_COUNTER1 = 0,
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PMU_EVT_COUNTER2 = 1,
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PMU_EVT_COUNTER3 = 2,
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} pmu_evt_cntr_e;
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typedef enum pmu_evt {
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PMU_EVT_SOFTWARE_INCREMENT = 0x0,
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PMU_EVT_ICACHE_MISS = 0x1,
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PMU_EVT_DCACHE_MISS = 0x3,
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PMU_EVT_DCACHE_ACCESS = 0x4,
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PMU_EVT_DATA_READ = 0x6,
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PMU_EVT_DATA_WRITE = 0x7,
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PMU_EVT_INSTRUCTION_EXECUTED = 0x8,
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PMU_EVT_DUAL_ISSUED_INSTUCTIONS = 0x5e,
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PMU_EVT_EXECPTION_TAKEN = 0x9,
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PMU_EVT_EXECPTION_RETURN = 0xa,
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PMU_EVT_CHANGE_CONTEXT_ID = 0xb,
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PMU_EVT_SW_CHANGE_PC = 0xc,
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PMU_EVT_BRANCH_IMMEDIATE = 0xd,
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PMU_EVT_PROCEDURE_RETURN = 0xe,
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PMU_EVT_UNALIGNED_ACCESS = 0xf,
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PMU_EVT_BRANCH_NOT_PREDICTED = 0x10,
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PMU_EVT_CYCLE_CNT = 0x11,
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PMU_EVT_BRANCH_PREDICTED = 0x12,
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PMU_EVT_STALL_INSTRUCTION = 0x40,
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PMU_EVT_STALL_DATA_DEPENDENCY = 0x41,
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PMU_EVT_DCACHE_WRITE_BACK = 0x42,
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PMU_EVT_EXT_MEMORY_REQ = 0x43,
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PMU_EVT_STALL_LSU_BUSY = 0x44,
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PMU_EVT_DRAIN_STORE_BUFFER = 0x45,
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PMU_EVT_FIQ_DISABLE_CYCLES = 0x46,
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PMU_EVT_IRQ_DISABLE_CYCLES = 0x47,
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PMU_EVT_ETMEXTOUTM0 = 0x48,
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PMU_EVT_ETMEXTOUTM1 = 0x49,
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PMU_EVT_ICACHE_TAG_ECCERR = 0x4a,
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PMU_EVT_ICACHE_DATA_ECCERR = 0x4b,
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PMU_EVT_DCACHE_TAG_ECCERR = 0x4c,
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PMU_EVT_DCACHE_DATA_ECCERR = 0x4d,
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PMU_EVT_TCM_ECCERR_PFU = 0x4e,
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PMU_EVT_TCM_ECCERR_LSU = 0x4f,
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PMU_EVT_STORE_BUFFER_MERGE = 0x50,
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PMU_EVT_LSU_STALL_BY_STORE_BUFFER = 0x51,
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PMU_EVT_LSU_STALL_BY_STORE_QUEUE = 0x52,
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PMU_EVT_INT_DIV = 0x53,
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PMU_EVT_STALL_CYCLE_BY_INT_DIV = 0x54,
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PMU_EVT_PLD_LINEFILL = 0x55,
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PMU_EVT_PLD_NO_LINEFILL = 0x56,
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PMU_EVT_NON_CACHEABLE_AXI_ACCESS = 0x57,
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PMU_EVT_ICACHE_ACCESS = 0x58,
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PMU_EVT_STORE_BUFFER_SLOT_ATTR_CONFLICT = 0x59,
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PMU_EVT_DUAL_ISSUE_CASE_A = 0x5a,
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PMU_EVT_DUAL_ISSUE_CASE_B1_B2_F2_F2D = 0x5b,
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PMU_EVT_DUAL_ISSUE_CASE_OTHER = 0x5c,
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PMU_EVT_DOUBLE_PRECISION_FLOAT_EXEC = 0x5d,
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PMU_EVT_DCACHE_DATA_FATAL_ECCERR = 0x60,
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PMU_EVT_DCACHE_TAG_FATAL_ECCERR = 0x61,
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PMU_EVT_PROCESSOR_LIVELOCK = 0x62,
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PMU_EVT_ATCM_MB_ECCERR = 0x64,
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PMU_EVT_B0TCM_MB_ECCERR = 0x65,
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PMU_EVT_B1TCM_MB_ECCERR = 0x66,
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PMU_EVT_ATCM_SB_ECCERR = 0x67,
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PMU_EVT_B0TCM_SB_ECCERR = 0x68,
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PMU_EVT_B1TCM_SB_ECCERR = 0x69,
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PMU_EVT_TCM_CORRECTABLE_ECCERR_LSU = 0x6a,
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PMU_EVT_TCM_CORRECTABLE_ECCERR_PFU = 0x6b,
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PMU_EVT_TCM_FATAL_ECCERR_AXI_SLAVE = 0x6c,
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PMU_EVT_TCM_CORRECTABLE_ECCERR_AXI_SLAVE = 0x6d,
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PMU_EVT_CORRECTABLE_EVENTS = 0x6e,
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PMU_EVT_FATAL_EVENTS = 0x6f,
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PMU_EVT_CORRECTABLE_BUS_FAULTS = 0x70,
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PMU_EVT_FATAL_BUS_FAULTS = 0x71,
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PMU_EVT_ACP_DCACHE_ACCESS = 0x72,
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PMU_EVT_ACP_DCACHE_INVALIDATE = 0x73,
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} pmu_evt_e;
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#define PMCR_E (1 << 0) /* pmu enable */
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#define PMCR_P (1 << 1) /* event counter reset */
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#define PMCR_C (1 << 2) /* cycle counter reset */
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#define PMCR_D (1 << 3) /* count every 64 clock cycles */
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#if CONFIG_ARM_WITH_PMU
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/* Enable the PMU. All counters are cleared. */
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static inline void pmu_enable(void)
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{
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uint32_t val = arm_read_pmcr();
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val |= PMCR_P | PMCR_C | PMCR_E;
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arm_write_pmcr(val);
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}
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/* Diable the PMU. All counters are cleared. */
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static inline void pmu_disable(void)
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{
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uint32_t val = arm_read_pmcr();
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val &= ~(PMCR_P | PMCR_C | PMCR_E);
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arm_write_pmcr(val);
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}
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/* Get cycle counter enable status */
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static inline bool pmu_cycle_cntr_status(void)
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{
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uint32_t val = arm_read_pmcntenset();
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return !!(val & (1U << 31));
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}
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/* Start cycle counter. Set div64 = true to count every
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* 64 clock cycles.
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*/
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static inline void pmu_start_cycle_cntr(bool div64)
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{
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uint32_t val = arm_read_pmcr();
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if (div64)
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val |= PMCR_D;
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else
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val &= ~PMCR_D;
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arm_write_pmcr(val);
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arm_write_pmcntenset(1U << 31);
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}
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/* Stop cycle counter. */
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static inline void pmu_stop_cycle_cntr(void)
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{
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arm_write_pmcntenclr(1U << 31);
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}
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/* Stop and clear the cycle counter. */
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static inline void pmu_stop_clear_cycle_cntr(void)
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{
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pmu_stop_cycle_cntr();
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arm_write_pmccntr(0);
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}
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/* Get cycle counter value. */
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static inline uint32_t pmu_get_cycle_cntr(void)
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{
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return arm_read_pmccntr();
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}
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/* Bind event counter to specific event and start it. */
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static inline void pmu_start_evt_cntr(pmu_evt_cntr_e cntr,
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pmu_evt_e evt)
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{
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arm_write_pmselr(cntr);
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arm_write_pmxevtyper(evt);
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arm_write_pmcntenset(1 << cntr);
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}
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/* Stop event counter without clearing. */
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static inline void pmu_stop_evt_cntr(pmu_evt_cntr_e cntr)
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{
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arm_write_pmcntenclr(1 << cntr);
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}
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/* Stop and clear the event counter. */
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static inline void pmu_stop_clear_evt_cntr(pmu_evt_cntr_e cntr)
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{
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pmu_stop_evt_cntr(cntr);
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arm_write_pmselr(cntr);
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arm_write_pmxevcntr(0);
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}
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/* Get event counter value. */
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static inline uint32_t pmu_get_evt_cntr(pmu_evt_cntr_e cntr)
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{
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arm_write_pmselr(cntr);
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return arm_read_pmxevcntr();
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}
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#else
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#define pmu_enable()
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#define pmu_disable()
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#define pmu_start_cycle_cntr(div64)
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#define pmu_stop_cycle_cntr()
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#define pmu_stop_clear_cycle_cntr()
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#define pmu_get_cycle_cntr()
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#define pmu_start_evt_cntr()
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#define pmu_stop_evt_cntr()
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#define pmu_stop_clear_evt_cntr()
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#define pmu_get_evt_cntr()
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#endif
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#endif /* ARCH_ARM_PMU_H */
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