/** * @file sdrv_pmu_reg.h * @brief Sdrv PMU head source. * * @copyright Copyright (c) 2022 Semidrive Semiconductor. * All rights reserved. */ #ifndef SDRV_TAISHAN_PMU_REG_H_ #define SDRV_TAISHAN_PMU_REG_H_ #define BC_VLD_WINDOW_OFF 0x0U #define FM_BC_VLD_WINDOW_BC_OFF_VLD_MAX (0xffU << 24U) #define FV_BC_VLD_WINDOW_BC_OFF_VLD_MAX(v) \ (((v) << 24U) & FM_BC_VLD_WINDOW_BC_OFF_VLD_MAX) #define GFV_BC_VLD_WINDOW_BC_OFF_VLD_MAX(v) \ (((v) & FM_BC_VLD_WINDOW_BC_OFF_VLD_MAX) >> 24U) #define FM_BC_VLD_WINDOW_BC_OFF_VLD_MIN (0xffU << 16U) #define FV_BC_VLD_WINDOW_BC_OFF_VLD_MIN(v) \ (((v) << 16U) & FM_BC_VLD_WINDOW_BC_OFF_VLD_MIN) #define GFV_BC_VLD_WINDOW_BC_OFF_VLD_MIN(v) \ (((v) & FM_BC_VLD_WINDOW_BC_OFF_VLD_MIN) >> 16U) #define FM_BC_VLD_WINDOW_BC_ON_VLD_MAX (0xffU << 8U) #define FV_BC_VLD_WINDOW_BC_ON_VLD_MAX(v) \ (((v) << 8U) & FM_BC_VLD_WINDOW_BC_ON_VLD_MAX) #define GFV_BC_VLD_WINDOW_BC_ON_VLD_MAX(v) \ (((v) & FM_BC_VLD_WINDOW_BC_ON_VLD_MAX) >> 8U) #define FM_BC_VLD_WINDOW_BC_ON_VLD_MIN (0xffU << 0U) #define FV_BC_VLD_WINDOW_BC_ON_VLD_MIN(v) \ (((v) << 0U) & FM_BC_VLD_WINDOW_BC_ON_VLD_MIN) #define GFV_BC_VLD_WINDOW_BC_ON_VLD_MIN(v) \ (((v) & FM_BC_VLD_WINDOW_BC_ON_VLD_MIN) >> 0U) #define BC_CTRL_SET_OFF 0x4U #define FM_BC_CTRL_SET_PWR_DWN_HW_REQ_ENABLE (0xffU << 24U) #define FV_BC_CTRL_SET_PWR_DWN_HW_REQ_ENABLE(v) \ (((v) << 24U) & FM_BC_CTRL_SET_PWR_DWN_HW_REQ_ENABLE) #define GFV_BC_CTRL_SET_PWR_DWN_HW_REQ_ENABLE(v) \ (((v) & FM_BC_CTRL_SET_PWR_DWN_HW_REQ_ENABLE) >> 24U) #define BM_BC_CTRL_SET_PWR_DWN_REQ_SOFT (0x01U << 23U) #define FM_BC_CTRL_SET_BC_FILTER_EDGE (0x3U << 21U) #define FV_BC_CTRL_SET_BC_FILTER_EDGE(v) \ (((v) << 21U) & FM_BC_CTRL_SET_BC_FILTER_EDGE) #define GFV_BC_CTRL_SET_BC_FILTER_EDGE(v) \ (((v) & FM_BC_CTRL_SET_BC_FILTER_EDGE) >> 21U) #define FM_BC_CTRL_SET_BC_FILTER_CNT (0xfU << 17U) #define FV_BC_CTRL_SET_BC_FILTER_CNT(v) \ (((v) << 17U) & FM_BC_CTRL_SET_BC_FILTER_CNT) #define GFV_BC_CTRL_SET_BC_FILTER_CNT(v) \ (((v) & FM_BC_CTRL_SET_BC_FILTER_CNT) >> 17U) #define FM_BC_CTRL_SET_BC_SAMPLE_INTERVAL (0x7U << 14U) #define FV_BC_CTRL_SET_BC_SAMPLE_INTERVAL(v) \ (((v) << 14U) & FM_BC_CTRL_SET_BC_SAMPLE_INTERVAL) #define GFV_BC_CTRL_SET_BC_SAMPLE_INTERVAL(v) \ (((v) & FM_BC_CTRL_SET_BC_SAMPLE_INTERVAL) >> 14U) #define BM_BC_CTRL_SET_BC_FILTER_BYPASS (0x01U << 13U) #define BM_BC_CTRL_SET_BC_DISABLE_LOCK (0x01U << 12U) #define BM_BC_CTRL_SET_BC_DISABLE (0x01U << 11U) #define BM_BC_CTRL_SET_BC_FSM_ENABLE (0x01U << 10U) #define BM_BC_CTRL_SET_BC_OFF_EDGE (0x01U << 9U) #define BM_BC_CTRL_SET_BC_ON_EDGE (0x01U << 8U) #define BM_BC_CTRL_SET_BC_OFF_POL (0x01U << 7U) #define BM_BC_CTRL_SET_BC_ON_POL (0x01U << 6U) #define BM_BC_CTRL_SET_BC_OFF_VLD_MAX_DISABLE (0x01U << 5U) #define BM_BC_CTRL_SET_BC_ON_VLD_MAX_DISABLE (0x01U << 4U) #define FM_BC_CTRL_SET_BC_CNT_UNIT (0xfU << 0U) #define FV_BC_CTRL_SET_BC_CNT_UNIT(v) \ (((v) << 0U) & FM_BC_CTRL_SET_BC_CNT_UNIT) #define GFV_BC_CTRL_SET_BC_CNT_UNIT(v) \ (((v) & FM_BC_CTRL_SET_BC_CNT_UNIT) >> 0U) #define WAKEUP_CTRL_OFF 0x8U #define BM_WAKEUP_CTRL_WKUP01_AND_ENABLE (0x01U << 31U) #define BM_WAKEUP_CTRL_WKUP1_DISABLE (0x01U << 30U) #define BM_WAKEUP_CTRL_WKUP0_DISABLE (0x01U << 29U) #define BM_WAKEUP_CTRL_WKUP1_POL (0x01U << 28U) #define BM_WAKEUP_CTRL_WKUP0_POL (0x01U << 27U) #define BM_WAKEUP_CTRL_WKUP1_EDGE (0x01U << 26U) #define BM_WAKEUP_CTRL_WKUP0_EDGE (0x01U << 25U) #define BM_WAKEUP_CTRL_WAKEUP_IN_RTC_LATCH (0x01U << 22U) #define BM_WAKEUP_CTRL_EXT_WAKEUP_EN (0x01U << 21U) #define BM_WAKEUP_CTRL_INT_WAKEUP_EN (0x01U << 20U) #define FM_WAKEUP_CTRL_WKUP1_FILTER_EDGE (0x3U << 18U) #define FV_WAKEUP_CTRL_WKUP1_FILTER_EDGE(v) \ (((v) << 18U) & FM_WAKEUP_CTRL_WKUP1_FILTER_EDGE) #define GFV_WAKEUP_CTRL_WKUP1_FILTER_EDGE(v) \ (((v) & FM_WAKEUP_CTRL_WKUP1_FILTER_EDGE) >> 18U) #define FM_WAKEUP_CTRL_WKUP1_FILTER_CNT (0xfU << 14U) #define FV_WAKEUP_CTRL_WKUP1_FILTER_CNT(v) \ (((v) << 14U) & FM_WAKEUP_CTRL_WKUP1_FILTER_CNT) #define GFV_WAKEUP_CTRL_WKUP1_FILTER_CNT(v) \ (((v) & FM_WAKEUP_CTRL_WKUP1_FILTER_CNT) >> 14U) #define FM_WAKEUP_CTRL_WKUP1_SAMPLE_INTERVAL (0x7U << 11U) #define FV_WAKEUP_CTRL_WKUP1_SAMPLE_INTERVAL(v) \ (((v) << 11U) & FM_WAKEUP_CTRL_WKUP1_SAMPLE_INTERVAL) #define GFV_WAKEUP_CTRL_WKUP1_SAMPLE_INTERVAL(v) \ (((v) & FM_WAKEUP_CTRL_WKUP1_SAMPLE_INTERVAL) >> 11U) #define BM_WAKEUP_CTRL_WKUP1_FILTER_BYPASS (0x01U << 10U) #define FM_WAKEUP_CTRL_WKUP0_FILTER_EDGE (0x3U << 8U) #define FV_WAKEUP_CTRL_WKUP0_FILTER_EDGE(v) \ (((v) << 8U) & FM_WAKEUP_CTRL_WKUP0_FILTER_EDGE) #define GFV_WAKEUP_CTRL_WKUP0_FILTER_EDGE(v) \ (((v) & FM_WAKEUP_CTRL_WKUP0_FILTER_EDGE) >> 8U) #define FM_WAKEUP_CTRL_WKUP0_FILTER_CNT (0xfU << 4U) #define FV_WAKEUP_CTRL_WKUP0_FILTER_CNT(v) \ (((v) << 4U) & FM_WAKEUP_CTRL_WKUP0_FILTER_CNT) #define GFV_WAKEUP_CTRL_WKUP0_FILTER_CNT(v) \ (((v) & FM_WAKEUP_CTRL_WKUP0_FILTER_CNT) >> 4U) #define FM_WAKEUP_CTRL_WKUP0_SAMPLE_INTERVAL (0x7U << 1U) #define FV_WAKEUP_CTRL_WKUP0_SAMPLE_INTERVAL(v) \ (((v) << 1U) & FM_WAKEUP_CTRL_WKUP0_SAMPLE_INTERVAL) #define GFV_WAKEUP_CTRL_WKUP0_SAMPLE_INTERVAL(v) \ (((v) & FM_WAKEUP_CTRL_WKUP0_SAMPLE_INTERVAL) >> 1U) #define BM_WAKEUP_CTRL_WKUP0_FILTER_BYPASS (0x01U << 0U) #define PGM_CTRL_OFF 0xcU #define FM_PGM_CTRL_PWR_ON_WDT_EN (0xfU << 28U) #define FV_PGM_CTRL_PWR_ON_WDT_EN(v) \ (((v) << 28U) & FM_PGM_CTRL_PWR_ON_WDT_EN) #define GFV_PGM_CTRL_PWR_ON_WDT_EN(v) \ (((v) & FM_PGM_CTRL_PWR_ON_WDT_EN) >> 28U) #define FM_PGM_CTRL_POR_TW (0xfU << 24U) #define FV_PGM_CTRL_POR_TW(v) \ (((v) << 24U) & FM_PGM_CTRL_POR_TW) #define GFV_PGM_CTRL_POR_TW(v) \ (((v) & FM_PGM_CTRL_POR_TW) >> 24U) #define FM_PGM_CTRL_POR_TW_ADJ (0x3U << 22U) #define FV_PGM_CTRL_POR_TW_ADJ(v) \ (((v) << 22U) & FM_PGM_CTRL_POR_TW_ADJ) #define GFV_PGM_CTRL_POR_TW_ADJ(v) \ (((v) & FM_PGM_CTRL_POR_TW_ADJ) >> 22U) #define FM_PGM_CTRL_HW_REBOOT_REQ_EN (0x3U << 20U) #define FV_PGM_CTRL_HW_REBOOT_REQ_EN(v) \ (((v) << 20U) & FM_PGM_CTRL_HW_REBOOT_REQ_EN) #define GFV_PGM_CTRL_HW_REBOOT_REQ_EN(v) \ (((v) & FM_PGM_CTRL_HW_REBOOT_REQ_EN) >> 20U) #define FM_PGM_CTRL_WDT_DIV (0xfU << 16U) #define FV_PGM_CTRL_WDT_DIV(v) \ (((v) << 16U) & FM_PGM_CTRL_WDT_DIV) #define GFV_PGM_CTRL_WDT_DIV(v) \ (((v) & FM_PGM_CTRL_WDT_DIV) >> 16U) #define FM_PGM_CTRL_PWR_ON3_WDT_CNT (0xfU << 12U) #define FV_PGM_CTRL_PWR_ON3_WDT_CNT(v) \ (((v) << 12U) & FM_PGM_CTRL_PWR_ON3_WDT_CNT) #define GFV_PGM_CTRL_PWR_ON3_WDT_CNT(v) \ (((v) & FM_PGM_CTRL_PWR_ON3_WDT_CNT) >> 12U) #define FM_PGM_CTRL_PWR_ON2_WDT_CNT (0xfU << 8U) #define FV_PGM_CTRL_PWR_ON2_WDT_CNT(v) \ (((v) << 8U) & FM_PGM_CTRL_PWR_ON2_WDT_CNT) #define GFV_PGM_CTRL_PWR_ON2_WDT_CNT(v) \ (((v) & FM_PGM_CTRL_PWR_ON2_WDT_CNT) >> 8U) #define FM_PGM_CTRL_PWR_ON1_WDT_CNT (0xfU << 4U) #define FV_PGM_CTRL_PWR_ON1_WDT_CNT(v) \ (((v) << 4U) & FM_PGM_CTRL_PWR_ON1_WDT_CNT) #define GFV_PGM_CTRL_PWR_ON1_WDT_CNT(v) \ (((v) & FM_PGM_CTRL_PWR_ON1_WDT_CNT) >> 4U) #define FM_PGM_CTRL_PWR_ON0_WDT_CNT (0xfU << 0U) #define FV_PGM_CTRL_PWR_ON0_WDT_CNT(v) \ (((v) << 0U) & FM_PGM_CTRL_PWR_ON0_WDT_CNT) #define GFV_PGM_CTRL_PWR_ON0_WDT_CNT(v) \ (((v) & FM_PGM_CTRL_PWR_ON0_WDT_CNT) >> 0U) #define PWR_CTRL_SET0_OFF 0x10U #define FM_PWR_CTRL_SET0_RTC_PWR_CTRL_SET0 (0xffU << 24U) #define FV_PWR_CTRL_SET0_RTC_PWR_CTRL_SET0(v) \ (((v) << 24U) & FM_PWR_CTRL_SET0_RTC_PWR_CTRL_SET0) #define GFV_PWR_CTRL_SET0_RTC_PWR_CTRL_SET0(v) \ (((v) & FM_PWR_CTRL_SET0_RTC_PWR_CTRL_SET0) >> 24U) #define FM_PWR_CTRL_SET0_RUN_PWR_CTRL_SET0 (0xffU << 16U) #define FV_PWR_CTRL_SET0_RUN_PWR_CTRL_SET0(v) \ (((v) << 16U) & FM_PWR_CTRL_SET0_RUN_PWR_CTRL_SET0) #define GFV_PWR_CTRL_SET0_RUN_PWR_CTRL_SET0(v) \ (((v) & FM_PWR_CTRL_SET0_RUN_PWR_CTRL_SET0) >> 16U) #define FM_PWR_CTRL_SET0_SLEEP_PWR_CTRL_SET0 (0xffU << 8U) #define FV_PWR_CTRL_SET0_SLEEP_PWR_CTRL_SET0(v) \ (((v) << 8U) & FM_PWR_CTRL_SET0_SLEEP_PWR_CTRL_SET0) #define GFV_PWR_CTRL_SET0_SLEEP_PWR_CTRL_SET0(v) \ (((v) & FM_PWR_CTRL_SET0_SLEEP_PWR_CTRL_SET0) >> 8U) #define FM_PWR_CTRL_SET0_HIBERNATE_PWR_CTRL_SET0 (0xffU << 0U) #define FV_PWR_CTRL_SET0_HIBERNATE_PWR_CTRL_SET0(v) \ (((v) << 0U) & FM_PWR_CTRL_SET0_HIBERNATE_PWR_CTRL_SET0) #define GFV_PWR_CTRL_SET0_HIBERNATE_PWR_CTRL_SET0(v) \ (((v) & FM_PWR_CTRL_SET0_HIBERNATE_PWR_CTRL_SET0) >> 0U) #define PWR_CTRL_SET1_OFF 0x14U #define BM_PWR_CTRL_SET1_PWR_UP_RUN_MIN_DELAY_ENABLE (0x01U << 31U) #define BM_PWR_CTRL_SET1_SLEEP_RUN_MIN_DELAY_ENABLE (0x01U << 30U) #define BM_PWR_CTRL_SET1_HIBERNATE_RUN_MIN_DELAY_ENABLE (0x01U << 29U) #define FM_PWR_CTRL_SET1_PWR_CTRL_POL (0xfU << 20U) #define FV_PWR_CTRL_SET1_PWR_CTRL_POL(v) \ (((v) << 20U) & FM_PWR_CTRL_SET1_PWR_CTRL_POL) #define GFV_PWR_CTRL_SET1_PWR_CTRL_POL(v) \ (((v) & FM_PWR_CTRL_SET1_PWR_CTRL_POL) >> 20U) #define FM_PWR_CTRL_SET1_SW_PWR_CTRL_EN (0xfU << 12U) #define FV_PWR_CTRL_SET1_SW_PWR_CTRL_EN(v) \ (((v) << 12U) & FM_PWR_CTRL_SET1_SW_PWR_CTRL_EN) #define GFV_PWR_CTRL_SET1_SW_PWR_CTRL_EN(v) \ (((v) & FM_PWR_CTRL_SET1_SW_PWR_CTRL_EN) >> 12U) #define FM_PWR_CTRL_SET1_SW_PWR_CTRL (0xfU << 8U) #define FV_PWR_CTRL_SET1_SW_PWR_CTRL(v) \ (((v) << 8U) & FM_PWR_CTRL_SET1_SW_PWR_CTRL) #define GFV_PWR_CTRL_SET1_SW_PWR_CTRL(v) \ (((v) & FM_PWR_CTRL_SET1_SW_PWR_CTRL) >> 8U) #define PWR_UP_PWR_CTRL_DELAY_OFF 0x18U #define FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_MAX (0x3U << 30U) #define FV_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_MAX(v) \ (((v) << 30U) & FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_MAX) #define GFV_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_MAX(v) \ (((v) & FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_MAX) >> 30U) #define FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_DELAY (0xffffffU << 0U) #define FV_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_DELAY(v) \ (((v) << 0U) & FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_DELAY) #define GFV_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_DELAY(v) \ (((v) & FM_PWR_UP_PWR_CTRL_DELAY_PWR_UP_PWR_CTRL_DELAY) >> 0U) #define RUN_PWR_CTRL_DELAY_OFF 0x1cU #define FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_MAX (0x3U << 30U) #define FV_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_MAX(v) \ (((v) << 30U) & FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_MAX) #define GFV_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_MAX(v) \ (((v) & FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_MAX) >> 30U) #define FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_DELAY (0xffffffU << 0U) #define FV_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_DELAY(v) \ (((v) << 0U) & FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_DELAY) #define GFV_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_DELAY(v) \ (((v) & FM_RUN_PWR_CTRL_DELAY_RUN_PWR_CTRL_DELAY) >> 0U) #define SLEEP_PWR_CTRL_DELAY_OFF 0x20U #define FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_MAX (0x3U << 30U) #define FV_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_MAX(v) \ (((v) << 30U) & FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_MAX) #define GFV_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_MAX(v) \ (((v) & FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_MAX) >> 30U) #define FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_DELAY (0xffffffU << 0U) #define FV_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_DELAY(v) \ (((v) << 0U) & FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_DELAY) #define GFV_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_DELAY(v) \ (((v) & FM_SLEEP_PWR_CTRL_DELAY_SLEEP_PWR_CTRL_DELAY) >> 0U) #define HIBERNATE_PWR_CTRL_DELAY_OFF 0x24U #define FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_MAX (0x3U << 30U) #define FV_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_MAX(v) \ (((v) << 30U) & FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_MAX) #define GFV_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_MAX(v) \ (((v) & FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_MAX) >> 30U) #define FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_DELAY (0xffffffU << 0U) #define FV_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_DELAY(v) \ (((v) << 0U) & FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_DELAY) #define GFV_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_DELAY(v) \ (((v) & FM_HIBERNATE_PWR_CTRL_DELAY_HIBERNATE_PWR_CTRL_DELAY) >> 0U) #define RTC_PWR_CTRL_DELAY_OFF 0x28U #define FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_MAX (0x3U << 30U) #define FV_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_MAX(v) \ (((v) << 30U) & FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_MAX) #define GFV_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_MAX(v) \ (((v) & FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_MAX) >> 30U) #define FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_DELAY (0xffffffU << 0U) #define FV_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_DELAY(v) \ (((v) << 0U) & FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_DELAY) #define GFV_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_DELAY(v) \ (((v) & FM_RTC_PWR_CTRL_DELAY_RTC_PWR_CTRL_DELAY) >> 0U) #define RUN_PWR_ON_SET_OFF 0x30U #define FM_RUN_PWR_ON_SET_RUN_PWR_ON_SET (0x3ffffU << 0U) #define FV_RUN_PWR_ON_SET_RUN_PWR_ON_SET(v) \ (((v) << 0U) & FM_RUN_PWR_ON_SET_RUN_PWR_ON_SET) #define GFV_RUN_PWR_ON_SET_RUN_PWR_ON_SET(v) \ (((v) & FM_RUN_PWR_ON_SET_RUN_PWR_ON_SET) >> 0U) #define SLEEP_PWR_ON_SET_OFF 0x34U #define FM_SLEEP_PWR_ON_SET_SLEEP_PWR_ON_SET (0x3ffffU << 0U) #define FV_SLEEP_PWR_ON_SET_SLEEP_PWR_ON_SET(v) \ (((v) << 0U) & FM_SLEEP_PWR_ON_SET_SLEEP_PWR_ON_SET) #define GFV_SLEEP_PWR_ON_SET_SLEEP_PWR_ON_SET(v) \ (((v) & FM_SLEEP_PWR_ON_SET_SLEEP_PWR_ON_SET) >> 0U) #define HIBERNATE_PWR_ON_SET_OFF 0x38U #define FM_HIBERNATE_PWR_ON_SET_HIBERNATE_PWR_ON_SET (0x3ffffU << 0U) #define FV_HIBERNATE_PWR_ON_SET_HIBERNATE_PWR_ON_SET(v) \ (((v) << 0U) & FM_HIBERNATE_PWR_ON_SET_HIBERNATE_PWR_ON_SET) #define GFV_HIBERNATE_PWR_ON_SET_HIBERNATE_PWR_ON_SET(v) \ (((v) & FM_HIBERNATE_PWR_ON_SET_HIBERNATE_PWR_ON_SET) >> 0U) #define RTC_PWR_ON_SET_OFF 0x3cU #define BM_RTC_PWR_ON_SET_RTC_TO_OFF_SF_HV_PG_DISABLE (0x01U << 31U) #define BM_RTC_PWR_ON_SET_RTC_TO_OFF_SF_LV_PG_DISABLE (0x01U << 30U) #define BM_RTC_PWR_ON_SET_RTC_TO_OFF_AP_HV_PG_DISABLE (0x01U << 29U) #define BM_RTC_PWR_ON_SET_RTC_TO_OFF_AP_LV_PG_DISABLE (0x01U << 28U) #define FM_RTC_PWR_ON_SET_RTC_PWR_ON_SET (0x3ffffU << 0U) #define FV_RTC_PWR_ON_SET_RTC_PWR_ON_SET(v) \ (((v) << 0U) & FM_RTC_PWR_ON_SET_RTC_PWR_ON_SET) #define GFV_RTC_PWR_ON_SET_RTC_PWR_ON_SET(v) \ (((v) & FM_RTC_PWR_ON_SET_RTC_PWR_ON_SET) >> 0U) #define PWR_UP_PWR_ON_DELAY_OFF 0x40U #define FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_AP_MAX (0x3U << 30U) #define FV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_AP_MAX(v) \ (((v) << 30U) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_AP_MAX) #define GFV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_AP_MAX(v) \ (((v) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_AP_MAX) >> 30U) #define FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_SF_MAX (0x3U << 28U) #define FV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_SF_MAX(v) \ (((v) << 28U) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_SF_MAX) #define GFV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_SF_MAX(v) \ (((v) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_SF_MAX) >> 28U) #define FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_DELAY (0xffffffU << 0U) #define FV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_DELAY(v) \ (((v) << 0U) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_DELAY) #define GFV_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_DELAY(v) \ (((v) & FM_PWR_UP_PWR_ON_DELAY_PWR_UP_PWR_ON_DELAY) >> 0U) #define RUN_PWR_ON_DELAY_OFF 0x44U #define FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_AP_MAX (0x3U << 30U) #define FV_RUN_PWR_ON_DELAY_RUN_PWR_ON_AP_MAX(v) \ (((v) << 30U) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_AP_MAX) #define GFV_RUN_PWR_ON_DELAY_RUN_PWR_ON_AP_MAX(v) \ (((v) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_AP_MAX) >> 30U) #define FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_SF_MAX (0x3U << 28U) #define FV_RUN_PWR_ON_DELAY_RUN_PWR_ON_SF_MAX(v) \ (((v) << 28U) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_SF_MAX) #define GFV_RUN_PWR_ON_DELAY_RUN_PWR_ON_SF_MAX(v) \ (((v) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_SF_MAX) >> 28U) #define FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_DELAY (0xffffffU << 0U) #define FV_RUN_PWR_ON_DELAY_RUN_PWR_ON_DELAY(v) \ (((v) << 0U) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_DELAY) #define GFV_RUN_PWR_ON_DELAY_RUN_PWR_ON_DELAY(v) \ (((v) & FM_RUN_PWR_ON_DELAY_RUN_PWR_ON_DELAY) >> 0U) #define SLEEP_PWR_ON_DELAY_OFF 0x48U #define FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_AP_MAX (0x3U << 30U) #define FV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_AP_MAX(v) \ (((v) << 30U) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_AP_MAX) #define GFV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_AP_MAX(v) \ (((v) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_AP_MAX) >> 30U) #define FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_SF_MAX (0x3U << 28U) #define FV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_SF_MAX(v) \ (((v) << 28U) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_SF_MAX) #define GFV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_SF_MAX(v) \ (((v) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_SF_MAX) >> 28U) #define FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_DELAY (0xffffffU << 0U) #define FV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_DELAY(v) \ (((v) << 0U) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_DELAY) #define GFV_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_DELAY(v) \ (((v) & FM_SLEEP_PWR_ON_DELAY_SLEEP_PWR_ON_DELAY) >> 0U) #define HIBERNATE_PWR_ON_DELAY_OFF 0x4cU #define FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_AP_MAX (0x3U << 30U) #define FV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_AP_MAX(v) \ (((v) << 30U) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_AP_MAX) #define GFV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_AP_MAX(v) \ (((v) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_AP_MAX) >> 30U) #define FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_SF_MAX (0x3U << 28U) #define FV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_SF_MAX(v) \ (((v) << 28U) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_SF_MAX) #define GFV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_SF_MAX(v) \ (((v) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_SF_MAX) >> 28U) #define FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_DELAY (0xffffffU << 0U) #define FV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_DELAY(v) \ (((v) << 0U) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_DELAY) #define GFV_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_DELAY(v) \ (((v) & FM_HIBERNATE_PWR_ON_DELAY_HIBERNATE_PWR_ON_DELAY) >> 0U) #define RTC_PWR_ON_DELAY_OFF 0x50U #define FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_AP_MAX (0x3U << 30U) #define FV_RTC_PWR_ON_DELAY_RTC_PWR_ON_AP_MAX(v) \ (((v) << 30U) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_AP_MAX) #define GFV_RTC_PWR_ON_DELAY_RTC_PWR_ON_AP_MAX(v) \ (((v) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_AP_MAX) >> 30U) #define FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_SF_MAX (0x3U << 28U) #define FV_RTC_PWR_ON_DELAY_RTC_PWR_ON_SF_MAX(v) \ (((v) << 28U) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_SF_MAX) #define GFV_RTC_PWR_ON_DELAY_RTC_PWR_ON_SF_MAX(v) \ (((v) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_SF_MAX) >> 28U) #define FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_DELAY (0xffffffU << 0U) #define FV_RTC_PWR_ON_DELAY_RTC_PWR_ON_DELAY(v) \ (((v) << 0U) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_DELAY) #define GFV_RTC_PWR_ON_DELAY_RTC_PWR_ON_DELAY(v) \ (((v) & FM_RTC_PWR_ON_DELAY_RTC_PWR_ON_DELAY) >> 0U) #define SW_OVERRIDE_OFF 0x54U #define BM_SW_OVERRIDE_SW_SF_HV_ISO_EN_ASSERT (0x01U << 31U) #define BM_SW_OVERRIDE_SW_SF_HV_ISO_EN_DEASSERT (0x01U << 30U) #define BM_SW_OVERRIDE_SW_AP_HV_ISO_EN_ASSERT (0x01U << 29U) #define BM_SW_OVERRIDE_SW_AP_HV_ISO_EN_DEASSERT (0x01U << 28U) #define BM_SW_OVERRIDE_SW_SF_POR_B_ASSERT (0x01U << 27U) #define BM_SW_OVERRIDE_SW_SF_POR_B_DEASSERT (0x01U << 26U) #define BM_SW_OVERRIDE_SW_SF_ISO_EN_ASSERT (0x01U << 25U) #define BM_SW_OVERRIDE_SW_SF_ISO_EN_DEASSERT (0x01U << 24U) #define BM_SW_OVERRIDE_SW_AP_POR_B_ASSERT (0x01U << 23U) #define BM_SW_OVERRIDE_SW_AP_POR_B_DEASSERT (0x01U << 22U) #define BM_SW_OVERRIDE_SW_AP_ISO_EN_ASSERT (0x01U << 21U) #define BM_SW_OVERRIDE_SW_AP_ISO_EN_DEASSERT (0x01U << 20U) #define BM_SW_OVERRIDE_SW_AP_HV_ISO_EN_EN (0x01U << 19U) #define BM_SW_OVERRIDE_SW_AP_HV_ISO_EN (0x01U << 18U) #define BM_SW_OVERRIDE_SW_SF_HV_ISO_EN_EN (0x01U << 17U) #define BM_SW_OVERRIDE_SW_SF_HV_ISO_EN (0x01U << 16U) #define BM_SW_OVERRIDE_SW_AP_ISO_EN_EN (0x01U << 15U) #define BM_SW_OVERRIDE_SW_AP_ISO_EN (0x01U << 14U) #define BM_SW_OVERRIDE_SW_SF_ISO_EN_EN (0x01U << 13U) #define BM_SW_OVERRIDE_SW_SF_ISO_EN (0x01U << 12U) #define BM_SW_OVERRIDE_SW_AP_POR_B_EN (0x01U << 11U) #define BM_SW_OVERRIDE_SW_AP_POR_B (0x01U << 10U) #define BM_SW_OVERRIDE_SW_SF_POR_B_EN (0x01U << 9U) #define BM_SW_OVERRIDE_SW_SF_POR_B (0x01U << 8U) #define FM_SW_OVERRIDE_SW_PWR_ON_EN (0xfU << 4U) #define FV_SW_OVERRIDE_SW_PWR_ON_EN(v) \ (((v) << 4U) & FM_SW_OVERRIDE_SW_PWR_ON_EN) #define GFV_SW_OVERRIDE_SW_PWR_ON_EN(v) \ (((v) & FM_SW_OVERRIDE_SW_PWR_ON_EN) >> 4U) #define FM_SW_OVERRIDE_SW_PWR_ON (0xfU << 0U) #define FV_SW_OVERRIDE_SW_PWR_ON(v) \ (((v) << 0U) & FM_SW_OVERRIDE_SW_PWR_ON) #define GFV_SW_OVERRIDE_SW_PWR_ON(v) \ (((v) & FM_SW_OVERRIDE_SW_PWR_ON) >> 0U) #define PG_LP_MODE_CTRL_OFF 0x58U #define FM_PG_LP_MODE_CTRL_RUN_LP_MODE (0xfU << 28U) #define FV_PG_LP_MODE_CTRL_RUN_LP_MODE(v) \ (((v) << 28U) & FM_PG_LP_MODE_CTRL_RUN_LP_MODE) #define GFV_PG_LP_MODE_CTRL_RUN_LP_MODE(v) \ (((v) & FM_PG_LP_MODE_CTRL_RUN_LP_MODE) >> 28U) #define FM_PG_LP_MODE_CTRL_SLEEP_LP_MODE (0xfU << 24U) #define FV_PG_LP_MODE_CTRL_SLEEP_LP_MODE(v) \ (((v) << 24U) & FM_PG_LP_MODE_CTRL_SLEEP_LP_MODE) #define GFV_PG_LP_MODE_CTRL_SLEEP_LP_MODE(v) \ (((v) & FM_PG_LP_MODE_CTRL_SLEEP_LP_MODE) >> 24U) #define FM_PG_LP_MODE_CTRL_HIBERNATE_LP_MODE (0xfU << 20U) #define FV_PG_LP_MODE_CTRL_HIBERNATE_LP_MODE(v) \ (((v) << 20U) & FM_PG_LP_MODE_CTRL_HIBERNATE_LP_MODE) #define GFV_PG_LP_MODE_CTRL_HIBERNATE_LP_MODE(v) \ (((v) & FM_PG_LP_MODE_CTRL_HIBERNATE_LP_MODE) >> 20U) #define BM_PG_LP_MODE_CTRL_RTC_LV_MONITOR (0x01U << 17U) #define BM_PG_LP_MODE_CTRL_RTC_HV_MONITOR (0x01U << 16U) #define BM_PG_LP_MODE_CTRL_RTC_SF_HV_PG_DISABLE (0x01U << 15U) #define BM_PG_LP_MODE_CTRL_SF_HV_PG_DISABLE (0x01U << 14U) #define BM_PG_LP_MODE_CTRL_RTC_AP_HV_PG_DISABLE (0x01U << 13U) #define BM_PG_LP_MODE_CTRL_AP_HV_PG_DISABLE (0x01U << 12U) #define BM_PG_LP_MODE_CTRL_RTC_SF_LV_PG_DISABLE (0x01U << 11U) #define BM_PG_LP_MODE_CTRL_SF_LV_PG_DISABLE (0x01U << 10U) #define BM_PG_LP_MODE_CTRL_RTC_AP_LV_PG_DISABLE (0x01U << 9U) #define BM_PG_LP_MODE_CTRL_AP_LV_PG_DISABLE (0x01U << 8U) #define FM_PG_LP_MODE_CTRL_SW_LP_MODE_EN (0xfU << 4U) #define FV_PG_LP_MODE_CTRL_SW_LP_MODE_EN(v) \ (((v) << 4U) & FM_PG_LP_MODE_CTRL_SW_LP_MODE_EN) #define GFV_PG_LP_MODE_CTRL_SW_LP_MODE_EN(v) \ (((v) & FM_PG_LP_MODE_CTRL_SW_LP_MODE_EN) >> 4U) #define FM_PG_LP_MODE_CTRL_SW_LP_MODE (0xfU << 0U) #define FV_PG_LP_MODE_CTRL_SW_LP_MODE(v) \ (((v) << 0U) & FM_PG_LP_MODE_CTRL_SW_LP_MODE) #define GFV_PG_LP_MODE_CTRL_SW_LP_MODE(v) \ (((v) & FM_PG_LP_MODE_CTRL_SW_LP_MODE) >> 0U) #define MIN_DELAY_STATE_TRAN_OFF 0x5cU #define FM_MIN_DELAY_STATE_TRAN_HIBERNATE_RUN_DELAY_MIN (0x3fU << 24U) #define FV_MIN_DELAY_STATE_TRAN_HIBERNATE_RUN_DELAY_MIN(v) \ (((v) << 24U) & FM_MIN_DELAY_STATE_TRAN_HIBERNATE_RUN_DELAY_MIN) #define GFV_MIN_DELAY_STATE_TRAN_HIBERNATE_RUN_DELAY_MIN(v) \ (((v) & FM_MIN_DELAY_STATE_TRAN_HIBERNATE_RUN_DELAY_MIN) >> 24U) #define FM_MIN_DELAY_STATE_TRAN_SLEEP_RUN_DELAY_MIN (0x3fU << 16U) #define FV_MIN_DELAY_STATE_TRAN_SLEEP_RUN_DELAY_MIN(v) \ (((v) << 16U) & FM_MIN_DELAY_STATE_TRAN_SLEEP_RUN_DELAY_MIN) #define GFV_MIN_DELAY_STATE_TRAN_SLEEP_RUN_DELAY_MIN(v) \ (((v) & FM_MIN_DELAY_STATE_TRAN_SLEEP_RUN_DELAY_MIN) >> 16U) #define FM_MIN_DELAY_STATE_TRAN_PWR_UP_RUN_DELAY_MIN (0x3fU << 8U) #define FV_MIN_DELAY_STATE_TRAN_PWR_UP_RUN_DELAY_MIN(v) \ (((v) << 8U) & FM_MIN_DELAY_STATE_TRAN_PWR_UP_RUN_DELAY_MIN) #define GFV_MIN_DELAY_STATE_TRAN_PWR_UP_RUN_DELAY_MIN(v) \ (((v) & FM_MIN_DELAY_STATE_TRAN_PWR_UP_RUN_DELAY_MIN) >> 8U) #define FM_MIN_DELAY_STATE_TRAN_PWR_ON_ISO_DELAY (0x3fU << 0U) #define FV_MIN_DELAY_STATE_TRAN_PWR_ON_ISO_DELAY(v) \ (((v) << 0U) & FM_MIN_DELAY_STATE_TRAN_PWR_ON_ISO_DELAY) #define GFV_MIN_DELAY_STATE_TRAN_PWR_ON_ISO_DELAY(v) \ (((v) & FM_MIN_DELAY_STATE_TRAN_PWR_ON_ISO_DELAY) >> 0U) #define LP_CTRL_ON_FRC_OFF 0x60U #define BM_LP_CTRL_ON_FRC_PWR_ON3_ASSERT (0x01U << 23U) #define BM_LP_CTRL_ON_FRC_PWR_ON2_ASSERT (0x01U << 22U) #define BM_LP_CTRL_ON_FRC_PWR_ON1_ASSERT (0x01U << 21U) #define BM_LP_CTRL_ON_FRC_PWR_ON0_ASSERT (0x01U << 20U) #define BM_LP_CTRL_ON_FRC_PWR_ON3_DEASSERT (0x01U << 19U) #define BM_LP_CTRL_ON_FRC_PWR_ON2_DEASSERT (0x01U << 18U) #define BM_LP_CTRL_ON_FRC_PWR_ON1_DEASSERT (0x01U << 17U) #define BM_LP_CTRL_ON_FRC_PWR_ON0_DEASSERT (0x01U << 16U) #define BM_LP_CTRL_ON_FRC_PWR_CTRL3_ASSERT (0x01U << 15U) #define BM_LP_CTRL_ON_FRC_PWR_CTRL2_ASSERT (0x01U << 14U) #define BM_LP_CTRL_ON_FRC_PWR_CTRL1_ASSERT (0x01U << 13U) #define BM_LP_CTRL_ON_FRC_PWR_CTRL0_ASSERT (0x01U << 12U) #define BM_LP_CTRL_ON_FRC_PWR_CTRL3_DEASSERT (0x01U << 11U) #define BM_LP_CTRL_ON_FRC_PWR_CTRL2_DEASSERT (0x01U << 10U) #define BM_LP_CTRL_ON_FRC_PWR_CTRL1_DEASSERT (0x01U << 9U) #define BM_LP_CTRL_ON_FRC_PWR_CTRL0_DEASSERT (0x01U << 8U) #define BM_LP_CTRL_ON_FRC_LP_MODE3_ASSERT (0x01U << 7U) #define BM_LP_CTRL_ON_FRC_LP_MODE2_ASSERT (0x01U << 6U) #define BM_LP_CTRL_ON_FRC_LP_MODE1_ASSERT (0x01U << 5U) #define BM_LP_CTRL_ON_FRC_LP_MODE0_ASSERT (0x01U << 4U) #define BM_LP_CTRL_ON_FRC_LP_MODE3_DEASSERT (0x01U << 3U) #define BM_LP_CTRL_ON_FRC_LP_MODE2_DEASSERT (0x01U << 2U) #define BM_LP_CTRL_ON_FRC_LP_MODE1_DEASSERT (0x01U << 1U) #define BM_LP_CTRL_ON_FRC_LP_MODE0_DEASSERT (0x01U << 0U) #define PMU_SW_RESET_OFF 0x64U #define FM_PMU_SW_RESET_PWR_DOWN_WAKEUP_EN (0x3U << 23U) #define FV_PMU_SW_RESET_PWR_DOWN_WAKEUP_EN(v) \ (((v) << 23U) & FM_PMU_SW_RESET_PWR_DOWN_WAKEUP_EN) #define GFV_PMU_SW_RESET_PWR_DOWN_WAKEUP_EN(v) \ (((v) & FM_PMU_SW_RESET_PWR_DOWN_WAKEUP_EN) >> 23U) #define BM_PMU_SW_RESET_PWR_DOWN_WAKEUP_TST (0x01U << 22U) #define BM_PMU_SW_RESET_PMU_AP_POR_B_TOGGLE (0x01U << 5U) #define BM_PMU_SW_RESET_PMU_SF_POR_B_TOGGLE (0x01U << 4U) #define BM_PMU_SW_RESET_PMU_SW_RESET_LOCK (0x01U << 1U) #define BM_PMU_SW_RESET_PMU_SW_RESET (0x01U << 0U) #define PMU_INT_OFF 0x68U #define FM_PMU_INT_PMU_INT_EN (0x1fffU << 16U) #define FV_PMU_INT_PMU_INT_EN(v) \ (((v) << 16U) & FM_PMU_INT_PMU_INT_EN) #define GFV_PMU_INT_PMU_INT_EN(v) \ (((v) & FM_PMU_INT_PMU_INT_EN) >> 16U) #define BM_PMU_INT_PWR_DOWN_REQ (0x01U << 12U) #define BM_PMU_INT_SWM_FATAL (0x01U << 11U) #define BM_PMU_INT_SWM_WARN (0x01U << 10U) #define BM_PMU_INT_RSV1 (0x01U << 9U) #define BM_PMU_INT_RSV0 (0x01U << 8U) #define BM_PMU_INT_LOCKSTEP_ERR_REBOOTED (0x01U << 7U) #define BM_PMU_INT_HIBERNATE_TO_RUN_REBOOTED (0x01U << 6U) #define BM_PMU_INT_SLEEP_TO_RUN_REBOOTED (0x01U << 5U) #define BM_PMU_INT_PWRUP_TO_RUN_REBOOTED (0x01U << 4U) #define BM_PMU_INT_PWR_ON3_WDT_ERR (0x01U << 3U) #define BM_PMU_INT_PWR_ON2_WDT_ERR (0x01U << 2U) #define BM_PMU_INT_PWR_ON1_WDT_ERR (0x01U << 1U) #define BM_PMU_INT_PWR_ON0_WDT_ERR (0x01U << 0U) #define PMU_COR_UNCOR_INT_OFF 0x6cU #define BM_PMU_COR_UNCOR_INT_PMU_COR_INT_EN (0x01U << 24U) #define FM_PMU_COR_UNCOR_INT_PMU_UNCOR_INT_EN (0x1fU << 16U) #define FV_PMU_COR_UNCOR_INT_PMU_UNCOR_INT_EN(v) \ (((v) << 16U) & FM_PMU_COR_UNCOR_INT_PMU_UNCOR_INT_EN) #define GFV_PMU_COR_UNCOR_INT_PMU_UNCOR_INT_EN(v) \ (((v) & FM_PMU_COR_UNCOR_INT_PMU_UNCOR_INT_EN) >> 16U) #define BM_PMU_COR_UNCOR_INT_PMU_PWDATA_COR_ERR (0x01U << 8U) #define BM_PMU_COR_UNCOR_INT_PMU_PWDATA_FATAL_ERR (0x01U << 4U) #define BM_PMU_COR_UNCOR_INT_PMU_PWDATA_UNC_ERR (0x01U << 3U) #define BM_PMU_COR_UNCOR_INT_PMU_PADDR_UNC_ERR (0x01U << 2U) #define BM_PMU_COR_UNCOR_INT_PMU_PN_PAIR_ERR (0x01U << 1U) #define BM_PMU_COR_UNCOR_INT_PMU_LOCKSTEP_ERR (0x01U << 0U) #define SRCS_BITS_OFF 0x70U #define FM_SRCS_BITS_SRCS_BITS (0xffffffffU << 0U) #define FV_SRCS_BITS_SRCS_BITS(v) \ (((v) << 0U) & FM_SRCS_BITS_SRCS_BITS) #define GFV_SRCS_BITS_SRCS_BITS(v) \ (((v) & FM_SRCS_BITS_SRCS_BITS) >> 0U) #define SRCS_BITS_SET_OFF 0x74U #define FM_SRCS_BITS_SET_SRCS_BITS (0xffffffffU << 0U) #define FV_SRCS_BITS_SET_SRCS_BITS(v) \ (((v) << 0U) & FM_SRCS_BITS_SET_SRCS_BITS) #define GFV_SRCS_BITS_SET_SRCS_BITS(v) \ (((v) & FM_SRCS_BITS_SET_SRCS_BITS) >> 0U) #define SRCS_BITS_CLR_OFF 0x78U #define FM_SRCS_BITS_CLR_SRCS_BITS (0xffffffffU << 0U) #define FV_SRCS_BITS_CLR_SRCS_BITS(v) \ (((v) << 0U) & FM_SRCS_BITS_CLR_SRCS_BITS) #define GFV_SRCS_BITS_CLR_SRCS_BITS(v) \ (((v) & FM_SRCS_BITS_CLR_SRCS_BITS) >> 0U) #define SRCS_BITS_TOG_OFF 0x7cU #define FM_SRCS_BITS_TOG_SRCS_BITS (0xffffffffU << 0U) #define FV_SRCS_BITS_TOG_SRCS_BITS(v) \ (((v) << 0U) & FM_SRCS_BITS_TOG_SRCS_BITS) #define GFV_SRCS_BITS_TOG_SRCS_BITS(v) \ (((v) & FM_SRCS_BITS_TOG_SRCS_BITS) >> 0U) #define PMU_DOWN_UP_STATUS_OFF 0x80U #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE11 (0x01U << 15U) #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE10 (0x01U << 14U) #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE9 (0x01U << 13U) #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE8 (0x01U << 12U) #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE7 (0x01U << 11U) #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE6 (0x01U << 10U) #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE5 (0x01U << 9U) #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE4 (0x01U << 8U) #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE3 (0x01U << 7U) #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE2 (0x01U << 6U) #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE1 (0x01U << 5U) #define BM_PMU_DOWN_UP_STATUS_PWR_DWN_SOURCE0 (0x01U << 4U) #define BM_PMU_DOWN_UP_STATUS_WAKEUP_SOURCE3 (0x01U << 3U) #define BM_PMU_DOWN_UP_STATUS_WAKEUP_SOURCE2 (0x01U << 2U) #define BM_PMU_DOWN_UP_STATUS_WAKEUP_SOURCE1 (0x01U << 1U) #define BM_PMU_DOWN_UP_STATUS_WAKEUP_SOURCE0 (0x01U << 0U) #define PMU_STATE_OFF 0x84U #define BM_PMU_STATE_RTC_AP_HV_PG (0x01U << 15U) #define BM_PMU_STATE_RTC_AP_LV_PG (0x01U << 14U) #define BM_PMU_STATE_RTC_SF_HV_PG (0x01U << 13U) #define BM_PMU_STATE_RTC_SF_LV_PG (0x01U << 12U) #define BM_PMU_STATE_AP_HV_PG (0x01U << 11U) #define BM_PMU_STATE_AP_LV_PG (0x01U << 10U) #define BM_PMU_STATE_SF_HV_PG (0x01U << 9U) #define BM_PMU_STATE_SF_LV_PG (0x01U << 8U) #define FM_PMU_STATE_PWR_RDY (0xfU << 4U) #define FV_PMU_STATE_PWR_RDY(v) \ (((v) << 4U) & FM_PMU_STATE_PWR_RDY) #define GFV_PMU_STATE_PWR_RDY(v) \ (((v) & FM_PMU_STATE_PWR_RDY) >> 4U) #define FM_PMU_STATE_PMU_STATE (0x7U << 0U) #define FV_PMU_STATE_PMU_STATE(v) \ (((v) << 0U) & FM_PMU_STATE_PMU_STATE) #define GFV_PMU_STATE_PMU_STATE(v) \ (((v) & FM_PMU_STATE_PMU_STATE) >> 0U) #define ERR_INJECTION_OFF 0x88U #define BM_ERR_INJECTION_ERR_INJ_EN (0x01U << 31U) #define FM_ERR_INJECTION_ERR_INJ_EN_SEL (0xffU << 16U) #define FV_ERR_INJECTION_ERR_INJ_EN_SEL(v) \ (((v) << 16U) & FM_ERR_INJECTION_ERR_INJ_EN_SEL) #define GFV_ERR_INJECTION_ERR_INJ_EN_SEL(v) \ (((v) & FM_ERR_INJECTION_ERR_INJ_EN_SEL) >> 16U) #define FM_ERR_INJECTION_ERR_INJECT_BITS (0xffU << 0U) #define FV_ERR_INJECTION_ERR_INJECT_BITS(v) \ (((v) << 0U) & FM_ERR_INJECTION_ERR_INJECT_BITS) #define GFV_ERR_INJECTION_ERR_INJECT_BITS(v) \ (((v) & FM_ERR_INJECTION_ERR_INJECT_BITS) >> 0U) #define ERR_INJECTION_WDATA_OFF 0x8cU #define FM_ERR_INJECTION_WDATA_ERR_INJECTION_WDATA (0xffffffffU << 0U) #define FV_ERR_INJECTION_WDATA_ERR_INJECTION_WDATA(v) \ (((v) << 0U) & FM_ERR_INJECTION_WDATA_ERR_INJECTION_WDATA) #define GFV_ERR_INJECTION_WDATA_ERR_INJECTION_WDATA(v) \ (((v) & FM_ERR_INJECTION_WDATA_ERR_INJECTION_WDATA) >> 0U) #define ISTC_DEBUG_OFF 0xf0U #define FM_ISTC_DEBUG_ISTC_DEBUG (0xffffffffU << 0U) #define FV_ISTC_DEBUG_ISTC_DEBUG(v) \ (((v) << 0U) & FM_ISTC_DEBUG_ISTC_DEBUG) #define GFV_ISTC_DEBUG_ISTC_DEBUG(v) \ (((v) & FM_ISTC_DEBUG_ISTC_DEBUG) >> 0U) #define PMU_LOCKSTEP_STATUS_OFF 0x8000U #define FM_PMU_LOCKSTEP_STATUS_CUR_RD_ADDR (0xffffU << 16U) #define FV_PMU_LOCKSTEP_STATUS_CUR_RD_ADDR(v) \ (((v) << 16U) & FM_PMU_LOCKSTEP_STATUS_CUR_RD_ADDR) #define GFV_PMU_LOCKSTEP_STATUS_CUR_RD_ADDR(v) \ (((v) & FM_PMU_LOCKSTEP_STATUS_CUR_RD_ADDR) >> 16U) #define BM_PMU_LOCKSTEP_STATUS_PRE2_RD_UPDATE (0x01U << 2U) #define BM_PMU_LOCKSTEP_STATUS_PRE_RD_UPDATE (0x01U << 1U) #define BM_PMU_LOCKSTEP_STATUS_CUR_RD_UPDATE (0x01U << 0U) #define PMU_APB_INT_OFF 0x8004U #define BM_PMU_APB_INT_APB_PN_CHK_ERR (0x01U << 3U) #define BM_PMU_APB_INT_APB_PCTL_UNC_ERR (0x01U << 2U) #define BM_PMU_APB_INT_APB_PADDR_UNC_ERR (0x01U << 1U) #define BM_PMU_APB_INT_APB_LKSTEP_ERR (0x01U << 0U) #define PMU_APB_INT_EN_OFF 0x8008U #define BM_PMU_APB_INT_EN_APB_PN_CHK_ERR_EN (0x01U << 3U) #define BM_PMU_APB_INT_EN_APB_PCTL_UNC_ERR_EN (0x01U << 2U) #define BM_PMU_APB_INT_EN_APB_PADDR_UNC_ERR_EN (0x01U << 1U) #define BM_PMU_APB_INT_EN_APB_LKSTEP_ERR_EN (0x01U << 0U) #define APB_ERR_INJECTION_OFF 0x800cU #define BM_APB_ERR_INJECTION_APB_ERROR_INJ_EN (0x01U << 8U) #define BM_APB_ERR_INJECTION_APB_ERROR_INJ_SEL (0x01U << 7U) #define FM_APB_ERR_INJECTION_APB_ERROR_INJ_BIT (0x7fU << 0U) #define FV_APB_ERR_INJECTION_APB_ERROR_INJ_BIT(v) \ (((v) << 0U) & FM_APB_ERR_INJECTION_APB_ERROR_INJ_BIT) #define GFV_APB_ERR_INJECTION_APB_ERROR_INJ_BIT(v) \ (((v) & FM_APB_ERR_INJECTION_APB_ERROR_INJ_BIT) >> 0U) #endif /* SDRV_TAISHAN_PMU_REG_H_ */