502 lines
21 KiB
C
502 lines
21 KiB
C
/** ************************************************************************************************
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* SEMIDRIVE Copyright Statement
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* Copyright (c) SEMIDRIVE. All rights reserved
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*
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* This software and all rights therein are owned by SEMIDRIVE, and are
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* protected by copyright law and other relevant laws, regulations and
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* protection. Without SEMIDRIVE's prior written consent and/or related rights,
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* please do not use this software or any potion thereof in any form or by any
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* means. You may not reproduce, modify or distribute this software except in
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* compliance with the License. Unless required by applicable law or agreed to
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* in writing, software distributed under the License is distributed on
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* an 'AS IS' basis, WITHOUT WARRANTIES OF ANY KIND, either express or implied.
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*
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**************************************************************************************************/
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/** ************************************************************************************************
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* \file sdrv_firewall_mpc.c
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* \brief SSDK Firewall MPC Driver
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*
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* <table>
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* <tr><th>Date <th>Version
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* <tr><td>2023/11/29 <td>1.0.0
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* </table>
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**************************************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************************************
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* Include header files
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**************************************************************************************************/
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#include <reg.h>
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#include "sdrv_firewall_mpc.h"
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/***************************************************************************************************
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* Private Macro definition
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**************************************************************************************************/
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/** \brief Address alignment. */
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#define MPC_REGION_ADDR(addr) ((uint32_t)(addr) >> 12U)
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/** \brief The address offset of the domain0 ~ 3 permissions register
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* for the different memory port.
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*/
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#define MPC_DOM_PER0(n) ((uint32_t)((uint32_t)(n)*0xCU))
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/** \brief The address offset of the domain4 ~ 7 permissions register \
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* for the different memory port. \
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*/ \
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#define MPC_DOM_PER1(n) \
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((uint32_t)(0x4U + ((uint32_t)(n)*0xCU)))
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/** \brief The mask of the permission lock. */
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#define MPC_DOM_PER_LOCK_MASK (0xFFU)
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/** \brief The address offset of the permission lock register. */
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#define MPC_DOM_PER_LOCK(n) ((uint32_t)(0x8U + ((uint32_t)(n)*0xCU)))
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/** \brief The bit offset of the domain0. */
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#define DOM_PER_DOMAIN0_BIT (4U)
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/** \brief The bit offset of the domain1. */
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#define DOM_PER_DOMAIN1_BIT (8U + 4U)
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/** \brief The bit offset of the domain2. */
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#define DOM_PER_DOMAIN2_BIT (16U + 4U)
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/** \brief The bit offset of the domain3. */
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#define DOM_PER_DOMAIN3_BIT (24U + 4U)
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/** \brief The bit offset of the domain4. */
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#define DOM_PER_DOMAIN4_BIT (4U)
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/** \brief The bit offset of the domain5. */
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#define DOM_PER_DOMAIN5_BIT (8U + 4U)
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/** \brief The bit offset of the domain6. */
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#define DOM_PER_DOMAIN6_BIT (16U + 4U)
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/** \brief The bit offset of the domain7. */
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#define DOM_PER_DOMAIN7_BIT (24U + 4U)
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/** \brief The address offset of the region start address register. */
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#define MPC_RGN_START_ADDR(n) (uint32_t)((0x140U + ((uint32_t)(n)*0x10U)))
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/** \brief The address offset of the region end address register. */
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#define MPC_RGN_END_ADDR(n) (uint32_t)((0x144U + ((uint32_t)(n)*0x10U)))
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/** \brief The bit mask of enabling region configuration. */
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#define MPC_RGN_ENABLE (0x1UL << 30U)
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/** \brief The bit mask of locking region configuration. */
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#define MPC_RGN_LOCK (0x1UL << 31U)
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/** \brief The address offset of the region low limit address register. */
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#define RGN_LOW_LIM(n) (uint32_t)((0x148U + ((uint32_t)(n)*0x10U)))
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/** \brief The address offset of the region up limit address register. */
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#define RGN_UP_LIM(n) (uint32_t)((0x14CU + ((uint32_t)(n)*0x10U)))
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/** \brief The address offset of the interrupt register of the specified memory
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* port. */
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#define MPC_FUNC_PORT_OFFSET_ADDR(portId) \
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((uint32_t)((uint32_t)(portId)*0x400U))
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/** \brief The address offset of the interrupt status register. */
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#define MPC_FUNC_INT_STA (uint32_t)(0x2E0U)
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/** \brief The address offset of the interrupt register of the specified memory
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* port. */
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#define MPC_FUNC_INT_STA_OFFSET_ADDR(portId) \
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((uint32_t)((uint32_t)(portId)*0x400U))
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/** \brief The address offset of the interrupt control register. */
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#define MPC_FUNC_INT_STA_EN ((uint32_t)0x2E4U)
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/** \brief The address offset of the interrupt signal register. */
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#define MPC_FUNC_INT_SIG_EN ((uint32_t)0x2E8U)
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/** \brief The bit mask of setting register access error. */
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#define MPC_REG_ACS_ERR (0x1U << 1U)
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/** \brief The bit mask of setting memory access error. */
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#define MPC_MEM_ACS_ERR (0x1U)
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/** \brief The address offset of the response error register. */
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#define MPC_RESP_ERR_DIS ((uint32_t)0x2F0U)
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/** \brief The bit mask of locking the response error configuration. */
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#define MPC_RESP_ERR_DIS_LOCK (0x1UL << 31U)
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/** \brief The bit mask of disabling the response error feature. */
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#define MPC_RESP_ERR_DIS_DIS (0x1UL)
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/** \brief Address alignment. */
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#define MPC_REGION_ADDR(addr) ((uint32_t)(addr) >> 12U)
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#ifdef CONFIG_E3
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/** \brief The base address of the sf firewall sem error scr. */
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#define FIREWALL_SCR_SF_BASE (0xF0681028U)
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/** \brief The bit mask of firewall Sem error. */
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#define FIREWALL_SCR_SF_APB_MAC_ENB_BIT (0xFFU << 4)
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#endif /* CONFIG_E3 */
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/***************************************************************************************************
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* Private Function Declarations
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**************************************************************************************************/
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static status_t mpc_per_region(uint32_t base,
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const sdrv_mpc_memport_cfg_t *memory);
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/***************************************************************************************************
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* Global Function Declarations
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**************************************************************************************************/
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/**
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* @brief Configure the permission of memory port regions in MPC module.
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*
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* This function configure memory ports in MPC module.
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* The permissions of memory regions in MPC module should be locked after
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* configuring.
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*
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* @param[in] base the address of the MAC module.
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* @param[in] mpc_cfg The configuration of memory.
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* @param[in] memport_num The number of memory port.
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*
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* @return The result of the MPC initialization function.
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* @details - return FIREWALL_E_OK : initializa MPC success.
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* - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
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* - return FIREWALL_E_MPC_PORT_NUM : The number of memory port is
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* unvalid.
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*/
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status_t sdrv_firewall_mpc_configure(uint32_t base,
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const sdrv_mpc_memport_cfg_t *mpc_cfg,
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uint32_t memport_num)
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{
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status_t ret_val = FIREWALL_E_OK;
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uint8_t port_num;
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/* #10 Check the parameters. */
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if (NULL == mpc_cfg)
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{
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ret_val = FIREWALL_E_NULL_POINTER;
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}
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else if (FIREWALL_MPC_MEMPORT_MAXNUM < memport_num)
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{
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ret_val = FIREWALL_E_MPC_PORT_NUM;
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}
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else
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{
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for (port_num = 0; port_num < memport_num; port_num++)
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{
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#ifdef CONFIG_E3
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/* Disable sem error check. */
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if (FIREWALL_MPC_GAMA_ADDR_OFFSET == mpc_cfg[port_num].base_offset)
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{
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writel(readl(FIREWALL_SCR_SF_BASE) &
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(~FIREWALL_SCR_SF_APB_MAC_ENB_BIT),
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FIREWALL_SCR_SF_BASE);
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}
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#endif /* #ifdef CONFIG_E3 */
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/* Configure all regions of the memory port. */
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ret_val = mpc_per_region(base, &mpc_cfg[port_num]);
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if (FIREWALL_E_OK != ret_val)
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{
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#ifdef CONFIG_E3
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/* Enable sem error check. */
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if (FIREWALL_MPC_GAMA_ADDR_OFFSET ==
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mpc_cfg[port_num].base_offset)
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{
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writel(readl(FIREWALL_SCR_SF_BASE) |
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FIREWALL_SCR_SF_APB_MAC_ENB_BIT,
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FIREWALL_SCR_SF_BASE);
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}
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#endif /* #ifdef CONFIG_E3 */
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break;
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}
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#if (1U == FIREWALL_INTERRUPT_EN)
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/* #30 Turn on inturrupt when illegal access. */
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writel(MPC_REG_ACS_ERR | MPC_MEM_ACS_ERR,
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base + mpc_cfg[port_num].base_offset + MPC_FUNC_INT_STA_EN);
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writel(MPC_REG_ACS_ERR | MPC_MEM_ACS_ERR,
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base + mpc_cfg[port_num].base_offset + MPC_FUNC_INT_SIG_EN);
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#endif /** #if (1U == FIREWALL_INTERRUPT_EN) */
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#if (1U != FIREWALL_RESPONSE_ERROR_EN)
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/* #40 Disable respone error when illegal access, and lock this
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* configuration. */
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/* disable respone error when illegal access */
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writel(MPC_RESP_ERR_DIS_DIS,
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base + mpc_cfg[port_num].base_offset + MPC_RESP_ERR_DIS);
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writel(MPC_RESP_ERR_DIS_DIS | MPC_RESP_ERR_DIS_LOCK,
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base + mpc_cfg[port_num].base_offset + MPC_RESP_ERR_DIS);
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#endif /** #if (1U != FIREWALL_RESPONSE_ERROR_EN) */
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#ifdef CONFIG_E3
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/* Enable sem error check. */
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if (FIREWALL_MPC_GAMA_ADDR_OFFSET == mpc_cfg[port_num].base_offset)
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{
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writel(readl(FIREWALL_SCR_SF_BASE) |
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FIREWALL_SCR_SF_APB_MAC_ENB_BIT,
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FIREWALL_SCR_SF_BASE);
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}
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#endif /* #ifdef CONFIG_E3 */
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}
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}
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return ret_val;
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}
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/**
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* @brief Lock MPC configuration.
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*
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* @param[in] base the address of the MAC module.
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*/
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void sdrv_firewall_mpc_lock(uint32_t base)
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{
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uint32_t port_base;
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uint8_t port_num;
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for (port_num = 0U; port_num < FIREWALL_MPC_MEMPORT_MAXNUM; ++port_num)
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{
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#ifdef CONFIG_E3
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if (FIREWALL_MPC_RESERVED_PORTID == port_num)
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{
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continue;
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}
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#endif /* #ifdef CONFIG_E3 */
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port_base = base + FIREWALL_MPC_ROMC_ADDR_OFFSET +
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MPC_FUNC_PORT_OFFSET_ADDR(port_num);
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/* Lock the permission configuration of all domains. */
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writel(readl(port_base + MPC_DOM_PER_LOCK(port_num)) |
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MPC_DOM_PER_LOCK_MASK,
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port_base + MPC_DOM_PER_LOCK(port_num));
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}
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#ifdef CONFIG_E3
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/* Disable sem error check. */
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writel(readl(FIREWALL_SCR_SF_BASE) & (~FIREWALL_SCR_SF_APB_MAC_ENB_BIT),
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FIREWALL_SCR_SF_BASE);
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#endif /* #ifdef CONFIG_E3 */
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port_base = base + FIREWALL_MPC_ROMC_ADDR_OFFSET +
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MPC_FUNC_PORT_OFFSET_ADDR(FIREWALL_MPC_MEMPORT_MAXNUM);
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/* Lock the permission configuration of all domains. */
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writel(readl(port_base + MPC_DOM_PER_LOCK(FIREWALL_MPC_MEMPORT_MAXNUM)) |
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MPC_DOM_PER_LOCK_MASK,
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port_base + MPC_DOM_PER_LOCK(FIREWALL_MPC_MEMPORT_MAXNUM));
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#ifdef CONFIG_E3
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/* Enable sem error check. */
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writel(readl(FIREWALL_SCR_SF_BASE) | FIREWALL_SCR_SF_APB_MAC_ENB_BIT,
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FIREWALL_SCR_SF_BASE);
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#endif /* #ifdef CONFIG_E3 */
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}
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/**
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* @brief Handle the interrupt status of the MPC module.
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*
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* This function get the illegal access error information of the MPC module.
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* The function exits as soon as it gets an illegal access message.
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* This function should be called by the firewall interrupt handler
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* sdrv_firewall_irq_handler().
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*
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* @param[in] base the address of the MAC module.
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* @param[in] mpc_cfg The configuration of memory.
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* @param[in] memport_num The number of memory port.
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* @param[out] mpc_irqsta The status of mpc interrupt.
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*
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* @return The result of the MPC handler.
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* @details - return FIREWALL_E_OK : Handle MPC interrupt success.
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* - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
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* - return FIREWALL_E_MPC_PORT_NUM : The number of memory port is
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* unvalid.
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*/
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status_t sdrv_firewall_mpc_irq_handler(uint32_t base,
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const sdrv_mpc_memport_cfg_t *mpc_cfg,
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uint32_t memport_num,
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sdrv_mpc_irqsta_t *mpc_irqsta)
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{
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status_t ret_val = FIREWALL_E_OK;
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uint8_t port_num;
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uint32_t sta_enable;
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uint32_t sig_enable;
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uint32_t port_base;
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/* #10 Check the parameters. */
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if ((NULL == mpc_cfg) || (NULL == mpc_irqsta))
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{
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ret_val = FIREWALL_E_NULL_POINTER;
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}
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else if (FIREWALL_MPC_MEMPORT_MAXNUM < memport_num)
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{
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ret_val = FIREWALL_E_MPC_PORT_NUM;
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}
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else
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{
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/* #20 Get the illegal access information from the MPC module interrupt.
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*/
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for (port_num = 0U; port_num < memport_num; ++port_num)
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{
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#ifdef CONFIG_E3
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/* Disable sem error check. */
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if (FIREWALL_MPC_GAMA_ADDR_OFFSET == mpc_cfg[port_num].base_offset)
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{
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writel(readl(FIREWALL_SCR_SF_BASE) &
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(~FIREWALL_SCR_SF_APB_MAC_ENB_BIT),
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FIREWALL_SCR_SF_BASE);
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}
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#endif /* #ifdef CONFIG_E3 */
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/* Get the interrupt status of the memory port. */
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port_base = base + mpc_cfg[port_num].base_offset;
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mpc_irqsta->mpc_intr_sta = readl(port_base + MPC_FUNC_INT_STA);
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if (0U < mpc_irqsta->mpc_intr_sta)
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{
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/* Clear the interrupt status of the memory port. */
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writel(mpc_irqsta->mpc_intr_sta, port_base + MPC_FUNC_INT_STA);
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sta_enable = readl(port_base + MPC_FUNC_INT_STA_EN);
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sig_enable = readl(port_base + MPC_FUNC_INT_SIG_EN);
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if (0U == ((uint32_t)mpc_irqsta->mpc_intr_sta & sta_enable &
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sig_enable))
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{
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mpc_irqsta->mpc_intr_sta = 0U;
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}
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else
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{
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mpc_irqsta->mpc_memport_id = port_num;
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}
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#ifdef CONFIG_E3
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/* Enable sem error check. */
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if (FIREWALL_MPC_GAMA_ADDR_OFFSET ==
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mpc_cfg[port_num].base_offset)
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{
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writel(readl(FIREWALL_SCR_SF_BASE) |
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FIREWALL_SCR_SF_APB_MAC_ENB_BIT,
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FIREWALL_SCR_SF_BASE);
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}
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#endif /* #ifdef CONFIG_E3 */
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break;
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} /* else not needed */
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#ifdef CONFIG_E3
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/* Enable sem error check. */
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if (FIREWALL_MPC_GAMA_ADDR_OFFSET == mpc_cfg[port_num].base_offset)
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{
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writel(readl(FIREWALL_SCR_SF_BASE) |
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FIREWALL_SCR_SF_APB_MAC_ENB_BIT,
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FIREWALL_SCR_SF_BASE);
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}
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#endif /* #ifdef CONFIG_E3 */
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}
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}
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return ret_val;
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}
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/**
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* @brief Clear the interrupt status of the MPC module.
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*
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* This function will clear the interrupt registers in the MPC module.
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* This function should not be called after the firewall has been initialized.
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*
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* @param[in] base the address of the MAC module.
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*/
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void sdrv_firewall_mpc_clear_interrupt(uint32_t base)
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{
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uint32_t port_base;
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uint8_t port_num;
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/* #10 Clear the interrupt of all memory ports. */
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for (port_num = 0U; port_num < FIREWALL_MPC_MEMPORT_MAXNUM; ++port_num)
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{
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#ifdef CONFIG_E3
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if (FIREWALL_MPC_RESERVED_PORTID == port_num)
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{
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continue;
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}
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#endif /* #ifdef CONFIG_E3 */
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port_base = base + FIREWALL_MPC_ROMC_ADDR_OFFSET +
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MPC_FUNC_PORT_OFFSET_ADDR(port_num);
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/* Disable the interrupt of the memory port. */
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writel(FIREWALL_REG_VALUE_MIN, port_base + MPC_FUNC_INT_STA_EN);
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/* Disable the interrupt signal of the memory port. */
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writel(FIREWALL_REG_VALUE_MIN, port_base + MPC_FUNC_INT_SIG_EN);
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/* Clear the interrupt status of the memory port. */
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writel(FIREWALL_REG_VALUE_MAX, port_base + MPC_FUNC_INT_STA);
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}
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#ifdef CONFIG_E3
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/* Disable sem error check. */
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writel(readl(FIREWALL_SCR_SF_BASE) & (~FIREWALL_SCR_SF_APB_MAC_ENB_BIT),
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FIREWALL_SCR_SF_BASE);
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#endif /* #ifdef CONFIG_E3 */
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port_base = base + FIREWALL_MPC_ROMC_ADDR_OFFSET +
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MPC_FUNC_PORT_OFFSET_ADDR(FIREWALL_MPC_MEMPORT_MAXNUM);
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/* Disable the interrupt of the memory port. */
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writel(FIREWALL_REG_VALUE_MIN, port_base + MPC_FUNC_INT_STA_EN);
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/* Disable the interrupt signal of the memory port. */
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writel(FIREWALL_REG_VALUE_MIN, port_base + MPC_FUNC_INT_SIG_EN);
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/* Clear the interrupt status of the memory port. */
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writel(FIREWALL_REG_VALUE_MAX, port_base + MPC_FUNC_INT_STA);
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#ifdef CONFIG_E3
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/* Enable sem error check. */
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writel(readl(FIREWALL_SCR_SF_BASE) | FIREWALL_SCR_SF_APB_MAC_ENB_BIT,
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FIREWALL_SCR_SF_BASE);
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#endif /* #ifdef CONFIG_E3 */
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}
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/***************************************************************************************************
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* Private Function Declarations
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**************************************************************************************************/
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/**
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* @brief Configure the permission of memory regions in MPC module.
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*
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* This function will be called by sdrv_firewall_mpc_configure().
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*
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* @param[in] base the address of the MAC module.
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* @param[in] memory the address of the MPC port configuration.
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*
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* @return The result of the configuration.
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* @details - return FIREWALL_E_OK : initializa MPC regions success.
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* - return FIREWALL_E_NULL_POINTER : The pointer is a NULL_PTR.
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* - return FIREWALL_E_MPC_REGION_NUM : The number of regions in the
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* port is unvalid.
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*/
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static status_t mpc_per_region(uint32_t base,
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const sdrv_mpc_memport_cfg_t *memory)
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{
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status_t ret_val = FIREWALL_E_OK;
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const sdrv_mpc_region_cfg_t *region;
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uint32_t port_base;
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uint32_t temp_val;
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uint8_t num;
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/* #10 Check the parameters. */
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if (NULL == memory)
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{
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ret_val = FIREWALL_E_NULL_POINTER;
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}
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else if (mpc_get_region_maxnum(memory->base_offset) < memory->region_nr)
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{
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ret_val = FIREWALL_E_MPC_REGION_NUM;
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}
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else
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{
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port_base = base + memory->base_offset;
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/* #20 Configure all regions of the memory port. */
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for (num = 0; num < memory->region_nr; num++)
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{
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region = &memory->region_config[num];
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/* Configure and lock the address range of the region. */
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writel(MPC_REGION_ADDR(region->start_addr),
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port_base + MPC_RGN_START_ADDR(num));
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writel(MPC_REGION_ADDR(region->end_addr),
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port_base + MPC_RGN_END_ADDR(num));
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writel(MPC_REGION_ADDR(region->start_addr),
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port_base + RGN_LOW_LIM(num));
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writel(MPC_REGION_ADDR(region->end_addr),
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port_base + RGN_UP_LIM(num));
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temp_val = MPC_REGION_ADDR(region->end_addr) | MPC_RGN_ENABLE;
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writel(temp_val, port_base + MPC_RGN_END_ADDR(num));
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temp_val |= MPC_RGN_LOCK;
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writel(temp_val, port_base + MPC_RGN_END_ADDR(num));
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/* configure domain 0-3 permission */
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temp_val = (uint32_t)region->domain0_perms << DOM_PER_DOMAIN0_BIT;
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temp_val |= (uint32_t)region->domain1_perms << DOM_PER_DOMAIN1_BIT;
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temp_val |= (uint32_t)region->domain2_perms << DOM_PER_DOMAIN2_BIT;
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temp_val |= (uint32_t)region->domain3_perms << DOM_PER_DOMAIN3_BIT;
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writel(temp_val, port_base + MPC_DOM_PER0(num));
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/* configure domain 4-7 permission */
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temp_val = (uint32_t)region->domain4_perms << DOM_PER_DOMAIN4_BIT;
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temp_val |= (uint32_t)region->domain5_perms << DOM_PER_DOMAIN5_BIT;
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temp_val |= (uint32_t)region->domain6_perms << DOM_PER_DOMAIN6_BIT;
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temp_val |= (uint32_t)region->domain7_perms << DOM_PER_DOMAIN7_BIT;
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writel(temp_val, port_base + MPC_DOM_PER1(num));
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}
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}
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return ret_val;
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}
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#ifdef __cplusplus
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}
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#endif
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/* End of file */
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