982 lines
30 KiB
C
982 lines
30 KiB
C
/**
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* @file sdrv_epwm.c
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* @brief sdrv epwm driver source file.
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*
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* @Copyright (c) 2022 Semidrive Semiconductor.
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* @All rights reserved.
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**/
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#include "sdrv_epwm.h"
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#include "bits.h"
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#include "clock_ip.h"
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#include "debug.h"
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#include "irq.h"
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#include "sdrv_epwm_reg.h"
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#include "string.h"
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/**
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* @brief sdrv epwm ns transfer to val.
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*
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* @param[in] clk src clk
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* @param[in] ns time val
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* @param[in] div src clk divider
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* @return ns_to_val
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*/
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uint32_t sdrv_epwm_ns_to_val(uint32_t clk, uint32_t ns, uint32_t div)
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{
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uint32_t clk_cnt_per_ms = (clk / (div + 1)) / 1000;
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uint32_t ns_to_val = (uint32_t)((uint64_t)ns * clk_cnt_per_ms / 1000000);
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return ns_to_val;
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}
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/**
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* @brief sdrv epwm ns transfer to val and minus 1.
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*
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* @param[in] clk src clk
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* @param[in] ns time val
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* @param[in] div src clk divider
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* @return ns_to_val_minus_1
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*/
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uint32_t sdrv_epwm_ns_to_val_1(uint32_t clk, uint32_t ns, uint32_t div)
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{
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uint32_t clk_cnt_per_ms = (clk / (div + 1)) / 1000;
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uint32_t ns_to_val = (uint32_t)((uint64_t)ns * clk_cnt_per_ms / 1000000);
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ns_to_val = ns_to_val - 1;
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return ns_to_val;
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}
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/**
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* @brief sdrv epwm val transfer to ns.
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*
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* @param[in] clk src clk
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* @param[in] cnt time val
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* @param[in] div src clk divider
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* @return val_to_ns
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*/
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uint32_t sdrv_epwm_val_to_ns(uint32_t clk, uint32_t val, uint32_t div)
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{
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uint32_t clk_cnt_per_ms = (clk / (div + 1)) / 1000;
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uint32_t val_to_ns = (uint32_t)((uint64_t)val * 1000000 / clk_cnt_per_ms);
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return val_to_ns;
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}
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/**
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* @brief Start ePWM channel output.
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*
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* This function start pwm output
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*
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* @param[in] dev pwm common instance
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*
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*/
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void sdrv_epwm_start(sdrv_epwm_t *dev)
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{
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ASSERT(dev != NULL);
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sdrv_epwm_cmp_en(dev, true);
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sdrv_epwm_cnt_en(dev, true);
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}
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/**
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* @brief Stop ePWM channel output.
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*
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* This function stop pwm output
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*
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* @param[in] dev pwm common instance
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*
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*/
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void sdrv_epwm_stop(sdrv_epwm_t *dev)
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{
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sdrv_epwm_cmp_en(dev, false);
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sdrv_epwm_cnt_en(dev, false);
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}
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/**
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* @brief epwm interrupt handler
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*
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* @param[in] irq irq_num
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* @param[in] arg input argument
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*
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*/
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static int sdrv_epwm_irq_handle(uint32_t irq, void *arg)
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{
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sdrv_epwm_controller_t *epwm_ctrl = (sdrv_epwm_controller_t *)arg;
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uint32_t int_sta = sdrv_epwm_lld_int_sta_get(epwm_ctrl->base);
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sdrv_epwm_lld_int_sta_clr(epwm_ctrl->base, int_sta);
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for (uint8_t id = SDRV_EPWM_CNT_G0; id < SDRV_EPWM_CNT_MAX_NUM; id++) {
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if (BIT_SET(int_sta, SDRV_EPWM_STA_CNT_OVF_SHIFT(id))) {
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sdrv_epwm_t *epwm_dev = epwm_ctrl->epwm_bank[id];
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epwm_dev->cb(epwm_dev, int_sta);
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}
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}
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return 0;
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}
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/**
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* @brief ePWM channel config.
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*
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* This function configure epwm
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*
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* @param[in] dev pwm common instance
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* @param[in] state pwm duty and period
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*
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*/
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status_t sdrv_epwm_config(sdrv_epwm_t *dev, const pwm_state_t *state)
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{
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ASSERT(dev != NULL);
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ASSERT(state != NULL);
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sdrv_epwm_controller_t *ctrl = dev->controller;
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sdrv_epwm_channel_e chnl = dev->chnl;
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epwm_cmp_cfg_t *cmp_cfg = &(dev->cmp_cfg);
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dev->base = ctrl->base;
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uint32_t clk_freq = 0;
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uint16_t waitTime = 0U;
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status_t retValue = SDRV_STATUS_FAIL;
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/* all epwm use same src clk */
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if (ctrl->clk_src == SDRV_EPWM_ALTERNATIVE_HIGH_FREQUENCY_CLOCK) {
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clk_freq = sdrv_ckgen_get_rate(CLK_NODE(g_ckgen_ip_xtrg));
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} else {
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clk_freq = sdrv_ckgen_get_rate(CLK_NODE(g_ckgen_ip_epwm1));
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}
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if ((state->duty1 > state->period) || (state->duty2 > state->period)) {
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return SDRV_STATUS_INVALID_PARAM;
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}
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uint32_t cmp_pulse_wid0_cmp00_cnt = sdrv_epwm_ns_to_val_1(
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clk_freq, cmp_cfg->cmp_pulse_wid0.cmp00, ctrl->clk_div);
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// cmp_pulse_wid0.cmp00 SHOULD LESS THAN OR EQUAL TO 1/EPWM_SRC_CLK * 0xFF
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uint32_t cmp_pulse_wid0_cmp01_cnt = sdrv_epwm_ns_to_val_1(
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clk_freq, cmp_cfg->cmp_pulse_wid0.cmp01, ctrl->clk_div);
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// cmp_pulse_wid0.cmp01 SHOULD LESS THAN OR EQUAL TO 1/EPWM_SRC_CLK * 0xFF
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uint32_t cmp_pulse_wid0_cmp10_cnt = sdrv_epwm_ns_to_val_1(
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clk_freq, cmp_cfg->cmp_pulse_wid0.cmp10, ctrl->clk_div);
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// cmp_pulse_wid0.cmp10 SHOULD LESS THAN OR EQUAL TO 1/EPWM_SRC_CLK * 0xFF
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uint32_t cmp_pulse_wid0_cmp11_cnt = sdrv_epwm_ns_to_val_1(
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clk_freq, cmp_cfg->cmp_pulse_wid0.cmp11, ctrl->clk_div);
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// cmp_pulse_wid0.cmp11 SHOULD LESS THAN OR EQUAL TO 1/EPWM_SRC_CLK * 0xFF
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uint32_t cmp_pulse_wid1_cmp0_ovf = sdrv_epwm_ns_to_val_1(
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clk_freq, cmp_cfg->cmp_pulse_wid1.cmp0_ovf, ctrl->clk_div);
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// cmp_pulse_wid0.cmp0_ovf SHOULD LESS THAN OR EQUAL TO 1/EPWM_SRC_CLK *
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// 0xFF
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uint32_t cmp_pulse_wid1_cmp1_ovf = sdrv_epwm_ns_to_val_1(
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clk_freq, cmp_cfg->cmp_pulse_wid1.cmp1_ovf, ctrl->clk_div);
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// cmp_pulse_wid0.cmp1_ovf SHOULD LESS THAN OR EQUAL TO 1/EPWM_SRC_CLK *
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// 0xFF
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sdrv_epwm_cmp_cfg_t cfg;
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memset(&cfg, 0, sizeof(cfg));
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cfg.con_mode = cmp_cfg->con_mode;
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cfg.cnt_sel = cmp_cfg->cmp_cnt_sel;
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cfg.cmp_x_out_mode = cmp_cfg->chnl_out_mode;
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cfg.cmp_x_mode = cmp_cfg->cmp_mode;
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cfg.refresh_intval = cmp_cfg->refresh_intval;
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cfg.out_mode.cmp00 = cmp_cfg->out_mode.cmp00;
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cfg.out_mode.cmp01 = cmp_cfg->out_mode.cmp01;
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cfg.out_mode.cmp10 = cmp_cfg->out_mode.cmp10;
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cfg.out_mode.cmp11 = cmp_cfg->out_mode.cmp11;
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cfg.out_mode.cmp0_ovf = cmp_cfg->out_mode.cmp0_ovf;
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cfg.out_mode.cmp1_ovf = cmp_cfg->out_mode.cmp1_ovf;
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cfg.wid0.cmp00 = cmp_pulse_wid0_cmp00_cnt;
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cfg.wid0.cmp01 = cmp_pulse_wid0_cmp01_cnt;
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cfg.wid0.cmp10 = cmp_pulse_wid0_cmp10_cnt;
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cfg.wid0.cmp11 = cmp_pulse_wid0_cmp11_cnt;
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cfg.wid1.cmp0_ovf = cmp_pulse_wid1_cmp0_ovf;
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cfg.wid1.cmp1_ovf = cmp_pulse_wid1_cmp1_ovf;
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cfg.sw_rld_mode = cmp_cfg->sw_rld_mode;
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// clk cfg
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sdrv_epwm_lld_clk_mon_en(dev->base, false, false);
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sdrv_epwm_lld_clk_config(dev->base, ctrl->clk_src, ctrl->clk_div);
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for(; waitTime < 1000U; waitTime++)
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{
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if(false == sdrv_epwm_lld_clk_config_div_num_upd_sta(dev->base))
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{
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retValue = SDRV_STATUS_OK;
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break;
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}
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}
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sdrv_epwm_lld_clk_mon_en(dev->base, true, true);
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// cnt cfg
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sdrv_epwm_cnt_ovf_upd(dev, state->period);
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// dma cfg
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if (cmp_cfg->dma_cfg.dma_enable) {
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sdrv_epwm_lld_dma_wml(dev->base, chnl, cmp_cfg->dma_cfg.fifo_wml);
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sdrv_epwm_lld_chn_dma_ctrl_chn_en(dev->base, chnl, true);
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} else
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sdrv_epwm_cmp_val_upd(dev, state);
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#if CONFIG_E3L
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if (cmp_cfg->center_align_mode)
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sdrv_epwm_center_align_mode_en(dev, true);
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#endif
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sdrv_epwm_lld_cmp_config(dev->base, chnl, &cfg);
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// irq cfg
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ctrl->epwm_bank[chnl] = dev;
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if (ctrl->irq > 0) {
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sdrv_epwm_lld_int_enable(dev->base, ctrl->irq_id);
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irq_attach(ctrl->irq, sdrv_epwm_irq_handle, ctrl);
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irq_enable(ctrl->irq);
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}
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return retValue;
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}
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/**
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* @brief epwm setup callback function
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*
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* @param[in] dev: epwm ctrl instance
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* @param[in] callback: user callback function
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* @return succeed:0 fail:other
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*/
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uint8_t sdrv_epwm_set_callback(sdrv_epwm_t *dev, pwm_callback_t callback)
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{
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ASSERT(dev != NULL);
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dev->cb = callback;
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return 0;
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}
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/**
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* @brief compare channel enable.
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*
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* This function enable compare channel
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*
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* @param[in] dev pwm common instance
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*
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*/
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void sdrv_epwm_cmp_en(sdrv_epwm_t *dev, bool en)
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{
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ASSERT(dev != NULL);
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sdrv_epwm_channel_e chnl = dev->chnl;
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sdrv_epwm_lld_cmp_ctrl_cmp_en(dev->base, chnl, en);
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}
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/**
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* @brief counter enable.
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*
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* This function enable CNTG0 or CNT_G1
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*
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* @param[in] dev pwm common instance
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*
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*/
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void sdrv_epwm_cnt_en(sdrv_epwm_t *dev, bool en)
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{
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ASSERT(dev != NULL);
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epwm_cmp_cfg_t *cmp_cfg = &(dev->cmp_cfg);
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sdrv_epwm_lld_cnt_en(dev->base, cmp_cfg->cmp_cnt_sel, en);
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}
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/**
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* @brief cnt overflow value upload (unit is ns)
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*
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* This function upload counter overflow value
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*
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* @param[in] dev pwm common instance
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* @param[in] period cnt overflow value
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*/
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void sdrv_epwm_cnt_ovf_upd(sdrv_epwm_t *dev, uint32_t period)
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{
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ASSERT(dev != NULL);
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epwm_cmp_cfg_t *cmp_cfg = &(dev->cmp_cfg);
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sdrv_epwm_controller_t *ctrl = dev->controller;
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uint32_t period_cnt;
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uint32_t clk_freq = 0;
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/* all epwm use same src clk */
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if (ctrl->clk_src == SDRV_EPWM_ALTERNATIVE_HIGH_FREQUENCY_CLOCK) {
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clk_freq = sdrv_ckgen_get_rate(CLK_NODE(g_ckgen_ip_xtrg));
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} else {
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clk_freq = sdrv_ckgen_get_rate(CLK_NODE(g_ckgen_ip_epwm1));
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}
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if (cmp_cfg->audio_enable)
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period_cnt = sdrv_epwm_ns_to_val_1(clk_freq, period, ctrl->clk_div) - 1;
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else {
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#if CONFIG_E3L
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if (cmp_cfg->center_align_mode)
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period_cnt =
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sdrv_epwm_ns_to_val(clk_freq, period, ctrl->clk_div) / 2 - 1;
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else
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#endif
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period_cnt = sdrv_epwm_ns_to_val_1(clk_freq, period, ctrl->clk_div);
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}
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sdrv_epwm_lld_cnt_ovf_val(dev->base, cmp_cfg->cmp_cnt_sel, period_cnt);
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sdrv_epwm_lld_cnt_cfg_ovf_upd(dev->base, cmp_cfg->cmp_cnt_sel);
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}
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/**
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* @brief compare value upload
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*
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* This function upload compare value
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*
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* @param[in] dev pwm common instance
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* @param[in] state pwm duty and period
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*/
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status_t sdrv_epwm_cmp_val_upd(sdrv_epwm_t *dev, const pwm_state_t *state)
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{
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ASSERT(dev != NULL);
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ASSERT(state != NULL);
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sdrv_epwm_channel_e chnl = dev->chnl;
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epwm_cmp_cfg_t *cmp_cfg = &(dev->cmp_cfg);
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sdrv_epwm_controller_t *ctrl = dev->controller;
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if ((state->duty1 > state->period) || (state->duty2 > state->period)) {
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return SDRV_STATUS_INVALID_PARAM;
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}
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uint32_t period_cnt;
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uint32_t dual_period_cnt_left1 = 0;
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uint32_t dual_period_cnt_right1 = 0;
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uint32_t dual_period_cnt_left2 = 0;
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uint32_t dual_period_cnt_right2 = 0;
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uint32_t clk_freq = 0;
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/* all epwm use same src clk */
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if (ctrl->clk_src == SDRV_EPWM_ALTERNATIVE_HIGH_FREQUENCY_CLOCK) {
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clk_freq = sdrv_ckgen_get_rate(CLK_NODE(g_ckgen_ip_xtrg));
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} else {
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clk_freq = sdrv_ckgen_get_rate(CLK_NODE(g_ckgen_ip_epwm1));
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}
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period_cnt = sdrv_epwm_ns_to_val(clk_freq, state->period, ctrl->clk_div);
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uint32_t duty1_cnt;
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uint32_t duty2_cnt;
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#if CONFIG_E3L
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if (cmp_cfg->center_align_mode) {
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// duty1_cnt SHOULD LESS THAN OR EQUAL TO period_cnt/2
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duty1_cnt =
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sdrv_epwm_ns_to_val(clk_freq, state->duty1, ctrl->clk_div) / 2;
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dual_period_cnt_left1 = (period_cnt) / 4 - duty1_cnt / 2;
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dual_period_cnt_right1 = (period_cnt) / 4 + duty1_cnt / 2;
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// duty2_cnt SHOULD LESS THAN OR EQUAL TO period_cnt/2
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duty2_cnt =
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sdrv_epwm_ns_to_val(clk_freq, state->duty2, ctrl->clk_div) / 2;
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dual_period_cnt_left2 = (period_cnt) / 4 - duty2_cnt / 2;
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dual_period_cnt_right2 = (period_cnt) / 4 + duty2_cnt / 2;
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} else {
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#endif
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duty1_cnt = sdrv_epwm_ns_to_val(clk_freq, state->duty1, ctrl->clk_div);
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dual_period_cnt_left1 = (period_cnt) / 2 - duty1_cnt / 2;
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dual_period_cnt_right1 = (period_cnt) / 2 + duty1_cnt / 2;
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duty2_cnt = sdrv_epwm_ns_to_val(clk_freq, state->duty2, ctrl->clk_div);
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dual_period_cnt_left2 = (period_cnt) / 2 - duty2_cnt / 2;
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dual_period_cnt_right2 = (period_cnt) / 2 + duty2_cnt / 2;
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#if CONFIG_E3L
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}
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#endif
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if (cmp_cfg->cmp_mode == SDRV_EPWM_SINGLE_COMPARE_MODE) {
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sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_00, duty1_cnt);
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if (cmp_cfg->chnl_out_mode == EPWM_BOTH_COMP0_AND_COMP1_OUTPUT)
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sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_10, duty2_cnt);
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} else if (cmp_cfg->cmp_mode == SDRV_EPWM_DUAL_COMPARE_MODE) {
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sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_00,
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dual_period_cnt_left1);
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sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_01,
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dual_period_cnt_right1);
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if (cmp_cfg->chnl_out_mode == EPWM_BOTH_COMP0_AND_COMP1_OUTPUT) {
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sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_10,
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dual_period_cnt_left2);
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sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_11,
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dual_period_cnt_right2);
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}
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}
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sdrv_epwm_lld_cmp_ctrl_cmp_val_upd(dev->base, chnl);
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return SDRV_STATUS_OK;
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}
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/**
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* @brief configure multi compare mode
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*
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* This function configure multi compare value
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*
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* @param[in] dev pwm common instance
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* @param[in] state pwm duty and period
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* @param[in] multi cmp00/01/10/11 val
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*
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*/
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status_t sdrv_epwm_multi_cmp_mode(sdrv_epwm_t *dev, pwm_state_t *state,
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epwm_multi_cmp_val_t *multi_cmp)
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{
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sdrv_epwm_channel_e chnl = dev->chnl;
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sdrv_epwm_controller_t *ctrl = dev->controller;
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uint32_t clk_freq = 0;
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/* all epwm use same src clk */
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if (ctrl->clk_src == SDRV_EPWM_ALTERNATIVE_HIGH_FREQUENCY_CLOCK) {
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clk_freq = sdrv_ckgen_get_rate(CLK_NODE(g_ckgen_ip_xtrg));
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} else {
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clk_freq = sdrv_ckgen_get_rate(CLK_NODE(g_ckgen_ip_epwm1));
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}
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if ((state->duty1 > state->period) || (state->duty2 > state->period)) {
|
|
return SDRV_STATUS_INVALID_PARAM;
|
|
}
|
|
|
|
uint32_t cmp00_cnt =
|
|
sdrv_epwm_ns_to_val(clk_freq, multi_cmp->cmp00_val, ctrl->clk_div);
|
|
uint32_t cmp01_cnt =
|
|
sdrv_epwm_ns_to_val(clk_freq, multi_cmp->cmp01_val, ctrl->clk_div);
|
|
uint32_t cmp10_cnt =
|
|
sdrv_epwm_ns_to_val(clk_freq, multi_cmp->cmp10_val, ctrl->clk_div);
|
|
uint32_t cmp11_cnt =
|
|
sdrv_epwm_ns_to_val(clk_freq, multi_cmp->cmp11_val, ctrl->clk_div);
|
|
|
|
sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_00, cmp00_cnt);
|
|
sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_01, cmp01_cnt);
|
|
sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_10, cmp10_cnt);
|
|
sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_11, cmp11_cnt);
|
|
|
|
sdrv_epwm_lld_cmp_ctrl_cmp_val_upd(dev->base, chnl);
|
|
|
|
return SDRV_STATUS_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief configure epwm counter clear
|
|
*
|
|
* This function configure counter clear
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] cnt_clr_trig_sel sellect cnt_clr_trig_polarity
|
|
* @param[in] clr_sel input_clr_sel_trig
|
|
*
|
|
*/
|
|
void sdrv_epwm_cnt_clr_cfg(sdrv_epwm_t *dev,
|
|
sdrv_epwm_event_trigger_mode_e cnt_clr_trig_sel,
|
|
sdrv_epwm_input_sel_trig_e clr_sel)
|
|
{
|
|
epwm_cmp_cfg_t *cmp_cfg = &(dev->cmp_cfg);
|
|
|
|
sdrv_epwm_lld_cnt_cfg_clr_trig_sel(dev->base, cmp_cfg->cmp_cnt_sel,
|
|
cnt_clr_trig_sel);
|
|
sdrv_epwm_lld_cnt_input_sel_clr(dev->base, cmp_cfg->cmp_cnt_sel, clr_sel);
|
|
}
|
|
|
|
/**
|
|
* @brief configure epwm counter overflow upload cfg
|
|
*
|
|
* This function configure counter overflow upload
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] set_mode_sel sellect set_mode
|
|
* @param[in] cnt_set_trig_sel sellect cnt_set_trig_polarity
|
|
* @param[in] set_sel input_set_sel_trig
|
|
*
|
|
*/
|
|
void sdrv_epwm_cnt_ovf_upd_cfg(sdrv_epwm_t *dev,
|
|
sdrv_epwm_cnt_cfg_set_upd_sel_e set_mode_sel,
|
|
sdrv_epwm_event_trigger_mode_e cnt_set_trig_sel,
|
|
sdrv_epwm_input_sel_trig_e set_sel)
|
|
{
|
|
epwm_cmp_cfg_t *cmp_cfg = &(dev->cmp_cfg);
|
|
|
|
sdrv_epwm_lld_cnt_cfg_set_trig_sel(dev->base, cmp_cfg->cmp_cnt_sel,
|
|
set_mode_sel, cnt_set_trig_sel);
|
|
sdrv_epwm_lld_cnt_input_sel_set(dev->base, cmp_cfg->cmp_cnt_sel, set_sel);
|
|
}
|
|
|
|
/**
|
|
* @brief software trigger
|
|
*
|
|
* This function configure software trigger, such as pulse.
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] tirg sellect trigger mode
|
|
*
|
|
*/
|
|
void sdrv_epwm_sw_trig(sdrv_epwm_t *dev, sdrv_epwm_sw_trig_ctrl_e trig)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_sw_trig_ctrl(dev->base, chnl, trig);
|
|
}
|
|
|
|
/**
|
|
* @brief configure epwm death time
|
|
*
|
|
* This function configure compare death time
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] prefin_pol prefinial polarity
|
|
* @param[in] dti_val death time value
|
|
*
|
|
*/
|
|
void sdrv_epwm_dti(sdrv_epwm_t *dev, sdrv_epwm_cmp_prefin_pol_t *prefin_pol,
|
|
const uint32_t dti_val)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
sdrv_epwm_controller_t *ctrl = dev->controller;
|
|
uint32_t clk_freq = 0;
|
|
/* all epwm use same src clk */
|
|
if (ctrl->clk_src == SDRV_EPWM_ALTERNATIVE_HIGH_FREQUENCY_CLOCK) {
|
|
clk_freq = sdrv_ckgen_get_rate(CLK_NODE(g_ckgen_ip_xtrg));
|
|
} else {
|
|
clk_freq = sdrv_ckgen_get_rate(CLK_NODE(g_ckgen_ip_epwm1));
|
|
}
|
|
|
|
uint32_t dti_cnt = sdrv_epwm_ns_to_val_1(clk_freq, dti_val, ctrl->clk_div);
|
|
|
|
sdrv_epwm_lld_cmp_prefin_pol(dev->base, chnl, prefin_pol);
|
|
|
|
sdrv_epwm_lld_cmp_dti_ctrl_inv(dev->base, chnl, true);
|
|
|
|
sdrv_epwm_lld_cmp_dti_wid(dev->base, chnl, dti_cnt, dti_cnt);
|
|
|
|
sdrv_epwm_lld_cmp_dti_ctrl_en(dev->base, chnl, true);
|
|
}
|
|
|
|
/**
|
|
* @brief configure sse epwm output
|
|
*
|
|
* This function configure compare sse mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] sse_cfg sse_mode and edge sellect
|
|
* @param[in] sse_reg_val sse register value
|
|
*
|
|
*/
|
|
void sdrv_epwm_sse(sdrv_epwm_t *dev, sdrv_epwm_cmp_sse_ctrl_t *sse_cfg,
|
|
uint32_t sse_reg_val)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_cmp_sse_ctrl_cfg(dev->base, chnl, sse_cfg);
|
|
sdrv_epwm_lld_cmp_sse_ctrl_cfg_so_det_fault(dev->base, chnl,
|
|
sse_cfg->sse_so_det_fault);
|
|
sdrv_epwm_lld_cmp_sse_reg(dev->base, chnl, sse_reg_val);
|
|
sdrv_epwm_lld_cmp_sse_ctrl_sse_en(dev->base, chnl, true);
|
|
}
|
|
|
|
/**
|
|
* @brief configure modulation frequency control
|
|
*
|
|
* This function configure compare mfc mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] val mfc up times to 2^val times
|
|
*
|
|
*/
|
|
void sdrv_epwm_mfc(sdrv_epwm_t *dev, uint8_t val)
|
|
{
|
|
epwm_cmp_cfg_t *cmp_cfg = &(dev->cmp_cfg);
|
|
|
|
sdrv_epwm_lld_cnt_mfc(dev->base, cmp_cfg->cmp_cnt_sel, val);
|
|
}
|
|
|
|
/**
|
|
* @brief configure compare data format
|
|
*
|
|
* This function configure compare data format, such as 8bit or 16bit.
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] dat_format cmp data formate
|
|
*/
|
|
void sdrv_epwm_cmp_data_format(
|
|
sdrv_epwm_t *dev, sdrv_epwm_chn_dma_ctrl_cmp_x_dat_format_e dat_format)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_chn_dma_ctrl_cmp_dat_format(dev->base, chnl, dat_format);
|
|
}
|
|
|
|
/**
|
|
* @brief configure compare dither mode
|
|
*
|
|
* This function configure compare dither mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] clip_rslt dither clip_rslt val
|
|
* @param[in] init_offset dither init_offset val
|
|
*/
|
|
void sdrv_epwm_cmp_dither(sdrv_epwm_t *dev, uint8_t clip_rslt,
|
|
uint16_t init_offset)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_cmp_dither(dev->base, chnl, clip_rslt, init_offset);
|
|
if (init_offset)
|
|
sdrv_epwm_lld_cmp_dither_init_offset_en(dev->base, chnl, true);
|
|
|
|
sdrv_epwm_lld_cmp_dither_en(dev->base, chnl, true);
|
|
}
|
|
|
|
/**
|
|
* @brief configure compare multi channels
|
|
*
|
|
* This function configure compare value of multi channels
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] full_en full channels enable
|
|
*/
|
|
void sdrv_epwm_cmp_multi_chnl(sdrv_epwm_t *dev, bool full_en)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
if (full_en)
|
|
sdrv_epwm_lld_chn_dma_ctrl_four_chan_mode(dev->base, true);
|
|
else
|
|
sdrv_epwm_lld_chn_dma_ctrl_two_chn_xx_mode(dev->base, chnl, true);
|
|
}
|
|
|
|
/**
|
|
* @brief configure compare event/cnt overflow event
|
|
*
|
|
* This function configure compare event or counter event
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] src_sel choose cmp or cnt trigger source
|
|
*/
|
|
void sdrv_epwm_ce_ctrl(sdrv_epwm_t *dev, bool src_sel)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
epwm_cmp_cfg_t *cmp_cfg = &(dev->cmp_cfg);
|
|
|
|
if (src_sel) {
|
|
sdrv_epwm_lld_cmp_config_ce_en(dev->base, chnl, true);
|
|
}
|
|
|
|
else {
|
|
sdrv_epwm_lld_cnt_cfg_ce_en(dev->base, cmp_cfg->cmp_cnt_sel, true);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief configure dma request except fifo wml trig
|
|
*
|
|
* This function configure pwm trig dma tranferrs with ce
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] sel_trig sellect trigger source
|
|
*/
|
|
void sdrv_epwm_ce_dma_trig(sdrv_epwm_t *dev, uint8_t sel_trig)
|
|
{
|
|
sdrv_epwm_lld_config_dma_ctl_cfg(dev->base, false, sel_trig);
|
|
sdrv_epwm_lld_config_dma_ctl_en(dev->base, true);
|
|
}
|
|
|
|
/**
|
|
* @brief filter input fault source signals
|
|
*
|
|
* This function configure fault event source
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] flt_cfg config filter
|
|
*/
|
|
void sdrv_epwm_fault_flt(sdrv_epwm_t *dev, sdrv_epwm_fault_flt_t *flt_cfg)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
// pos/neg_band_wid should equal or greater than 2 due to 0~15 indicate
|
|
// 2~17 sample interval
|
|
// smpl_intval should equal or greater than 1 due to 0~255 indicate
|
|
// 1~256 timer clock cycles
|
|
sdrv_epwm_lld_fault_flt(dev->base, chnl, flt_cfg);
|
|
|
|
sdrv_epwm_lld_fault_flt_en(dev->base, chnl, true);
|
|
}
|
|
|
|
/**
|
|
* @brief configure input fault event
|
|
*
|
|
* This function configure compare fault event
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] fault_src config which fault source to trigger
|
|
* @param[in] fault_cfg config fault event
|
|
* @param[in] fs_state cmp failsafe status
|
|
*/
|
|
void sdrv_epwm_fault_event(sdrv_epwm_t *dev, uint8_t fault_src,
|
|
sdrv_epwm_cmp_fault_event_ctrl_t *fault_cfg,
|
|
epwm_fs_state_t *fs_state)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_cmp_fault_event_ctrl_config(
|
|
dev->base, chnl, (sdrv_epwm_cmp_fault_e)fault_src, fault_cfg);
|
|
|
|
sdrv_epwm_lld_cmp_fault_event_fs_sta_set(
|
|
dev->base, chnl, fs_state->cmp0_fs_state, fs_state->cmp1_fs_state);
|
|
|
|
sdrv_epwm_lld_cmp_fault_event_ctrl_en(
|
|
dev->base, chnl, (sdrv_epwm_cmp_fault_e)fault_src, true);
|
|
}
|
|
|
|
/**
|
|
* @brief input fault event clr
|
|
*
|
|
* This function clear fault status in sticky mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] fault_src config which fault source to trigger
|
|
*/
|
|
void sdrv_epwm_fault_event_clr(sdrv_epwm_t *dev, uint8_t fault_src)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_cmp_fault_event_ctrl_clr(dev->base, chnl,
|
|
(sdrv_epwm_cmp_fault_e)fault_src);
|
|
}
|
|
|
|
/**
|
|
* @brief cnt overflow value upload directly (unit is cnt val)
|
|
*
|
|
* This function configure counter overflow upload
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] period_cnt counter overflow value
|
|
*/
|
|
void sdrv_epwm_cnt_ovf_dir_upd(sdrv_epwm_t *dev, uint32_t period_cnt)
|
|
{
|
|
epwm_cmp_cfg_t *cmp_cfg = &(dev->cmp_cfg);
|
|
|
|
sdrv_epwm_lld_cnt_ovf_val(dev->base, cmp_cfg->cmp_cnt_sel, period_cnt);
|
|
sdrv_epwm_lld_cnt_cfg_ovf_upd(dev->base, cmp_cfg->cmp_cnt_sel);
|
|
}
|
|
|
|
/**
|
|
* @brief upload chnl_b/c/d compare value with dual mode 100% duty check(unit is
|
|
* cnt val)
|
|
*
|
|
* This function upload channel_b/c/d value with 100% over two period
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] left_point dual mode left cmp_val
|
|
* @param[in] right_point dual mode right cmp_val
|
|
*/
|
|
void sdrv_epwm_cmp_bcd_update(sdrv_epwm_t *dev, uint32_t left_point,
|
|
uint32_t right_point)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
epwm_cmp_cfg_t *cmp_cfg = &(dev->cmp_cfg);
|
|
epwm_dual_duty_state_t *pre_duty = &(dev->pre_duty);
|
|
|
|
uint32_t cnt_ovf = 0;
|
|
|
|
if (pre_duty->left_point == 0 && left_point != 0) {
|
|
cnt_ovf = sdrv_epwm_lld_cnt_ovf_val_rd(dev->base, cmp_cfg->cmp_cnt_sel);
|
|
sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_01, cnt_ovf + 1);
|
|
sdrv_epwm_lld_cmp_ctrl_cmp_val_upd(dev->base, chnl);
|
|
sdrv_epwm_cmp_sw_rld(dev);
|
|
}
|
|
|
|
if (left_point != 0)
|
|
sdrv_epwm_cmp_val_upd_bcd(dev, left_point, right_point);
|
|
else {
|
|
sdrv_epwm_cmp_val_upd_bcd(dev, left_point, right_point + 1);
|
|
}
|
|
|
|
pre_duty->left_point = left_point;
|
|
pre_duty->right_point = right_point;
|
|
}
|
|
|
|
/**
|
|
* @brief compare value chnl_b/c/d upload (unit is cnt val)
|
|
*
|
|
* This function upload compare value in dual mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] left_point dual mode left cmp_val
|
|
* @param[in] right_point dual mode right cmp_val
|
|
*/
|
|
void sdrv_epwm_cmp_val_upd_bcd(sdrv_epwm_t *dev, uint32_t left_point,
|
|
uint32_t right_point)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_00, left_point);
|
|
|
|
if (left_point != 0)
|
|
sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_01, right_point);
|
|
else
|
|
sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_01,
|
|
right_point - 1);
|
|
|
|
sdrv_epwm_lld_cmp_ctrl_cmp_val_upd(dev->base, chnl);
|
|
}
|
|
|
|
/**
|
|
* @brief compare value chnl_a upload (unit is cnt val)
|
|
*
|
|
* This function upload channel a value
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] trig_point set trig point to tmux
|
|
*/
|
|
void sdrv_epwm_cmp_val_upd_a(sdrv_epwm_t *dev, uint32_t trig_point)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_00, trig_point);
|
|
|
|
sdrv_epwm_lld_cmp_ctrl_cmp_val_upd(dev->base, chnl);
|
|
}
|
|
|
|
/**
|
|
* @brief compare software reload
|
|
*
|
|
* This function set compare value valid immediately
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
*/
|
|
void sdrv_epwm_cmp_sw_rld(sdrv_epwm_t *dev)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_cmp_config_sw_rld_set(dev->base, chnl, true);
|
|
}
|
|
|
|
/**
|
|
* @brief compare clr/set configure
|
|
*
|
|
* This function configure compare clear/set source
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] input_sel input sellect
|
|
* @param[in] set_trig cmp set trigger sel
|
|
* @param[in] clr_trig cmp clr trigger sel
|
|
*/
|
|
void sdrv_epwm_cmp_input(sdrv_epwm_t *dev, sdrv_epwm_input_sel_t *input_sel,
|
|
uint8_t set_trig, uint8_t clr_trig)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_cmp_config_clr_set(dev->base, chnl,
|
|
(sdrv_epwm_event_trigger_mode_e)set_trig,
|
|
(sdrv_epwm_event_trigger_mode_e)clr_trig);
|
|
sdrv_epwm_lld_cmp_input_sel(dev->base, chnl, input_sel);
|
|
}
|
|
|
|
/**
|
|
* @brief configure compare a event id
|
|
*
|
|
* This function configure cmpa0 event id
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] eid_val cmp00/01/10/11 eid
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*/
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void sdrv_epwm_cmp_a_eid(sdrv_epwm_t *dev, epwm_eid_val_t *eid_val)
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{
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sdrv_epwm_lld_cmp_a_eid(dev->base, SDRV_EPWM_CMP_00, eid_val->eid00);
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sdrv_epwm_lld_cmp_a_eid(dev->base, SDRV_EPWM_CMP_01, eid_val->eid01);
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sdrv_epwm_lld_cmp_a_eid(dev->base, SDRV_EPWM_CMP_10, eid_val->eid10);
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sdrv_epwm_lld_cmp_a_eid(dev->base, SDRV_EPWM_CMP_11, eid_val->eid11);
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sdrv_epwm_lld_cmp_ctrl_cmp_eid_upd(dev->base);
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|
}
|
|
|
|
/**
|
|
* @brief epwm initial status.
|
|
*
|
|
* This function configure compare initial value
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] cmp0_init cmp0 channel init status
|
|
* @param[in] cmp1_init cmp1 channel init status
|
|
*
|
|
*/
|
|
void sdrv_epwm_init_sta(sdrv_epwm_t *dev, bool cmp0_init, bool cmp1_init)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_cmp_ctrl_cmp_init_status(dev->base, chnl, cmp0_init,
|
|
cmp1_init);
|
|
|
|
sdrv_epwm_lld_cmp_ctrl_cmp_init_upd(dev->base, chnl, 0);
|
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sdrv_epwm_lld_cmp_ctrl_cmp_init_upd(dev->base, chnl, 1);
|
|
}
|
|
|
|
/**
|
|
* @brief epwm upload chnl_b/c/d [X]0/1 compare value
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] subchnl choose cmp0 or cmp1
|
|
* @param[in] left_point dual mode left cmp_val
|
|
* @param[in] right_point dual mode right cmp_val
|
|
*
|
|
*/
|
|
void sdrv_epwm_val_chnl_bcd_upd_split(sdrv_epwm_t *dev,
|
|
sdrv_epwm_output_e subchnl,
|
|
uint32_t left_point, uint32_t right_point)
|
|
{
|
|
if (!subchnl) {
|
|
sdrv_epwm_lld_cmp_val(dev->base, dev->chnl, SDRV_EPWM_CMP_00,
|
|
left_point);
|
|
sdrv_epwm_lld_cmp_val(dev->base, dev->chnl, SDRV_EPWM_CMP_01,
|
|
right_point);
|
|
} else {
|
|
sdrv_epwm_lld_cmp_val(dev->base, dev->chnl, SDRV_EPWM_CMP_10,
|
|
left_point);
|
|
sdrv_epwm_lld_cmp_val(dev->base, dev->chnl, SDRV_EPWM_CMP_11,
|
|
right_point);
|
|
}
|
|
|
|
sdrv_epwm_lld_cmp_ctrl_cmp_val_upd(dev->base, dev->chnl);
|
|
}
|
|
|
|
/**
|
|
* @brief epwm upload chnl_b/c/d [X]0/1 compare value
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] cmp0_left_point cmp0 dual mode left cmp_val
|
|
* @param[in] cmp0_right_point cmp0 dual mode right cmp_val
|
|
* @param[in] cmp1_left_point cmp1 dual mode left cmp_val
|
|
* @param[in] cmp1_right_point cmp1 dual mode right cmp_val
|
|
*
|
|
*/
|
|
void sdrv_epwm_val_chnl_bcd_upd_split_both(sdrv_epwm_t *dev,
|
|
uint32_t cmp0_left_point,
|
|
uint32_t cmp0_right_point,
|
|
uint32_t cmp1_left_point,
|
|
uint32_t cmp1_right_point)
|
|
{
|
|
sdrv_epwm_val_chnl_bcd_upd_split(dev, SDRV_EPWM_CMP0_OUTPUT,
|
|
cmp0_left_point, cmp0_right_point);
|
|
sdrv_epwm_val_chnl_bcd_upd_split(dev, SDRV_EPWM_CMP1_OUTPUT,
|
|
cmp1_left_point, cmp1_right_point);
|
|
}
|
|
|
|
#if CONFIG_E3L
|
|
/**
|
|
* @brief center align mode enable.
|
|
*
|
|
* This function configure align mode enable
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] en enable/diable center align mode
|
|
*
|
|
*/
|
|
void sdrv_epwm_center_align_mode_en(sdrv_epwm_t *dev, bool en)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
epwm_cmp_cfg_t *cmp_cfg = &(dev->cmp_cfg);
|
|
|
|
sdrv_epwm_lld_cnt_cfg_ovf_rst_dis(dev->base, cmp_cfg->cmp_cnt_sel, en);
|
|
|
|
sdrv_epwm_lld_cnt_center_align_mode_en(dev->base, cmp_cfg->cmp_cnt_sel, en);
|
|
|
|
sdrv_epwm_lld_cmp_center_align_mode_en(dev->base, chnl, en);
|
|
}
|
|
|
|
/**
|
|
* @brief compare value chnl_b/c/d upload in center align mode (unit is cnt val)
|
|
*
|
|
* This function configure channel_b/c/d value upload in center align mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] cmp_point center align mode cmp_val
|
|
*/
|
|
void sdrv_epwm_cmp_center_align_val_upd_bcd(sdrv_epwm_t *dev,
|
|
uint32_t cmp_point)
|
|
{
|
|
sdrv_epwm_channel_e chnl = dev->chnl;
|
|
|
|
sdrv_epwm_lld_cmp_val(dev->base, chnl, SDRV_EPWM_CMP_00, cmp_point);
|
|
|
|
sdrv_epwm_lld_cmp_ctrl_cmp_val_upd(dev->base, chnl);
|
|
}
|
|
#endif
|