276 lines
7.9 KiB
C
276 lines
7.9 KiB
C
/**
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* @file sdrv_pll_hw_access.h
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* @brief taishan pll hw access header file.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#ifndef SDRV_PLL_HW_ACCESS_H_
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#define SDRV_PLL_HW_ACCESS_H_
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#include <sdrv_ckgen.h>
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#include <types.h>
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/* Control register */
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#define PLL_CTRL (0x0u)
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#define PLL_CTRL_PD (0u)
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#define PLL_CTRL_GATING_MODE (1u)
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#define PLL_CTRL_LOCK_MODE (2u)
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#define PLL_CTRL_LOCK_TIME_LSB (3u)
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#define PLL_CTRL_LOCK_TIME_MASK (0xFu)
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#define PLL_CTRL_POSTDIV (7u)
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#define PLL_CTRL_FORCE_LOCK (8u)
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#define PLL_CTRL_DSM_DISABLE (9u)
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#define PLL_CTRL_RESETN (10u)
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#define PLL_CTRL_RESETN_SEL (11u)
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#define PLL_CTRL_ICP_LSB (16u)
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#define PLL_CTRL_ICP_MASK (0x7u)
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#define PLL_CTRL_LDO_V0P8_LSB (19u)
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#define PLL_CTRL_LDO_V0P8_MASK (0x3u)
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#define PLL_CTRL_VCO_BAND_LSB (21u)
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#define PLL_CTRL_VCO_BAND_MASK (0x7u)
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#define PLL_CTRL_RESETN_DLY_LSB (25u)
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#define PLL_CTRL_RESETN_DLY_MASK (0xFu)
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#define PLL_CTRL_FORCE_BYPASS (29u)
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#define PLL_CTRL_SEM_SWITCH_EN (30u)
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#define PLL_CTRL_SEMM_SWITCH_SRC_SEL (31u)
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/* N Number register */
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#define PLL_N_NUM (0x4u)
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#define PLL_N_NUM_VAL_LSB (0u)
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#define PLL_N_NUM_VAL_MASK (0x7Fu)
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/* M Number register */
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#define PLL_M_NUM (0x8u)
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#define PLL_M_NUM_VAL_LSB (0u)
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#define PLL_M_NUM_VAL_MASK (0x3FFFFFFu)
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#define PLL_M_NUM_SW_READY (30u)
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#define PLL_M_NUM_READY_SEL (31u)
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/* DSM register */
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#define PLL_DSM (0xCu)
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#define PLL_DSM_SSC_OFFSET_LSB (0u)
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#define PLL_DSM_SSc_OFFSET_MASK (0x3u)
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#define PLL_DSM_SSC_FREQ_LSB (2u)
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#define PLL_DSM_SSC_FREQ_MASK (0x3u)
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#define PLL_DSM_SSC_MODE_LSB (4u)
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#define PLL_DSM_SSC_MODE_MASK (0x3u)
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#define PLL_DSM_SSC_DEP_LSB (6u)
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#define PLL_DSM_SSC_DEP_MASK (0x1Fu)
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/* DTEST register */
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#define PLL_DTEST (0x10u)
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#define PLL_DTEST_EN (0u)
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#define PLL_DTEST_SEL_LSB (1u)
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#define PLL_DTEST_SEL_MASK (0x3u)
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#define PLL_DTEST_REF_TEST_SEL (3u)
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#define PLL_DTEST_DTESTO (31u)
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/* ATEST register */
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#define PLL_ATEST (0x14u)
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#define PLL_ATEST_EN (0u)
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#define PLL_ATEST_SEL_LSB (1u)
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#define PLL_ATEST_SEL_MASK (0x3u)
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/* STATUS register */
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#define PLL_STATUS (0x20u)
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#define PLL_STATUS_LOCK (0u)
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#define PLL_STATUS_DUTY_DET (1u)
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#define PLL_STATUS_NO_REFCK (2u)
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#define PLL_STATUS_PLL_M_READY (3u)
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#define PLL_STATUS_LOCK_LOSS (8u)
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#define PLL_STATUS_DUTY_LOSS (9u)
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#define PLL_STATUS_REFCK_LOSS (10u)
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/* LVDS_CTL register */
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#define PLL_LVDS_CTL (0xA0u)
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#define PLL_LVDS_CTL_DIV2_GATING_EN (0u)
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#define PLL_LVDS_CTL_DIV7_GATING_EN (1u)
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#define PLL_LVDS_CTL_DIV2_NUM_LSB (2u)
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#define PLL_LVDS_CTL_DIV2_NUM_MASK (0x1Fu)
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#define PLL_LVDS_CTL_DIV7_NUM_LSB (7u)
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#define PLL_LVDS_CTL_DIV7_NUM_MASK (0x1Fu)
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#define PLL_LVDS_CTL_GATING_EN (12u)
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#define PLL_LVDS_CTL_CKGEN_GATING_EN (16u)
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#define PLL_LVDS_CTL_CKGEN_DIV_NUM_LSB (17u)
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#define PLL_LVDS_CTL_CKGEN_DIV_NUM_MASK (0xFu)
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#define PLL_LVDS_CTL_CKGEN_GATING_STATUS (25u)
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#define PLL_LVDS_CTL_CKGEN_CHG_BUSY (26u)
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#define PLL_LVDS_CTL_GATING_STATUS (27u)
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#define PLL_LVDS_CTL_DIV7_GATING_STATUS (28u)
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#define PLL_LVDS_CTL_DIV2_GATING_STATUS (29u)
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#define PLL_LVDS_CTL_DIV7_CHG_BUSY (30u)
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#define PLL_LVDS_CTL_DIV2_CHG_BUSY (31u)
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#define PLL_LVDS_OUT_DIV_MIN (1u)
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#define PLL_LVDS_OUT_DIV_MAX (32u)
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#define PLL_LVDS_CKGEN_IN_DIV_MAX (16u)
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#define PLL_VCO_FMAX 2400000000ul
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#define PLL_VCO_FMIN 500000000ul
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#define PLL_VCO_BAND 1000000000ul
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/* PLL lock wait time */
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#define PLL_WAIT_TIME 10000u
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/**
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* @brief PLL VCO Enable.
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*
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* This function enable pll vco, set vco in run status.
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*
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* @param [in] base pll base
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* @param [in] enable enable or disable
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* @return enable result
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*/
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status_t sdrv_pll_vco_enable(uint32_t base, bool enable);
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/**
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* @brief PLL Set VCO Rate.
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*
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* This function set pll vco rate.
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*
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* @param [in] base pll base
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* @param [in] src_rate pll source clk rate
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* @param [in] rate set rate
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* @param [in] ssc_cfg ssc config
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* @return set result
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*/
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status_t sdrv_pll_set_vco_rate(uint32_t base, uint32_t src_rate,
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uint32_t rate, sdrv_ckgen_pll_ssc_config_t *ssc_cfg);
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/**
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* @brief PLL Get VCO Rate.
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*
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* This function get pll vco rate.
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*
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* @param [in] base pll base
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* @param [in] src_rate pll source clk rate
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* @return get rate
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*/
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uint32_t sdrv_pll_get_vco_rate(uint32_t base, uint32_t src_rate);
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/**
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* @brief PLL Enable LVDS Clk0 Gate.
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*
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* This function enable LVDS Clk0 gate.
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*
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* @param [in] base pll base
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* @param [in] enable enable or disable
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* @return enable result
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*/
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status_t sdrv_pll_lvds_clk0_enable(uint32_t base, bool enable);
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/**
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* @brief PLL Enable LVDS Clk1 Gate.
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*
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* This function enable LVDS Clk1 gate.
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*
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* @param [in] base pll base
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* @param [in] enable enable or disable
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* @return enable result
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*/
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status_t sdrv_pll_lvds_clk1_enable(uint32_t base, bool enable);
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/**
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* @brief PLL Enable LVDS Clk2 Gate.
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*
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* This function enable LVDS Clk2 gate.
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*
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* @param [in] base pll base
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* @param [in] enable enable or disable
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* @return enable result
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*/
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status_t sdrv_pll_lvds_clk2_enable(uint32_t base, bool enable);
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/**
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* @brief PLL Enable LVDS ckgen Gate.
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*
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* This function enable LVDS ckgen gate.
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*
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* @param [in] base pll base
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* @param [in] enable enable or disable
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* @return enable result
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*/
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status_t sdrv_pll_lvds_ckgen_enable(uint32_t base, bool enable);
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/**
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* @brief PLL Set LVDS Div2.
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*
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* This function set LVDS div2 value.
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*
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* @param [in] base pll base
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* @param [in] div div2 number
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* @return set result
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*/
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status_t sdrv_pll_set_lvds_clk1_div(uint32_t base, uint8_t div);
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/**
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* @brief PLL Set LVDS Div7.
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*
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* This function set LVDS div7 value.
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*
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* @param [in] base pll base
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* @param [in] div div7 number
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* @return set result
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*/
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status_t sdrv_pll_set_lvds_clk2_div(uint32_t base, uint8_t div);
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/**
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* @brief PLL Set LVDS div ckgen
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*
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* This function set LVDS div ckgen value.
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*
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* @param [in] base pll base
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* @param [in] div div ckgen number
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* @return set result
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*/
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status_t sdrv_pll_set_lvds_ckgen_div(uint32_t base, uint8_t div);
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/**
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* @brief PLL Get LVDS Div2.
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*
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* This function Get LVDS div2 value.
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*
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* @param [in] base pll base
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* @return div2 number
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*/
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uint8_t sdrv_pll_get_lvds_clk1_div(uint32_t base);
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/**
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* @brief PLL Get LVDS Div7.
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*
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* This function Get LVDS div7 value.
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*
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* @param [in] base pll base
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* @return div7 number
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*/
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uint8_t sdrv_pll_get_lvds_clk2_div(uint32_t base);
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/**
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* @brief PLL Get LVDS div ckgen.
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*
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* This function Get LVDS div ckgen value.
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*
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* @param [in] base pll base
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* @return div ckgen number
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*/
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uint8_t sdrv_pll_get_lvds_ckgen_div(uint32_t base);
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/**
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* @brief PLL Get Lock Status.
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*
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* This function get pll lock status.
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*
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* @param [in] base pll base
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* @return lock status
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*/
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bool sdrv_pll_get_lock_status(uint32_t base);
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void sdrv_pll_set_dsm_ssc_dep(uint32_t base, uint32_t ssc_dep);
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void sdrv_pll_set_dsm_ssc_freq(uint32_t base, uint32_t ssc_freq);
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void sdrv_pll_set_dsm_ssc_mode(uint32_t base, uint32_t mode);
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#endif /* SDRV_PLL_HW_ACCESS_H_ */ |