758 lines
21 KiB
C
758 lines
21 KiB
C
/**
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* @file sdrv_acmp.c
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* @brief semidrive acmp driver
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* All rights reserved.
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*/
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#include <types.h>
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#include <bits.h>
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#include <debug.h>
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#include <string.h>
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#include <reg.h>
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#include <irq.h>
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#include <udelay/udelay.h>
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#include "sdrv_acmp.h"
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/* Define the register offsets of acmp component */
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#define ACMP_MAX_CSEL_NUM 4
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#define ACMP_MAX_INDEX_NUM 32
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#define ACMP_INIT_POLLs 200000
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#define ACMP_SOFT (0x00)
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#define ACMP_SOFT_RST (0)
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#define ACMP_SOFT_RC_TMR_RST (1)
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#define ACMP_MODE (0x04)
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#define ACMP_IT_MODE_CFG (0x08)
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#define ACMP_IT_MODE_CFG_TG_START (0)
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#define ACMP_IT_MODE_CFG_QSTART (8)
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#define ACMP_IT_MODE_CFG_QEND (16)
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#define ACMP_IT_MODE_CFG_CUR_ENTRY_PT (24)
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#define ACMP_TIMER (0x0C)
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#define ACMP_TIMER_COMPARE_VAL (0)
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#define ACMP_TIMER_TERMINAL_VAL (16)
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#define ACMP_CFG_INDEX(n) (0x10 + n * 4)
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#define ACMP_CFG_INDEX_AMSEL (0)
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#define ACMP_CFG_INDEX_CSEL (12)
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#define ACMP_CFG_INDEX_IE (16)
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#define ACMP_CFG_INDEX_UIE (17)
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#define ACMP_ANA_CFG(n) (0x90 + n * 4)
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#define ACMP_ANA_CFG_REFSEL (0)
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#define ACMP_ANA_CFG_SDSEL (1)
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#define ACMP_ANA_CFG_HCFG (4)
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#define ACMP_ANA_CFG_DAIN (8)
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#define ACMP_CTRL_CFG(n) (0xA0 + n * 4)
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#define ACMP_CTRL_CFG_AMUX_SETUP (0)
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#define ACMP_CTRL_CFG_PROP_DLY (8)
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#define ACMP_CTRL_CFG_RBW (16)
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#define ACMP_CTRL_CFG_FBW (20)
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#define ACMP_CTRL_CFG_SAMPLE_EN (24)
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#define ACMP_CTRL_CFG_MASK_EN (25)
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#define ACMP_CTRL_CFG_POL_ADJ (26)
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#define ACMP_CTRL_CFG_SYNC_EN (27)
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#define ACMP_IRQ (0xB0)
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#define ACMP_IRQ_UNCOR (0xB4)
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#define ANA_EXT_MUX_ERR (0xB8)
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#define ANA_EXT_MUX_ERR_STATUS (0)
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#define ANA_EXT_MUX_ERR_SIG_EN (16)
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#define ACMP_PD_CTRL (0xBC)
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#define ACMP_PD_CTRL_CMP (0)
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#define ACMP_PD_CTRL_DAC (1)
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#define ACMP_PD_CTRL_Q_CH_CMP (8)
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#define ACMP_PD_CTRL_Q_CH_DAC (9)
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#define ACMP_INIT (0xC0)
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#define ACMP_INIT_CNT_THRD (0)
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#define ACMP_INIT_DONE (16)
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#define ACMP_LOW_POWER (0xC4)
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#define ACMP_SCH (0xC8)
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#define ACMP_SCH_ACMP_EN (0)
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#define ACMP_SCH_ANA_INSEL_ON (1)
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#define REG_PARITY_ERR_INT_STAT (0xD0)
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#define REG_PARITY_ERR_INT_STAT_EN (0xD4)
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#define REG_PARITY_ERR_INT_SIG_EN (0xD8)
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#define FUSA_COR_ERR_INT_STAT (0xE0)
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#define FUSA_COR_ERR_INT_STAT_EN (0xE4)
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#define FUSA_COR_ERR_INT_SIG_EN (0xE8)
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#define FUSA_UNCOR_ERR_INT_STAT (0xF0)
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#define FUSA_UNCOR_ERR_INT_STAT_PWDATA_UNCOR_ERR (0)
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#define FUSA_UNCOR_ERR_INT_STAT_PWDATA_DATAL_ERR (1)
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#define FUSA_UNCOR_ERR_INT_STAT_PADDR_UNCOR_ERR (2)
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#define FUSA_UNCOR_ERR_INT_STAT_PCTL_UNCOR_ERR (3)
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#define FUSA_UNCOR_ERR_INT_STAT_INPUT_ERR (4)
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#define FUSA_UNCOR_ERR_INT_STAT_EN (0xF4)
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#define FUSA_UNCOR_ERR_INT_STAT_EN_PWDATA_UNCOR_ERR (0)
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#define FUSA_UNCOR_ERR_INT_STAT_EN_PWDATA_DATAL_ERR (1)
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#define FUSA_UNCOR_ERR_INT_STAT_EN_PADDR_UNCOR_ERR (2)
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#define FUSA_UNCOR_ERR_INT_STAT_EN_PCTL_UNCOR_ERR (3)
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#define FUSA_UNCOR_ERR_INT_STAT_EN_INPUT_ERR (4)
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#define FUSA_UNCOR_ERR_INT_SIG_EN (0xF8)
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#define FUSA_UNCOR_ERR_INT_SIG_EN_PWDATA_UNCOR_ERR (0)
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#define FUSA_UNCOR_ERR_INT_SIG_EN_PWDATA_DATAL_ERR (1)
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#define FUSA_UNCOR_ERR_INT_SIG_EN_PADDR_UNCOR_ERR (2)
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#define FUSA_UNCOR_ERR_INT_SIG_EN_PCTL_UNCOR_ERR (3)
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#define FUSA_UNCOR_ERR_INT_SIG_EN_INPUT_ERR (4)
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#define PWDATA_INJ (0x100)
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#define PWECC_INJ (0x104)
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#define SELFTEST_MODE (0x108)
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#define PRDATAINJ (0x10C)
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#define INT_ERR_INJ (0x110)
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#define INT_ERR_INJ_IE_ERR (0)
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#define INT_ERR_INJ_COR_ERR (1)
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#define INT_ERR_INJ_UNC_ERR (2)
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/**
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* @brief sdrv acmp soft reset
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*
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* @param[in] base sdrv acmp address
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*/
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static void sdrv_acmp_soft_reset(paddr_t base)
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{
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RMWREG32(base + ACMP_SOFT, ACMP_SOFT_RST, 1, 1);
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RMWREG32(base + ACMP_SOFT, ACMP_SOFT_RST, 1, 0);
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}
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/**
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* @brief sdrv acmp config mode.
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*
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* @param[in] base sdrv acmp address
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* @param[in] mode sdrv acmp mode
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*/
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static void sdrv_acmp_config_mode(paddr_t base, sdrv_acmp_mode_t mode)
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{
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writel(mode, base + ACMP_MODE);
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}
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/**
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* @brief sdrv acmp get mode.
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*
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* @param[in] base sdrv acmp address
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* @param[in] mode sdrv acmp mode
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*/
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static sdrv_acmp_mode_t sdrv_acmp_get_mode(paddr_t base)
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{
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return (sdrv_acmp_mode_t)(readl(base + ACMP_MODE) & 0x1U);
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}
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/**
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* @brief sdrv acmp config it mode.
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*
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* @param[in] base sdrv acmp address
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* @param[in] qstart sdrv acmp trigger start id number for loop
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* @param[in] qend sdrv acmp trigger end id number for loop
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* @param[in] cur_entry_pt sdrv acmp trigger first access id number
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* @return SDRV_STATUS_OK represents success or other error code
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*/
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static status_t sdrv_acmp_config_it_mode(paddr_t base, uint8_t qstart,
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uint8_t qend, uint8_t cur_entry_pt)
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{
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if ((qstart <= cur_entry_pt) && (cur_entry_pt <= qend)) {
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RMWREG32(base + ACMP_IT_MODE_CFG, ACMP_IT_MODE_CFG_QSTART, 5, qstart & 0x1F);
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RMWREG32(base + ACMP_IT_MODE_CFG, ACMP_IT_MODE_CFG_QEND, 5, qend & 0x1F);
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RMWREG32(base + ACMP_IT_MODE_CFG, ACMP_IT_MODE_CFG_CUR_ENTRY_PT, 5,
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cur_entry_pt & 0x1F);
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return SDRV_STATUS_OK;
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}
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else {
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return SDRV_ACMP_STATUS_INVALID_PARAM;
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}
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}
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/**
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* @brief sdrv acmp get it mode config.
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*
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* @param[in] base sdrv acmp address
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* @param[in] qstart sdrv acmp trigger start id number for loop
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* @param[in] qend sdrv acmp trigger end id number for loop
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* @param[in] cur_entry_pt sdrv acmp trigger first access id number
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*/
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static void sdrv_acmp_get_it_mode_config(paddr_t base, uint8_t *qstart,
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uint8_t *qend, uint8_t *cur_entry_pt)
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{
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uint32_t it_cfg = readl(base + ACMP_IT_MODE_CFG);
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*qstart = (it_cfg >> ACMP_IT_MODE_CFG_QSTART) & 0x1F;
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*qend = (it_cfg >> ACMP_IT_MODE_CFG_QEND) & 0x1F;
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*cur_entry_pt = (it_cfg >> ACMP_IT_MODE_CFG_CUR_ENTRY_PT) & 0x1F;
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}
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/**
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* @brief sdrv acmp config timer.
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*
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* @param[in] base sdrv acmp address
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* @param[in] compare_val acmp timer compare value
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* @param[in] terminal_val acmp timer terminal value
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* @return SDRV_STATUS_OK represents success or other error code
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*/
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static status_t sdrv_acmp_config_timer(paddr_t base, uint16_t compare_val,
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uint16_t terminal_val)
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{
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RMWREG32(base + ACMP_TIMER, ACMP_TIMER_COMPARE_VAL, 16, compare_val & 0xFFFF);
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if (terminal_val > compare_val) {
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RMWREG32(base + ACMP_TIMER, ACMP_TIMER_TERMINAL_VAL, 16, terminal_val & 0xFFFF);
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}
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else {
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return SDRV_ACMP_STATUS_INVALID_PARAM;
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}
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return SDRV_STATUS_OK;
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}
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/**
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* @brief sdrv acmp start it generate.
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*
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* @param[in] base sdrv acmp address
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* @param[in] trigger_start acmp it generate start
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*/
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static void sdrv_acmp_it_gen_start(paddr_t base, bool trigger_start)
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{
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RMWREG32(base + ACMP_IT_MODE_CFG, ACMP_IT_MODE_CFG_TG_START, 1, trigger_start);
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}
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/**
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* @brief sdrv acmp config csel
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*
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* @param[in] base sdrv acmp address
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* @param[in] csel_cfg sdrv acmp csel cfg
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*/
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static void sdrv_acmp_config_csel(paddr_t base, sdrv_acmp_csel_cfg_t *csel_cfg)
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{
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uint32_t val = 0;
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/* acmp ctrl cfg*/
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val = (csel_cfg->sync_en << ACMP_CTRL_CFG_SYNC_EN) |
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(csel_cfg->pol_adj << ACMP_CTRL_CFG_POL_ADJ) |
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(csel_cfg->mask_en << ACMP_CTRL_CFG_MASK_EN) |
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(csel_cfg->sample_en << ACMP_CTRL_CFG_SAMPLE_EN) |
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(csel_cfg->fbw << ACMP_CTRL_CFG_FBW) |
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(csel_cfg->rbw << ACMP_CTRL_CFG_RBW) |
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(csel_cfg->prop_delay << ACMP_CTRL_CFG_PROP_DLY) |
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(csel_cfg->amux_setup << ACMP_CTRL_CFG_AMUX_SETUP);
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writel(val, base + ACMP_CTRL_CFG(csel_cfg->csel_idx));
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/* acmp ana cfg*/
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val = (csel_cfg->dain << ACMP_ANA_CFG_DAIN) |
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(csel_cfg->hcfg << ACMP_ANA_CFG_HCFG) |
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(csel_cfg->sdsel << ACMP_ANA_CFG_SDSEL) |
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(csel_cfg->refsel << ACMP_ANA_CFG_REFSEL);
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writel(val, base + ACMP_ANA_CFG(csel_cfg->csel_idx));
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}
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/**
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* @brief sdrv acmp config index
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*
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* @param[in] base sdrv acmp address
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* @param[in] index_cfg sdrv acmp index cfg
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*/
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static void sdrv_acmp_config_index(paddr_t base,
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sdrv_acmp_index_cfg_t *index_cfg)
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{
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uint32_t val = 0;
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val = (index_cfg->uie << ACMP_CFG_INDEX_UIE) |
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(index_cfg->ie << ACMP_CFG_INDEX_IE) |
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(index_cfg->csel << ACMP_CFG_INDEX_CSEL) |
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(index_cfg->amsel << ACMP_CFG_INDEX_AMSEL);
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writel(val, base + ACMP_CFG_INDEX(index_cfg->idx));
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}
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/**
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* @brief sdrv acmp get irq state.
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*
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* @param[in] base sdrv acmp address
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* @return irq status
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*/
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static uint32_t sdrv_acmp_get_irq_state(paddr_t base)
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{
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return readl(base + ACMP_IRQ);
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}
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/**
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* @brief sdrv acmp clear irq.
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*
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* @param[in] base sdrv acmp address
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* @param[in] state irq state
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*/
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static void sdrv_acmp_clear_irq(paddr_t base, uint32_t state)
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{
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writel(state, base + ACMP_IRQ);
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}
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/**
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* @brief sdrv acmp get irq status.
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*
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* @param[in] base sdrv acmp address
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* @return init done
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*/
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static bool sdrv_acmp_lld_get_init_done(paddr_t base)
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{
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return ((readl(base + ACMP_INIT) >> ACMP_INIT_DONE) & 0x1);
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}
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/**
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* @brief sdrv acmp set low power req_n delay num.
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*
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* @param[in] base sdrv acmp address
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* @param[in] req_n_dly req_n delay number
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*/
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static void sdrv_acmp_set_low_power(paddr_t base, uint8_t req_n_dly)
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{
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writel(req_n_dly & 0xFFFF, base + ACMP_LOW_POWER);
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}
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/**
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* @brief sdrv acmp dac recieve q channel low power requset.
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*
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* @param[in] base sdrv acmp address
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* @param[in] enable cmp recieve q channel low power requset
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*/
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static void sdrv_acmp_rcv_qch_cmp(paddr_t base, bool enable)
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{
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RMWREG32(base + ACMP_PD_CTRL, ACMP_PD_CTRL_CMP, 1, enable);
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}
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/**
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* @brief sdrv acmp comperitor recieve q channel low power requset.
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*
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* @param[in] base sdrv acmp address
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* @param[in] enable dac recieve q channel low power requset
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*/
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static void sdrv_acmp_rcv_qch_dac(paddr_t base, bool enable)
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{
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RMWREG32(base + ACMP_PD_CTRL, ACMP_PD_CTRL_DAC, 1, enable);
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}
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/**
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* @brief sdrv acmp irq handler
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*
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* @param[in] irq irq number
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* @param[in] arg irq arg
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* return irq handler result
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*/
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static int sdrv_acmp_irq_handler(uint32_t irq, void *arg)
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{
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sdrv_acmp_t *dev = arg;
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uint32_t irq_state;
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int ret = 0;
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ASSERT(dev);
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irq_state = sdrv_acmp_get_irq_state(dev->base);
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if (irq_state) {
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if (dev->callback) {
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ret = dev->callback(dev, irq_state);
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}
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sdrv_acmp_clear_irq(dev->base, irq_state);
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}
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return ret;
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}
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/**
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* @brief sdrv acmp init
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*
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* This function initializes acmp device and attach callback function.
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*
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* @param[in] dev sdrv acmp device
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* @param[in] cfg sdrv acmp configuration parameters
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* @param[in] callback sdrv acmp callback function
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* @return SDRV_STATUS_OK represents success or other error code
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*/
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status_t sdrv_acmp_init(sdrv_acmp_t *dev, sdrv_acmp_config_t *cfg,
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sdrv_acmp_callback callback)
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{
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status_t ret;
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uint32_t i = 0;
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uint32_t tms = 0;
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if (cfg->base == 0) {
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return SDRV_ACMP_STATUS_INVALID_PARAM;
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}
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dev->base = cfg->base;
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dev->irq = cfg->irq;
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dev->callback = callback;
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#if (CONFIG_E3 || CONFIG_D3)
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if (IS_P0) {
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/* close ADC self-test to avoid disturbing the ACMP reference voltage */
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#if APB_ADC1_BASE
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writel(0xFFFF, APB_ADC1_BASE + 0x244);
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#endif
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#if APB_ADC2_BASE
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writel(0xFFFF, APB_ADC2_BASE + 0x244);
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#endif
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#if APB_ADC3_BASE
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writel(0xFFFF, APB_ADC3_BASE + 0x244);
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#endif
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}
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#endif
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/* soft reset */
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sdrv_acmp_soft_reset(dev->base);
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/* wait init done */
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while (!sdrv_acmp_lld_get_init_done(dev->base)) {
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if (tms++ > ACMP_INIT_POLLs) {
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return SDRV_STATUS_TIMEOUT;
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}
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}
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/* config mode */
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sdrv_acmp_config_mode(dev->base, cfg->mode);
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if (cfg->mode == ACMP_IT_MODE) {
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ret = sdrv_acmp_config_it_mode(dev->base, cfg->qstart, cfg->qend,
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cfg->cur_entry_pt);
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if (ret != SDRV_STATUS_OK) {
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return ret;
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}
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ret = sdrv_acmp_config_timer(dev->base, cfg->timer_compare_val,
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cfg->timer_terminal_val);
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if (ret != SDRV_STATUS_OK) {
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return ret;
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}
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}
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/* config csel */
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if ((cfg->csel_num > 0) && (cfg->csel_num <= ACMP_MAX_CSEL_NUM)) {
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for (i = 0; i < cfg->csel_num; i++) {
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sdrv_acmp_config_csel(dev->base, &cfg->csel_cfg[i]);
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}
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}
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else {
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return SDRV_ACMP_STATUS_INVALID_PARAM;
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}
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||
|
||
/* config index */
|
||
if ((cfg->index_num > 0) && (cfg->index_num <= ACMP_MAX_INDEX_NUM)) {
|
||
for (i = 0; i < cfg->index_num; i++) {
|
||
sdrv_acmp_config_index(dev->base, &cfg->index_cfg[i]);
|
||
}
|
||
}
|
||
else {
|
||
return SDRV_ACMP_STATUS_INVALID_PARAM;
|
||
}
|
||
|
||
/* set low power req_n delay */
|
||
if (cfg->req_n_dly > 0) {
|
||
sdrv_acmp_set_low_power(dev->base, cfg->req_n_dly);
|
||
}
|
||
|
||
/* competitor recv q channel low power request */
|
||
sdrv_acmp_rcv_qch_cmp(dev->base, cfg->qch_cmp_en);
|
||
|
||
/* dac recv q channel low power request */
|
||
sdrv_acmp_rcv_qch_dac(dev->base, cfg->qch_dac_en);
|
||
|
||
/* start it generate */
|
||
if (cfg->mode == ACMP_IT_MODE) {
|
||
sdrv_acmp_it_gen_start(dev->base, true);
|
||
}
|
||
else {
|
||
sdrv_acmp_it_gen_start(dev->base, false);
|
||
}
|
||
|
||
if (dev->irq > 0) {
|
||
irq_attach(dev->irq, sdrv_acmp_irq_handler, dev);
|
||
irq_enable(dev->irq);
|
||
}
|
||
else {
|
||
return SDRV_ACMP_STATUS_INVALID_PARAM;
|
||
}
|
||
|
||
return SDRV_STATUS_OK;
|
||
}
|
||
|
||
/**
|
||
* @brief sdrv acmp start
|
||
*
|
||
* This function is used to start or stop acmp comparation.
|
||
* All the parameters are remained when acmp stop, and the previous comparation will restart when acmp start.
|
||
*
|
||
* @param[in] dev sdrv acmp dev
|
||
* @param[in] start sdrv acmp start
|
||
* @return SDRV_STATUS_OK represents success
|
||
*/
|
||
status_t sdrv_acmp_start(sdrv_acmp_t *dev, bool start)
|
||
{
|
||
if (dev->base == 0) {
|
||
return SDRV_ACMP_STATUS_INVALID_PARAM;
|
||
}
|
||
|
||
RMWREG32(dev->base + ACMP_SCH, ACMP_SCH_ANA_INSEL_ON, 1, 0);
|
||
|
||
RMWREG32(dev->base + ACMP_SCH, ACMP_SCH_ACMP_EN, 1, start);
|
||
|
||
return SDRV_STATUS_OK;
|
||
}
|
||
|
||
/**
|
||
* @brief sdrv acmp IT mode trigger start
|
||
*
|
||
* This function is used to stop or restart trigger with differnet id numbers in IT mode.
|
||
* The new comparation will use the same comparation parameters with the former comparation.
|
||
* If the parameters need to be modified, acmp should be stopped and reinitialized.
|
||
*
|
||
* @param[in] dev sdrv acmp device
|
||
* @param[in] qstart sdrv acmp trigger start id number for loop
|
||
* @param[in] qend sdrv acmp trigger end id number for loop
|
||
* @param[in] cur_entry_pt sdrv acmp trigger first access id number
|
||
* @param[in] trigger_start acmp IT mode trigger start
|
||
* @return SDRV_STATUS_OK represents success
|
||
*/
|
||
status_t sdrv_acmp_it_trigger_start(sdrv_acmp_t *dev, uint8_t qstart, uint8_t qend, uint8_t cur_entry_pt,
|
||
bool trigger_start)
|
||
{
|
||
if (dev->base == 0) {
|
||
return SDRV_ACMP_STATUS_INVALID_PARAM;
|
||
}
|
||
|
||
/* check ACMP_IT_MODE */
|
||
if (sdrv_acmp_get_mode(dev->base) == ACMP_HT_MODE) {
|
||
return SDRV_ACMP_STATUS_WRONG_MODE;
|
||
}
|
||
|
||
/* trigger stop */
|
||
sdrv_acmp_it_gen_start(dev->base, false);
|
||
|
||
/* trigger restart */
|
||
if (trigger_start) {
|
||
sdrv_acmp_config_it_mode(dev->base, qstart, qend, cur_entry_pt);
|
||
|
||
sdrv_acmp_it_gen_start(dev->base, trigger_start);
|
||
}
|
||
|
||
return SDRV_STATUS_OK;
|
||
}
|
||
|
||
/**
|
||
* @brief sdrv acmp IT mode update valid irq state
|
||
*
|
||
* This function is used to workaround for multiple trigger if interrupt is required in IT mode.
|
||
* Occurrence scenario:
|
||
* Only appers in multiple triggers of IT mode using interrupt, but this is not a problem
|
||
* if not changing the configuration(index and analog config) at next trigger.
|
||
* At the end of each trigger, if acmp voltage comparision result is pulled up one clock cycle
|
||
* before next trigger, the interrupt generated by this trigger will update to the register ID
|
||
* of the next trigger. Other functions of ACMP are not affected.
|
||
*
|
||
* How to use this function:
|
||
* Call the function at beginning of acmp callback function.
|
||
*
|
||
* @param[in] dev sdrv acmp device
|
||
* @param[in] state sdrv acmp irq state
|
||
* @param[in] wait_time check irq valid wait time (unit: μs)，
|
||
* the period should be a little longer than terminal time.
|
||
* @return SDRV_STATUS_OK represents success
|
||
*/
|
||
status_t sdrv_acmp_it_update_valid_irq(sdrv_acmp_t *dev, uint32_t *state, uint32_t wait_time)
|
||
{
|
||
uint8_t save_qstart = 0;
|
||
uint8_t save_qend = 0;
|
||
uint8_t save_cur_entry_pt = 0;
|
||
uint8_t irq_bit = 0;
|
||
|
||
if (dev->base == 0) {
|
||
return SDRV_ACMP_STATUS_INVALID_PARAM;
|
||
}
|
||
|
||
/* check ACMP_IT_MODE */
|
||
if (sdrv_acmp_get_mode(dev->base) == ACMP_HT_MODE) {
|
||
return SDRV_ACMP_STATUS_WRONG_MODE;
|
||
}
|
||
|
||
/* save IT mode qstart/qend/cur_entry_pt */
|
||
sdrv_acmp_get_it_mode_config(dev->base, &save_qstart, &save_qend, &save_cur_entry_pt);
|
||
|
||
/* check state, and clear invalid bits */
|
||
while (*state >> irq_bit) {
|
||
/* check irq_bit */
|
||
if (BIT(*state, irq_bit)) {
|
||
/* clear irq_bit */
|
||
sdrv_acmp_clear_irq(dev->base, 1 << irq_bit);
|
||
|
||
/* stop tg_start */
|
||
sdrv_acmp_it_gen_start(dev->base, false);
|
||
|
||
/* only trigger irq_bit */
|
||
sdrv_acmp_config_it_mode(dev->base, irq_bit, irq_bit, irq_bit);
|
||
|
||
/* restart tg_start */
|
||
sdrv_acmp_it_gen_start(dev->base, true);//
|
||
|
||
/* wait more than terminal time */
|
||
udelay(wait_time);
|
||
}
|
||
|
||
/* check next bit */
|
||
irq_bit ++;
|
||
if (irq_bit > 31) {
|
||
break;
|
||
}
|
||
}
|
||
|
||
/* update irq state */
|
||
*state = sdrv_acmp_get_irq_state(dev->base);
|
||
|
||
/* restore IT mode qstart/qend/cur_entry_pt */
|
||
if (save_cur_entry_pt >= save_qend) {
|
||
save_cur_entry_pt = save_qstart;
|
||
}
|
||
else {
|
||
save_cur_entry_pt = save_cur_entry_pt + 1;
|
||
}
|
||
return sdrv_acmp_config_it_mode(dev->base, save_qstart, save_qend, save_cur_entry_pt);
|
||
}
|
||
|
||
/**
|
||
* @brief sdrv acmp power ctrl
|
||
*
|
||
* This function sets the sdrv acmp power mode.
|
||
* The status is default power on after acmp initilization.
|
||
* If the acmp comparation is finished, the power mode can be set to power down to reduce power consumption.
|
||
*
|
||
* @param[in] dev sdrv acmp device
|
||
* @param[in] down 0 power on (default), 1 power down
|
||
* @return SDRV_STATUS_OK represents success
|
||
*/
|
||
status_t sdrv_acmp_power_ctrl(sdrv_acmp_t *dev, bool down)
|
||
{
|
||
if (dev->base == 0) {
|
||
return SDRV_ACMP_STATUS_INVALID_PARAM;
|
||
}
|
||
|
||
/* power down analog competitor */
|
||
RMWREG32(dev->base + ACMP_PD_CTRL, ACMP_PD_CTRL_CMP, 1, down);
|
||
|
||
/* power down analog dac */
|
||
RMWREG32(dev->base + ACMP_PD_CTRL, ACMP_PD_CTRL_DAC, 1, down);
|
||
|
||
return SDRV_STATUS_OK;
|
||
}
|
||
|
||
/**
|
||
* @brief sdrv acmp allows analog competitor and dac enter lowpower mode
|
||
*
|
||
* This function allows competitor and dac recv q channel low power request.
|
||
* And than if the lowpower request is received, the competitor and dac will enter
|
||
* low power mode after req_n_dly clock cycle.
|
||
*
|
||
* @param[in] dev sdrv acmp device
|
||
* @param[in] cmp_en competitor enable or disable
|
||
* @param[in] dac_en dac enable or disable
|
||
* @param[in] req_n_dly enter lowpower mode delay number
|
||
* @return SDRV_STATUS_OK represents success
|
||
*/
|
||
status_t sdrv_acmp_enable_low_power(sdrv_acmp_t *dev, bool cmp_en, bool dac_en,
|
||
uint8_t req_n_dly)
|
||
{
|
||
if (dev->base == 0) {
|
||
return SDRV_ACMP_STATUS_INVALID_PARAM;
|
||
}
|
||
|
||
/* set low power req_n delay */
|
||
sdrv_acmp_set_low_power(dev->base, req_n_dly);
|
||
|
||
/* competitor recv q channel low power request */
|
||
sdrv_acmp_rcv_qch_cmp(dev->base, cmp_en);
|
||
|
||
/* dac recv q channel low power request */
|
||
sdrv_acmp_rcv_qch_dac(dev->base, dac_en);
|
||
|
||
return SDRV_STATUS_OK;
|
||
}
|
||
|
||
/**
|
||
* @brief sdrv acmp set callback
|
||
*
|
||
* This function is used to set the sdrv acmp callback function separately, after acmp initilization.
|
||
*
|
||
* @param[in] dev sdrv acmp device
|
||
* @param[in] callback acmp callback function
|
||
* @return SDRV_STATUS_OK represents success
|
||
*/
|
||
status_t sdrv_acmp_set_callback(sdrv_acmp_t *dev, sdrv_acmp_callback callback)
|
||
{
|
||
dev->callback = callback;
|
||
|
||
return SDRV_STATUS_OK;
|
||
}
|
||
|
||
/**
|
||
* @brief sdrv acmp deinit
|
||
*
|
||
* This function stops acmp and deletes acmp initilization.
|
||
* Acmp must be de-initiated before entering lowpower mode.
|
||
*
|
||
* @param[in] dev sdrv acmp device
|
||
* @return SDRV_STATUS_OK represents success
|
||
*/
|
||
status_t sdrv_acmp_deinit(sdrv_acmp_t *dev)
|
||
{
|
||
status_t ret;
|
||
|
||
if (dev->irq > 0) {
|
||
irq_disable(dev->irq);
|
||
irq_detach(dev->irq);
|
||
}
|
||
|
||
/* stop acmp */
|
||
ret = sdrv_acmp_start(dev, false);
|
||
|
||
/* clear ACMP IT mode */
|
||
sdrv_acmp_config_mode(dev->base, ACMP_HT_MODE);
|
||
|
||
/* soft reset */
|
||
sdrv_acmp_soft_reset(dev->base);
|
||
|
||
/* clear the acmp controller. */
|
||
(void)memset(dev, 0, sizeof(sdrv_acmp_t));
|
||
|
||
return ret;
|
||
}
|