131 lines
5.0 KiB
C
131 lines
5.0 KiB
C
/*
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* csi_reg.h
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*
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* Semidrive platform mipi csi2 header file
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*
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* Copyright (C) 2021, Semidrive Communications Inc.
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*
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* This file is licensed under a dual GPLv2 or X11 license.
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*/
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#ifndef __CSI_REG_H__
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#define __CSI_REG_H__
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/* all registers in csi ip */
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#define CSI_REG_ENABLE 0x00
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#define CSI_REG_INT_STAT0 0x04
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#define CSI_REG_INT_STAT1 0x08
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#define CSI_REG_INT_MASK0 0x0c
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#define CSI_REG_INT_MASK1 0x10
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#define CSI_REG_REG_LOAD 0x14
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/* n: 0 ~ 3, indicates image channel. */
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#define CSI_REG_IMG_RGBY_BADDR_H(n) (0x100 + n * 0x80)
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#define CSI_REG_IMG_RGBY_BADDR_L(n) (0x104 + n * 0x80)
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#define CSI_REG_IMG_U_BADDR_H(n) (0x108 + n * 0x80)
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#define CSI_REG_IMG_U_BADDR_L(n) (0x10c + n * 0x80)
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#define CSI_REG_IMG_V_BADDR_H(n) (0x110 + n * 0x80)
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#define CSI_REG_IMG_V_BADDR_L(n) (0x114 + n * 0x80)
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#define CSI_REG_IMG_RGBY_STRIDE(n) (0x118 + n * 0x80)
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#define CSI_REG_IMG_U_STRIDE(n) (0x11c + n * 0x80)
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#define CSI_REG_IMG_V_STRIDE(n) (0x120 + n * 0x80)
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#define CSI_REG_IMG_SIZE(n) (0x124 + n * 0x80)
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#define CSI_REG_IMG_IPI_CTRL(n) (0x128 + n * 0x80)
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#define CSI_REG_IMG_IF_PIXEL_MASK0(n) (0x12c + n * 0x80)
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#define CSI_REG_IMG_IF_PIXEL_MASK1(n) (0x130 + n * 0x80)
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#define CSI_REG_IMG_CHN_CTRL(n) (0x134 + n * 0x80)
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#define CSI_REG_IMG_CHN_SPLIT0(n) (0x138 + n * 0x80)
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#define CSI_REG_IMG_CHN_SPLIT1(n) (0x13c + n * 0x80)
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#define CSI_REG_IMG_CHN_SPLIT2(n) (0x140 + n * 0x80)
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#define CSI_REG_IMG_CHN_CROP0(n) (0x144 + n * 0x80)
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#define CSI_REG_IMG_CHN_CROP1(n) (0x148 + n * 0x80)
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#define CSI_REG_IMG_CHN_CROP2(n) (0x14c + n * 0x80)
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#define CSI_REG_IMG_CHN_PACK0(n) (0x150 + n * 0x80)
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#define CSI_REG_IMG_CHN_PACK1(n) (0x154 + n * 0x80)
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#define CSI_REG_IMG_CHN_PACK2(n) (0x158 + n * 0x80)
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#define CSI_REG_IMG_CHN_VCROP0(n) (0x15c + n * 0x80)
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/* n: 0 ~ 7, indicates wdma output channel, max 2 channels for each image */
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#define CSI_REG_WDMA_CHN_DFIFO(n) (0x300 + n * 0x20)
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#define CSI_REG_WDMA_CHN_CFIFO(n) (0x304 + n * 0x20)
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#define CSI_REG_WDMA_CHN_AXI_CTRL0(n) (0x308 + n * 0x20)
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#define CSI_REG_WDMA_CHN_AXI_CTRL1(n) (0x30c + n * 0x20)
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#define CSI_REG_WDMA_CHN_AXI_CTRL2(n) (0x310 + n * 0x20)
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#define CSI_REG_WDMA_CHN_STATE(n) (0x314 + n * 0x20)
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/* n: 0 ~ 3, indicates image channel.
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* Actually 1~3 will never be used because only image0 can get input from
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* outside of SOC
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*/
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#define CSI_REG_PARA_BT_CTRL0(n) (0x500 + n * 0x40)
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#define CSI_REG_PARA_BT_CTRL1(n) (0x504 + n * 0x40)
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#define CSI_REG_PARA_BT_CTRL2(n) (0x508 + n * 0x40)
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#define CSI_REG_PIXEL_MAP(n) (0x50C + n * 0x40)
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/* n: 0 ~ 1, indicates image channel. */
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#define CSI_REG_IMG_FB_CTRL(n) (0x800 + n * 0x80)
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#define CSI_REG_IMG_UP_RGBY_ADDR(n) (0x804 + n * 0x80)
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#define CSI_REG_IMG_LOW_RGBY_ADDR(n) (0x808 + n * 0x80)
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#define CSI_REG_IMG_UP_U_ADDR(n) (0x810 + n * 0x80)
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#define CSI_REG_IMG_LOW_U_ADDR(n) (0x814 + n * 0x80)
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#define CSI_REG_IMG_UP_V_ADDR(n) (0x818 + n * 0x80)
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#define CSI_REG_IMG_LOW_V_ADDR(n) (0x81c + n * 0x80)
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enum csi_int0_status {
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CSI_INT0_STORE_DONE0 = (1 << 0),
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CSI_INT0_STORE_DONE1 = (1 << 1),
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CSI_INT0_STORE_DONE2 = (1 << 2),
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CSI_INT0_STORE_DONE3 = (1 << 3),
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CSI_INT0_SHADOW_SET0 = (1 << 4),
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CSI_INT0_SHADOW_SET1 = (1 << 5),
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CSI_INT0_SHADOW_SET2 = (1 << 6),
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CSI_INT0_SHADOW_SET3 = (1 << 7),
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CSI_INT0_BT_ERR = (1 << 8),
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CSI_INT0_BT_FATAL = (1 << 9),
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CSI_INT0_BT_FIELD_CHANGE = (1 << 10),
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};
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enum csi_int1_status {
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CSI_INT1_CROP_ERR0 = (1 << 0),
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CSI_INT1_CROP_ERR1 = (1 << 1),
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CSI_INT1_CROP_ERR2 = (1 << 2),
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CSI_INT1_CROP_ERR3 = (1 << 3),
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CSI_INT1_PIXEL_ERR0 = (1 << 4),
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CSI_INT1_PIXEL_ERR1 = (1 << 5),
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CSI_INT1_PIXEL_ERR2 = (1 << 6),
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CSI_INT1_PIXEL_ERR3 = (1 << 7),
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CSI_INT1_OVERFLOW0 = (1 << 8),
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CSI_INT1_OVERFLOW1 = (1 << 9),
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CSI_INT1_OVERFLOW2 = (1 << 10),
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CSI_INT1_OVERFLOW3 = (1 << 11),
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CSI_INT1_IMG0_BUSERR0 = (1 << 12),
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CSI_INT1_IMG0_BUSERR1 = (1 << 13),
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CSI_INT1_IMG0_BUSERR2 = (1 << 14),
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CSI_INT1_IMG1_BUSERR0 = (1 << 15),
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CSI_INT1_IMG1_BUSERR1 = (1 << 16),
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CSI_INT1_IMG1_BUSERR2 = (1 << 17),
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CSI_INT1_IMG2_BUSERR0 = (1 << 18),
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CSI_INT1_IMG2_BUSERR1 = (1 << 19),
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CSI_INT1_IMG2_BUSERR2 = (1 << 20),
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CSI_INT1_IMG3_BUSERR0 = (1 << 21),
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CSI_INT1_IMG3_BUSERR1 = (1 << 22),
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CSI_INT1_IMG3_BUSERR2 = (1 << 23),
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};
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#define INT0_ERR_MASK(n) ((CSI_INT0_BT_ERR << n) | (CSI_INT0_BT_FATAL << 0))
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#define INT0_MASK(n) (CSI_INT0_SHADOW_SET0 << n)
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#define INT0_BT_MASK(n) (INT0_ERR_MASK(n) | (CSI_INT0_SHADOW_SET0 << n))
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#define INT0_ERR_MASK_ALL \
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(INT0_ERR_MASK(0) | INT0_ERR_MASK(1) | INT0_ERR_MASK(2) | INT0_ERR_MASK(3))
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#define INT1_ERR_MASK(n) \
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(((CSI_INT1_CROP_ERR0 | CSI_INT1_PIXEL_ERR0 | CSI_INT1_OVERFLOW0) << n) | \
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(CSI_INT1_IMG0_BUSERR0 << (n * 3)))
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#define INT1_ERR_MASK_ALL \
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(INT1_ERR_MASK(0) | INT1_ERR_MASK(1) | INT1_ERR_MASK(2) | INT1_ERR_MASK(3))
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#endif /* __CSI_REG_H__ */ |