718 lines
22 KiB
C
718 lines
22 KiB
C
/**
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* @file sdrv_epwm.h
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* @brief SemiDrive Energy Pulse-Width Modulation (EPWM) driver header file.
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*
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* @copyright Copyright (c) 2022 Semidrive Semiconductor.
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* @All rights reserved.
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*
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*/
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#ifndef SDRV_EPWM_DRV_H_
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#define SDRV_EPWM_DRV_H_
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#include "../source/epwm/sdrv_epwm_reg.h"
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#if CONFIG_E3L
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#if ((CONFIG_E3106) || (CONFIG_E3104))
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#define EPWM_SOURCE_CLK 150
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#else
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#define EPWM_SOURCE_CLK 198
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#endif
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#else
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#define EPWM_SOURCE_CLK 250
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#endif
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#define EPWM_FIFO_A_OFFSET (0xc0U)
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#define EPWM_FIFO_B_OFFSET (0xc4U)
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#define EPWM_FIFO_C_OFFSET (0xc8U)
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#define EPWM_FIFO_D_OFFSET (0xccU)
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#define EPWM_CNT_G0_OVF_OFFSET (0x104U)
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#define EPWM_CNT_G1_OVF_OFFSET (0x124U)
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#define EPWM_INT_STA_EN (0x3f << 0 | 0xf << 20)
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#define EPWM_COR_ERR_INT_STA_EN (0xf << 0 | 0xffff << 8)
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#define EPWM_UNC_ERR_INT_STA_EN (0xf << 0 | 0xffff << 8)
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#define EPWM_BM_INT_EN_CHN_D_DMA_REQ_SHIFT (23U)
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#define EPWM_BM_INT_EN_CHN_C_DMA_REQ_SHIFT (22U)
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#define EPWM_BM_INT_EN_CHN_B_DMA_REQ_SHIFT (21U)
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#define EPWM_BM_INT_EN_CHN_A_DMA_REQ_SHIFT (20U)
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#define EPWM_BM_INT_EN_CNT_G1_OVF_SHIFT (5U)
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#define EPWM_BM_INT_EN_CNT_G0_OVF_SHIFT (4U)
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#define EPWM_BM_INT_EN_CMP_D_SHIFT (3U)
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#define EPWM_BM_INT_EN_CMP_C_SHIFT (2U)
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#define EPWM_BM_INT_EN_CMP_B_SHIFT (1U)
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#define EPWM_BM_INT_EN_CMP_A_SHIFT (0U)
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#define EPWM_BM_ERR_INT_STA_CMP_D_REG_UPD_TWICE_SHIFT (23U)
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#define EPWM_BM_ERR_INT_STA_CMP_C_REG_UPD_TWICE_SHIFT (22U)
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#define EPWM_BM_ERR_INT_STA_CMP_B_REG_UPD_TWICE_SHIFT (21U)
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#define EPWM_BM_ERR_INT_STA_CMP_A_REG_UPD_TWICE_SHIFT (20U)
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#define EPWM_BM_ERR_INT_STA_CMP_D_REG_NO_UPD_SHIFT (19U)
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#define EPWM_BM_ERR_INT_STA_CMP_C_REG_NO_UPD_SHIFT (18U)
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#define EPWM_BM_ERR_INT_STA_CMP_B_REG_NO_UPD_SHIFT (17U)
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#define EPWM_BM_ERR_INT_STA_CMP_A_REG_NO_UPD_SHIFT (16U)
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#define EPWM_BM_ERR_INT_STA_CMP_D_FAULT_EVENT_SHIFT (15U)
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#define EPWM_BM_ERR_INT_STA_CMP_C_FAULT_EVENT_SHIFT (14U)
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#define EPWM_BM_ERR_INT_STA_CMP_B_FAULT_EVENT_SHIFT (13U)
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#define EPWM_BM_ERR_INT_STA_CMP_A_FAULT_EVENT_SHIFT (12U)
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#define EPWM_BM_ERR_INT_STA_CMP_D0_FAULT_SHIFT (11U)
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#define EPWM_BM_ERR_INT_STA_CMP_C0_FAULT_SHIFT (10U)
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#define EPWM_BM_ERR_INT_STA_CMP_B0_FAULT_SHIFT (9U)
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#define EPWM_BM_ERR_INT_STA_CMP_A0_FAULT_SHIFT (8U)
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#define EPWM_BM_ERR_INT_STA_FIFO_D_UNDERRUN_SHIFT (3U)
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#define EPWM_BM_ERR_INT_STA_FIFO_C_UNDERRUN_SHIFT (2U)
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#define EPWM_BM_ERR_INT_STA_FIFO_B_UNDERRUN_SHIFT (1U)
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#define EPWM_BM_ERR_INT_STA_FIFO_A_UNDERRUN_SHIFT (0U)
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#define EPWM_BM_CHN_D_DMA_REQ (1 << EPWM_BM_INT_EN_CHN_D_DMA_REQ_SHIFT)
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#define EPWM_BM_CHN_C_DMA_REQ (1 << EPWM_BM_INT_EN_CHN_C_DMA_REQ_SHIFT)
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#define EPWM_BM_CHN_B_DMA_REQ (1 << EPWM_BM_INT_EN_CHN_B_DMA_REQ_SHIFT)
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#define EPWM_BM_CHN_A_DMA_REQ (1 << EPWM_BM_INT_EN_CHN_A_DMA_REQ_SHIFT)
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#define EPWM_BM_CNT_G0_OVF (1 << EPWM_BM_INT_EN_CNT_G0_OVF_SHIFT)
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#define EPWM_BM_CNT_G1_OVF (1 << EPWM_BM_INT_EN_CNT_G1_OVF_SHIFT)
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#define EPWM_BM_CMP_D (1 << EPWM_BM_INT_EN_CMP_D_SHIFT)
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#define EPWM_BM_CMP_C (1 << EPWM_BM_INT_EN_CMP_C_SHIFT)
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#define EPWM_BM_CMP_B (1 << EPWM_BM_INT_EN_CMP_B_SHIFT)
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#define EPWM_BM_CMP_A (1 << EPWM_BM_INT_EN_CMP_A_SHIFT)
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#define EPWM_BM_CMP_D_REG_UPD_TWICE \
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(1 << EPWM_BM_ERR_INT_STA_CMP_D_REG_UPD_TWICE_SHIFT)
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#define EPWM_BM_CMP_C_REG_UPD_TWICE \
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(1 << EPWM_BM_ERR_INT_STA_CMP_C_REG_UPD_TWICE_SHIFT)
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#define EPWM_BM_CMP_B_REG_UPD_TWICE \
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(1 << EPWM_BM_ERR_INT_STA_CMP_B_REG_UPD_TWICE_SHIFT)
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#define EPWM_BM_CMP_A_REG_UPD_TWICE \
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(1 << EPWM_BM_ERR_INT_STA_CMP_A_REG_UPD_TWICE_SHIFT)
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#define EPWM_BM_CMP_D_REG_NO_UPD \
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(1 << EPWM_BM_ERR_INT_STA_CMP_D_REG_NO_UPD_SHIFT)
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#define EPWM_BM_CMP_C_REG_NO_UPD \
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(1 << EPWM_BM_ERR_INT_STA_CMP_C_REG_NO_UPD_SHIFT)
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#define EPWM_BM_CMP_B_REG_NO_UPD \
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(1 << EPWM_BM_ERR_INT_STA_CMP_B_REG_NO_UPD_SHIFT)
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#define EPWM_BM_CMP_A_REG_NO_UPD \
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(1 << EPWM_BM_ERR_INT_STA_CMP_A_REG_NO_UPD_SHIFT)
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#define EPWM_BM_CMP_D_FAULT_EVENT \
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(1 << EPWM_BM_ERR_INT_STA_CMP_D_FAULT_EVENT_SHIFT)
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#define EPWM_BM_CMP_C_FAULT_EVENT \
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(1 << EPWM_BM_ERR_INT_STA_CMP_C_FAULT_EVENT_SHIFT)
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#define EPWM_BM_CMP_B_FAULT_EVENT \
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(1 << EPWM_BM_ERR_INT_STA_CMP_B_FAULT_EVENT_SHIFT)
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#define EPWM_BM_CMP_A_FAULT_EVENT \
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(1 << EPWM_BM_ERR_INT_STA_CMP_A_FAULT_EVENT_SHIFT)
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#define EPWM_BM_CMP_D0_FAULT (1 << EPWM_BM_ERR_INT_STA_CMP_D0_FAULT_SHIFT)
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#define EPWM_BM_CMP_C0_FAULT (1 << EPWM_BM_ERR_INT_STA_CMP_C0_FAULT_SHIFT)
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#define EPWM_BM_CMP_B0_FAULT (1 << EPWM_BM_ERR_INT_STA_CMP_B0_FAULT_SHIFT)
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#define EPWM_BM_CMP_A0_FAULT (1 << EPWM_BM_ERR_INT_STA_CMP_A0_FAULT_SHIFT)
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#define EPWM_BM_FIFO_D_UNDERRUN (1 << EPWM_BM_ERR_INT_STA_FIFO_D_UNDERRUN_SHIFT)
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#define EPWM_BM_FIFO_C_UNDERRUN (1 << EPWM_BM_ERR_INT_STA_FIFO_C_UNDERRUN_SHIFT)
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#define EPWM_BM_FIFO_B_UNDERRUN (1 << EPWM_BM_ERR_INT_STA_FIFO_B_UNDERRUN_SHIFT)
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#define EPWM_BM_FIFO_A_UNDERRUN (1 << EPWM_BM_ERR_INT_STA_FIFO_A_UNDERRUN_SHIFT)
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#if CONFIG_E3L
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_D_CMP11 (0x01U << 15U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_D_CMP10 (0x01U << 14U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_D_CMP01 (0x01U << 13U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_D_CMP00 (0x01U << 12U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_C_CMP11 (0x01U << 11U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_C_CMP10 (0x01U << 10U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_C_CMP01 (0x01U << 9U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_C_CMP00 (0x01U << 8U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_B_CMP11 (0x01U << 7U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_B_CMP10 (0x01U << 6U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_B_CMP01 (0x01U << 5U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_B_CMP00 (0x01U << 4U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_A_CMP11 (0x01U << 3U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_A_CMP10 (0x01U << 2U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_A_CMP01 (0x01U << 1U)
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#define EPWM_BM_CENTER_ALIGN_CMP_INT_STA_CMP_A_CMP00 (0x01U << 0U)
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#endif
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/**
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* @brief epwm_cmp_cfg_con_mode.
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*/
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typedef enum epwm_cmp_cfg_con_mode {
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EPWM_CONSECUTIVE_MODE,
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EPWM_ONLY_EXECUTE_ONE_TIME,
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} epwm_cmp_cfg_con_mode_e;
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/**
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* @brief epwm_cmp_out_mode.
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*/
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typedef enum epwm_cmp_out_mode {
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EPWM_ONLY_COMP0_OUTPUT,
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EPWM_BOTH_COMP0_AND_COMP1_OUTPUT,
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} epwm_cmp_out_mode_e;
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/**
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* @brief epwm_cfg_ctrl_dma_trig_sel.
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*/
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typedef enum epwm_cfg_ctrl_dma_trig_sel {
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EPWM_CMP_A_CE = 1 << 0,
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EPWM_CMP_B_CE = 1 << 1,
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EPWM_CMP_C_CE = 1 << 2,
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EPWM_CMP_D_CE = 1 << 3,
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EPWM_CNT_G0_CE = 1 << 4,
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EPWM_CNT_G1_CE = 1 << 5,
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} epwm_cfg_ctrl_dma_trig_sel_e;
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/**
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* @brief epwm_cmpxx_val NS.
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*/
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typedef struct epwm_multi_cmp_val {
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uint32_t cmp00_val; /**< multi compare00 value*/
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uint32_t cmp01_val; /**< multi compare01 value*/
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uint32_t cmp10_val; /**< multi compare10 value*/
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uint32_t cmp11_val; /**< multi compare11 value*/
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} epwm_multi_cmp_val_t;
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/**
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* @brief epwm_eid_val.
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*/
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typedef struct epwm_eid_val {
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uint8_t eid00; /**< compare00 event ID*/
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uint8_t eid01; /**< compare01 event ID*/
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uint8_t eid10; /**< compare10 event ID*/
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uint8_t eid11; /**< compare11 event ID*/
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} epwm_eid_val_t;
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/**
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* @brief epwm_dual_duty_state.
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*/
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typedef struct epwm_dual_duty_state {
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uint32_t left_point; /**< dual compare mode left point value*/
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uint32_t right_point; /**< dual compare mode right point value*/
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} epwm_dual_duty_state_t;
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/**
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* @brief epwm_fs_sta.
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*/
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typedef struct epwm_fs_state {
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bool cmp0_fs_state; /**< cmp0 failsafe state*/
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bool cmp1_fs_state; /**< cmp1 failsafe state*/
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} epwm_fs_state_t;
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/**
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* @brief epwm_dma_cfg.
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*/
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typedef struct epwm_dma_cfg {
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bool dma_enable; /**< compare channel dma enable*/
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uint8_t fifo_wml; /**< compare channel fifo water mark level*/
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} epwm_dma_cfg_t;
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/**
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* @brief pwm_status.
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*
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*/
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typedef struct pwm_status {
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uint32_t period; /**< PWM period in nano seconds. */
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uint32_t duty1; /**< PWM cmp0 dutycycle in nano seconds. */
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uint32_t duty2; /**< PWM cmp1 dutycycle in nano seconds. */
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} pwm_state_t;
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typedef struct sdrv_epwm_controller sdrv_epwm_controller_t;
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typedef void (*pwm_callback_t)(void *arg, uint32_t irq_status);
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/**
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* @brief epwm_cmp_cfg.
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*/
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typedef struct epwm_cmp_cfg {
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/**< pwm cnt sellect */
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sdrv_epwm_cnt_gx_e cmp_cnt_sel;
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/**< pwm [x]0 or [x]1 output */
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epwm_cmp_out_mode_e chnl_out_mode;
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/**< pwm consecutive mode */
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epwm_cmp_cfg_con_mode_e con_mode;
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/**< pwm cmp_mode */
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sdrv_epwm_cmp_mode_e cmp_mode;
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/**< pwm cmp event mode */
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sdrv_epwm_cmp_event_out_t out_mode;
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/**< pwm cmp00/01/10/11 pulse width */
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sdrv_epwm_cmp_pulse_wid0_t cmp_pulse_wid0;
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/**< pwm ovf00/01 pulse width */
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sdrv_epwm_cmp_pulse_wid1_t cmp_pulse_wid1;
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/**< pwm refresh time */
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uint8_t refresh_intval;
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/**< pwm enable audio */
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bool audio_enable;
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/**< pwm dma enable */
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epwm_dma_cfg_t dma_cfg;
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/**< pwm software reload */
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bool sw_rld_mode;
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#if CONFIG_E3L
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/**< pwm center align mode */
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bool center_align_mode;
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#endif
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} epwm_cmp_cfg_t;
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/**
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* @brief ePWM controller.
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*
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*/
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typedef struct sdrv_epwm {
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/**< module base addr */
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paddr_t base;
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/**< callback function */
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pwm_callback_t cb;
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/**< pwm cmp cfg */
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epwm_cmp_cfg_t cmp_cfg;
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/**< pwm cmp channel id */
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sdrv_epwm_channel_e chnl;
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/**< pwm dual cmp value aux */
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epwm_dual_duty_state_t pre_duty;
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/**< pwm module controller */
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sdrv_epwm_controller_t *controller;
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} sdrv_epwm_t;
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/* sdrv epwm controller module */
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struct sdrv_epwm_controller {
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/**< module base addr */
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uint32_t base;
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/**< module irq id */
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uint8_t irq;
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/**< irq cntg0/g1 */
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/**< when using cntg0 ovf int, must set channel a callback function */
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/**< when using cntg1 ovf int, must set channel b callback function */
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uint32_t irq_id;
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/**< clk src */
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sdrv_epwm_clk_config_src_clk_sel_e clk_src;
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/**< clk_div */
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uint16_t clk_div;
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/**< channel ctrl */
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sdrv_epwm_t *epwm_bank[SDRV_EPWM_CHANNEL_NR];
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};
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/**
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* @brief sdrv epwm ns transfer to val.
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*
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* @param[in] clk src clk
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* @param[in] ns time val
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* @param[in] div src clk divider
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* @return ns_to_val
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*/
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uint32_t sdrv_epwm_ns_to_val(uint32_t clk, uint32_t ns, uint32_t div);
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/**
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* @brief sdrv epwm ns transfer to val and minus 1.
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*
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* @param[in] clk src clk
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* @param[in] ns time val
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* @param[in] div src clk divider
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* @return ns_to_val_minus_1
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*/
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uint32_t sdrv_epwm_ns_to_val_1(uint32_t clk, uint32_t ns, uint32_t div);
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/**
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* @brief sdrv epwm val transfer to ns.
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*
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* @param[in] clk src clk
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* @param[in] cnt time val
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* @param[in] div src clk divider
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* @return val_to_ns
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*/
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uint32_t sdrv_epwm_val_to_ns(uint32_t clk, uint32_t val, uint32_t div);
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/**
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* @brief compare channel enable.
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*
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* This function enable compare channel
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*
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* @param[in] dev pwm common instance
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*
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*/
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void sdrv_epwm_cmp_en(sdrv_epwm_t *dev, bool en);
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/**
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* @brief counter enable.
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*
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* This function enable CNTG0 or CNT_G1
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*
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* @param[in] dev pwm common instance
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*
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*/
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void sdrv_epwm_cnt_en(sdrv_epwm_t *dev, bool en);
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/**
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* @brief Start ePWM channel output.
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*
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* This function start pwm output
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*
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* @param[in] dev pwm common instance
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*
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*/
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void sdrv_epwm_start(sdrv_epwm_t *dev);
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/**
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* @brief Stop ePWM channel output.
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*
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* This function stop pwm output
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*
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* @param[in] dev pwm common instance
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*
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*/
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void sdrv_epwm_stop(sdrv_epwm_t *dev);
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/**
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* @brief cnt overflow value upload (unit is ns)
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*
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* This function upload counter overflow value
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*
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* @param[in] dev pwm common instance
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* @param[in] period cnt overflow value
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*/
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void sdrv_epwm_cnt_ovf_upd(sdrv_epwm_t *dev, uint32_t period);
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/**
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* @brief compare value upload
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*
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* This function upload compare value
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*
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* @param[in] dev pwm common instance
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* @param[in] state pwm duty and period
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*/
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status_t sdrv_epwm_cmp_val_upd(sdrv_epwm_t *dev, const pwm_state_t *state);
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/**
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* @brief ePWM channel config.
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*
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* This function configure epwm
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*
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* @param[in] dev pwm common instance
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* @param[in] state pwm duty and period
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*
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*/
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status_t sdrv_epwm_config(sdrv_epwm_t *dev, const pwm_state_t *state);
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/**
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* @brief epwm setup callback function
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*
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* @param[in] dev: epwm ctrl instance
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* @param[in] callback: user callback function
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* @return succeed:0 fail:other
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|
*/
|
|
uint8_t sdrv_epwm_set_callback(sdrv_epwm_t *dev, pwm_callback_t callback);
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|
|
|
/**
|
|
* @brief configure multi compare mode
|
|
*
|
|
* This function configure multi compare value
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] state pwm duty and period
|
|
* @param[in] multi cmp00/01/10/11 val
|
|
*
|
|
*/
|
|
status_t sdrv_epwm_multi_cmp_mode(sdrv_epwm_t *dev, pwm_state_t *state,
|
|
epwm_multi_cmp_val_t *multi_cmp);
|
|
|
|
/**
|
|
* @brief configure epwm counter clear
|
|
*
|
|
* This function configure counter clear
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] cnt_clr_trig_sel sellect cnt_clr_trig_polarity
|
|
* @param[in] clr_sel input_clr_sel_trig
|
|
*
|
|
*/
|
|
void sdrv_epwm_cnt_clr_cfg(sdrv_epwm_t *dev,
|
|
sdrv_epwm_event_trigger_mode_e cnt_clr_trig_sel,
|
|
sdrv_epwm_input_sel_trig_e clr_sel);
|
|
|
|
/**
|
|
* @brief configure epwm counter overflow upload cfg
|
|
*
|
|
* This function configure counter overflow upload
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] set_mode_sel sellect set_mode
|
|
* @param[in] cnt_set_trig_sel sellect cnt_set_trig_polarity
|
|
* @param[in] set_sel input_set_sel_trig
|
|
*
|
|
*/
|
|
void sdrv_epwm_cnt_ovf_upd_cfg(sdrv_epwm_t *dev,
|
|
sdrv_epwm_cnt_cfg_set_upd_sel_e set_mode_sel,
|
|
sdrv_epwm_event_trigger_mode_e cnt_set_trig_sel,
|
|
sdrv_epwm_input_sel_trig_e set_sel);
|
|
|
|
/**
|
|
* @brief software trigger
|
|
*
|
|
* This function configure software trigger, such as pulse.
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] tirg sellect trigger mode
|
|
*
|
|
*/
|
|
void sdrv_epwm_sw_trig(sdrv_epwm_t *dev, sdrv_epwm_sw_trig_ctrl_e trig);
|
|
|
|
/**
|
|
* @brief configure epwm death time
|
|
*
|
|
* This function configure compare death time
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] prefin_pol prefinial polarity
|
|
* @param[in] dti_val death time value
|
|
*
|
|
*/
|
|
void sdrv_epwm_dti(sdrv_epwm_t *dev, sdrv_epwm_cmp_prefin_pol_t *prefin_pol,
|
|
const uint32_t dti_val);
|
|
|
|
/**
|
|
* @brief configure sse epwm output
|
|
*
|
|
* This function configure compare sse mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] sse_cfg sse_mode and edge sellect
|
|
* @param[in] sse_reg_val sse register value
|
|
*
|
|
*/
|
|
void sdrv_epwm_sse(sdrv_epwm_t *dev, sdrv_epwm_cmp_sse_ctrl_t *sse_cfg,
|
|
uint32_t sse_reg_val);
|
|
|
|
/**
|
|
* @brief configure modulation frequency control
|
|
*
|
|
* This function configure compare mfc mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] val mfc up times to 2^val times
|
|
*
|
|
*/
|
|
void sdrv_epwm_mfc(sdrv_epwm_t *dev, uint8_t val);
|
|
|
|
/**
|
|
* @brief configure compare data format
|
|
*
|
|
* This function configure compare data format, such as 8bit or 16bit.
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] dat_format cmp data formate
|
|
*/
|
|
void sdrv_epwm_cmp_data_format(
|
|
sdrv_epwm_t *dev, sdrv_epwm_chn_dma_ctrl_cmp_x_dat_format_e dat_format);
|
|
|
|
/**
|
|
* @brief configure compare dither mode
|
|
*
|
|
* This function configure compare dither mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] clip_rslt dither clip_rslt val
|
|
* @param[in] init_offset dither init_offset val
|
|
*/
|
|
void sdrv_epwm_cmp_dither(sdrv_epwm_t *dev, uint8_t clip_rslt,
|
|
uint16_t init_offset);
|
|
|
|
/**
|
|
* @brief configure compare multi channels
|
|
*
|
|
* This function configure compare value of multi channels
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] full_en full channels enable
|
|
*/
|
|
void sdrv_epwm_cmp_multi_chnl(sdrv_epwm_t *dev, bool full_en);
|
|
|
|
/**
|
|
* @brief configure compare event/cnt overflow event
|
|
*
|
|
* This function configure compare event or counter event
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] src_sel choose cmp or cnt trigger source
|
|
*/
|
|
void sdrv_epwm_ce_ctrl(sdrv_epwm_t *dev, bool src_sel);
|
|
|
|
/**
|
|
* @brief configure dma request except fifo wml trig
|
|
*
|
|
* This function configure pwm trig dma tranferrs with ce
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] sel_trig sellect trigger source
|
|
*/
|
|
void sdrv_epwm_ce_dma_trig(sdrv_epwm_t *dev, uint8_t sel_trig);
|
|
|
|
/**
|
|
* @brief filter input fault source signals
|
|
*
|
|
* This function configure fault event source
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] flt_cfg config filter
|
|
*/
|
|
void sdrv_epwm_fault_flt(sdrv_epwm_t *dev, sdrv_epwm_fault_flt_t *flt_cfg);
|
|
|
|
/**
|
|
* @brief configure input fault event
|
|
*
|
|
* This function configure compare fault event
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] fault_src config which fault source to trigger
|
|
* @param[in] fault_cfg config fault event
|
|
* @param[in] fs_state cmp failsafe status
|
|
*/
|
|
void sdrv_epwm_fault_event(sdrv_epwm_t *dev, uint8_t fault_src,
|
|
sdrv_epwm_cmp_fault_event_ctrl_t *fault_cfg,
|
|
epwm_fs_state_t *fs_state);
|
|
|
|
/**
|
|
* @brief input fault event clr
|
|
*
|
|
* This function clear fault status in sticky mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] fault_src config which fault source to trigger
|
|
*/
|
|
void sdrv_epwm_fault_event_clr(sdrv_epwm_t *dev, uint8_t fault_src);
|
|
|
|
/**
|
|
* @brief cnt overflow value upload directly (unit is cnt val)
|
|
*
|
|
* This function configure counter overflow upload
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] period_cnt counter overflow value
|
|
*/
|
|
void sdrv_epwm_cnt_ovf_dir_upd(sdrv_epwm_t *dev, uint32_t period_cnt);
|
|
|
|
/**
|
|
* @brief upload chnl_b/c/d compare value with dual mode 100% duty check(unit is
|
|
* cnt val)
|
|
*
|
|
* This function upload channel_b/c/d value with 100% over two period
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] left_point dual mode left cmp_val
|
|
* @param[in] right_point dual mode right cmp_val
|
|
*/
|
|
void sdrv_epwm_cmp_bcd_update(sdrv_epwm_t *dev, uint32_t left_point,
|
|
uint32_t right_point);
|
|
|
|
/**
|
|
* @brief compare value chnl_b/c/d upload (unit is cnt val)
|
|
*
|
|
* This function upload compare value in dual mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] left_point dual mode left cmp_val
|
|
* @param[in] right_point dual mode right cmp_val
|
|
*/
|
|
void sdrv_epwm_cmp_val_upd_bcd(sdrv_epwm_t *dev, uint32_t left_point,
|
|
uint32_t right_point);
|
|
|
|
/**
|
|
* @brief compare value chnl_a upload (unit is cnt val)
|
|
*
|
|
* This function upload channel a value
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] trig_point set trig point to tmux
|
|
*/
|
|
void sdrv_epwm_cmp_val_upd_a(sdrv_epwm_t *dev, uint32_t trig_point);
|
|
|
|
/**
|
|
* @brief compare software reload
|
|
*
|
|
* This function set compare value valid immediately
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
*/
|
|
void sdrv_epwm_cmp_sw_rld(sdrv_epwm_t *dev);
|
|
|
|
/**
|
|
* @brief compare clr/set configure
|
|
*
|
|
* This function configure compare clear/set source
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] input_sel input sellect
|
|
* @param[in] set_trig cmp set trigger sel
|
|
* @param[in] clr_trig cmp clr trigger sel
|
|
*/
|
|
void sdrv_epwm_cmp_input(sdrv_epwm_t *dev, sdrv_epwm_input_sel_t *input_sel,
|
|
uint8_t set_trig, uint8_t clr_trig);
|
|
|
|
/**
|
|
* @brief configure compare a event id
|
|
*
|
|
* This function configure cmpa0 event id
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] eid_val cmp00/01/10/11 eid
|
|
*/
|
|
void sdrv_epwm_cmp_a_eid(sdrv_epwm_t *dev, epwm_eid_val_t *eid_val);
|
|
|
|
/**
|
|
* @brief epwm initial status.
|
|
*
|
|
* This function configure compare initial value
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] cmp0_init cmp0 channel init status
|
|
* @param[in] cmp1_init cmp1 channel init status
|
|
*
|
|
*/
|
|
void sdrv_epwm_init_sta(sdrv_epwm_t *dev, bool cmp0_init, bool cmp1_init);
|
|
|
|
/**
|
|
* @brief epwm upload chnl_b/c/d [X]0/1 compare value
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] subchnl choose cmp0 or cmp1
|
|
* @param[in] left_point dual mode left cmp_val
|
|
* @param[in] right_point dual mode right cmp_val
|
|
*
|
|
*/
|
|
void sdrv_epwm_val_chnl_bcd_upd_split(sdrv_epwm_t *dev,
|
|
sdrv_epwm_output_e subchnl,
|
|
uint32_t left_point,
|
|
uint32_t right_point);
|
|
|
|
/**
|
|
* @brief epwm upload chnl_b/c/d [X]0/1 compare value
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] cmp0_left_point cmp0 dual mode left cmp_val
|
|
* @param[in] cmp0_right_point cmp0 dual mode right cmp_val
|
|
* @param[in] cmp1_left_point cmp1 dual mode left cmp_val
|
|
* @param[in] cmp1_right_point cmp1 dual mode right cmp_val
|
|
*
|
|
*/
|
|
void sdrv_epwm_val_chnl_bcd_upd_split_both(sdrv_epwm_t *dev,
|
|
uint32_t cmp0_left_point,
|
|
uint32_t cmp0_right_point,
|
|
uint32_t cmp1_left_point,
|
|
uint32_t cmp1_right_point);
|
|
|
|
#if CONFIG_E3L
|
|
/**
|
|
* @brief center align mode enable.
|
|
*
|
|
* This function configure align mode enable
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] en enable/diable center align mode
|
|
*
|
|
*/
|
|
void sdrv_epwm_center_align_mode_en(sdrv_epwm_t *dev, bool en);
|
|
|
|
/**
|
|
* @brief compare value chnl_b/c/d upload in center align mode (unit is cnt val)
|
|
*
|
|
* This function configure channel_b/c/d value upload in center align mode
|
|
*
|
|
* @param[in] dev pwm common instance
|
|
* @param[in] cmp_point center align mode cmp_val
|
|
*/
|
|
void sdrv_epwm_cmp_center_align_val_upd_bcd(sdrv_epwm_t *dev,
|
|
uint32_t cmp_point);
|
|
|
|
#endif
|
|
|
|
#endif
|