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<li class="navelem"><a class="el" href="dir_14bc92f4b96c8519b376567118ac28b3.html">drivers</a></li><li class="navelem"><a class="el" href="dir_ee023d43c33bfccc31aa50a48a76892b.html">include</a></li> </ul>
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<div class="textblock"><code>#include &lt;<a class="el" href="sdrv__common_8h_source.html">sdrv_common.h</a>&gt;</code><br />
<code>#include &lt;lib/list.h&gt;</code><br />
<code>#include &lt;types.h&gt;</code><br />
<code>#include &lt;part.h&gt;</code><br />
<code>#include &lt;<a class="el" href="sdrv__rtc_8h_source.html">sdrv_rtc.h</a>&gt;</code><br />
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<p><a href="sdrv__ckgen_8h_source.html">Go to the source code of this file.</a></p>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__slice__node.html">sdrv_ckgen_slice_node</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__cg__node.html">sdrv_ckgen_cg_node</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__pll__node.html">sdrv_pll_node</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__rate__config__node.html">sdrv_ckgen_rate_config_node</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__rate__config.html">sdrv_ckgen_rate_config</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__bus__config__node.html">sdrv_ckgen_bus_config_node</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__bus__config.html">sdrv_ckgen_bus_config</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structsdrv__ckgen__gating__config__node.html">sdrv_ckgen_gating_config_node</a></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><dl class="section copyright"><dt>Copyright</dt><dd>Copyright (c) 2020 Semidrive Semiconductor. All rights reserved. </dd></dl>
</div><h2 class="groupheader">Macro Definition Documentation</h2>
<a id="aeffffd3d0059e783ea3be40855dfd246" name="aeffffd3d0059e783ea3be40855dfd246"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aeffffd3d0059e783ea3be40855dfd246">&#9670;&nbsp;</a></span>CLK_MHZ</h2>
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<td class="memname">#define CLK_MHZ</td>
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<td>&#160;&#160;&#160;((x) * 1000 * 1000)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a4792d8000234a7dfecbae649fdd2cd40">&#9670;&nbsp;</a></span>CLK_NODE</h2>
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<td class="memname">#define CLK_NODE</td>
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<td class="paramname">node</td><td>)</td>
<td>&#160;&#160;&#160;(<a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *)&amp;(node.clk_node)</td>
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<h2 class="memtitle"><span class="permalink"><a href="#acd33a0639839848620ca92ab68355ca5">&#9670;&nbsp;</a></span>CONFIG_CKGEN_PARENTS_NUM</h2>
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<td class="memname">#define CONFIG_CKGEN_PARENTS_NUM&#160;&#160;&#160;5</td>
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<h2 class="memtitle"><span class="permalink"><a href="#abc316433377d7b0e9d7f7e42ad713f46">&#9670;&nbsp;</a></span>RTC_SS_ACCESS_END</h2>
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<td class="memname">#define RTC_SS_ACCESS_END</td>
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<h2 class="memtitle"><span class="permalink"><a href="#a4e338ded2df3a6d1ac804fc07d1302a0">&#9670;&nbsp;</a></span>RTC_SS_ACCESS_START</h2>
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<td class="memname">#define RTC_SS_ACCESS_START</td>
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<h2 class="groupheader">Typedef Documentation</h2>
<a id="aea76bbc819ce137c43b00e35583185a1" name="aea76bbc819ce137c43b00e35583185a1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aea76bbc819ce137c43b00e35583185a1">&#9670;&nbsp;</a></span>sdrv_ckgen_bus_config_node_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__bus__config__node.html">sdrv_ckgen_bus_config_node</a> <a class="el" href="sdrv__ckgen_8h.html#aea76bbc819ce137c43b00e35583185a1">sdrv_ckgen_bus_config_node_t</a></td>
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<p>Clock rate config for Bus node. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a50d53483d761ee11c18de98e90b3b5a6">&#9670;&nbsp;</a></span>sdrv_ckgen_bus_config_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__bus__config.html">sdrv_ckgen_bus_config</a> <a class="el" href="sdrv__ckgen_8h.html#a50d53483d761ee11c18de98e90b3b5a6">sdrv_ckgen_bus_config_t</a></td>
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<p>Clock rate config lists for Bus node. </p>
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<a id="affdb81462250b8762932cc24f8136e53" name="affdb81462250b8762932cc24f8136e53"></a>
<h2 class="memtitle"><span class="permalink"><a href="#affdb81462250b8762932cc24f8136e53">&#9670;&nbsp;</a></span>sdrv_ckgen_bus_out_type_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__ckgen_8h.html#acc1c7a3e9f86477c71b3e31e38b1676d">sdrv_ckgen_bus_out_type</a> <a class="el" href="sdrv__ckgen_8h.html#affdb81462250b8762932cc24f8136e53">sdrv_ckgen_bus_out_type_e</a></td>
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<p>Config bus slice node output type. For SF/SP BUS, clk_out_m for core, clk_out_n for AXI, clk_out_p for APB For AP domain bus, clk_out_m not used, clk_out_n for AXI, clk_out_p for APB. </p>
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<a id="ae14bb1844ba0c75e2b74de020ffc640a" name="ae14bb1844ba0c75e2b74de020ffc640a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae14bb1844ba0c75e2b74de020ffc640a">&#9670;&nbsp;</a></span>sdrv_ckgen_bus_post_div_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__ckgen_8h.html#a1c3e48b7cf5abf2ab1077d43f9f1781e">sdrv_ckgen_bus_post_div</a> <a class="el" href="sdrv__ckgen_8h.html#ae14bb1844ba0c75e2b74de020ffc640a">sdrv_ckgen_bus_post_div_e</a></td>
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<p>Bus slice post divide ratio. </p>
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<a id="a9a92c21e55131c7af14c1cd032e14304" name="a9a92c21e55131c7af14c1cd032e14304"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9a92c21e55131c7af14c1cd032e14304">&#9670;&nbsp;</a></span>sdrv_ckgen_cg_node_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__cg__node.html">sdrv_ckgen_cg_node</a> <a class="el" href="sdrv__ckgen_8h.html#a9a92c21e55131c7af14c1cd032e14304">sdrv_ckgen_cg_node_t</a></td>
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<p>Abstract xcg node for driver operate. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a3fd5699149fcbb5c750fbbbf7bd96175">&#9670;&nbsp;</a></span>sdrv_ckgen_config_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__config.html">sdrv_ckgen_config</a> <a class="el" href="sdrv__ckgen_8h.html#a3fd5699149fcbb5c750fbbbf7bd96175">sdrv_ckgen_config_t</a></td>
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<p>Initialize clock config for system setup. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ab8cc17ab4dc5e8387949578a73c94f74">&#9670;&nbsp;</a></span>sdrv_ckgen_gating_config_node_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__gating__config__node.html">sdrv_ckgen_gating_config_node</a> <a class="el" href="sdrv__ckgen_8h.html#ab8cc17ab4dc5e8387949578a73c94f74">sdrv_ckgen_gating_config_node_t</a></td>
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<p>Gate config for xcg node. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a9f94e7e5b8252045ab4e30a38a488f53">&#9670;&nbsp;</a></span>sdrv_ckgen_gating_config_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__gating__config.html">sdrv_ckgen_gating_config</a> <a class="el" href="sdrv__ckgen_8h.html#a9f94e7e5b8252045ab4e30a38a488f53">sdrv_ckgen_gating_config_t</a></td>
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<p>Gate config list for XCG node. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a64dfa5e13aab16f05210e4933c5b56ff">&#9670;&nbsp;</a></span>sdrv_ckgen_ip_clock_config_node_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__ip__clock__config__node.html">sdrv_ckgen_ip_clock_config_node</a> <a class="el" href="sdrv__ckgen_8h.html#a64dfa5e13aab16f05210e4933c5b56ff">sdrv_ckgen_ip_clock_config_node_t</a></td>
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<p>IP clock enable/disable config node. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a145fadf9ee199e81c211cfd2a367e572">&#9670;&nbsp;</a></span>sdrv_ckgen_ip_clock_config_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__ip__clock__config.html">sdrv_ckgen_ip_clock_config</a> <a class="el" href="sdrv__ckgen_8h.html#a145fadf9ee199e81c211cfd2a367e572">sdrv_ckgen_ip_clock_config_t</a></td>
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<p>IP clock enable or disable config. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a0f6d54a51fb4ab9ccab2884ef6ce012a">&#9670;&nbsp;</a></span>sdrv_ckgen_lp_mode_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__ckgen_8h.html#a38176540662dddd18a83f2411b68dc51">sdrv_ckgen_lp_mode</a> <a class="el" href="sdrv__ckgen_8h.html#a0f6d54a51fb4ab9ccab2884ef6ce012a">sdrv_ckgen_lp_mode_e</a></td>
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<p>Low power mode for clock config. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ad8d0e7efa2d7e48c2718e0d76cb4bc37">&#9670;&nbsp;</a></span>sdrv_ckgen_node_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__node.html">sdrv_ckgen_node</a> <a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a></td>
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<p>Abstract clock common node for driver operate. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a7300a10350a12be4f8c652c3c67431be">&#9670;&nbsp;</a></span>sdrv_ckgen_rate_config_node_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__rate__config__node.html">sdrv_ckgen_rate_config_node</a> <a class="el" href="sdrv__ckgen_8h.html#a7300a10350a12be4f8c652c3c67431be">sdrv_ckgen_rate_config_node_t</a></td>
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<p>Clock rate config for IP/Core/PLL node. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#aac6484f5e4b9746a5e7a3789d3b04825">&#9670;&nbsp;</a></span>sdrv_ckgen_rate_config_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__rate__config.html">sdrv_ckgen_rate_config</a> <a class="el" href="sdrv__ckgen_8h.html#aac6484f5e4b9746a5e7a3789d3b04825">sdrv_ckgen_rate_config_t</a></td>
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<p>Clock rate config lists for IP/Core/PLL node. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a55479468d29a78b34f4cd92d329323d1">&#9670;&nbsp;</a></span>sdrv_ckgen_slice_node_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__slice__node.html">sdrv_ckgen_slice_node</a> <a class="el" href="sdrv__ckgen_8h.html#a55479468d29a78b34f4cd92d329323d1">sdrv_ckgen_slice_node_t</a></td>
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<p>Abstract clock slice node for driver operate. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#accc13077b049b985d3ad56d92e5ca955">&#9670;&nbsp;</a></span>sdrv_ckgen_ssc_amplitude_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__ckgen_8h.html#ad648f27952770438fd6c39052cad951b">sdrv_ckgen_ssc_amplitude</a> <a class="el" href="sdrv__ckgen_8h.html#accc13077b049b985d3ad56d92e5ca955">sdrv_ckgen_ssc_amplitude_e</a></td>
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<p>PLL Spread amplitude. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a51be8a6fb5c192573123cf21aacab979">&#9670;&nbsp;</a></span>sdrv_ckgen_ssc_freq_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__ckgen_8h.html#a6691c859def077800e297c71cac76b9e">sdrv_ckgen_ssc_freq</a> <a class="el" href="sdrv__ckgen_8h.html#a51be8a6fb5c192573123cf21aacab979">sdrv_ckgen_ssc_freq_e</a></td>
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<p>PLL Spread Modulation frequency. </p>
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<a id="a57d8485aa107144bda3c83050489882a" name="a57d8485aa107144bda3c83050489882a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a57d8485aa107144bda3c83050489882a">&#9670;&nbsp;</a></span>sdrv_ckgen_ssc_mode_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__ckgen_8h.html#a5b2436f269fa5c1df3fb90899161342b">sdrv_ckgen_ssc_mode</a> <a class="el" href="sdrv__ckgen_8h.html#a57d8485aa107144bda3c83050489882a">sdrv_ckgen_ssc_mode_e</a></td>
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<p>PLL Spread mode. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a8ab88c77f21ef313b6f9454b6aa4af1a">&#9670;&nbsp;</a></span>sdrv_ckgen_type_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__ckgen_8h.html#a314d93b0b524d8eaa5de7ba6ec3125e5">sdrv_ckgen_type</a> <a class="el" href="sdrv__ckgen_8h.html#a8ab88c77f21ef313b6f9454b6aa4af1a">sdrv_ckgen_type_e</a></td>
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<p>Clock node type. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#af8335a0ebab784d1127a721be40c872a">&#9670;&nbsp;</a></span>sdrv_ckgen_xcg_set_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__ckgen__xcg__set.html">sdrv_ckgen_xcg_set</a> <a class="el" href="sdrv__ckgen_8h.html#af8335a0ebab784d1127a721be40c872a">sdrv_ckgen_xcg_set_t</a></td>
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<p>CKGEN XCG List. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a8145d2e9d681bce98d264a987c57044e">&#9670;&nbsp;</a></span>sdrv_clk_config_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__clk__config.html">sdrv_clk_config</a> <a class="el" href="sdrv__ckgen_8h.html#a8145d2e9d681bce98d264a987c57044e">sdrv_clk_config_t</a></td>
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<p>System default total clock node list. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ab0db7961bee0096db6e44da4f48ba91f">&#9670;&nbsp;</a></span>sdrv_clk_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__clk.html">sdrv_clk</a> <a class="el" href="sdrv__ckgen_8h.html#ab0db7961bee0096db6e44da4f48ba91f">sdrv_clk_t</a></td>
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<p>Definition for clock tree node. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#af0b7322e80c208ca2ad55d6840bd302f">&#9670;&nbsp;</a></span>sdrv_fs_src_type_e</h2>
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<td class="memname">typedef enum <a class="el" href="sdrv__ckgen_8h.html#a188d9d3f94af470606913020ead5584e">sdrv_fs_src_type</a> <a class="el" href="sdrv__ckgen_8h.html#af0b7322e80c208ca2ad55d6840bd302f">sdrv_fs_src_type_e</a></td>
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<p>Function Safe clock source. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a40c1836548a893f1ca75f4e88cb0b1b9">&#9670;&nbsp;</a></span>sdrv_pll_node_t</h2>
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<td class="memname">typedef struct <a class="el" href="structsdrv__pll__node.html">sdrv_pll_node</a> <a class="el" href="sdrv__ckgen_8h.html#a40c1836548a893f1ca75f4e88cb0b1b9">sdrv_pll_node_t</a></td>
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<p>Abstract pll node for driver operate. </p>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#acc1c7a3e9f86477c71b3e31e38b1676d">&#9670;&nbsp;</a></span>sdrv_ckgen_bus_out_type</h2>
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<td class="memname">enum <a class="el" href="sdrv__ckgen_8h.html#acc1c7a3e9f86477c71b3e31e38b1676d">sdrv_ckgen_bus_out_type</a></td>
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<p>Config bus slice node output type. For SF/SP BUS, clk_out_m for core, clk_out_n for AXI, clk_out_p for APB For AP domain bus, clk_out_m not used, clk_out_n for AXI, clk_out_p for APB. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="acc1c7a3e9f86477c71b3e31e38b1676dae0aaeac1f1e4c529c513b9e2f3e668a9" name="acc1c7a3e9f86477c71b3e31e38b1676dae0aaeac1f1e4c529c513b9e2f3e668a9"></a>CKGEN_BUS_CLK_OUT&#160;</td><td class="fielddoc"><p >use clk_in4, no divide as output clock </p>
</td></tr>
<tr><td class="fieldname"><a id="acc1c7a3e9f86477c71b3e31e38b1676dab78a3ed0ac0213aa96e2bec9d8344729" name="acc1c7a3e9f86477c71b3e31e38b1676dab78a3ed0ac0213aa96e2bec9d8344729"></a>CKGEN_BUS_CLK_OUT_M&#160;</td><td class="fielddoc"><p >output clock divided by div_m_num </p>
</td></tr>
<tr><td class="fieldname"><a id="acc1c7a3e9f86477c71b3e31e38b1676dab9d7bb2ad003df1fb536d9448030938d" name="acc1c7a3e9f86477c71b3e31e38b1676dab9d7bb2ad003df1fb536d9448030938d"></a>CKGEN_BUS_CLK_OUT_N&#160;</td><td class="fielddoc"><p >output clock divided by div_n_num </p>
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<tr><td class="fieldname"><a id="acc1c7a3e9f86477c71b3e31e38b1676da746ff735e1746187aedc41bb28ee31f6" name="acc1c7a3e9f86477c71b3e31e38b1676da746ff735e1746187aedc41bb28ee31f6"></a>CKGEN_BUS_CLK_OUT_P&#160;</td><td class="fielddoc"><p >output clock divided by div_p_num </p>
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<tr><td class="fieldname"><a id="acc1c7a3e9f86477c71b3e31e38b1676da449c3dab42cca455897cb5ded3c873e4" name="acc1c7a3e9f86477c71b3e31e38b1676da449c3dab42cca455897cb5ded3c873e4"></a>CKGEN_BUS_CLK_OUT_Q&#160;</td><td class="fielddoc"><p >output clock divided by div_q_num </p>
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<h2 class="memtitle"><span class="permalink"><a href="#a1c3e48b7cf5abf2ab1077d43f9f1781e">&#9670;&nbsp;</a></span>sdrv_ckgen_bus_post_div</h2>
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<td class="memname">enum <a class="el" href="sdrv__ckgen_8h.html#a1c3e48b7cf5abf2ab1077d43f9f1781e">sdrv_ckgen_bus_post_div</a></td>
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<p>Bus slice post divide ratio. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a1c3e48b7cf5abf2ab1077d43f9f1781ea03db3976e4614161c8f486d923aab03e" name="a1c3e48b7cf5abf2ab1077d43f9f1781ea03db3976e4614161c8f486d923aab03e"></a>CKGEN_BUS_DIV_4_2_1&#160;</td><td class="fielddoc"><p >divm/divn/divp = 4/2/1 </p>
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<tr><td class="fieldname"><a id="a1c3e48b7cf5abf2ab1077d43f9f1781ea79b1efb903dbdaa509121355b60314e0" name="a1c3e48b7cf5abf2ab1077d43f9f1781ea79b1efb903dbdaa509121355b60314e0"></a>CKGEN_BUS_DIV_2_2_1&#160;</td><td class="fielddoc"><p >divm/divn/divp = 2/2/1 </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ae21ef226f1db7e5023a8c455f4d76e41">&#9670;&nbsp;</a></span>sdrv_ckgen_error</h2>
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<td class="memname">enum <a class="el" href="sdrv__ckgen_8h.html#ae21ef226f1db7e5023a8c455f4d76e41">sdrv_ckgen_error</a></td>
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<p>CKGEN status error code. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41aa816d7d7b9e248346c334ee85af42866" name="ae21ef226f1db7e5023a8c455f4d76e41aa816d7d7b9e248346c334ee85af42866"></a>SDRV_CKGEN_POINTER_IS_NULL&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a8d39ed3863ecc10587a4c23afe3ca61c" name="ae21ef226f1db7e5023a8c455f4d76e41a8d39ed3863ecc10587a4c23afe3ca61c"></a>SDRV_CKGEN_XTAL24M_NOT_READY&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a73ed0be2cd46af6ed5456743e22178bf" name="ae21ef226f1db7e5023a8c455f4d76e41a73ed0be2cd46af6ed5456743e22178bf"></a>SDRV_CKGEN_FS24M_WAIT_ACTIVE_TIMEOUT&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a8a3b5d2f60fbea824b747da9a7c017c7" name="ae21ef226f1db7e5023a8c455f4d76e41a8a3b5d2f60fbea824b747da9a7c017c7"></a>SDRV_CKGEN_XTAL32K_NOT_READY&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41ab1130a13f28fd4a02dfe675d30cdfd84" name="ae21ef226f1db7e5023a8c455f4d76e41ab1130a13f28fd4a02dfe675d30cdfd84"></a>SDRV_CKGEN_FS32K_WAIT_ACTIVE_TIMEOUT&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41ae51ed7e24d30461d3d7c8bed0fecbf7a" name="ae21ef226f1db7e5023a8c455f4d76e41ae51ed7e24d30461d3d7c8bed0fecbf7a"></a>SDRV_CKGEN_PLL_NOT_LOCK&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a3765cbd8f46448e9f07ca0f23ff28e3d" name="ae21ef226f1db7e5023a8c455f4d76e41a3765cbd8f46448e9f07ca0f23ff28e3d"></a>SDRV_CKGEN_PLL_RATE_WRONG&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a55303e0b6747016d11931844d5bf72d8" name="ae21ef226f1db7e5023a8c455f4d76e41a55303e0b6747016d11931844d5bf72d8"></a>SDRV_CKGEN_PLL_LVDS_DIV2_CHG_BUSY&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41aac76ad78798ed37347849d25baa148c2" name="ae21ef226f1db7e5023a8c455f4d76e41aac76ad78798ed37347849d25baa148c2"></a>SDRV_CKGEN_PLL_LVDS_DIV7_CHG_BUSY&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a60c5d59a0ba05b8a577c4b248fb3a8c7" name="ae21ef226f1db7e5023a8c455f4d76e41a60c5d59a0ba05b8a577c4b248fb3a8c7"></a>SDRV_CKGEN_PLL_LVDS_CKGEN_CHG_BUSY&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41ae93039794ca8be7e432f9e225fdf6e8c" name="ae21ef226f1db7e5023a8c455f4d76e41ae93039794ca8be7e432f9e225fdf6e8c"></a>SDRV_CKGEN_PLL_NOT_DSM_MODE&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a181e68a18dc4c0ec135e43d30961035c" name="ae21ef226f1db7e5023a8c455f4d76e41a181e68a18dc4c0ec135e43d30961035c"></a>SDRV_CKGEN_SLICE_TYPE_ERROR&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a2a563b334317a61ab544b74900d5759c" name="ae21ef226f1db7e5023a8c455f4d76e41a2a563b334317a61ab544b74900d5759c"></a>SDRV_CKGEN_SLICE_NO_SUITABLE_PARENT&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41af4c60a1a13d8be43541979592f390d7b" name="ae21ef226f1db7e5023a8c455f4d76e41af4c60a1a13d8be43541979592f390d7b"></a>SDRV_CKGEN_SLICE_MAIN_STATUS_ERROR&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41ab33efbfd9294b352c9dff0ffad62b5da" name="ae21ef226f1db7e5023a8c455f4d76e41ab33efbfd9294b352c9dff0ffad62b5da"></a>SDRV_CKGEN_SLICE_PRE_STATUS_ERROR&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a8be39684c1ce5a1e9666bc5784004ad6" name="ae21ef226f1db7e5023a8c455f4d76e41a8be39684c1ce5a1e9666bc5784004ad6"></a>SDRV_CKGEN_SLICE_D0_ACTIVE_ERROR&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41ae520ff25b7b75526c8c30e3920c6de48" name="ae21ef226f1db7e5023a8c455f4d76e41ae520ff25b7b75526c8c30e3920c6de48"></a>SDRV_CKGEN_SLICE_POST_D0_ACTIVE_ERROR&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a4b47e872c06caad869b94a910d9ab62c" name="ae21ef226f1db7e5023a8c455f4d76e41a4b47e872c06caad869b94a910d9ab62c"></a>SDRV_CKGEN_SLICE_DIV_CHG_BUSY&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41ad7e5bc379f41bded327b15fb7e7c83bc" name="ae21ef226f1db7e5023a8c455f4d76e41ad7e5bc379f41bded327b15fb7e7c83bc"></a>SDRV_CKGEN_BEYOND_MAX_DIVIDER&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a012d244797ad5af5e6bd068db2d69355" name="ae21ef226f1db7e5023a8c455f4d76e41a012d244797ad5af5e6bd068db2d69355"></a>SDRV_CKGEN_FREQUENCY_INCORRECT&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a2923e6a19d2e6ab2a71c29ba8d775f36" name="ae21ef226f1db7e5023a8c455f4d76e41a2923e6a19d2e6ab2a71c29ba8d775f36"></a>SDRV_CKGEN_CONSTRUCT_CLKTREE_FAILED&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a6822524b3aa68bb6f35d85e4d261909e" name="ae21ef226f1db7e5023a8c455f4d76e41a6822524b3aa68bb6f35d85e4d261909e"></a>SDRV_CKGEN_PARENT_NODE_NULL&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a0ba59a7fb6d23f9eb6564fc777c70c78" name="ae21ef226f1db7e5023a8c455f4d76e41a0ba59a7fb6d23f9eb6564fc777c70c78"></a>SDRV_CKGEN_BEYOND_MAX_AXI_RATE&#160;</td><td class="fielddoc"></td></tr>
<tr><td class="fieldname"><a id="ae21ef226f1db7e5023a8c455f4d76e41a85f2198f8ae20e4f1fa0364d33739aee" name="ae21ef226f1db7e5023a8c455f4d76e41a85f2198f8ae20e4f1fa0364d33739aee"></a>SDRV_CKGEN_CLOCK_SET_TIMEOUT&#160;</td><td class="fielddoc"></td></tr>
</table>
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</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a38176540662dddd18a83f2411b68dc51">&#9670;&nbsp;</a></span>sdrv_ckgen_lp_mode</h2>
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<td class="memname">enum <a class="el" href="sdrv__ckgen_8h.html#a38176540662dddd18a83f2411b68dc51">sdrv_ckgen_lp_mode</a></td>
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<p>Low power mode for clock config. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a38176540662dddd18a83f2411b68dc51a662020032e3365c5014c26e19dd203e1" name="a38176540662dddd18a83f2411b68dc51a662020032e3365c5014c26e19dd203e1"></a>CKGEN_RUN_MODE&#160;</td><td class="fielddoc"><p >CKGEN RUN MODE </p>
</td></tr>
<tr><td class="fieldname"><a id="a38176540662dddd18a83f2411b68dc51a01ccaca0c490522e8aad1906a44c7aaa" name="a38176540662dddd18a83f2411b68dc51a01ccaca0c490522e8aad1906a44c7aaa"></a>CKGEN_HIB_MODE&#160;</td><td class="fielddoc"><p >CKGEN HIBERNATE MODE </p>
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<tr><td class="fieldname"><a id="a38176540662dddd18a83f2411b68dc51aa72fb51e14ecf7368adb339cf867ee9b" name="a38176540662dddd18a83f2411b68dc51aa72fb51e14ecf7368adb339cf867ee9b"></a>CKGEN_SLP_MODE&#160;</td><td class="fielddoc"><p >CKGEN SLEEP MODE </p>
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<h2 class="memtitle"><span class="permalink"><a href="#ad648f27952770438fd6c39052cad951b">&#9670;&nbsp;</a></span>sdrv_ckgen_ssc_amplitude</h2>
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<td class="memname">enum <a class="el" href="sdrv__ckgen_8h.html#ad648f27952770438fd6c39052cad951b">sdrv_ckgen_ssc_amplitude</a></td>
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<p>PLL Spread amplitude. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951bab4ad96fd0e4f58d71284fcc756d8df26" name="ad648f27952770438fd6c39052cad951bab4ad96fd0e4f58d71284fcc756d8df26"></a>CKGEN_SSC_0P0_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 0.0% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951bafcf53b2d12fea3584f68fc25dba06113" name="ad648f27952770438fd6c39052cad951bafcf53b2d12fea3584f68fc25dba06113"></a>CKGEN_SSC_0P1_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 0.1% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951baeb66e026907acf4980e86da9d9f18ca3" name="ad648f27952770438fd6c39052cad951baeb66e026907acf4980e86da9d9f18ca3"></a>CKGEN_SSC_0P2_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 0.2% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba024268af982e8a22788bf165295165f5" name="ad648f27952770438fd6c39052cad951ba024268af982e8a22788bf165295165f5"></a>CKGEN_SSC_0P3_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 0.3% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951baab4e54d9433e99ccb52115faa5831039" name="ad648f27952770438fd6c39052cad951baab4e54d9433e99ccb52115faa5831039"></a>CKGEN_SSC_0P4_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 0.4% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951bad80170f0e1e7955e1ad694dfd93a22b9" name="ad648f27952770438fd6c39052cad951bad80170f0e1e7955e1ad694dfd93a22b9"></a>CKGEN_SSC_0P5_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 0.5% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba97abae923a5818ba87f4bc71158533e6" name="ad648f27952770438fd6c39052cad951ba97abae923a5818ba87f4bc71158533e6"></a>CKGEN_SSC_0P6_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 0.6% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba578ca4c6ce6823d740e7ff1a15d20032" name="ad648f27952770438fd6c39052cad951ba578ca4c6ce6823d740e7ff1a15d20032"></a>CKGEN_SSC_0P7_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 0.7% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba711c5299dddf9234eea4ef2520363bd6" name="ad648f27952770438fd6c39052cad951ba711c5299dddf9234eea4ef2520363bd6"></a>CKGEN_SSC_0P8_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 0.8% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951bad370983b5e15f3b7eb6f59404d52dd91" name="ad648f27952770438fd6c39052cad951bad370983b5e15f3b7eb6f59404d52dd91"></a>CKGEN_SSC_0P9_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 0.9% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba9a228260bebd59313e0d83c1ecaee120" name="ad648f27952770438fd6c39052cad951ba9a228260bebd59313e0d83c1ecaee120"></a>CKGEN_SSC_1P0_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 1.0% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba28943c18575df8fd369f3a0a315e9b5d" name="ad648f27952770438fd6c39052cad951ba28943c18575df8fd369f3a0a315e9b5d"></a>CKGEN_SSC_1P1_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 1.1% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba7294d21fd1098df59542882931dfdd75" name="ad648f27952770438fd6c39052cad951ba7294d21fd1098df59542882931dfdd75"></a>CKGEN_SSC_1P2_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 1.2% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba4d4e4c725a9819c419be36d12b7e600f" name="ad648f27952770438fd6c39052cad951ba4d4e4c725a9819c419be36d12b7e600f"></a>CKGEN_SSC_1P3_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 1.3% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba0f71a27873b99cc0dcf2ed1fe3b91fc7" name="ad648f27952770438fd6c39052cad951ba0f71a27873b99cc0dcf2ed1fe3b91fc7"></a>CKGEN_SSC_1P4_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 1.4% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba44d45d63229254f1b3f98fef7ce04783" name="ad648f27952770438fd6c39052cad951ba44d45d63229254f1b3f98fef7ce04783"></a>CKGEN_SSC_1P5_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 1.5% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951bacd0e634f5c4ad261b5f7f2fe89dabc28" name="ad648f27952770438fd6c39052cad951bacd0e634f5c4ad261b5f7f2fe89dabc28"></a>CKGEN_SSC_1P6_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 1.6% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba0f17d1a74d017ad66e3e1a7a0ea9dd5a" name="ad648f27952770438fd6c39052cad951ba0f17d1a74d017ad66e3e1a7a0ea9dd5a"></a>CKGEN_SSC_1P7_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 1.7% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba9aed2bcb2035ccf65706464b340c44b7" name="ad648f27952770438fd6c39052cad951ba9aed2bcb2035ccf65706464b340c44b7"></a>CKGEN_SSC_1P8_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 1.8% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba3a9889c2dae5a0c6047fc60976981170" name="ad648f27952770438fd6c39052cad951ba3a9889c2dae5a0c6047fc60976981170"></a>CKGEN_SSC_1P9_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 1.9% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba75348c648382b409306a7792f183d7fc" name="ad648f27952770438fd6c39052cad951ba75348c648382b409306a7792f183d7fc"></a>CKGEN_SSC_2P0_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 2.0% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951baca0b4e6b2416dce4da8708cd81024a22" name="ad648f27952770438fd6c39052cad951baca0b4e6b2416dce4da8708cd81024a22"></a>CKGEN_SSC_2P1_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 2.1% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba419caf9e9451261d2b2012ad73664f1a" name="ad648f27952770438fd6c39052cad951ba419caf9e9451261d2b2012ad73664f1a"></a>CKGEN_SSC_2P2_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 2.2% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951bae5dad03155a1ceeaa8942b3dbc72ab8d" name="ad648f27952770438fd6c39052cad951bae5dad03155a1ceeaa8942b3dbc72ab8d"></a>CKGEN_SSC_2P3_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 2.3% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba138e721d0c62c4478526b2e232de1bea" name="ad648f27952770438fd6c39052cad951ba138e721d0c62c4478526b2e232de1bea"></a>CKGEN_SSC_2P4_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 2.4% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba235db4168a2da853557d12c3d5826d62" name="ad648f27952770438fd6c39052cad951ba235db4168a2da853557d12c3d5826d62"></a>CKGEN_SSC_2P5_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 2.5% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba891abe444a764b4ccd189f3afed2b2f5" name="ad648f27952770438fd6c39052cad951ba891abe444a764b4ccd189f3afed2b2f5"></a>CKGEN_SSC_2P6_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 2.6% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba3692735b81999d95a2ef86a696b0685e" name="ad648f27952770438fd6c39052cad951ba3692735b81999d95a2ef86a696b0685e"></a>CKGEN_SSC_2P7_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 2.7% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba5d203bf87e86872b923d80aadfccfa27" name="ad648f27952770438fd6c39052cad951ba5d203bf87e86872b923d80aadfccfa27"></a>CKGEN_SSC_2P8_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 2.8% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951babac80999328bb795edef001002ffb483" name="ad648f27952770438fd6c39052cad951babac80999328bb795edef001002ffb483"></a>CKGEN_SSC_2P9_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 2.9% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951ba0a9afcb9951f4da372698af3f8ddff94" name="ad648f27952770438fd6c39052cad951ba0a9afcb9951f4da372698af3f8ddff94"></a>CKGEN_SSC_3P0_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 3.0% </p>
</td></tr>
<tr><td class="fieldname"><a id="ad648f27952770438fd6c39052cad951baacb575497e92df799cda7f57033af93f" name="ad648f27952770438fd6c39052cad951baacb575497e92df799cda7f57033af93f"></a>CKGEN_SSC_3P1_PERCENT&#160;</td><td class="fielddoc"><p >SSC_DEP 3.1% </p>
</td></tr>
</table>
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<h2 class="memtitle"><span class="permalink"><a href="#a6691c859def077800e297c71cac76b9e">&#9670;&nbsp;</a></span>sdrv_ckgen_ssc_freq</h2>
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<td class="memname">enum <a class="el" href="sdrv__ckgen_8h.html#a6691c859def077800e297c71cac76b9e">sdrv_ckgen_ssc_freq</a></td>
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<p>PLL Spread Modulation frequency. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a6691c859def077800e297c71cac76b9ea3558d5c67b5a59113912082fc6dc4911" name="a6691c859def077800e297c71cac76b9ea3558d5c67b5a59113912082fc6dc4911"></a>CKGEN_FREF_DIV_507&#160;</td><td class="fielddoc"><p >For 16MHz ref. It's 31.5KHz </p>
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<tr><td class="fieldname"><a id="a6691c859def077800e297c71cac76b9ea655f4a73854799e579181f8d745af651" name="a6691c859def077800e297c71cac76b9ea655f4a73854799e579181f8d745af651"></a>CKGEN_FREF_DIV_761&#160;</td><td class="fielddoc"><p >For 24MHz ref. It's 31.5KHz </p>
</td></tr>
<tr><td class="fieldname"><a id="a6691c859def077800e297c71cac76b9ea3cd30a2a15e3f06dea01f9d63b624a76" name="a6691c859def077800e297c71cac76b9ea3cd30a2a15e3f06dea01f9d63b624a76"></a>CKGEN_FREF_DIV_793&#160;</td><td class="fielddoc"><p >For 25MHz ref. It's 31.5KHz </p>
</td></tr>
<tr><td class="fieldname"><a id="a6691c859def077800e297c71cac76b9ea4f797e5ac3fbe29b859951b04f39cda1" name="a6691c859def077800e297c71cac76b9ea4f797e5ac3fbe29b859951b04f39cda1"></a>CKGEN_FREF_DIV_857&#160;</td><td class="fielddoc"><p >For 27MHz ref. It's 31.5KHz </p>
</td></tr>
</table>
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<h2 class="memtitle"><span class="permalink"><a href="#a5b2436f269fa5c1df3fb90899161342b">&#9670;&nbsp;</a></span>sdrv_ckgen_ssc_mode</h2>
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<td class="memname">enum <a class="el" href="sdrv__ckgen_8h.html#a5b2436f269fa5c1df3fb90899161342b">sdrv_ckgen_ssc_mode</a></td>
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<p>PLL Spread mode. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a5b2436f269fa5c1df3fb90899161342bac14ee6b7eae41ffc3e22773677f32902" name="a5b2436f269fa5c1df3fb90899161342bac14ee6b7eae41ffc3e22773677f32902"></a>CKGEN_NO_SSC&#160;</td><td class="fielddoc"><p >PLL no spread </p>
</td></tr>
<tr><td class="fieldname"><a id="a5b2436f269fa5c1df3fb90899161342ba8d681f2f8c9b56b24f00998bcb5b5b26" name="a5b2436f269fa5c1df3fb90899161342ba8d681f2f8c9b56b24f00998bcb5b5b26"></a>CKGEN_DOWN_SPREADING&#160;</td><td class="fielddoc"><p >PLL down spread </p>
</td></tr>
<tr><td class="fieldname"><a id="a5b2436f269fa5c1df3fb90899161342ba5ce3761dc227dd4b3fe7afc4fec0d187" name="a5b2436f269fa5c1df3fb90899161342ba5ce3761dc227dd4b3fe7afc4fec0d187"></a>CKGEN_CENTER_SPREADING&#160;</td><td class="fielddoc"><p >PLL center spread </p>
</td></tr>
</table>
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<h2 class="memtitle"><span class="permalink"><a href="#a314d93b0b524d8eaa5de7ba6ec3125e5">&#9670;&nbsp;</a></span>sdrv_ckgen_type</h2>
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<td class="memname">enum <a class="el" href="sdrv__ckgen_8h.html#a314d93b0b524d8eaa5de7ba6ec3125e5">sdrv_ckgen_type</a></td>
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<p>Clock node type. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5a6cfb84a9975b35eaf88a918b3da57769" name="a314d93b0b524d8eaa5de7ba6ec3125e5a6cfb84a9975b35eaf88a918b3da57769"></a>CKGEN_IP_SLICE_TYPE&#160;</td><td class="fielddoc"><p >ip slice type </p>
</td></tr>
<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5a764f6d61facfe9a0b61247c1e7517a2c" name="a314d93b0b524d8eaa5de7ba6ec3125e5a764f6d61facfe9a0b61247c1e7517a2c"></a>CKGEN_SF_BUS_SLICE_TYPE&#160;</td><td class="fielddoc"><p >sf/sp bus slice type </p>
</td></tr>
<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5abab13d395159be24b83b29830bc8490a" name="a314d93b0b524d8eaa5de7ba6ec3125e5abab13d395159be24b83b29830bc8490a"></a>CKGEN_BUS_SLICE_TYPE&#160;</td><td class="fielddoc"><p >except sf/sp bus slice type </p>
</td></tr>
<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5ac79045330dd036da523e9450eb2c5169" name="a314d93b0b524d8eaa5de7ba6ec3125e5ac79045330dd036da523e9450eb2c5169"></a>CKGEN_CORE_SLICE_TYPE&#160;</td><td class="fielddoc"><p >core slice type </p>
</td></tr>
<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5ab555231b2dbfa46d3c43384907303a36" name="a314d93b0b524d8eaa5de7ba6ec3125e5ab555231b2dbfa46d3c43384907303a36"></a>CKGEN_PCG_TYPE&#160;</td><td class="fielddoc"><p >PCG type </p>
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<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5aa6ea6bb3209da1e58046081ccaf34c4b" name="a314d93b0b524d8eaa5de7ba6ec3125e5aa6ea6bb3209da1e58046081ccaf34c4b"></a>CKGEN_BCG_TYPE&#160;</td><td class="fielddoc"><p >BCG type </p>
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<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5ace33bfe95c8ced162a2964c9248cd7a5" name="a314d93b0b524d8eaa5de7ba6ec3125e5ace33bfe95c8ced162a2964c9248cd7a5"></a>CKGEN_CCG_TYPE&#160;</td><td class="fielddoc"><p >CCG type </p>
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<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5a5992487eacca9483a5fae2cd0662f0f5" name="a314d93b0b524d8eaa5de7ba6ec3125e5a5992487eacca9483a5fae2cd0662f0f5"></a>CKGEN_PLL_CG_TYPE&#160;</td><td class="fielddoc"><p >PLL CG type </p>
</td></tr>
<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5ad5737a9bf0453d7cc46b925018e0ef27" name="a314d93b0b524d8eaa5de7ba6ec3125e5ad5737a9bf0453d7cc46b925018e0ef27"></a>CKGEN_XTAL_CG_TYPE&#160;</td><td class="fielddoc"><p >XTAL CG type </p>
</td></tr>
<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5ad7519ef8665f4eba42fc4152790eac2e" name="a314d93b0b524d8eaa5de7ba6ec3125e5ad7519ef8665f4eba42fc4152790eac2e"></a>CKGEN_PLL_CTRL_TYPE&#160;</td><td class="fielddoc"><p >PLL CTRL type </p>
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<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5a138bb7a20db6cc424ed4a41eb6aeeada" name="a314d93b0b524d8eaa5de7ba6ec3125e5a138bb7a20db6cc424ed4a41eb6aeeada"></a>CKGEN_PLL_LVDS_TYPE&#160;</td><td class="fielddoc"><p >PLL LVDS type </p>
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<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5a470b5504750c2aecb32860f572ba19c4" name="a314d93b0b524d8eaa5de7ba6ec3125e5a470b5504750c2aecb32860f572ba19c4"></a>CKGEN_RC24M_TYPE&#160;</td><td class="fielddoc"><p >RC24M type </p>
</td></tr>
<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5aecfb817fde7581c5a78df75b88dee3ba" name="a314d93b0b524d8eaa5de7ba6ec3125e5aecfb817fde7581c5a78df75b88dee3ba"></a>CKGEN_FS24M_TYPE&#160;</td><td class="fielddoc"><p >FS24M type </p>
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<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5aa56fa79c36d4440a24b36a5994c05d7e" name="a314d93b0b524d8eaa5de7ba6ec3125e5aa56fa79c36d4440a24b36a5994c05d7e"></a>CKGEN_RC32K_TYPE&#160;</td><td class="fielddoc"><p >RC32K type </p>
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<tr><td class="fieldname"><a id="a314d93b0b524d8eaa5de7ba6ec3125e5ac22b34eb6eba9684a1c432d04bbbf418" name="a314d93b0b524d8eaa5de7ba6ec3125e5ac22b34eb6eba9684a1c432d04bbbf418"></a>CKGEN_FS32K_TYPE&#160;</td><td class="fielddoc"><p >FS32K type </p>
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</table>
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<h2 class="memtitle"><span class="permalink"><a href="#a188d9d3f94af470606913020ead5584e">&#9670;&nbsp;</a></span>sdrv_fs_src_type</h2>
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<td class="memname">enum <a class="el" href="sdrv__ckgen_8h.html#a188d9d3f94af470606913020ead5584e">sdrv_fs_src_type</a></td>
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<p>Function Safe clock source. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="a188d9d3f94af470606913020ead5584ea147b620d402e466c39ca0d4aced00592" name="a188d9d3f94af470606913020ead5584ea147b620d402e466c39ca0d4aced00592"></a>FS_SRC_RC&#160;</td><td class="fielddoc"><p >RC oscillator </p>
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<tr><td class="fieldname"><a id="a188d9d3f94af470606913020ead5584ea637dd42ba032b193d7c938ac24e76ddf" name="a188d9d3f94af470606913020ead5584ea637dd42ba032b193d7c938ac24e76ddf"></a>FS_SRC_XTAL&#160;</td><td class="fielddoc"><p >XTAL oscillator </p>
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<h2 class="groupheader">Function Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#aac4449e0541d294a4ac1302e8be8507a">&#9670;&nbsp;</a></span>sdrv_ckgen_bus_get_rate()</h2>
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<td class="memname">uint32_t sdrv_ckgen_bus_get_rate </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramkey"></td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#affdb81462250b8762932cc24f8136e53">sdrv_ckgen_bus_out_type_e</a>&#160;</td>
<td class="paramname"><em>clk_out</em>&#160;</td>
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<p>Get clock rate for Bus slice node. </p>
<p >This function can get Bus slice clock rate, it can get clk_in4 clock directly without divide, or Clk_out_m/Clk_out_n/Clk_out_p/Clk_out_q divided by m/n/p/q.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CKGEN_SF_BUS_SLICE_TYPE or CKGEN_BUS_SLICE_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">clk_out</td><td>Clk_out/Clk_out_m/Clk_out_n/Clk_out_p/Clk_out_q. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>clock rate. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#acb0585b9ea52d1a939584c484870596c">&#9670;&nbsp;</a></span>sdrv_ckgen_bus_set_rate()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_ckgen_bus_set_rate </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramtype">uint32_t&#160;</td>
<td class="paramname"><em>rate</em>, </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ae14bb1844ba0c75e2b74de020ffc640a">sdrv_ckgen_bus_post_div_e</a>&#160;</td>
<td class="paramname"><em>div</em>&#160;</td>
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<p>Config clock rate for Bus slice node. </p>
<p >This function configure expected clock rate for specific ckgen BUS slice node, since bus slice can output clock direct, or clock divide by m/n/p/q, and their ratio only has two option, one is 4:2:1, other is 2:2:1. Clk_out_m is for core clock rate, Clk_out_n is for AXI bus clock rate, Clk_out_p is for APB bus clock rate.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CKGEN_SF_BUS_SLICE_TYPE or CKGEN_BUS_SLICE_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">rate</td><td>clock rate to be set for Clk_out_m. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">div</td><td>m/n/p,q ratio select. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ac093e8a2fe102868718781b362c1c439">&#9670;&nbsp;</a></span>sdrv_ckgen_cg_mask()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_ckgen_cg_mask </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramtype">bool&#160;</td>
<td class="paramname"><em>mask</em>&#160;</td>
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<p>Set CG NODE whether participate in low power handshake. </p>
<p >This function config CG Node lowpower mask bit. If set to mask, cg status is ignored under low power handshake. Otherwize, cg status is considerd into low power handshake.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CG NODE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">mask</td><td>true or false. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a1b590ce6dc328af3f5ec3d5aeeffe74f">&#9670;&nbsp;</a></span>sdrv_ckgen_clock_config()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_ckgen_clock_config </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramtype">bool&#160;</td>
<td class="paramname"><em>enable</em>&#160;</td>
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<p>Config clock enable or disable in run mode. </p>
<p >This function configure clock gating status in run mode.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CG NODE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>clock enable or disable. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 represents success, otherwise failed. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a267e5bfa9c4b2ad726dd053c160752a1">&#9670;&nbsp;</a></span>sdrv_ckgen_get_fs32k_real_frequency()</h2>
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<td class="memname">uint32_t sdrv_ckgen_get_fs32k_real_frequency </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
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<p>Get FS32K real output clock frequency. </p>
<p >This function use FS24M to check FS32K clock frequency. So you must make sure FS24M is accurate. If you want check RC32K frequency, first change FS32K source to RC, then call this function. If you want check XTAL32K frequency, first change FS32K source to XTAL, then call this function.</p>
<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS24M_TYPE. </td></tr>
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</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Real FS32K output frequency. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ab2690e544c2acbb4b0694baf734991d0">&#9670;&nbsp;</a></span>sdrv_ckgen_get_rate()</h2>
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<td class="memname">uint32_t sdrv_ckgen_get_rate </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
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<p>Get clock rate for Core/IP slice node. </p>
<p >This function get clock rate for CORE or IP slice node.</p>
<dl class="params"><dt>Parameters</dt><dd>
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<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CKGEN_IP_SLICE_TYPE or CKGEN_CORE_SLICE_TYPE. </td></tr>
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</dd>
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<dl class="section return"><dt>Returns</dt><dd>CORE/IP clock rate. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a93b9309bca8241c37cac4e3f0aba90fe">&#9670;&nbsp;</a></span>sdrv_ckgen_init()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_ckgen_init </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#a3fd5699149fcbb5c750fbbbf7bd96175">sdrv_ckgen_config_t</a> *&#160;</td>
<td class="paramname"><em>config</em></td><td>)</td>
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<p>System clock initialize. </p>
<p >This function initialize all system clock as pre-defined. It will change core clock to 24M, then config PLL, after PLL is locked, config BUS and CORE to expect rate. After that config IP clock if defined, and enable or disable clock gate.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">config</td><td>pre-defined clock config list. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a9947d6b21c668c098145f198f4fa6c34">&#9670;&nbsp;</a></span>sdrv_ckgen_ip_clock_enable()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_ckgen_ip_clock_enable </td>
<td>(</td>
<td class="paramtype">const <a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen_ip</em>[], </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#a0f6d54a51fb4ab9ccab2884ef6ce012a">sdrv_ckgen_lp_mode_e</a>&#160;</td>
<td class="paramname"><em>mode</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">bool&#160;</td>
<td class="paramname"><em>enable</em>&#160;</td>
</tr>
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<td></td>
<td>)</td>
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<p>Config IP clock enable/disable in run/sleep/hibernate mode. </p>
<p >This function config all xcg belongs to this IP in run/sleep/hibernate mode.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen_ip</td><td>CG Node list belongs to this IP. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>Run/Sleep/Hibernate. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>clock enable or disable. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ac39d3f887cad798b25ce1a6ed2e08ac5">&#9670;&nbsp;</a></span>sdrv_ckgen_is_gated()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_ckgen_is_gated </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em></td><td>)</td>
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<p>Get ckgen xcg node gating status. </p>
<p >This function check whether xcg node is gated.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CG NODE. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents clock is gated, false represents clock is active, negative is error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a93dfc627eba974228d305b07d3ccdc25">&#9670;&nbsp;</a></span>sdrv_ckgen_set_gate()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_ckgen_set_gate </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#a0f6d54a51fb4ab9ccab2884ef6ce012a">sdrv_ckgen_lp_mode_e</a>&#160;</td>
<td class="paramname"><em>lp_mode</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">bool&#160;</td>
<td class="paramname"><em>gating</em>&#160;</td>
</tr>
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<td></td>
<td>)</td>
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<p>Config xcg status under run/sleep/hibernate mode. </p>
<p >This function configure clock gating status in run/sleep/hibernate mode, when system enter run/sleep/hibernate mode, hardware auto enable or disable clock as configured.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CG NODE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">lp_mode</td><td>Run/Sleep/Hibernate. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">gating</td><td>gating enable or disable. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a61340ec27bf9024adde70bb8386ab177">&#9670;&nbsp;</a></span>sdrv_ckgen_set_pll_power()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_ckgen_set_pll_power </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#a0f6d54a51fb4ab9ccab2884ef6ce012a">sdrv_ckgen_lp_mode_e</a>&#160;</td>
<td class="paramname"><em>lp_mode</em>, </td>
</tr>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">bool&#160;</td>
<td class="paramname"><em>power_down</em>&#160;</td>
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<tr>
<td></td>
<td>)</td>
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<p>Config PLL power down under run/sleep/hibernate mode. </p>
<p >This function config enable or disable PLL power under run/sleep/hibernate mode.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CKGEN_PLL_CG_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">lp_mode</td><td>Run/Sleep/Hibernate. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">power_down</td><td>power down enable or disable. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a5097c23d8e13095fe0aee13a09d11512">&#9670;&nbsp;</a></span>sdrv_ckgen_set_rate()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_ckgen_set_rate </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">uint32_t&#160;</td>
<td class="paramname"><em>rate</em>&#160;</td>
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<td>)</td>
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<p>Config clock rate for Core/IP slice node. </p>
<p >This function configures expected clock rate for specific ckgen node, it will search all his parent nodes, and select a closest clock rate at last.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CKGEN_IP_SLICE_TYPE or CKGEN_CORE_SLICE_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">rate</td><td>expected clock rate. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a30871eeb17778cb8747728effa81830b">&#9670;&nbsp;</a></span>sdrv_ckgen_slice_gated()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_ckgen_slice_gated </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em></td><td>)</td>
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<p>Get slice node gating status. </p>
<p >This function check whether slice node is gated.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be IP/Core/Bus slice. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents clock is gated, false represents clock is active, negative is error code. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ab79d2aa8242671d9329f5b1bfa3138bc">&#9670;&nbsp;</a></span>sdrv_ckgen_xcg_type_set()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_ckgen_xcg_type_set </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#af8335a0ebab784d1127a721be40c872a">sdrv_ckgen_xcg_set_t</a> *&#160;</td>
<td class="paramname"><em>xcg</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#a0f6d54a51fb4ab9ccab2884ef6ce012a">sdrv_ckgen_lp_mode_e</a>&#160;</td>
<td class="paramname"><em>mode</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype">bool&#160;</td>
<td class="paramname"><em>gate</em>&#160;</td>
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<td></td>
<td>)</td>
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<p>Config All xcg gate or active. </p>
<p >This function config PCG/BCG/CCG all gate or active.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">xcg</td><td>xcg info. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">mode</td><td>run mode. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">gate</td><td>true or false. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ab32d44e580c6768e04b6919425399f7f">&#9670;&nbsp;</a></span>sdrv_clktree_dump()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_clktree_dump </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#a8145d2e9d681bce98d264a987c57044e">sdrv_clk_config_t</a> *&#160;</td>
<td class="paramname"><em>clk_config</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ab0db7961bee0096db6e44da4f48ba91f">sdrv_clk_t</a> *&#160;</td>
<td class="paramname"><em>clk_node</em>&#160;</td>
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<p>Dump system clock tree. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">clk_config</td><td>system total clock node list. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">clk_node</td><td>the root clock node begin to dump, if set NULL means dump all clock. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a707485816157a0674d637fbee652041a">&#9670;&nbsp;</a></span>sdrv_fs24m_change_src()</h2>
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<td class="memname">int sdrv_fs24m_change_src </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#af0b7322e80c208ca2ad55d6840bd302f">sdrv_fs_src_type_e</a>&#160;</td>
<td class="paramname"><em>src</em>&#160;</td>
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<p>Config FS24M clock source. </p>
<p >This function select FS24M clock source, RC oscillator or XTAL oscillator.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS24M_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">src</td><td>RC oscillator or XTAL oscillator </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents success, false represents fail. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#acc67abbba274551c8ea9b45b815b1625">&#9670;&nbsp;</a></span>sdrv_fs32k_change_src()</h2>
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<td class="memname">int sdrv_fs32k_change_src </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#af0b7322e80c208ca2ad55d6840bd302f">sdrv_fs_src_type_e</a>&#160;</td>
<td class="paramname"><em>src</em>&#160;</td>
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<td>)</td>
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<p>Config FS32K clock source. </p>
<p >This function select FS32K clock source, RC oscillator or XTAL oscillator.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS32K_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">src</td><td>RC oscillator or XTAL oscillator </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents success, false represents fail. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a28fe81d2ed6ed14211d31591bec62ff9">&#9670;&nbsp;</a></span>sdrv_fs32k_change_src_nowait()</h2>
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<td class="memname">int sdrv_fs32k_change_src_nowait </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#af0b7322e80c208ca2ad55d6840bd302f">sdrv_fs_src_type_e</a>&#160;</td>
<td class="paramname"><em>src</em>&#160;</td>
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<td>)</td>
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<p>Config FS32K clock source without wait active status. </p>
<p >This function select FS32K clock source, RC oscillator or XTAL oscillator.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS32K_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">src</td><td>RC oscillator or XTAL oscillator </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents success, false represents fail. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a6f6e56f703fc0fd1bcf1b5ec9c4b750b">&#9670;&nbsp;</a></span>sdrv_fs32k_get_src_active_status()</h2>
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<td class="memname">bool sdrv_fs32k_get_src_active_status </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#af0b7322e80c208ca2ad55d6840bd302f">sdrv_fs_src_type_e</a>&#160;</td>
<td class="paramname"><em>src</em>&#160;</td>
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<p>Get FS32K clock source active status. </p>
<p >This function get FS32K clock source, RC oscillator or XTAL oscillator, active status.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS32K_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">src</td><td>RC oscillator or XTAL oscillator </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents clock source as FS32K </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a1f21538a25529adffa58be9c44201eb8">&#9670;&nbsp;</a></span>sdrv_fs32k_lpvd_power_ctrl()</h2>
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<td class="memname">int sdrv_fs32k_lpvd_power_ctrl </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
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<td class="paramname"><em>power_on</em>&#160;</td>
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<p>Control low power voltage detector power on or down. </p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS32K_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">power_on</td><td>True or False. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents success, false represents fail. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#acbbef9e262a4d274d4ee0829db0b381d">&#9670;&nbsp;</a></span>sdrv_pll_get_rate()</h2>
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<td class="memname">uint32_t sdrv_pll_get_rate </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em></td><td>)</td>
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<p>Get PLL rate. </p>
<p >This function get clock rate for specific PLL.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CKGEN_PLL_CTRL_TYPE or CKGEN_PLL_LVDS_TYPE. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>pll clock rate. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ad02e234bc9c0b52e31674ab620af85c4">&#9670;&nbsp;</a></span>sdrv_pll_is_locked()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_pll_is_locked </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em></td><td>)</td>
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<p>Get PLL lock detector status. </p>
<p >This function check whether pll is locked.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CKGEN_PLL_CTRL_TYPE. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represets locked, false represents unlocked, negative is error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#ad1dd265ac31a4071729bcff522f2bb15">&#9670;&nbsp;</a></span>sdrv_pll_set_rate()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_pll_set_rate </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td></td>
<td class="paramtype">uint32_t&#160;</td>
<td class="paramname"><em>rate</em>&#160;</td>
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<p>Config PLL rate. </p>
<p >This function config clock rate for specific PLL.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CKGEN_PLL_CTRL_TYPE or CKGEN_PLL_LVDS_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">rate</td><td>clock rate to be set. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#aaf4a098e5318098d3179ff02564266d1">&#9670;&nbsp;</a></span>sdrv_pll_set_rate_with_dsm()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_pll_set_rate_with_dsm </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramtype">uint32_t&#160;</td>
<td class="paramname"><em>rate</em>, </td>
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<td class="paramtype">bool&#160;</td>
<td class="paramname"><em>dsm_en</em>&#160;</td>
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<p>Config PLL rate with delta-sigma modulator enable config. </p>
<p >This function config clock rate for specific PLL, and when rate configed work as integer pll, it's up to user whether enable fractional.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type can be CKGEN_PLL_CTRL_TYPE or CKGEN_PLL_LVDS_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">rate</td><td>clock rate to be set. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">dsm_en</td><td>dsm enable or not. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a8b90116f8ad25ab380224c053437d0a9">&#9670;&nbsp;</a></span>sdrv_pll_set_ssc_amplitude()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_pll_set_ssc_amplitude </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#accc13077b049b985d3ad56d92e5ca955">sdrv_ckgen_ssc_amplitude_e</a>&#160;</td>
<td class="paramname"><em>amplitude</em>&#160;</td>
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<p>Set PLL spread amplitude. </p>
<p >This function set SSC amplitude for specific pll.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node only can be CKGEN_PLL_CTRL_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">amplitude</td><td>SSC amplitude 0-31 represents 0.0% - 3.1%. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#abc4a31724dc5d24d824413d63f01b900">&#9670;&nbsp;</a></span>sdrv_pll_set_ssc_frequency()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_pll_set_ssc_frequency </td>
<td>(</td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td></td>
<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#a51be8a6fb5c192573123cf21aacab979">sdrv_ckgen_ssc_freq_e</a>&#160;</td>
<td class="paramname"><em>ssc_freq</em>&#160;</td>
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<p>Set PLL spread frequency. </p>
<p >This function set SSC frequency for specific pll.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node only can be CKGEN_PLL_CTRL_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">ssc_freq</td><td>SSC modulation frequency. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a7777a60cc733815f326bd819ff45ac53">&#9670;&nbsp;</a></span>sdrv_pll_set_ssc_mode()</h2>
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<td class="memname"><a class="el" href="sdrv__common_8h.html#aaabdaf7ee58ca7269bd4bf24efcde092">status_t</a> sdrv_pll_set_ssc_mode </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#a57d8485aa107144bda3c83050489882a">sdrv_ckgen_ssc_mode_e</a>&#160;</td>
<td class="paramname"><em>ssc_mode</em>&#160;</td>
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<p>Set PLL spread mode. </p>
<p >This function set SSC mode for specific pll. This function will check PLL work mode first, if pll config DSM_DISABLE, set spread mode will failed.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node only can be CKGEN_PLL_CTRL_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">ssc_mode</td><td>SSC mode. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SDRV_STATUS_OK or error code. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a57d1685c15bc4fe2d74e13017291ad06">&#9670;&nbsp;</a></span>sdrv_xtal24m_enable()</h2>
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<td class="memname">int sdrv_xtal24m_enable </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
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<p>Config XTAL24M oscillator. </p>
<p >This function enable or disable xtal24m oscillator.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS24M_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>true represents enable oscillator, false represents disable oscillator. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents success, false represents fail. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a82ccdba0e3b02bce3734343b0ab267a4">&#9670;&nbsp;</a></span>sdrv_xtal24m_from_active_crystal()</h2>
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<td class="memname">int sdrv_xtal24m_from_active_crystal </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
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<p>Config XTAL24M oscillator. </p>
<p >This function config 24M clock from external active crystal.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS24M_TYPE. </td></tr>
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</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents success, false represents fail. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a99f7d2da9c8b1696ceaee4f2f168e73f">&#9670;&nbsp;</a></span>sdrv_xtal32k_enable()</h2>
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<td class="memname">int sdrv_xtal32k_enable </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
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<p>Config XTAL32K oscillator. </p>
<p >This function enable or disable xtal32k oscillator.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS32K_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>true represents enable oscillator, false represents disable oscillator. </td></tr>
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</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents success, false represents fail. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#aece73628a6f82f5d2c6c6bcad9399b0f">&#9670;&nbsp;</a></span>sdrv_xtal32k_enable_nowait()</h2>
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<td class="memname">int sdrv_xtal32k_enable_nowait </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em>, </td>
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<td class="paramname"><em>enable</em>&#160;</td>
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<p>Config XTAL32K oscillator. </p>
<p >This function enable or disable xtal32k oscillator without wait ready status.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS32K_TYPE. </td></tr>
<tr><td class="paramdir">[in]</td><td class="paramname">enable</td><td>true represents enable oscillator, false represents disable oscillator. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents success, false represents fail. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#a081250401bf072239e8d09fd0982b96d">&#9670;&nbsp;</a></span>sdrv_xtal32k_from_active_crystal()</h2>
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<td class="memname">int sdrv_xtal32k_from_active_crystal </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
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<p>Config XTAL32K oscillator. </p>
<p >This function config 32k clock from external active crystal.</p>
<dl class="params"><dt>Parameters</dt><dd>
<table class="params">
<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS32K_TYPE. </td></tr>
</table>
</dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>true represents success, false represents fail. </dd></dl>
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<h2 class="memtitle"><span class="permalink"><a href="#acda6324e3be374951e903ba1fd5eea07">&#9670;&nbsp;</a></span>sdrv_xtal32k_get_ready_status()</h2>
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<td class="memname">bool sdrv_xtal32k_get_ready_status </td>
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<td class="paramtype"><a class="el" href="sdrv__ckgen_8h.html#ad8d0e7efa2d7e48c2718e0d76cb4bc37">sdrv_ckgen_node_t</a> *&#160;</td>
<td class="paramname"><em>ckgen</em></td><td>)</td>
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<p>Get xtal32k ready status. </p>
<p >This function get xtal32k ready status.</p>
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<tr><td class="paramdir">[in]</td><td class="paramname">ckgen</td><td>ckgen node type must be CKGEN_FS32K_TYPE. </td></tr>
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<dl class="section return"><dt>Returns</dt><dd>true represents xtal32k ready, false represents xtal32 not ready. </dd></dl>
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